FPU float<->int conversion optimization
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@@ -11,15 +11,15 @@ gen_sources: sources.txt
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ase-1c: gen_sources setup-ase-1c
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make -C $(ASE_BUILD_DIR)_1c
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cp $(RTL_DIR)/fp_cores/altera/*.hex $(ASE_BUILD_DIR)_1c/work
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cp $(RTL_DIR)/fp_cores/altera/arria10/*.hex $(ASE_BUILD_DIR)_1c/work
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ase-2c: gen_sources setup-ase-2c
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make -C $(ASE_BUILD_DIR)_2c
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cp $(RTL_DIR)/fp_cores/altera/*.hex $(ASE_BUILD_DIR)_2c/work
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cp $(RTL_DIR)/fp_cores/altera/arria10/*.hex $(ASE_BUILD_DIR)_2c/work
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ase-4c: gen_sources setup-ase-4c
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make -C $(ASE_BUILD_DIR)_4c
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cp $(RTL_DIR)/fp_cores/altera/*.hex $(ASE_BUILD_DIR)_4c/work
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cp $(RTL_DIR)/fp_cores/altera/arria10/*.hex $(ASE_BUILD_DIR)_4c/work
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setup-ase-1c: $(ASE_BUILD_DIR)_1c/Makefile
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@@ -38,15 +38,12 @@ $(ASE_BUILD_DIR)_4c/Makefile: sources.txt
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fpga-1c: gen_sources setup-fpga-1c
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cd $(FPGA_BUILD_DIR)_1c && qsub-synth
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cp $(RTL_DIR)/fp_cores/altera/*.hex $(FPGA_BUILD_DIR)_1c
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fpga-2c: gen_sources setup-fpga-2c
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cd $(FPGA_BUILD_DIR)_2c && qsub-synth
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cp $(RTL_DIR)/fp_cores/altera/*.hex $(FPGA_BUILD_DIR)_2c
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fpga-4c: gen_sources setup-fpga-4c
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cd $(FPGA_BUILD_DIR)_4c && qsub-synth
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cp $(RTL_DIR)/fp_cores/altera/*.hex $(FPGA_BUILD_DIR)_4c
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setup-fpga-1c: $(FPGA_BUILD_DIR)_1c/build/dcp.qpf
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