diff --git a/driver/tests/dogfood/testcases.h b/driver/tests/dogfood/testcases.h index cbae336b..3d6da593 100644 --- a/driver/tests/dogfood/testcases.h +++ b/driver/tests/dogfood/testcases.h @@ -490,8 +490,8 @@ public: auto a = (float*)src1; auto b = (float*)src2; for (int i = 0; i < n; ++i) { - a[i] = fround((n/2 - i) * (1.0f/n)); - b[i] = fround((n/2 - i) * (1.0f/n)); + a[i] = fround((n/2 - i) + (float(i)/n)); + b[i] = fround((n/2 - i) + (float(i)/n)); } } @@ -519,8 +519,8 @@ public: auto a = (float*)src1; auto b = (float*)src2; for (int i = 0; i < n; ++i) { - a[i] = fround(i * (1.0f/n)); - b[i] = fround(i * (1.0f/n)); + a[i] = fround(i + (float(i)/n)); + b[i] = fround(i + (float(i)/n)); } } diff --git a/hw/opae/Makefile b/hw/opae/Makefile index 9d927d5e..fb6cbe25 100644 --- a/hw/opae/Makefile +++ b/hw/opae/Makefile @@ -11,15 +11,15 @@ gen_sources: sources.txt ase-1c: gen_sources setup-ase-1c make -C $(ASE_BUILD_DIR)_1c - cp $(RTL_DIR)/fp_cores/altera/*.hex $(ASE_BUILD_DIR)_1c/work + cp $(RTL_DIR)/fp_cores/altera/arria10/*.hex $(ASE_BUILD_DIR)_1c/work ase-2c: gen_sources setup-ase-2c make -C $(ASE_BUILD_DIR)_2c - cp $(RTL_DIR)/fp_cores/altera/*.hex $(ASE_BUILD_DIR)_2c/work + cp $(RTL_DIR)/fp_cores/altera/arria10/*.hex $(ASE_BUILD_DIR)_2c/work ase-4c: gen_sources setup-ase-4c make -C $(ASE_BUILD_DIR)_4c - cp $(RTL_DIR)/fp_cores/altera/*.hex $(ASE_BUILD_DIR)_4c/work + cp $(RTL_DIR)/fp_cores/altera/arria10/*.hex $(ASE_BUILD_DIR)_4c/work setup-ase-1c: $(ASE_BUILD_DIR)_1c/Makefile @@ -38,15 +38,12 @@ $(ASE_BUILD_DIR)_4c/Makefile: sources.txt fpga-1c: gen_sources setup-fpga-1c cd $(FPGA_BUILD_DIR)_1c && qsub-synth - cp $(RTL_DIR)/fp_cores/altera/*.hex $(FPGA_BUILD_DIR)_1c fpga-2c: gen_sources setup-fpga-2c cd $(FPGA_BUILD_DIR)_2c && qsub-synth - cp $(RTL_DIR)/fp_cores/altera/*.hex $(FPGA_BUILD_DIR)_2c fpga-4c: gen_sources setup-fpga-4c cd $(FPGA_BUILD_DIR)_4c && qsub-synth - cp $(RTL_DIR)/fp_cores/altera/*.hex $(FPGA_BUILD_DIR)_4c setup-fpga-1c: $(FPGA_BUILD_DIR)_1c/build/dcp.qpf diff --git a/hw/opae/gen_sources.sh b/hw/opae/gen_sources.sh index 1caa1c84..9f4aec31 100755 --- a/hw/opae/gen_sources.sh +++ b/hw/opae/gen_sources.sh @@ -1,23 +1,40 @@ #!/bin/bash rtl_dir="../rtl" - -dir_list="$rtl_dir/libs $rtl_dir/cache $rtl_dir/interfaces $rtl_dir $rtl_dir/fp_cores/fpnew/src/common_cells/include $rtl_dir/fp_cores $rtl_dir/fp_cores/altera $rtl_dir/afu" - exclude_list="VX_fpnew.v" +file_list="" -# read design sources -for dir in $dir_list; do - echo "+incdir+$dir" - for file in $(find $dir -maxdepth 1 -name '*.v' -o -name '*.sv' -type f); do - exclude=0 - for fe in $exclude_list; do - if [[ $file =~ $fe ]]; then - exclude=1 +add_dirs() +{ + for dir in $*; do + echo "+incdir+$dir" + for file in $(find $dir -maxdepth 1 -name '*.v' -o -name '*.sv' -type f); do + exclude=0 + for fe in $exclude_list; do + if [[ $file =~ $fe ]]; then + exclude=1 + fi + done + if [[ $exclude == 0 ]]; then + file_list="$file_list $file" fi done - if [[ $exclude == 0 ]]; then - echo $file - fi done +} + +add_files() +{ + for file in $*; do + file_list="$file_list $file" + done +} + +add_dirs $rtl_dir/fp_cores/altera/arria10 +#add_dirs $rtl_dir/fp_cores/altera/stratix10 + +add_dirs $rtl_dir/libs $rtl_dir/interfaces $rtl_dir/fp_cores $rtl_dir/cache $rtl_dir $rtl_dir/afu + +# dump file list +for file in $file_list; do + echo $file done \ No newline at end of file diff --git a/hw/rtl/VX_alu_unit.v b/hw/rtl/VX_alu_unit.v index 916bd884..1077de02 100644 --- a/hw/rtl/VX_alu_unit.v +++ b/hw/rtl/VX_alu_unit.v @@ -96,14 +96,13 @@ module VX_alu_unit #( wire stall_out = ~alu_commit_if.ready && alu_commit_if.valid; - VX_generic_register #( - .N(1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32) + 1 + `BR_BITS + 32 + 33), - .R(1) + VX_pipe_register #( + .DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32) + 1 + `BR_BITS + 32 + 33), + .RESETW (1) ) pipe_reg ( .clk (clk), .reset (reset), - .stall (stall_out), - .flush (1'b0), + .enable (!stall_out), .data_in ({alu_req_if.valid, alu_req_if.wid, alu_req_if.tmask, alu_req_if.PC, alu_req_if.rd, alu_req_if.wb, alu_jal_result, is_br_op, br_op, br_dest, cmp_result}), .data_out ({alu_commit_if.valid, alu_commit_if.wid, alu_commit_if.tmask, alu_commit_if.PC, alu_commit_if.rd, alu_commit_if.wb, alu_commit_if.data, is_br_op_r, br_op_r, branch_ctl_if.dest, cmp_result_r}) ); diff --git a/hw/rtl/VX_commit.v b/hw/rtl/VX_commit.v index 9c1b2cb4..3936991a 100644 --- a/hw/rtl/VX_commit.v +++ b/hw/rtl/VX_commit.v @@ -60,14 +60,13 @@ module VX_commit #( .count (commit_size) ); - VX_generic_register #( - .N(1 + CMTW), - .R(1) + VX_pipe_register #( + .DATAW (1 + CMTW), + .RESETW (1) ) pipe_reg ( .clk (clk), .reset (reset), - .stall (1'b0), - .flush (1'b0), + .enable (1'b1), .data_in ({commit_fire, commit_size}), .data_out ({cmt_to_csr_if.valid, cmt_to_csr_if.commit_size}) ); diff --git a/hw/rtl/VX_config.vh b/hw/rtl/VX_config.vh index 61d2ac14..0efc7fd4 100644 --- a/hw/rtl/VX_config.vh +++ b/hw/rtl/VX_config.vh @@ -92,12 +92,12 @@ `define LATENCY_IMUL 3 `endif -`ifndef LATENCY_FNONCOMP -`define LATENCY_FNONCOMP 1 +`ifndef LATENCY_FNCOMP +`define LATENCY_FNCOMP 2 `endif -`ifndef LATENCY_FMADD -`define LATENCY_FMADD 4 +`ifndef LATENCY_FMA +`define LATENCY_FMA 4 `endif `ifndef LATENCY_FDIV @@ -125,11 +125,11 @@ `endif `ifndef LATENCY_FDIVSQRT -`define LATENCY_FDIVSQRT 10 +`define LATENCY_FDIVSQRT 32 `endif `ifndef LATENCY_FCONV -`define LATENCY_FCONV 3 +`define LATENCY_FCONV 4 `endif // CSR Addresses ////////////////////////////////////////////////////////////// diff --git a/hw/rtl/VX_csr_unit.v b/hw/rtl/VX_csr_unit.v index 311034ab..8ff25b4a 100644 --- a/hw/rtl/VX_csr_unit.v +++ b/hw/rtl/VX_csr_unit.v @@ -108,14 +108,13 @@ module VX_csr_unit #( wire stall_out = ~csr_pipe_rsp_if.ready && csr_pipe_rsp_if.valid; - VX_generic_register #( - .N(1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + 1 + `CSR_ADDR_BITS + 1 + 32 + 32), - .R(1) + VX_pipe_register #( + .DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + 1 + `CSR_ADDR_BITS + 1 + 32 + 32), + .RESETW (1) ) pipe_reg ( .clk (clk), .reset (reset), - .stall (stall_out), - .flush (1'b0), + .enable (!stall_out), .data_in ({pipe_req_valid_qual, csr_pipe_req_if.wid, csr_pipe_req_if.tmask, csr_pipe_req_if.PC, csr_pipe_req_if.rd, csr_pipe_req_if.wb, csr_we_s0_unqual, csr_pipe_req_if.csr_addr, csr_pipe_req_if.is_io, csr_read_data_qual, csr_updated_data}), .data_out ({csr_pipe_rsp_if.valid, csr_pipe_rsp_if.wid, csr_pipe_rsp_if.tmask, csr_pipe_rsp_if.PC, csr_pipe_rsp_if.rd, csr_pipe_rsp_if.wb, csr_we_s1, csr_addr_s1, select_io_rsp, csr_read_data_s1, csr_updated_data_s1}) ); diff --git a/hw/rtl/VX_fpu_unit.v b/hw/rtl/VX_fpu_unit.v index 229034f5..ede9a8db 100644 --- a/hw/rtl/VX_fpu_unit.v +++ b/hw/rtl/VX_fpu_unit.v @@ -150,14 +150,13 @@ module VX_fpu_unit #( wire stall_out = ~fpu_commit_if.ready && fpu_commit_if.valid; - VX_generic_register #( - .N(1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32) + 1 + `FFG_BITS), - .R(1) + VX_pipe_register #( + .DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32) + 1 + `FFG_BITS), + .RESETW (1) ) pipe_reg ( .clk (clk), .reset (reset), - .stall (stall_out), - .flush (1'b0), + .enable (!stall_out), .data_in ({valid_out, rsp_wid, rsp_tmask, rsp_PC, rsp_rd, rsp_wb, result, has_fflags, rsp_fflags}), .data_out ({fpu_commit_if.valid, fpu_commit_if.wid, fpu_commit_if.tmask, fpu_commit_if.PC, fpu_commit_if.rd, fpu_commit_if.wb, fpu_commit_if.data, has_fflags_r, fflags_r}) ); diff --git a/hw/rtl/VX_gpu_unit.v b/hw/rtl/VX_gpu_unit.v index 688c767c..c3bce8a0 100644 --- a/hw/rtl/VX_gpu_unit.v +++ b/hw/rtl/VX_gpu_unit.v @@ -75,14 +75,13 @@ module VX_gpu_unit #( wire stall = ~gpu_commit_if.ready && gpu_commit_if.valid; - VX_generic_register #( - .N(1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + `GPU_TMC_SIZE + `GPU_WSPAWN_SIZE + `GPU_SPLIT_SIZE + `GPU_BARRIER_SIZE), - .R(1) + VX_pipe_register #( + .DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + `GPU_TMC_SIZE + `GPU_WSPAWN_SIZE + `GPU_SPLIT_SIZE + `GPU_BARRIER_SIZE), + .RESETW (1) ) pipe_reg ( .clk (clk), .reset (reset), - .stall (stall), - .flush (1'b0), + .enable (!stall), .data_in ({gpu_req_if.valid, gpu_req_if.wid, gpu_req_if.tmask, gpu_req_if.PC, gpu_req_if.rd, gpu_req_if.wb, tmc, wspawn, split, barrier}), .data_out ({gpu_commit_if.valid, gpu_commit_if.wid, gpu_commit_if.tmask, gpu_commit_if.PC, gpu_commit_if.rd, gpu_commit_if.wb, warp_ctl_if.tmc, warp_ctl_if.wspawn, warp_ctl_if.split, warp_ctl_if.barrier}) ); diff --git a/hw/rtl/VX_ibuffer.v b/hw/rtl/VX_ibuffer.v index 83d63287..f08f1f16 100644 --- a/hw/rtl/VX_ibuffer.v +++ b/hw/rtl/VX_ibuffer.v @@ -40,7 +40,7 @@ module VX_ibuffer #( wire push = writing && !is_slot0; wire pop = reading && sizeMany_r[i]; - VX_generic_queue #( + VX_fifo_queue #( .DATAW (DATAW), .SIZE (SIZE), .BUFFERED (1), diff --git a/hw/rtl/VX_instr_demux.v b/hw/rtl/VX_instr_demux.v index ede08971..affa797b 100644 --- a/hw/rtl/VX_instr_demux.v +++ b/hw/rtl/VX_instr_demux.v @@ -18,7 +18,7 @@ module VX_instr_demux ( ); wire [`NT_BITS-1:0] tid; VX_priority_encoder #( - .N(`NUM_THREADS) + .DATAW (`NUM_THREADS) ) tid_select ( .data_in (execute_if.tmask), .data_out (tid), diff --git a/hw/rtl/VX_lsu_unit.v b/hw/rtl/VX_lsu_unit.v index 2d16f348..7eb74eb5 100644 --- a/hw/rtl/VX_lsu_unit.v +++ b/hw/rtl/VX_lsu_unit.v @@ -75,14 +75,13 @@ module VX_lsu_unit #( wire ready_in; wire stall_in = ~ready_in & req_valid; - VX_generic_register #( - .N(1 + `NW_BITS + `NUM_THREADS + 32 + 1 + `NR_BITS + 1 + (`NUM_THREADS * 32) + 2 + (`NUM_THREADS * (30 + 2 + 4 + 32))), - .R(1) + VX_pipe_register #( + .DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + 1 + `NR_BITS + 1 + (`NUM_THREADS * 32) + 2 + (`NUM_THREADS * (30 + 2 + 4 + 32))), + .RESETW (1) ) req_pipe_reg ( .clk (clk), .reset (reset), - .stall (stall_in), - .flush (1'b0), + .enable (!stall_in), .data_in ({lsu_req_if.valid, lsu_req_if.wid, lsu_req_if.tmask, lsu_req_if.PC, lsu_req_if.rw, lsu_req_if.rd, lsu_req_if.wb, full_address, mem_req_sext, mem_req_addr, mem_req_offset, mem_req_byteen, mem_req_data}), .data_out ({req_valid, req_wid, req_tmask, req_pc, req_rw, req_rd, req_wb, req_address, req_sext, req_addr, req_offset, req_byteen, req_data}) ); @@ -210,14 +209,13 @@ module VX_lsu_unit #( wire load_rsp_stall = ~ld_commit_if.ready && ld_commit_if.valid; - VX_generic_register #( - .N(1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32)), - .R(1) + VX_pipe_register #( + .DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32)), + .RESETW (1) ) rsp_pipe_reg ( .clk (clk), .reset (reset), - .stall (load_rsp_stall), - .flush (1'b0), + .enable (!load_rsp_stall), .data_in ({is_load_rsp, rsp_wid, dcache_rsp_if.valid, rsp_pc, rsp_rd, rsp_wb, rsp_data}), .data_out ({ld_commit_if.valid, ld_commit_if.wid, ld_commit_if.tmask, ld_commit_if.PC, ld_commit_if.rd, ld_commit_if.wb, ld_commit_if.data}) ); diff --git a/hw/rtl/VX_mul_unit.v b/hw/rtl/VX_mul_unit.v index 9c765509..3f86e81b 100644 --- a/hw/rtl/VX_mul_unit.v +++ b/hw/rtl/VX_mul_unit.v @@ -127,14 +127,13 @@ module VX_mul_unit #( wire rsp_wb = mul_valid_out ? mul_wb_out : div_wb_out; wire [`NUM_THREADS-1:0][31:0] rsp_data = mul_valid_out ? mul_result : div_result; - VX_generic_register #( - .N(1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32)), - .R(1) + VX_pipe_register #( + .DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32)), + .RESETW (1) ) pipe_reg ( .clk (clk), .reset (reset), - .stall (stall_out), - .flush (1'b0), + .enable (!stall_out), .data_in ({rsp_valid, rsp_wid, rsp_tmask, rsp_PC, rsp_rd, rsp_wb, rsp_data}), .data_out ({mul_commit_if.valid, mul_commit_if.wid, mul_commit_if.tmask, mul_commit_if.PC, mul_commit_if.rd, mul_commit_if.wb, mul_commit_if.data}) ); diff --git a/hw/rtl/VX_types.vh b/hw/rtl/VX_types.vh index 8874cdec..dcf68401 100644 --- a/hw/rtl/VX_types.vh +++ b/hw/rtl/VX_types.vh @@ -9,16 +9,16 @@ typedef struct packed { logic is_subnormal; logic is_inf; logic is_nan; - logic is_signaling; logic is_quiet; + logic is_signaling; } fp_type_t; typedef struct packed { - logic NV; // Invalid - logic DZ; // Divide by zero - logic OF; // Overflow - logic UF; // Underflow - logic NX; // Inexact + logic NV; // 4-Invalid + logic DZ; // 3-Divide by zero + logic OF; // 2-Overflow + logic UF; // 1-Underflow + logic NX; // 0-Inexact } fflags_t; `define FFG_BITS $bits(fflags_t) diff --git a/hw/rtl/VX_warp_sched.v b/hw/rtl/VX_warp_sched.v index 326e83b8..249f23b8 100644 --- a/hw/rtl/VX_warp_sched.v +++ b/hw/rtl/VX_warp_sched.v @@ -195,16 +195,16 @@ module VX_warp_sched #( wire pop = join_if.valid && (i == join_if.wid); VX_ipdom_stack #( - .WIDTH(1+32+`NUM_THREADS), - .DEPTH(2 ** (`NT_BITS+1)) + .WIDTH (1+32+`NUM_THREADS), + .DEPTH (2 ** (`NT_BITS+1)) ) ipdom_stack ( - .clk (clk), - .reset(reset), - .push (push), - .pop (pop), - .q1 (q1), - .q2 (q2), - .d (ipdom[i]), + .clk (clk), + .reset (reset), + .push (push), + .pop (pop), + .q1 (q1), + .q2 (q2), + .d (ipdom[i]), `UNUSED_PIN (empty), `UNUSED_PIN (full) ); @@ -237,14 +237,13 @@ module VX_warp_sched #( assign scheduled_warp = schedule_valid && ~stall_out; - VX_generic_register #( - .N(1 + `NUM_THREADS + 32 + `NW_BITS), - .R(1) + VX_pipe_register #( + .DATAW (1 + `NUM_THREADS + 32 + `NW_BITS), + .RESETW (1) ) pipe_reg ( .clk (clk), .reset (reset), - .stall (stall_out), - .flush (1'b0), + .enable (!stall_out), .data_in ({scheduled_warp, thread_mask, warp_pc, warp_to_schedule}), .data_out ({ifetch_req_if.valid, ifetch_req_if.tmask, ifetch_req_if.PC, ifetch_req_if.wid}) ); diff --git a/hw/rtl/VX_writeback.v b/hw/rtl/VX_writeback.v index f97d933d..7caff91f 100644 --- a/hw/rtl/VX_writeback.v +++ b/hw/rtl/VX_writeback.v @@ -73,14 +73,13 @@ module VX_writeback #( wire stall = ~writeback_if.ready && writeback_if.valid; - VX_generic_register #( - .N(1 + `NW_BITS + 32 + `NUM_THREADS + `NR_BITS + (`NUM_THREADS * 32)), - .R(1) + VX_pipe_register #( + .DATAW (1 + `NW_BITS + 32 + `NUM_THREADS + `NR_BITS + (`NUM_THREADS * 32)), + .RESETW (1) ) pipe_reg ( .clk (clk), .reset (reset), - .stall (stall), - .flush (1'b0), + .enable (!stall), .data_in ({wb_valid, wb_wid, wb_PC, wb_tmask, wb_rd, wb_data}), .data_out ({writeback_if.valid, writeback_if.wid, writeback_if.PC, writeback_if.tmask, writeback_if.rd, writeback_if.data}) ); diff --git a/hw/rtl/afu/VX_avs_wrapper.v b/hw/rtl/afu/VX_avs_wrapper.v index eced0d34..e853c3af 100644 --- a/hw/rtl/afu/VX_avs_wrapper.v +++ b/hw/rtl/afu/VX_avs_wrapper.v @@ -73,7 +73,7 @@ module VX_avs_wrapper #( end end - VX_generic_queue #( + VX_fifo_queue #( .DATAW (REQ_TAGW), .SIZE (RD_QUEUE_SIZE), .BUFFERED(1), @@ -90,7 +90,7 @@ module VX_avs_wrapper #( `UNUSED_PIN (size) ); - VX_generic_queue #( + VX_fifo_queue #( .DATAW (AVS_DATAW), .SIZE (RD_QUEUE_SIZE), .BUFFERED(1), diff --git a/hw/rtl/afu/vortex_afu.sv b/hw/rtl/afu/vortex_afu.sv index 4896367a..933473f4 100644 --- a/hw/rtl/afu/vortex_afu.sv +++ b/hw/rtl/afu/vortex_afu.sv @@ -710,7 +710,7 @@ always @(posedge clk) begin end end -VX_generic_queue #( +VX_fifo_queue #( .DATAW (CCI_RD_RQ_DATAW), .SIZE (CCI_RD_QUEUE_SIZE), .FASTRAM (1) diff --git a/hw/rtl/cache/VX_bank.v b/hw/rtl/cache/VX_bank.v index 2806df24..cd977be5 100644 --- a/hw/rtl/cache/VX_bank.v +++ b/hw/rtl/cache/VX_bank.v @@ -125,7 +125,7 @@ module VX_bank #( wire drsq_full; assign dram_rsp_ready = !drsq_full; - VX_generic_queue #( + VX_fifo_queue #( .DATAW (`LINE_ADDR_WIDTH + $bits(dram_rsp_data)), .SIZE (DRSQ_SIZE), .BUFFERED (1), @@ -166,7 +166,7 @@ module VX_bank #( wire creq_push = (| core_req_valid) && core_req_ready; assign core_req_ready = !creq_full; - VX_generic_queue #( + VX_fifo_queue #( .DATAW (CORE_TAG_WIDTH + `REQS_BITS + 1 + WORD_SIZE + `WORD_ADDR_WIDTH + `WORD_WIDTH), .SIZE (CREQ_SIZE), .BUFFERED (1), @@ -350,14 +350,13 @@ if (DRAM_ENABLE) begin wire mshr_pending_hazard_st0 = mshr_pending_hazard_unqual_st0 || (valid_st3 && (miss_st3 || force_miss_st3) && (addr_st3 == addr_st0)); - VX_generic_register #( - .N(1 + 1 + 1 + `LINE_ADDR_WIDTH + `UP(`WORD_SELECT_WIDTH) + `WORD_WIDTH + 1 + `BANK_LINE_WIDTH + 1 + WORD_SIZE + `REQS_BITS + `REQ_TAG_WIDTH), - .R(1) + VX_pipe_register #( + .DATAW (1 + 1 + 1 + `LINE_ADDR_WIDTH + `UP(`WORD_SELECT_WIDTH) + `WORD_WIDTH + 1 + `BANK_LINE_WIDTH + 1 + WORD_SIZE + `REQS_BITS + `REQ_TAG_WIDTH), + .RESETW (1) ) pipe_reg0 ( .clk (clk), .reset (reset), - .stall (pipeline_stall), - .flush (1'b0), + .enable (!pipeline_stall), .data_in ({valid_st0, is_mshr_st0, mshr_pending_hazard_st0, addr_st0, wsel_st0, writeword_st0, is_fill_st0, writedata_st0, mem_rw_st0, byteen_st0, req_tid_st0, tag_st0}), .data_out ({valid_st1, is_mshr_st1, mshr_pending_hazard_st1, addr_st1, wsel_st1, writeword_st1, is_fill_st1, writedata_st1, mem_rw_st1, byteen_st1, req_tid_st1, tag_st1}) ); @@ -420,14 +419,13 @@ if (DRAM_ENABLE) begin wire incoming_fill_st1 = !drsq_empty && (addr_st1 == drsq_addr_st0); - VX_generic_register #( - .N(1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `UP(`WORD_SELECT_WIDTH) + `WORD_WIDTH + `TAG_SELECT_BITS + 1 + `BANK_LINE_WIDTH + 1 + WORD_SIZE + `REQS_BITS + `REQ_TAG_WIDTH), - .R(1) + VX_pipe_register #( + .DATAW (1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `UP(`WORD_SELECT_WIDTH) + `WORD_WIDTH + `TAG_SELECT_BITS + 1 + `BANK_LINE_WIDTH + 1 + WORD_SIZE + `REQS_BITS + `REQ_TAG_WIDTH), + .RESETW (1) ) pipe_reg1 ( .clk (clk), .reset (reset), - .stall (pipeline_stall), - .flush (1'b0), + .enable (!pipeline_stall), .data_in ({valid_st1, incoming_fill_st1, core_req_hit_st1, is_mshr_st1, writeen_st1, force_miss_st1, dirty_st1, is_fill_st1, addr_st1, wsel_st1, writeword_st1, readtag_st1, miss_st1, writedata_st1, mem_rw_st1, byteen_st1, req_tid_st1, tag_st1}), .data_out ({valid_st2, incoming_fill_st2, core_req_hit_st2, is_mshr_st2, writeen_st2, force_miss_st2, dirty_st2, is_fill_st2, addr_st2, wsel_st2, writeword_st2, readtag_st2, miss_st2, writedata_st2, mem_rw_st2, byteen_st2, req_tid_st2, tag_st2}) ); @@ -554,14 +552,13 @@ end wire crsq_push_st2 = core_req_hit_st2 && !mem_rw_st2; - VX_generic_register #( - .N(1 + 1+ 1 + 1 + 1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `UP(`WORD_SELECT_WIDTH) + `WORD_WIDTH + `TAG_SELECT_BITS + BANK_LINE_SIZE + 1 + WORD_SIZE + `WORD_WIDTH + `BANK_LINE_WIDTH + `REQS_BITS + `REQ_TAG_WIDTH), - .R(1) + VX_pipe_register #( + .DATAW (1 + 1+ 1 + 1 + 1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `UP(`WORD_SELECT_WIDTH) + `WORD_WIDTH + `TAG_SELECT_BITS + BANK_LINE_SIZE + 1 + WORD_SIZE + `WORD_WIDTH + `BANK_LINE_WIDTH + `REQS_BITS + `REQ_TAG_WIDTH), + .RESETW (1) ) pipe_reg2 ( .clk (clk), .reset (reset), - .stall (pipeline_stall), - .flush (1'b0), + .enable (!pipeline_stall), .data_in ({valid_st2, mshr_push_st2, crsq_push_st2, dreq_push_st2, do_writeback_st2, incoming_fill_qual_st2, force_miss_st2, is_mshr_st2, addr_st2, wsel_st2, writeword_st2, readtag_st2, miss_st2, dirtyb_st2, mem_rw_st2, byteen_st2, readword_st2, readdata_st2, req_tid_st2, tag_st2}), .data_out ({valid_st3, mshr_push_st3, crsq_push_st3, dreq_push_st3, do_writeback_st3, incoming_fill_st3, force_miss_st3, is_mshr_st3, addr_st3, wsel_st3, writeword_st3, readtag_st3, miss_st3, dirtyb_st3, mem_rw_st3, byteen_st3, readword_st3, readdata_st3, req_tid_st3, tag_st3}) ); @@ -581,12 +578,7 @@ end wire mshr_push = mshr_push_unqual && !crsq_push_stall - && !dreq_push_stall; - - wire mshr_full; - always @(posedge clk) begin - assert(!mshr_push || !mshr_full); // mmshr stall is detected before issuing new requests - end + && !dreq_push_stall; wire incoming_fill_qual_st3 = (!drsq_empty && (addr_st3 == drsq_addr_st0)) || incoming_fill_st3; @@ -632,7 +624,7 @@ end .enqueue_data_st3 ({writeword_st3, req_tid_st3, tag_st3, mem_rw_st3, byteen_st3, wsel_st3}), .enqueue_is_mshr_st3(is_mshr_st3), .enqueue_ready_st3 (mshr_init_ready_state_st3), - .enqueue_full (mshr_full), + `UNUSED_PIN (enqueue_full), // fill .update_ready_st0 (update_ready_st0), @@ -655,7 +647,6 @@ end `UNUSED_VAR (byteen_st3) `UNUSED_VAR (incoming_fill_st3) assign mshr_pending_hazard_unqual_st0 = 0; - assign mshr_full = 0; assign mshr_valid_st0 = 0; assign mshr_addr_st0 = 0; assign mshr_wsel_st0 = 0; @@ -684,7 +675,7 @@ end wire [CORE_TAG_WIDTH-1:0] crsq_tag_st3 = CORE_TAG_WIDTH'(tag_st3); wire [`WORD_WIDTH-1:0] crsq_data_st3 = readword_st3; - VX_generic_queue #( + VX_fifo_queue #( .DATAW (`REQS_BITS + CORE_TAG_WIDTH + `WORD_WIDTH), .SIZE (CRSQ_SIZE), .BUFFERED (1), @@ -726,7 +717,7 @@ end wire [BANK_LINE_SIZE-1:0] dreq_byteen = writeback ? dirtyb_st3 : {BANK_LINE_SIZE{1'b1}}; if (DRAM_ENABLE) begin - VX_generic_queue #( + VX_fifo_queue #( .DATAW (1 + BANK_LINE_SIZE + `LINE_ADDR_WIDTH + `BANK_LINE_WIDTH), .SIZE (DREQ_SIZE), .BUFFERED (1), diff --git a/hw/rtl/fp_cores/VX_fp_cvt.v b/hw/rtl/fp_cores/VX_fp_cvt.v new file mode 100644 index 00000000..bf306148 --- /dev/null +++ b/hw/rtl/fp_cores/VX_fp_cvt.v @@ -0,0 +1,452 @@ +`include "VX_define.vh" + +`ifndef SYNTHESIS +`include "float_dpi.vh" +`endif + +module VX_fp_cvt #( + parameter TAGW = 1, + parameter LANES = 1 +) ( + input wire clk, + input wire reset, + + output wire ready_in, + input wire valid_in, + + input wire [TAGW-1:0] tag_in, + + input wire [`FRM_BITS-1:0] frm, + + input wire is_itof, + input wire is_signed, + + input wire [LANES-1:0][31:0] dataa, + output wire [LANES-1:0][31:0] result, + + output wire has_fflags, + output fflags_t [LANES-1:0] fflags, + + output wire [TAGW-1:0] tag_out, + + input wire ready_out, + output wire valid_out +); + //! Constants + + localparam MAN_BITS = 23; + localparam EXP_BITS = 8; + localparam EXP_BIAS = 2**(EXP_BITS-1)-1; + + // Use 32-bit integer + localparam MAX_INT_WIDTH = 32; + + // The internal mantissa includes normal bit or an entire integer + localparam INT_MAN_WIDTH = `MAX(MAN_BITS + 1, MAX_INT_WIDTH); + + // The lower 2p+3 bits of the internal FMA result will be needed for leading-zero detection + localparam LZC_RESULT_WIDTH = $clog2(INT_MAN_WIDTH); + + // The internal exponent must be able to represent the smallest denormal input value as signed + // or the number of bits in an integer + localparam INT_EXP_WIDTH = `MAX($clog2(MAX_INT_WIDTH), `MAX(EXP_BITS, $clog2(EXP_BIAS + MAN_BITS))) + 1; + + // shift amount for denormalization + localparam SHAMT_BITS = $clog2(INT_MAN_WIDTH+1); + + localparam FMT_SHIFT_COMPENSATION = INT_MAN_WIDTH - 1 - MAN_BITS; + localparam NUM_FP_STICKY = 2 * INT_MAN_WIDTH - MAN_BITS - 1; // removed mantissa, 1. and R + localparam NUM_INT_STICKY = 2 * INT_MAN_WIDTH - MAX_INT_WIDTH; // removed int and R + + //*------------------------------------------------ + //! Input processing + + fp_type_t [LANES-1:0] in_a_type; + + for (genvar i = 0; i < LANES; ++i) begin + VX_fp_type fp_type ( + .exp_i (dataa[i][30:23]), + .man_i (dataa[i][22:0]), + .type_o (in_a_type[i]) + ); + end + + wire [LANES-1:0][INT_MAN_WIDTH-1:0] encoded_mant; // input mantissa with implicit bit + wire signed [LANES-1:0][INT_EXP_WIDTH-1:0] fmt_exponent; + wire [LANES-1:0] input_sign; + + for (genvar i = 0; i < LANES; ++i) begin + wire [INT_MAN_WIDTH-1:0] int_mantissa; + wire [INT_MAN_WIDTH-1:0] fmt_mantissa; + wire fmt_sign = dataa[i][31]; + wire int_sign = dataa[i][31] & is_signed; + assign int_mantissa = int_sign ? $unsigned(-dataa[i]) : dataa[i]; + assign fmt_mantissa = INT_MAN_WIDTH'({in_a_type[i].is_normal, dataa[i][MAN_BITS-1:0]}); + + assign fmt_exponent[i] = $signed({1'b0, dataa[i][MAN_BITS+EXP_BITS-1:MAN_BITS]}); + assign encoded_mant[i] = is_itof ? int_mantissa : fmt_mantissa; + assign input_sign[i] = is_itof ? int_sign : fmt_sign; + end + + wire [LANES-1:0][LZC_RESULT_WIDTH-1:0] renorm_shamt; // renormalization shift amount + wire [LANES-1:0] mant_is_zero; // for integer zeroes + + for (genvar i = 0; i < LANES; ++i) begin + // Leading zero counter for cancellations + wire mant_is_nonzero; + VX_lzc #( + .DATAW (INT_MAN_WIDTH) + ) lzc ( + .data_in (encoded_mant[i]), + .data_out (renorm_shamt[i]), + .valid_out (mant_is_nonzero) + ); + assign mant_is_zero[i] = ~mant_is_nonzero; + end + + //*------------------------------------------------ + //! Stage0 pipeline + + wire valid_in_s0; + wire [TAGW-1:0] tag_in_s0; + wire is_itof_s0; + wire unsigned_s0; + wire [2:0] rnd_mode_s0; + fp_type_t [LANES-1:0] in_a_type_s0; + wire [LANES-1:0] input_sign_s0; + wire signed [LANES-1:0][INT_EXP_WIDTH-1:0] fmt_exponent_s0; + wire [LANES-1:0][INT_MAN_WIDTH-1:0] encoded_mant_s0; + wire [LANES-1:0][LZC_RESULT_WIDTH-1:0] renorm_shamt_s0; + wire [LANES-1:0] mant_is_zero_s0; + + wire stall; + + VX_pipe_register #( + .DATAW (1 + TAGW + 1 + `FRM_BITS + 1 + LANES * ($bits(fp_type_t) + 1 +INT_EXP_WIDTH + INT_MAN_WIDTH + LZC_RESULT_WIDTH + 1)), + .RESETW (1), + .DEPTH (1) + ) pipe_reg0 ( + .clk (clk), + .reset (reset), + .enable (~stall), + .data_in ({valid_in, tag_in, is_itof, !is_signed, frm, in_a_type, input_sign, fmt_exponent, encoded_mant, renorm_shamt, mant_is_zero}), + .data_out ({valid_in_s0, tag_in_s0, is_itof_s0, unsigned_s0, rnd_mode_s0, in_a_type_s0, input_sign_s0, fmt_exponent_s0, encoded_mant_s0, renorm_shamt_s0, mant_is_zero_s0}) + ); + + //*------------------------------------------------ + //! Normalization + + wire [LANES-1:0][INT_MAN_WIDTH-1:0] input_mant; // normalized input mantissa + wire signed [LANES-1:0][INT_EXP_WIDTH-1:0] input_exp; // unbiased true exponent + wire signed [LANES-1:0][INT_EXP_WIDTH-1:0] destination_exp; // re-biased exponent for destination + + for (genvar i = 0; i < LANES; ++i) begin + `IGNORE_WARNINGS_BEGIN + // Input mantissa needs to be normalized + wire signed [INT_EXP_WIDTH-1:0] fp_input_exp; + wire signed [INT_EXP_WIDTH-1:0] int_input_exp; + wire [LZC_RESULT_WIDTH:0] renorm_shamt_sgn; + + // signed form for calculations + assign renorm_shamt_sgn = $signed({1'b0, renorm_shamt_s0[i]}); + + // Realign input mantissa, append zeroes if destination is wider + assign input_mant[i] = encoded_mant_s0[i] << renorm_shamt_s0[i]; + + // Unbias exponent and compensate for shift + assign fp_input_exp = $signed(fmt_exponent_s0[i] + + $signed({1'b0, in_a_type_s0[i].is_subnormal}) - + $signed(EXP_BIAS) - + renorm_shamt_sgn + + $signed(FMT_SHIFT_COMPENSATION)); + + assign int_input_exp = $signed(INT_MAN_WIDTH - 1 - renorm_shamt_sgn); + + assign input_exp[i] = is_itof_s0 ? int_input_exp : fp_input_exp; + + // Rebias the exponent + assign destination_exp[i] = input_exp[i] + $signed(EXP_BIAS); + `IGNORE_WARNINGS_END + end + + //*------------------------------------------------ + //! Stage1 pipeline + + wire valid_in_s1; + wire [TAGW-1:0] tag_in_s1; + wire is_itof_s1; + wire unsigned_s1; + wire [2:0] rnd_mode_s1; + fp_type_t [LANES-1:0] in_a_type_s1; + wire [LANES-1:0] mant_is_zero_s1; + wire [LANES-1:0] input_sign_s1; + wire signed [LANES-1:0][INT_EXP_WIDTH-1:0] input_exp_s1; + wire signed [LANES-1:0][INT_EXP_WIDTH-1:0] destination_exp_s1; + wire [LANES-1:0][INT_MAN_WIDTH-1:0] input_mant_s1; + + VX_pipe_register #( + .DATAW (1 + TAGW + 1 + `FRM_BITS + 1 + LANES * ($bits(fp_type_t) + 1 + 1 + INT_MAN_WIDTH + 2*INT_EXP_WIDTH)), + .RESETW (1), + .DEPTH (1) + ) pipe_reg1 ( + .clk (clk), + .reset (reset), + .enable (~stall), + .data_in ({valid_in_s0, tag_in_s0, is_itof_s0, unsigned_s0, rnd_mode_s0, in_a_type_s0, mant_is_zero_s0, input_sign_s0, input_mant, input_exp, destination_exp}), + .data_out ({valid_in_s1, tag_in_s1, is_itof_s1, unsigned_s1, rnd_mode_s1, in_a_type_s1, mant_is_zero_s1, input_sign_s1, input_mant_s1, input_exp_s1, destination_exp_s1}) + ); + + //*------------------------------------------------ + //! Casting + reg [LANES-1:0][INT_EXP_WIDTH-1:0] final_exp; // after eventual adjustments + + reg [LANES-1:0][2*INT_MAN_WIDTH:0] preshift_mant; // mantissa before final shift + wire [LANES-1:0][2*INT_MAN_WIDTH:0] destination_mant; // mantissa from shifter, with rnd bit + wire [LANES-1:0][MAN_BITS-1:0] final_mant; // mantissa after adjustments + wire [LANES-1:0][MAX_INT_WIDTH-1:0] final_int; // integer shifted in position + + reg [LANES-1:0][SHAMT_BITS-1:0] denorm_shamt; // shift amount for denormalization + + wire [LANES-1:0][1:0] fp_round_sticky_bits, int_round_sticky_bits, round_sticky_bits; + reg [LANES-1:0] of_before_round; + + // Perform adjustments to mantissa and exponent + for (genvar i = 0; i < LANES; ++i) begin + `IGNORE_WARNINGS_BEGIN + always @(*) begin + // Default assignment + final_exp[i] = $unsigned(destination_exp_s1[i]); // take exponent as is, only look at lower bits + preshift_mant[i] = 65'b0; // initialize mantissa container with zeroes + denorm_shamt[i] = MAN_BITS - MAN_BITS; // right of mantissa + of_before_round[i] = 1'b0; + + // Place mantissa to the left of the shifter + preshift_mant[i] = {input_mant_s1[i], 33'b0}; + + // Handle INT casts + if (is_itof_s1) begin + // Overflow or infinities (for proper rounding) + if ((destination_exp_s1[i] >= 2**EXP_BITS-1) + || (~is_itof_s1 && in_a_type_s1[i].is_inf)) begin + final_exp[i] = $unsigned(2**EXP_BITS-2); // largest normal value + preshift_mant[i] = ~0; // largest normal value and RS bits set + of_before_round[i] = 1'b1; + // Denormalize underflowing values + end else if ((destination_exp_s1[i] < 1) + && (destination_exp_s1[i] >= -$signed(MAN_BITS))) begin + final_exp[i] = 0; // denormal result + denorm_shamt[i] = $unsigned(denorm_shamt[i] + 1 - destination_exp_s1[i]); // adjust right shifting + // Limit the shift to retain sticky bits + end else if (destination_exp_s1[i] < -$signed(MAN_BITS)) begin + final_exp[i] = 0; // denormal result + denorm_shamt[i] = $unsigned(denorm_shamt[i] + 2 + MAN_BITS); // to sticky + end + end else begin + // By default right shift mantissa to be an integer + denorm_shamt[i] = $unsigned(MAX_INT_WIDTH - 1 - input_exp_s1[i]); + // overflow: when converting to unsigned the range is larger by one + if (input_exp_s1[i] >= $signed(MAX_INT_WIDTH -1 + unsigned_s1)) begin + denorm_shamt[i] = 1'b0; // prevent shifting + of_before_round[i] = 1'b1; + // underflow + end else if (input_exp_s1[i] < -1) begin + denorm_shamt[i] = MAX_INT_WIDTH + 1; // all bits go to the sticky + end + end + end + + // Mantissa adjustment shift + assign destination_mant[i] = preshift_mant[i] >> denorm_shamt[i]; + + // Extract final mantissa and round bit, discard the normal bit (for FP) + assign {final_mant[i], fp_round_sticky_bits[i][1]} = destination_mant[i][2*INT_MAN_WIDTH-1 : 2*INT_MAN_WIDTH-1 - (MAN_BITS+1) + 1]; + assign {final_int[i], int_round_sticky_bits[i][1]} = destination_mant[i][2*INT_MAN_WIDTH : 2*INT_MAN_WIDTH - (MAX_INT_WIDTH+1) + 1]; + + // Collapse sticky bits + assign fp_round_sticky_bits[i][0] = (| destination_mant[i][NUM_FP_STICKY-1:0]); + assign int_round_sticky_bits[i][0] = (| destination_mant[i][NUM_INT_STICKY-1:0]); + + // select RS bits for destination operation + assign round_sticky_bits[i] = is_itof_s1 ? fp_round_sticky_bits[i] : int_round_sticky_bits[i]; + `IGNORE_WARNINGS_END + end + + //*------------------------------------------------ + //! Rouding and classification + + wire [LANES-1:0] rounded_sign; + wire [LANES-1:0][31:0] rounded_abs; // absolute value of result after rounding + + for (genvar i = 0; i < LANES; ++i) begin + // Pack exponent and mantissa into proper rounding form + wire [31:0] fmt_pre_round_abs = {1'b0, final_exp[i][EXP_BITS-1:0], final_mant[i][MAN_BITS-1:0]}; + + // Sign-extend integer result + wire [31:0] ifmt_pre_round_abs = final_int[i]; + + // Select output with destination format and operation + wire [31:0] pre_round_abs = is_itof_s1 ? fmt_pre_round_abs : ifmt_pre_round_abs; + + // Perform the rounding + VX_fp_rounding #( + .DAT_WIDTH (32) + ) fp_rounding ( + .abs_value_i (pre_round_abs), + .sign_i (input_sign_s1[i]), + .round_sticky_bits_i (round_sticky_bits[i]), + .rnd_mode_i (rnd_mode_s1), + .effective_subtraction_i (1'b0), + .abs_rounded_o (rounded_abs[i]), + .sign_o (rounded_sign[i]), + `UNUSED_PIN (exact_zero_o) + ); + end + + //*------------------------------------------------ + //! Stage2 pipeline + + wire valid_in_s2; + wire [TAGW-1:0] tag_in_s2; + wire is_itof_s2; + wire unsigned_s2; + fp_type_t [LANES-1:0] in_a_type_s2; + wire [LANES-1:0] mant_is_zero_s2; + wire [LANES-1:0] input_sign_s2; + wire [LANES-1:0] rounded_sign_s2; + wire [LANES-1:0][31:0] rounded_abs_s2; + + VX_pipe_register #( + .DATAW (1 + TAGW + 1 + 1 + LANES * ($bits(fp_type_t) + 1 + 1 + 32 + 1)), + .RESETW (1), + .DEPTH (1) + ) pipe_reg2 ( + .clk (clk), + .reset (reset), + .enable (~stall), + .data_in ({valid_in_s1, tag_in_s1, is_itof_s1, unsigned_s1, in_a_type_s1, mant_is_zero_s1, input_sign_s1, rounded_abs, rounded_sign}), + .data_out ({valid_in_s2, tag_in_s2, is_itof_s2, unsigned_s2, in_a_type_s2, mant_is_zero_s2, input_sign_s2, rounded_abs_s2, rounded_sign_s2}) + ); + + wire [LANES-1:0] of_after_round; + wire [LANES-1:0] uf_after_round; + + wire [LANES-1:0][31:0] fmt_result; + + wire [LANES-1:0][31:0] rounded_int_res; // after possible inversion + wire [LANES-1:0] rounded_int_res_zero; // after rounding + + for (genvar i = 0; i < LANES; ++i) begin + // Assemble regular result, nan box short ones. Int zeroes need to be detected + assign fmt_result[i] = (is_itof_s2 & mant_is_zero_s2[i]) ? 0 : {rounded_sign_s2[i], rounded_abs_s2[i][EXP_BITS+MAN_BITS-1:0]}; + + // Classification after rounding select by destination format + assign uf_after_round[i] = (rounded_abs_s2[i][EXP_BITS+MAN_BITS-1:MAN_BITS] == 0); // denormal + assign of_after_round[i] = (rounded_abs_s2[i][EXP_BITS+MAN_BITS-1:MAN_BITS] == ~0); // inf exp. + + // Negative integer result needs to be brought into two's complement + assign rounded_int_res[i] = rounded_sign_s2[i] ? $unsigned(-rounded_abs_s2[i]) : rounded_abs_s2[i]; + assign rounded_int_res_zero[i] = (rounded_int_res[i] == 0); + end + + //*------------------------------------------------ + //! FP Special case handling + + wire [LANES-1:0][31:0] fp_special_result; + fflags_t [LANES-1:0] fp_special_status; + wire [LANES-1:0] fp_result_is_special; + + localparam logic [EXP_BITS-1:0] QNAN_EXPONENT = 2**EXP_BITS-1; + localparam logic [MAN_BITS-1:0] QNAN_MANTISSA = 2**(MAN_BITS-1); + + for (genvar i = 0; i < LANES; ++i) begin + // Detect special case from source format, I2F casts don't produce a special result + assign fp_result_is_special[i] = ~is_itof_s2 & (in_a_type_s2[i].is_zero | in_a_type_s2[i].is_nan); + + // Signalling input NaNs raise invalid flag, otherwise no flags set + assign fp_special_status[i] = in_a_type_s2[i].is_signaling ? {1'b1, 4'h0} : 5'h0; // invalid operation + + // Assemble result according to destination format + assign fp_special_result[i] = in_a_type_s2[i].is_zero ? (32'(input_sign_s2) << 31) // signed zero + : {1'b0, QNAN_EXPONENT, QNAN_MANTISSA}; // qNaN + end + + //*------------------------------------------------ + //! INT Special case handling + + reg [LANES-1:0][31:0] int_special_result; + fflags_t [LANES-1:0] int_special_status; + wire [LANES-1:0] int_result_is_special; + + for (genvar i = 0; i < LANES; ++i) begin + // Assemble result according to destination format + always @(*) begin + if (input_sign_s2[i] && !in_a_type_s2[i].is_nan) begin + int_special_result[i][30:0] = 0; // alone yields 2**(31)-1 + int_special_result[i][31] = ~unsigned_s2; // for unsigned casts yields 2**31 + end else begin + int_special_result[i][30:0] = 2**(31) -1; // alone yields 2**(31)-1 + int_special_result[i][31] = unsigned_s2; // for unsigned casts yields 2**31 + end + end + + // Detect special case from source format (inf, nan, overflow, nan-boxing or negative unsigned) + assign int_result_is_special[i] = in_a_type_s2[i].is_nan + | in_a_type_s2[i].is_inf + | of_before_round[i] + | (input_sign_s2[i] & unsigned_s2 & ~rounded_int_res_zero[i]); + + // All integer special cases are invalid + assign int_special_status[i] = {1'b1, 4'h0}; + end + + //*------------------------------------------------ + //! Result selection and Output handshake + + fflags_t [LANES-1:0] tmp_fflags; + wire [LANES-1:0][31:0] tmp_result; + + for (genvar i = 0; i < LANES; ++i) begin + fflags_t fp_regular_status, int_regular_status; + fflags_t fp_status, int_status; + wire [31:0] fp_result, int_result; + + wire inexact = is_itof_s2 ? (| fp_round_sticky_bits[i]) // overflow is invalid in i2f; + : (| fp_round_sticky_bits[i]) | (~in_a_type_s2[i].is_inf & (of_before_round[i] | of_after_round[i])); + + assign fp_regular_status.NV = is_itof_s2 & (of_before_round[i] | of_after_round[i]); // overflow is invalid for I2F casts + assign fp_regular_status.DZ = 1'b0; // no divisions + assign fp_regular_status.OF = ~is_itof_s2 & (~in_a_type_s2[i].is_inf & (of_before_round[i] | of_after_round[i])); // inf casts no OF + assign fp_regular_status.UF = uf_after_round[i] & inexact; + assign fp_regular_status.NX = inexact; + + assign int_regular_status = (| int_round_sticky_bits[i]) ? {4'h0, 1'b1} : 5'h0; + + assign fp_result = fp_result_is_special[i] ? fp_special_result[i] : fmt_result[i]; + assign int_result = int_result_is_special[i] ? int_special_result[i] : rounded_int_res[i]; + + assign fp_status = fp_result_is_special[i] ? fp_special_status[i] : fp_regular_status; + assign int_status = int_result_is_special[i] ? int_special_status[i] : int_regular_status; + + // Select output depending on special case detection + assign tmp_result[i] = is_itof_s2 ? fp_result : int_result; + assign tmp_fflags[i] = is_itof_s2 ? fp_status : int_status; + end + + assign stall = ~ready_out && valid_out; + + VX_pipe_register #( + .DATAW (1 + TAGW + (LANES * 32) + (LANES * `FFG_BITS)), + .RESETW (1) + ) pipe_reg3 ( + .clk (clk), + .reset (reset), + .enable (!stall), + .data_in ({valid_in_s2, tag_in_s2, tmp_result, tmp_fflags}), + .data_out ({valid_out, tag_out, result, fflags}) + ); + + assign ready_in = ~stall; + + assign has_fflags = 1'b1; + +endmodule diff --git a/hw/rtl/fp_cores/VX_fp_div.v b/hw/rtl/fp_cores/VX_fp_div.v index 87395296..48218671 100644 --- a/hw/rtl/fp_cores/VX_fp_div.v +++ b/hw/rtl/fp_cores/VX_fp_div.v @@ -16,9 +16,14 @@ module VX_fp_div #( input wire [TAGW-1:0] tag_in, + input wire [`FRM_BITS-1:0] frm, + input wire [LANES-1:0][31:0] dataa, input wire [LANES-1:0][31:0] datab, - output wire [LANES-1:0][31:0] result, + output wire [LANES-1:0][31:0] result, + + output wire has_fflags, + output fflags_t [LANES-1:0] fflags, output wire [TAGW-1:0] tag_out, @@ -44,7 +49,7 @@ module VX_fp_div #( fdiv_h = dpi_register(); end always @(posedge clk) begin - dpi_fdiv (fdiv_h, enable, dataa[i], datab[i], result[i]); + dpi_fdiv (fdiv_h, enable, dataa[i], datab[i], `LATENCY_FDIV, result[i]); end `endif end @@ -63,4 +68,8 @@ module VX_fp_div #( assign ready_in = enable; + `UNUSED_VAR (frm) + assign has_fflags = 0; + assign fflags = 0; + endmodule diff --git a/hw/rtl/fp_cores/VX_fp_madd.v b/hw/rtl/fp_cores/VX_fp_fma.v similarity index 86% rename from hw/rtl/fp_cores/VX_fp_madd.v rename to hw/rtl/fp_cores/VX_fp_fma.v index defaa752..c0f0ba98 100644 --- a/hw/rtl/fp_cores/VX_fp_madd.v +++ b/hw/rtl/fp_cores/VX_fp_fma.v @@ -4,7 +4,7 @@ `include "float_dpi.vh" `endif -module VX_fp_madd #( +module VX_fp_fma #( parameter TAGW = 1, parameter LANES = 1 ) ( @@ -15,6 +15,8 @@ module VX_fp_madd #( input wire valid_in, input wire [TAGW-1:0] tag_in, + + input wire [`FRM_BITS-1:0] frm, input wire do_madd, input wire do_sub, @@ -23,7 +25,10 @@ module VX_fp_madd #( input wire [LANES-1:0][31:0] dataa, input wire [LANES-1:0][31:0] datab, input wire [LANES-1:0][31:0] datac, - output wire [LANES-1:0][31:0] result, + output wire [LANES-1:0][31:0] result, + + output wire has_fflags, + output fflags_t [LANES-1:0] fflags, output wire [TAGW-1:0] tag_out, @@ -75,14 +80,14 @@ module VX_fp_madd #( fmadd_h = dpi_register(); end always @(posedge clk) begin - dpi_fmadd (fmadd_h, enable, a, b, c, result[i]); + dpi_fmadd (fmadd_h, enable, a, b, c, `LATENCY_FMA, result[i]); end `endif end VX_shift_register #( .DATAW (1 + TAGW), - .DEPTH (`LATENCY_FMADD), + .DEPTH (`LATENCY_FMA), .RESETW (1) ) shift_reg ( .clk(clk), @@ -94,4 +99,8 @@ module VX_fp_madd #( assign ready_in = enable; + `UNUSED_VAR (frm) + assign has_fflags = 0; + assign fflags = 0; + endmodule diff --git a/hw/rtl/fp_cores/VX_fp_fpga.v b/hw/rtl/fp_cores/VX_fp_fpga.v index 27ef14e1..85553c69 100644 --- a/hw/rtl/fp_cores/VX_fp_fpga.v +++ b/hw/rtl/fp_cores/VX_fp_fpga.v @@ -27,7 +27,7 @@ module VX_fp_fpga #( input wire ready_out, output wire valid_out ); - localparam NUM_FPC = 6; + localparam NUM_FPC = 5; localparam FPC_BITS = `LOG2UP(NUM_FPC); wire [NUM_FPC-1:0] per_core_ready_in; @@ -36,16 +36,17 @@ module VX_fp_fpga #( reg [NUM_FPC-1:0] per_core_ready_out; wire [NUM_FPC-1:0] per_core_valid_out; - wire fpnew_has_fflags; - fflags_t [`NUM_THREADS-1:0] fpnew_fflags; + wire [NUM_FPC-1:0] per_core_has_fflags; + fflags_t [NUM_FPC-1:0][`NUM_THREADS-1:0] per_core_fflags; reg [FPC_BITS-1:0] core_select; - reg do_madd, do_sub, do_neg, is_signed; + reg do_madd, do_sub, do_neg, is_itof, is_signed; always @(*) begin do_madd = 'x; do_sub = 'x; do_neg = 'x; + is_itof = 'x; is_signed = 'x; case (op_type) `FPU_ADD: begin core_select = 0; do_madd = 0; do_sub = 0; do_neg = 0; end @@ -57,29 +58,32 @@ module VX_fp_fpga #( `FPU_NMSUB: begin core_select = 0; do_madd = 1; do_sub = 1; do_neg = 1; end `FPU_DIV: begin core_select = 1; end `FPU_SQRT: begin core_select = 2; end - `FPU_CVTWS: begin core_select = 3; is_signed = 1; end - `FPU_CVTWUS: begin core_select = 3; is_signed = 0; end - `FPU_CVTSW: begin core_select = 4; is_signed = 1; end - `FPU_CVTSWU: begin core_select = 4; is_signed = 0; end - default: begin core_select = 5; end + `FPU_CVTWS: begin core_select = 3; is_itof = 0; is_signed = 1; end + `FPU_CVTWUS: begin core_select = 3; is_itof = 0; is_signed = 0; end + `FPU_CVTSW: begin core_select = 3; is_itof = 1; is_signed = 1; end + `FPU_CVTSWU: begin core_select = 3; is_itof = 1; is_signed = 0; end + default: begin core_select = 4; end endcase end - VX_fp_madd #( + VX_fp_fma #( .TAGW (TAGW), .LANES(`NUM_THREADS) - ) fp_madd ( + ) fp_fma ( .clk (clk), .reset (reset), .valid_in (valid_in && (core_select == 0)), .ready_in (per_core_ready_in[0]), .tag_in (tag_in), + .frm (frm), .do_madd (do_madd), .do_sub (do_sub), .do_neg (do_neg), .dataa (dataa), .datab (datab), .datac (datac), + .has_fflags (per_core_has_fflags[0]), + .fflags (per_core_fflags[0]), .result (per_core_result[0]), .tag_out (per_core_tag_out[0]), .ready_out (per_core_ready_out[0]), @@ -94,9 +98,12 @@ module VX_fp_fpga #( .reset (reset), .valid_in (valid_in && (core_select == 1)), .ready_in (per_core_ready_in[1]), - .tag_in (tag_in), + .tag_in (tag_in), + .frm (frm), .dataa (dataa), - .datab (datab), + .datab (datab), + .has_fflags (per_core_has_fflags[1]), + .fflags (per_core_fflags[1]), .result (per_core_result[1]), .tag_out (per_core_tag_out[1]), .ready_out (per_core_ready_out[1]), @@ -111,97 +118,88 @@ module VX_fp_fpga #( .reset (reset), .valid_in (valid_in && (core_select == 2)), .ready_in (per_core_ready_in[2]), - .tag_in (tag_in), + .tag_in (tag_in), + .frm (frm), .dataa (dataa), + .has_fflags (per_core_has_fflags[2]), + .fflags (per_core_fflags[2]), .result (per_core_result[2]), .tag_out (per_core_tag_out[2]), .ready_out (per_core_ready_out[2]), .valid_out (per_core_valid_out[2]) ); - VX_fp_ftoi #( + VX_fp_cvt #( .TAGW (TAGW), .LANES(`NUM_THREADS) - ) fp_ftoi ( + ) fp_cvt ( .clk (clk), .reset (reset), .valid_in (valid_in && (core_select == 3)), .ready_in (per_core_ready_in[3]), .tag_in (tag_in), - .is_signed (is_signed), + .frm (frm), + .is_itof (is_itof), + .is_signed (is_signed), .dataa (dataa), + .has_fflags (per_core_has_fflags[3]), + .fflags (per_core_fflags[3]), .result (per_core_result[3]), .tag_out (per_core_tag_out[3]), .ready_out (per_core_ready_out[3]), .valid_out (per_core_valid_out[3]) ); - VX_fp_itof #( + VX_fp_ncomp #( .TAGW (TAGW), .LANES(`NUM_THREADS) - ) fp_itof ( - .clk (clk), - .reset (reset), - .valid_in (valid_in && (core_select == 4)), - .ready_in (per_core_ready_in[4]), - .tag_in (tag_in), - .is_signed (is_signed), - .dataa (dataa), - .result (per_core_result[4]), - .tag_out (per_core_tag_out[4]), - .ready_out (per_core_ready_out[4]), - .valid_out (per_core_valid_out[4]) - ); - - VX_fp_noncomp #( - .TAGW (TAGW), - .LANES(`NUM_THREADS) - ) fp_noncomp ( + ) fp_ncomp ( .clk (clk), .reset (reset), - .valid_in (valid_in && (core_select == 5)), - .ready_in (per_core_ready_in[5]), + .valid_in (valid_in && (core_select == 4)), + .ready_in (per_core_ready_in[4]), .tag_in (tag_in), .op_type (op_type), .frm (frm), .dataa (dataa), .datab (datab), - .result (per_core_result[5]), - .has_fflags (fpnew_has_fflags), - .fflags (fpnew_fflags), - .tag_out (per_core_tag_out[5]), - .ready_out (per_core_ready_out[5]), - .valid_out (per_core_valid_out[5]) + .result (per_core_result[4]), + .has_fflags (per_core_has_fflags[4]), + .fflags (per_core_fflags[4]), + .tag_out (per_core_tag_out[4]), + .ready_out (per_core_ready_out[4]), + .valid_out (per_core_valid_out[4]) ); - reg valid_out_n; reg has_fflags_n; + fflags_t [`NUM_THREADS-1:0] fflags_n; reg [`NUM_THREADS-1:0][31:0] result_n; reg [TAGW-1:0] tag_out_n; always @(*) begin per_core_ready_out = 0; - valid_out_n = 0; has_fflags_n = 'x; + fflags_n = 'x; result_n = 'x; tag_out_n = 'x; for (integer i = 0; i < NUM_FPC; i++) begin - if (per_core_valid_out[i]) begin - per_core_ready_out[i] = ready_out; - valid_out_n = 1; - has_fflags_n = fpnew_has_fflags && (i == 5); + if (per_core_valid_out[i]) begin + has_fflags_n = per_core_has_fflags[i]; + fflags_n = per_core_fflags[i]; result_n = per_core_result[i]; tag_out_n = per_core_tag_out[i]; + per_core_ready_out[i] = ready_out; break; end end end - assign ready_in = per_core_ready_in[core_select]; - assign valid_out = valid_out_n; + assign valid_out = (| per_core_valid_out); assign has_fflags = has_fflags_n; assign tag_out = tag_out_n; assign result = result_n; - assign fflags = fpnew_fflags; + assign fflags = fflags_n; + + assign ready_in = per_core_ready_in[core_select]; endmodule \ No newline at end of file diff --git a/hw/rtl/fp_cores/VX_fp_ftoi.v b/hw/rtl/fp_cores/VX_fp_ftoi.v deleted file mode 100644 index fd7cf663..00000000 --- a/hw/rtl/fp_cores/VX_fp_ftoi.v +++ /dev/null @@ -1,84 +0,0 @@ -`include "VX_define.vh" - -`ifndef SYNTHESIS -`include "float_dpi.vh" -`endif - -module VX_fp_ftoi #( - parameter TAGW = 1, - parameter LANES = 1 -) ( - input wire clk, - input wire reset, - - output wire ready_in, - input wire valid_in, - - input wire [TAGW-1:0] tag_in, - - input wire is_signed, - - input wire [LANES-1:0][31:0] dataa, - output wire [LANES-1:0][31:0] result, - - output wire [TAGW-1:0] tag_out, - - input wire ready_out, - output wire valid_out -); - wire stall = ~ready_out && valid_out; - wire enable = ~stall; - - reg is_signed_r; - - for (genvar i = 0; i < LANES; i++) begin - - wire [31:0] result_s; - wire [31:0] result_u; - - `ifdef QUARTUS - acl_ftoi ftoi ( - .clk (clk), - .areset (reset), - .en (enable), - .a (dataa[i]), - .q (result_s) - ); - - acl_ftou ftou ( - .clk (clk), - .areset (reset), - .en (enable), - .a (dataa[i]), - .q (result_u) - ); - `else - integer ftoi_h, ftou_h; - initial begin - ftoi_h = dpi_register(); - ftou_h = dpi_register(); - end - always @(posedge clk) begin - dpi_ftoi (ftoi_h, enable, dataa[i], result_s); - dpi_ftou (ftou_h, enable, dataa[i], result_u); - end - `endif - - assign result[i] = is_signed_r ? result_s : result_u; - end - - VX_shift_register #( - .DATAW (1 + TAGW + 1), - .DEPTH (`LATENCY_FTOI), - .RESETW (1) - ) shift_reg ( - .clk (clk), - .reset (reset), - .enable (enable), - .data_in ({valid_in, tag_in, is_signed}), - .data_out ({valid_out, tag_out, is_signed_r}) - ); - - assign ready_in = enable; - -endmodule diff --git a/hw/rtl/fp_cores/VX_fp_itof.v b/hw/rtl/fp_cores/VX_fp_itof.v deleted file mode 100644 index e3a77a7e..00000000 --- a/hw/rtl/fp_cores/VX_fp_itof.v +++ /dev/null @@ -1,84 +0,0 @@ -`include "VX_define.vh" - -`ifndef SYNTHESIS -`include "float_dpi.vh" -`endif - -module VX_fp_itof #( - parameter TAGW = 1, - parameter LANES = 1 -) ( - input wire clk, - input wire reset, - - output wire ready_in, - input wire valid_in, - - input wire [TAGW-1:0] tag_in, - - input wire is_signed, - - input wire [LANES-1:0][31:0] dataa, - output wire [LANES-1:0][31:0] result, - - output wire [TAGW-1:0] tag_out, - - input wire ready_out, - output wire valid_out -); - wire stall = ~ready_out && valid_out; - wire enable = ~stall; - - reg is_signed_r; - - for (genvar i = 0; i < LANES; i++) begin - - wire [31:0] result_s; - wire [31:0] result_u; - - `ifdef QUARTUS - acl_itof itof ( - .clk (clk), - .areset (reset), - .en (enable), - .a (dataa[i]), - .q (result_s) - ); - - acl_utof utof ( - .clk (clk), - .areset (reset), - .en (enable), - .a (dataa[i]), - .q (result_u) - ); - `else - integer itof_h, utof_h; - initial begin - itof_h = dpi_register(); - utof_h = dpi_register(); - end - always @(posedge clk) begin - dpi_itof (itof_h, enable, dataa[i], result_s); - dpi_utof (utof_h, enable, dataa[i], result_u); - end - `endif - - assign result[i] = is_signed_r ? result_s : result_u; - end - - VX_shift_register #( - .DATAW (1 + TAGW + 1), - .DEPTH (`LATENCY_ITOF), - .RESETW (1) - ) shift_reg ( - .clk (clk), - .reset (reset), - .enable (enable), - .data_in ({valid_in, tag_in, is_signed}), - .data_out ({valid_out, tag_out, is_signed_r}) - ); - - assign ready_in = enable; - -endmodule diff --git a/hw/rtl/fp_cores/VX_fp_noncomp.v b/hw/rtl/fp_cores/VX_fp_ncomp.v similarity index 62% rename from hw/rtl/fp_cores/VX_fp_noncomp.v rename to hw/rtl/fp_cores/VX_fp_ncomp.v index ea2cb3af..b5cb2707 100644 --- a/hw/rtl/fp_cores/VX_fp_noncomp.v +++ b/hw/rtl/fp_cores/VX_fp_ncomp.v @@ -1,6 +1,6 @@ `include "VX_define.vh" -module VX_fp_noncomp #( +module VX_fp_ncomp #( parameter TAGW = 1, parameter LANES = 1 ) ( @@ -46,70 +46,55 @@ module VX_fp_noncomp #( reg [LANES-1:0][31:0] dataa_r; reg [LANES-1:0][31:0] datab_r; - reg [LANES-1:0] a_sign, b_sign; - reg [LANES-1:0][7:0] a_exponent; - reg [LANES-1:0][22:0] a_mantissa; - fp_type_t [LANES-1:0] a_type, b_type; - reg [LANES-1:0] a_smaller, ab_equal; + reg [LANES-1:0] a_sign, b_sign, tmp_a_sign, tmp_b_sign; + reg [LANES-1:0][7:0] a_exponent, tmp_a_exponent, tmp_b_exponent; + reg [LANES-1:0][22:0] a_mantissa, tmp_a_mantissa, tmp_b_mantissa; + fp_type_t [LANES-1:0] a_type, b_type, tmp_a_type, tmp_b_type; + reg [LANES-1:0] a_smaller, ab_equal, tmp_a_smaller, tmp_ab_equal; reg [LANES-1:0][31:0] fclass_mask; // generate a 10-bit mask for integer reg reg [LANES-1:0][31:0] fminmax_res; // result of fmin/fmax reg [LANES-1:0][31:0] fsgnj_res; // result of sign injection reg [LANES-1:0][31:0] fcmp_res; // result of comparison - reg [LANES-1:0][ 4:0] fcmp_excp; // exception of comparison + fflags_t [LANES-1:0] fcmp_fflags; // comparison fflags wire stall = ~ready_out && valid_out; // Setup for (genvar i = 0; i < LANES; i++) begin - wire tmp_a_sign = dataa[i][31]; - wire [7:0] tmp_a_exponent = dataa[i][30:23]; - wire [22:0] tmp_a_mantissa = dataa[i][22:0]; + assign tmp_a_sign[i] = dataa[i][31]; + assign tmp_a_exponent[i] = dataa[i][30:23]; + assign tmp_a_mantissa[i] = dataa[i][22:0]; - wire tmp_b_sign = datab[i][31]; - wire [7:0] tmp_b_exponent = datab[i][30:23]; - wire [22:0] tmp_b_mantissa = datab[i][22:0]; - - fp_type_t tmp_a_type, tmp_b_type; + assign tmp_b_sign[i] = datab[i][31]; + assign tmp_b_exponent[i] = datab[i][30:23]; + assign tmp_b_mantissa[i] = datab[i][22:0]; VX_fp_type fp_type_a ( - .exponent(tmp_a_exponent), - .mantissa(tmp_a_mantissa), - .o_type(tmp_a_type) + .exp_i (tmp_a_exponent[i]), + .man_i (tmp_a_mantissa[i]), + .type_o (tmp_a_type[i]) ); VX_fp_type fp_type_b ( - .exponent(tmp_b_exponent), - .mantissa(tmp_b_mantissa), - .o_type(tmp_b_type) + .exp_i (tmp_b_exponent[i]), + .man_i (tmp_b_mantissa[i]), + .type_o (tmp_b_type[i]) ); - wire tmp_a_smaller = $signed(dataa[i]) < $signed(datab[i]); - wire tmp_ab_equal = (dataa[i] == datab[i]) | (tmp_a_type[4] & tmp_b_type[4]); - - VX_generic_register #( - .N(1 + 1 + 8 + 23 + $bits(fp_type_t) + $bits(fp_type_t) + 1 + 1), - .R(0) - ) pipe_reg0 ( - .clk (clk), - .reset (reset), - .stall (stall), - .flush (1'b0), - .data_in ({tmp_a_sign, tmp_b_sign, tmp_a_exponent, tmp_a_mantissa, tmp_a_type, tmp_b_type, tmp_a_smaller, tmp_ab_equal}), - .data_out ({a_sign[i], b_sign[i], a_exponent[i], a_mantissa[i], a_type[i], b_type[i], a_smaller[i], ab_equal[i]}) - ); + assign tmp_a_smaller[i] = $signed(dataa[i]) < $signed(datab[i]); + assign tmp_ab_equal[i] = (dataa[i] == datab[i]) | (tmp_a_type[i].is_zero & tmp_b_type[i].is_zero); end - VX_generic_register #( - .N(1 + TAGW + `FPU_BITS + `FRM_BITS + (2 * `NUM_THREADS * 32)), - .R(1) - ) pipe_reg1 ( + VX_pipe_register #( + .DATAW (1 + TAGW + `FPU_BITS + `FRM_BITS + LANES * (2 * 32 + 1 + 1 + 8 + 23 + 2 * $bits(fp_type_t) + 1 + 1)), + .RESETW (1) + ) pipe_reg0 ( .clk (clk), .reset (reset), - .stall (stall), - .flush (1'b0), - .data_in ({valid_in, tag_in, op_type, frm, dataa, datab}), - .data_out ({valid_in_r, tag_in_r, op_type_r, frm_r, dataa_r, datab_r}) + .enable (!stall), + .data_in ({valid_in, tag_in, op_type, frm, dataa, datab, tmp_a_sign, tmp_b_sign, tmp_a_exponent, tmp_a_mantissa, tmp_a_type, tmp_b_type, tmp_a_smaller, tmp_ab_equal}), + .data_out ({valid_in_r, tag_in_r, op_type_r, frm_r, dataa_r, datab_r, a_sign, b_sign, a_exponent, a_mantissa, a_type, b_type, a_smaller, ab_equal}) ); // FCLASS @@ -155,7 +140,7 @@ module VX_fp_noncomp #( end end - // Sign Injection + // Sign injection for (genvar i = 0; i < LANES; i++) begin always @(*) begin case (frm_r) @@ -172,39 +157,35 @@ module VX_fp_noncomp #( always @(*) begin case (frm_r) `FRM_RNE: begin + fcmp_fflags[i] = 5'h0; if (a_type[i].is_nan || b_type[i].is_nan) begin - fcmp_res[i] = 32'h0; // result is 0 when either operand is NaN - fcmp_excp[i] = {1'b1, 4'h0}; // raise NV flag when either operand is NaN - end - else begin + fcmp_res[i] = 32'h0; + fcmp_fflags[i].NV = 1'b1; + end else begin fcmp_res[i] = {31'h0, (a_smaller[i] | ab_equal[i])}; - fcmp_excp[i] = 5'h0; end end - `FRM_RTZ: begin + `FRM_RTZ: begin + fcmp_fflags[i] = 5'h0; if (a_type[i].is_nan || b_type[i].is_nan) begin - fcmp_res[i] = 32'h0; // result is 0 when either operand is NaN - fcmp_excp[i] = {1'b1, 4'h0}; // raise NV flag when either operand is NaN - end - else begin + fcmp_res[i] = 32'h0; + fcmp_fflags[i].NV = 1'b1; + end else begin fcmp_res[i] = {31'h0, (a_smaller[i] & ~ab_equal[i])}; - fcmp_excp[i] = 5'h0; end end `FRM_RDN: begin + fcmp_fflags[i] = 5'h0; if (a_type[i].is_nan || b_type[i].is_nan) begin - fcmp_res[i] = 32'h0; // result is 0 when either operand is NaN - // FEQS only raise NV flag when either operand is signaling NaN - fcmp_excp[i] = {(a_type[i].is_signaling | b_type[i].is_signaling), 4'h0}; - end - else begin + fcmp_res[i] = 32'h0; + fcmp_fflags[i].NV = a_type[i].is_signaling | b_type[i].is_signaling; + end else begin fcmp_res[i] = {31'h0, ab_equal[i]}; - fcmp_excp[i] = 5'h0; end end default: begin - fcmp_res[i] = 'x; // don't care value - fcmp_excp[i] = 5'h0; + fcmp_res[i] = 'x; + fcmp_fflags[i] = 'x; end endcase end @@ -212,35 +193,36 @@ module VX_fp_noncomp #( // outputs - fflags_t [LANES-1:0] tmp_fflags; reg [LANES-1:0][31:0] tmp_result; + fflags_t [LANES-1:0] tmp_fflags; for (genvar i = 0; i < LANES; i++) begin always @(*) begin case (op_type_r) `FPU_CLASS: begin tmp_result[i] = fclass_mask[i]; - {tmp_fflags[i].NV, tmp_fflags[i].DZ, tmp_fflags[i].OF, tmp_fflags[i].UF, tmp_fflags[i].NX} = 5'h0; + tmp_fflags[i] = 'x; end `FPU_CMP: begin tmp_result[i] = fcmp_res[i]; - {tmp_fflags[i].NV, tmp_fflags[i].DZ, tmp_fflags[i].OF, tmp_fflags[i].UF, tmp_fflags[i].NX} = fcmp_excp[i]; + tmp_fflags[i] = fcmp_fflags[i]; end //`FPU_MISC: default: begin case (frm_r) - 0,1,2: begin + 0,1,2: begin tmp_result[i] = fsgnj_res[i]; - {tmp_fflags[i].NV, tmp_fflags[i].DZ, tmp_fflags[i].OF, tmp_fflags[i].UF, tmp_fflags[i].NX} = 5'h0; + tmp_fflags[i] = 'x; end 3,4: begin tmp_result[i] = fminmax_res[i]; - {tmp_fflags[i].NV, tmp_fflags[i].DZ, tmp_fflags[i].OF, tmp_fflags[i].UF, tmp_fflags[i].NX} = {a_type[i][0] | b_type[i][0], 4'h0}; + tmp_fflags[i] = 0; + tmp_fflags[i].NV = a_type[i].is_signaling | b_type[i].is_signaling; end //5,6,7: default: begin tmp_result[i] = dataa[i]; - {tmp_fflags[i].NV, tmp_fflags[i].DZ, tmp_fflags[i].OF, tmp_fflags[i].UF, tmp_fflags[i].NX} = 5'h0; + tmp_fflags[i] = 'x; end endcase end @@ -251,14 +233,13 @@ module VX_fp_noncomp #( wire tmp_has_fflags = ((op_type_r == `FPU_MISC) && (frm == 3 || frm == 4)) // MIN/MAX || (op_type_r == `FPU_CMP); // CMP - VX_generic_register #( - .N(1 + TAGW + (LANES * 32) + 1 + (LANES * `FFG_BITS)), - .R(1) - ) pipe_reg2 ( + VX_pipe_register #( + .DATAW (1 + TAGW + (LANES * 32) + 1 + (LANES * `FFG_BITS)), + .RESETW (1) + ) pipe_reg1 ( .clk (clk), .reset (reset), - .stall (stall), - .flush (1'b0), + .enable (!stall), .data_in ({valid_in_r, tag_in_r, tmp_result, tmp_has_fflags, tmp_fflags}), .data_out ({valid_out, tag_out, result, has_fflags, fflags}) ); diff --git a/hw/rtl/fp_cores/VX_fp_rounding.v b/hw/rtl/fp_cores/VX_fp_rounding.v new file mode 100644 index 00000000..53ea2435 --- /dev/null +++ b/hw/rtl/fp_cores/VX_fp_rounding.v @@ -0,0 +1,61 @@ + +`include "VX_define.vh" + +module VX_fp_rounding #( + parameter DAT_WIDTH = 2 // Width of the abolute value, without sign bit +) ( + // inputs + input wire [DAT_WIDTH-1:0] abs_value_i, // absolute value without sign + input wire sign_i, + // rounding information + input wire [1:0] round_sticky_bits_i, // round and sticky bits {RS} + input wire [2:0] rnd_mode_i, + input wire effective_subtraction_i, // sign of inputs affects rounding of zeroes + // outputs + output wire [DAT_WIDTH-1:0] abs_rounded_o, // absolute value without sign + output wire sign_o, + output wire exact_zero_o // output is an exact zero +); + + reg round_up; // Rounding decision + + // Take the rounding decision according to RISC-V spec + // RoundMode | Mnemonic | Meaning + // :--------:|:--------:|:------- + // 000 | RNE | Round to Nearest, ties to Even + // 001 | RTZ | Round towards Zero + // 010 | RDN | Round Down (towards -\infty) + // 011 | RUP | Round Up (towards \infty) + // 100 | RMM | Round to Nearest, ties to Max Magnitude + // others | | *invalid* + + always @(*) begin + case (rnd_mode_i) + `FRM_RNE: // Decide accoring to round/sticky bits + case (round_sticky_bits_i) + 2'b00, + 2'b01: round_up = 1'b0; // < ulp/2 away, round down + 2'b10: round_up = abs_value_i[0]; // = ulp/2 away, round towards even result + 2'b11: round_up = 1'b1; // > ulp/2 away, round up + default: round_up = 1'bx; + endcase + `FRM_RTZ: round_up = 1'b0; // always round down + `FRM_RDN: round_up = (| round_sticky_bits_i) & sign_i; // to 0 if +, away if - + `FRM_RUP: round_up = (| round_sticky_bits_i) & ~sign_i; // to 0 if -, away if + + `FRM_RMM: round_up = round_sticky_bits_i[1]; // round down if < ulp/2 away, else up + default: round_up = 1'bx; // propagate x + endcase + end + + // Perform the rounding, exponent change and overflow to inf happens automagically + assign abs_rounded_o = abs_value_i + DAT_WIDTH'(round_up); + + // True zero result is a zero result without dirty round/sticky bits + assign exact_zero_o = (abs_value_i == 0) && (round_sticky_bits_i == 0); + + // In case of effective subtraction (thus signs of addition operands must have differed) and a + // true zero result, the result sign is '-' in case of RDN and '+' for other modes. + assign sign_o = (exact_zero_o && effective_subtraction_i) ? (rnd_mode_i == `FRM_RDN) + : sign_i; + +endmodule \ No newline at end of file diff --git a/hw/rtl/fp_cores/VX_fp_sqrt.v b/hw/rtl/fp_cores/VX_fp_sqrt.v index 7af2a78f..07dbd042 100644 --- a/hw/rtl/fp_cores/VX_fp_sqrt.v +++ b/hw/rtl/fp_cores/VX_fp_sqrt.v @@ -15,9 +15,14 @@ module VX_fp_sqrt #( input wire valid_in, input wire [TAGW-1:0] tag_in, + + input wire [`FRM_BITS-1:0] frm, input wire [LANES-1:0][31:0] dataa, - output wire [LANES-1:0][31:0] result, + output wire [LANES-1:0][31:0] result, + + output wire has_fflags, + output fflags_t [LANES-1:0] fflags, output wire [TAGW-1:0] tag_out, @@ -42,7 +47,7 @@ module VX_fp_sqrt #( fsqrt_h = dpi_register(); end always @(posedge clk) begin - dpi_fsqrt (fsqrt_h, enable, dataa[i], result[i]); + dpi_fsqrt (fsqrt_h, enable, dataa[i], `LATENCY_FSQRT, result[i]); end `endif end @@ -61,4 +66,8 @@ module VX_fp_sqrt #( assign ready_in = enable; + `UNUSED_VAR (frm) + assign has_fflags = 0; + assign fflags = 0; + endmodule diff --git a/hw/rtl/fp_cores/VX_fp_type.v b/hw/rtl/fp_cores/VX_fp_type.v index 850936a8..706afaac 100644 --- a/hw/rtl/fp_cores/VX_fp_type.v +++ b/hw/rtl/fp_cores/VX_fp_type.v @@ -3,25 +3,25 @@ module VX_fp_type ( // inputs - input [7:0] exponent, - input [22:0] mantissa, + input [7:0] exp_i, + input [22:0] man_i, // outputs - output fp_type_t o_type + output fp_type_t type_o ); - wire is_normal = (exponent != 8'd0) && (exponent != 8'hff); - wire is_zero = (exponent == 8'd0) && (mantissa == 23'd0); - wire is_subnormal = (exponent == 8'd0) && !is_zero; - wire is_inf = (exponent == 8'hff) && (mantissa == 23'd0); - wire is_nan = (exponent == 8'hff) && (mantissa != 23'd0); - wire is_signaling = is_nan && (mantissa[22] == 1'b0); + wire is_normal = (exp_i != 8'd0) && (exp_i != 8'hff); + wire is_zero = (exp_i == 8'd0) && (man_i == 23'd0); + wire is_subnormal = (exp_i == 8'd0) && !is_zero; + wire is_inf = (exp_i == 8'hff) && (man_i == 23'd0); + wire is_nan = (exp_i == 8'hff) && (man_i != 23'd0); + wire is_signaling = is_nan && (man_i[22] == 1'b0); wire is_quiet = is_nan && !is_signaling; - assign o_type.is_normal = is_normal; - assign o_type.is_zero = is_zero; - assign o_type.is_subnormal = is_subnormal; - assign o_type.is_inf = is_inf; - assign o_type.is_nan = is_nan; - assign o_type.is_signaling = is_signaling; - assign o_type.is_quiet = is_quiet; + assign type_o.is_normal = is_normal; + assign type_o.is_zero = is_zero; + assign type_o.is_subnormal = is_subnormal; + assign type_o.is_inf = is_inf; + assign type_o.is_nan = is_nan; + assign type_o.is_signaling = is_signaling; + assign type_o.is_quiet = is_quiet; endmodule \ No newline at end of file diff --git a/hw/rtl/fp_cores/VX_fpnew.v b/hw/rtl/fp_cores/VX_fpnew.v index 8fa35215..a04f431d 100644 --- a/hw/rtl/fp_cores/VX_fpnew.v +++ b/hw/rtl/fp_cores/VX_fpnew.v @@ -55,9 +55,9 @@ module VX_fpnew }; localparam fpnew_pkg::fpu_implementation_t FPU_IMPLEMENTATION = '{ - PipeRegs:'{'{`LATENCY_FADDMUL, 0, 0, 0, 0}, // ADDMUL + PipeRegs:'{'{`LATENCY_FMA, 0, 0, 0, 0}, // ADDMUL '{default: `LATENCY_FDIVSQRT}, // DIVSQRT - '{default: `LATENCY_FNONCOMP}, // NONCOMP + '{default: `LATENCY_FNCOMP}, // NONCOMP '{default: `LATENCY_FCONV}}, // CONV UnitTypes:'{'{default: UNIT_FMULADD}, // ADDMUL '{default: UNIT_FDIVSQRT}, // DIVSQRT diff --git a/hw/rtl/fp_cores/altera/arria10/acl_ftoi.sv b/hw/rtl/fp_cores/altera/arria10/acl_ftoi.sv deleted file mode 100644 index 46140a3e..00000000 --- a/hw/rtl/fp_cores/altera/arria10/acl_ftoi.sv +++ /dev/null @@ -1,508 +0,0 @@ -// ------------------------------------------------------------------------- -// High Level Design Compiler for Intel(R) FPGAs Version 17.1 (Release Build #273) -// Quartus Prime development tool and MATLAB/Simulink Interface -// -// Legal Notice: Copyright 2017 Intel Corporation. All rights reserved. -// Your use of Intel Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly -// subject to the terms and conditions of the Intel FPGA Software License -// Agreement, Intel MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for -// the sole purpose of programming logic devices manufactured by Intel -// and sold by Intel or its authorized distributors. Please refer to the -// applicable agreement for further details. -// --------------------------------------------------------------------------- - -// SystemVerilog created from acl_ftoi -// SystemVerilog created on Sun Dec 27 09:47:21 2020 - - -(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) -module acl_ftoi ( - input wire [31:0] a, - input wire [0:0] en, - output wire [31:0] q, - input wire clk, - input wire areset - ); - - wire [0:0] GND_q; - wire [7:0] cstAllOWE_uid6_fpToFxPTest_q; - wire [22:0] cstZeroWF_uid7_fpToFxPTest_q; - wire [7:0] cstAllZWE_uid8_fpToFxPTest_q; - wire [7:0] exp_x_uid9_fpToFxPTest_b; - wire [22:0] frac_x_uid10_fpToFxPTest_b; - wire [0:0] excZ_x_uid11_fpToFxPTest_qi; - reg [0:0] excZ_x_uid11_fpToFxPTest_q; - wire [0:0] expXIsMax_uid12_fpToFxPTest_qi; - reg [0:0] expXIsMax_uid12_fpToFxPTest_q; - wire [0:0] fracXIsZero_uid13_fpToFxPTest_qi; - reg [0:0] fracXIsZero_uid13_fpToFxPTest_q; - wire [0:0] fracXIsNotZero_uid14_fpToFxPTest_q; - wire [0:0] excI_x_uid15_fpToFxPTest_q; - wire [0:0] excN_x_uid16_fpToFxPTest_q; - wire [0:0] invExcXZ_uid22_fpToFxPTest_q; - wire [23:0] oFracX_uid23_fpToFxPTest_q; - wire [0:0] signX_uid25_fpToFxPTest_b; - wire [8:0] ovfExpVal_uid26_fpToFxPTest_q; - wire [10:0] ovfExpRange_uid27_fpToFxPTest_a; - wire [10:0] ovfExpRange_uid27_fpToFxPTest_b; - logic [10:0] ovfExpRange_uid27_fpToFxPTest_o; - wire [0:0] ovfExpRange_uid27_fpToFxPTest_n; - wire [7:0] udfExpVal_uid28_fpToFxPTest_q; - wire [10:0] udf_uid29_fpToFxPTest_a; - wire [10:0] udf_uid29_fpToFxPTest_b; - logic [10:0] udf_uid29_fpToFxPTest_o; - wire [0:0] udf_uid29_fpToFxPTest_n; - wire [8:0] ovfExpVal_uid30_fpToFxPTest_q; - wire [10:0] shiftValE_uid31_fpToFxPTest_a; - wire [10:0] shiftValE_uid31_fpToFxPTest_b; - logic [10:0] shiftValE_uid31_fpToFxPTest_o; - wire [9:0] shiftValE_uid31_fpToFxPTest_q; - wire [5:0] shiftValRaw_uid32_fpToFxPTest_in; - wire [5:0] shiftValRaw_uid32_fpToFxPTest_b; - wire [5:0] maxShiftCst_uid33_fpToFxPTest_q; - wire [11:0] shiftOutOfRange_uid34_fpToFxPTest_a; - wire [11:0] shiftOutOfRange_uid34_fpToFxPTest_b; - logic [11:0] shiftOutOfRange_uid34_fpToFxPTest_o; - wire [0:0] shiftOutOfRange_uid34_fpToFxPTest_n; - wire [0:0] shiftVal_uid35_fpToFxPTest_s; - reg [5:0] shiftVal_uid35_fpToFxPTest_q; - wire [31:0] shifterIn_uid37_fpToFxPTest_q; - wire [31:0] maxPosValueS_uid39_fpToFxPTest_q; - wire [31:0] maxNegValueS_uid40_fpToFxPTest_q; - wire [32:0] zRightShiferNoStickyOut_uid41_fpToFxPTest_q; - wire [32:0] xXorSignE_uid42_fpToFxPTest_b; - wire [32:0] xXorSignE_uid42_fpToFxPTest_q; - wire [2:0] d0_uid43_fpToFxPTest_q; - wire [33:0] sPostRndFull_uid44_fpToFxPTest_a; - wire [33:0] sPostRndFull_uid44_fpToFxPTest_b; - logic [33:0] sPostRndFull_uid44_fpToFxPTest_o; - wire [33:0] sPostRndFull_uid44_fpToFxPTest_q; - wire [32:0] sPostRnd_uid45_fpToFxPTest_in; - wire [31:0] sPostRnd_uid45_fpToFxPTest_b; - wire [34:0] sPostRnd_uid46_fpToFxPTest_in; - wire [33:0] sPostRnd_uid46_fpToFxPTest_b; - wire [35:0] rndOvfPos_uid47_fpToFxPTest_a; - wire [35:0] rndOvfPos_uid47_fpToFxPTest_b; - logic [35:0] rndOvfPos_uid47_fpToFxPTest_o; - wire [0:0] rndOvfPos_uid47_fpToFxPTest_c; - wire [0:0] ovfPostRnd_uid48_fpToFxPTest_q; - wire [2:0] muxSelConc_uid49_fpToFxPTest_q; - reg [1:0] muxSel_uid50_fpToFxPTest_q; - wire [31:0] maxNegValueU_uid51_fpToFxPTest_q; - wire [1:0] finalOut_uid52_fpToFxPTest_s; - reg [31:0] finalOut_uid52_fpToFxPTest_q; - wire [15:0] rightShiftStage0Idx1Rng16_uid56_rightShiferNoStickyOut_uid38_fpToFxPTest_b; - wire [15:0] rightShiftStage0Idx1Pad16_uid57_rightShiferNoStickyOut_uid38_fpToFxPTest_q; - wire [31:0] rightShiftStage0Idx1_uid58_rightShiferNoStickyOut_uid38_fpToFxPTest_q; - wire [1:0] rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_s; - reg [31:0] rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q; - wire [27:0] rightShiftStage1Idx1Rng4_uid63_rightShiferNoStickyOut_uid38_fpToFxPTest_b; - wire [3:0] rightShiftStage1Idx1Pad4_uid64_rightShiferNoStickyOut_uid38_fpToFxPTest_q; - wire [31:0] rightShiftStage1Idx1_uid65_rightShiferNoStickyOut_uid38_fpToFxPTest_q; - wire [23:0] rightShiftStage1Idx2Rng8_uid66_rightShiferNoStickyOut_uid38_fpToFxPTest_b; - wire [31:0] rightShiftStage1Idx2_uid68_rightShiferNoStickyOut_uid38_fpToFxPTest_q; - wire [19:0] rightShiftStage1Idx3Rng12_uid69_rightShiferNoStickyOut_uid38_fpToFxPTest_b; - wire [11:0] rightShiftStage1Idx3Pad12_uid70_rightShiferNoStickyOut_uid38_fpToFxPTest_q; - wire [31:0] rightShiftStage1Idx3_uid71_rightShiferNoStickyOut_uid38_fpToFxPTest_q; - wire [1:0] rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_s; - reg [31:0] rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_q; - wire [30:0] rightShiftStage2Idx1Rng1_uid74_rightShiferNoStickyOut_uid38_fpToFxPTest_b; - wire [31:0] rightShiftStage2Idx1_uid76_rightShiferNoStickyOut_uid38_fpToFxPTest_q; - wire [29:0] rightShiftStage2Idx2Rng2_uid77_rightShiferNoStickyOut_uid38_fpToFxPTest_b; - wire [1:0] rightShiftStage2Idx2Pad2_uid78_rightShiferNoStickyOut_uid38_fpToFxPTest_q; - wire [31:0] rightShiftStage2Idx2_uid79_rightShiferNoStickyOut_uid38_fpToFxPTest_q; - wire [28:0] rightShiftStage2Idx3Rng3_uid80_rightShiferNoStickyOut_uid38_fpToFxPTest_b; - wire [2:0] rightShiftStage2Idx3Pad3_uid81_rightShiferNoStickyOut_uid38_fpToFxPTest_q; - wire [31:0] rightShiftStage2Idx3_uid82_rightShiferNoStickyOut_uid38_fpToFxPTest_q; - wire [1:0] rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_s; - reg [31:0] rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_q; - wire [1:0] rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select_b; - wire [1:0] rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select_c; - wire [1:0] rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select_d; - reg [31:0] redist0_sPostRnd_uid45_fpToFxPTest_b_1_q; - reg [5:0] redist1_shiftValRaw_uid32_fpToFxPTest_b_1_q; - reg [0:0] redist2_udf_uid29_fpToFxPTest_n_3_q; - reg [0:0] redist3_ovfExpRange_uid27_fpToFxPTest_n_3_q; - reg [0:0] redist4_signX_uid25_fpToFxPTest_b_2_q; - reg [0:0] redist5_signX_uid25_fpToFxPTest_b_3_q; - reg [0:0] redist6_fracXIsZero_uid13_fpToFxPTest_q_2_q; - reg [0:0] redist7_expXIsMax_uid12_fpToFxPTest_q_3_q; - reg [22:0] redist8_frac_x_uid10_fpToFxPTest_b_1_q; - - - // maxNegValueU_uid51_fpToFxPTest(CONSTANT,50) - assign maxNegValueU_uid51_fpToFxPTest_q = 32'b00000000000000000000000000000000; - - // maxNegValueS_uid40_fpToFxPTest(CONSTANT,39) - assign maxNegValueS_uid40_fpToFxPTest_q = 32'b10000000000000000000000000000000; - - // maxPosValueS_uid39_fpToFxPTest(CONSTANT,38) - assign maxPosValueS_uid39_fpToFxPTest_q = 32'b01111111111111111111111111111111; - - // d0_uid43_fpToFxPTest(CONSTANT,42) - assign d0_uid43_fpToFxPTest_q = 3'b001; - - // signX_uid25_fpToFxPTest(BITSELECT,24)@0 - assign signX_uid25_fpToFxPTest_b = a[31:31]; - - // redist4_signX_uid25_fpToFxPTest_b_2(DELAY,90) - dspba_delay_ver #( .width(1), .depth(2), .reset_kind("ASYNC") ) - redist4_signX_uid25_fpToFxPTest_b_2 ( .xin(signX_uid25_fpToFxPTest_b), .xout(redist4_signX_uid25_fpToFxPTest_b_2_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // GND(CONSTANT,0) - assign GND_q = 1'b0; - - // rightShiftStage2Idx3Pad3_uid81_rightShiferNoStickyOut_uid38_fpToFxPTest(CONSTANT,80) - assign rightShiftStage2Idx3Pad3_uid81_rightShiferNoStickyOut_uid38_fpToFxPTest_q = 3'b000; - - // rightShiftStage2Idx3Rng3_uid80_rightShiferNoStickyOut_uid38_fpToFxPTest(BITSELECT,79)@1 - assign rightShiftStage2Idx3Rng3_uid80_rightShiferNoStickyOut_uid38_fpToFxPTest_b = rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_q[31:3]; - - // rightShiftStage2Idx3_uid82_rightShiferNoStickyOut_uid38_fpToFxPTest(BITJOIN,81)@1 - assign rightShiftStage2Idx3_uid82_rightShiferNoStickyOut_uid38_fpToFxPTest_q = {rightShiftStage2Idx3Pad3_uid81_rightShiferNoStickyOut_uid38_fpToFxPTest_q, rightShiftStage2Idx3Rng3_uid80_rightShiferNoStickyOut_uid38_fpToFxPTest_b}; - - // rightShiftStage2Idx2Pad2_uid78_rightShiferNoStickyOut_uid38_fpToFxPTest(CONSTANT,77) - assign rightShiftStage2Idx2Pad2_uid78_rightShiferNoStickyOut_uid38_fpToFxPTest_q = 2'b00; - - // rightShiftStage2Idx2Rng2_uid77_rightShiferNoStickyOut_uid38_fpToFxPTest(BITSELECT,76)@1 - assign rightShiftStage2Idx2Rng2_uid77_rightShiferNoStickyOut_uid38_fpToFxPTest_b = rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_q[31:2]; - - // rightShiftStage2Idx2_uid79_rightShiferNoStickyOut_uid38_fpToFxPTest(BITJOIN,78)@1 - assign rightShiftStage2Idx2_uid79_rightShiferNoStickyOut_uid38_fpToFxPTest_q = {rightShiftStage2Idx2Pad2_uid78_rightShiferNoStickyOut_uid38_fpToFxPTest_q, rightShiftStage2Idx2Rng2_uid77_rightShiferNoStickyOut_uid38_fpToFxPTest_b}; - - // rightShiftStage2Idx1Rng1_uid74_rightShiferNoStickyOut_uid38_fpToFxPTest(BITSELECT,73)@1 - assign rightShiftStage2Idx1Rng1_uid74_rightShiferNoStickyOut_uid38_fpToFxPTest_b = rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_q[31:1]; - - // rightShiftStage2Idx1_uid76_rightShiferNoStickyOut_uid38_fpToFxPTest(BITJOIN,75)@1 - assign rightShiftStage2Idx1_uid76_rightShiferNoStickyOut_uid38_fpToFxPTest_q = {GND_q, rightShiftStage2Idx1Rng1_uid74_rightShiferNoStickyOut_uid38_fpToFxPTest_b}; - - // rightShiftStage1Idx3Pad12_uid70_rightShiferNoStickyOut_uid38_fpToFxPTest(CONSTANT,69) - assign rightShiftStage1Idx3Pad12_uid70_rightShiferNoStickyOut_uid38_fpToFxPTest_q = 12'b000000000000; - - // rightShiftStage1Idx3Rng12_uid69_rightShiferNoStickyOut_uid38_fpToFxPTest(BITSELECT,68)@1 - assign rightShiftStage1Idx3Rng12_uid69_rightShiferNoStickyOut_uid38_fpToFxPTest_b = rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q[31:12]; - - // rightShiftStage1Idx3_uid71_rightShiferNoStickyOut_uid38_fpToFxPTest(BITJOIN,70)@1 - assign rightShiftStage1Idx3_uid71_rightShiferNoStickyOut_uid38_fpToFxPTest_q = {rightShiftStage1Idx3Pad12_uid70_rightShiferNoStickyOut_uid38_fpToFxPTest_q, rightShiftStage1Idx3Rng12_uid69_rightShiferNoStickyOut_uid38_fpToFxPTest_b}; - - // cstAllZWE_uid8_fpToFxPTest(CONSTANT,7) - assign cstAllZWE_uid8_fpToFxPTest_q = 8'b00000000; - - // rightShiftStage1Idx2Rng8_uid66_rightShiferNoStickyOut_uid38_fpToFxPTest(BITSELECT,65)@1 - assign rightShiftStage1Idx2Rng8_uid66_rightShiferNoStickyOut_uid38_fpToFxPTest_b = rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q[31:8]; - - // rightShiftStage1Idx2_uid68_rightShiferNoStickyOut_uid38_fpToFxPTest(BITJOIN,67)@1 - assign rightShiftStage1Idx2_uid68_rightShiferNoStickyOut_uid38_fpToFxPTest_q = {cstAllZWE_uid8_fpToFxPTest_q, rightShiftStage1Idx2Rng8_uid66_rightShiferNoStickyOut_uid38_fpToFxPTest_b}; - - // rightShiftStage1Idx1Pad4_uid64_rightShiferNoStickyOut_uid38_fpToFxPTest(CONSTANT,63) - assign rightShiftStage1Idx1Pad4_uid64_rightShiferNoStickyOut_uid38_fpToFxPTest_q = 4'b0000; - - // rightShiftStage1Idx1Rng4_uid63_rightShiferNoStickyOut_uid38_fpToFxPTest(BITSELECT,62)@1 - assign rightShiftStage1Idx1Rng4_uid63_rightShiferNoStickyOut_uid38_fpToFxPTest_b = rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q[31:4]; - - // rightShiftStage1Idx1_uid65_rightShiferNoStickyOut_uid38_fpToFxPTest(BITJOIN,64)@1 - assign rightShiftStage1Idx1_uid65_rightShiferNoStickyOut_uid38_fpToFxPTest_q = {rightShiftStage1Idx1Pad4_uid64_rightShiferNoStickyOut_uid38_fpToFxPTest_q, rightShiftStage1Idx1Rng4_uid63_rightShiferNoStickyOut_uid38_fpToFxPTest_b}; - - // rightShiftStage0Idx1Pad16_uid57_rightShiferNoStickyOut_uid38_fpToFxPTest(CONSTANT,56) - assign rightShiftStage0Idx1Pad16_uid57_rightShiferNoStickyOut_uid38_fpToFxPTest_q = 16'b0000000000000000; - - // rightShiftStage0Idx1Rng16_uid56_rightShiferNoStickyOut_uid38_fpToFxPTest(BITSELECT,55)@1 - assign rightShiftStage0Idx1Rng16_uid56_rightShiferNoStickyOut_uid38_fpToFxPTest_b = shifterIn_uid37_fpToFxPTest_q[31:16]; - - // rightShiftStage0Idx1_uid58_rightShiferNoStickyOut_uid38_fpToFxPTest(BITJOIN,57)@1 - assign rightShiftStage0Idx1_uid58_rightShiferNoStickyOut_uid38_fpToFxPTest_q = {rightShiftStage0Idx1Pad16_uid57_rightShiferNoStickyOut_uid38_fpToFxPTest_q, rightShiftStage0Idx1Rng16_uid56_rightShiferNoStickyOut_uid38_fpToFxPTest_b}; - - // exp_x_uid9_fpToFxPTest(BITSELECT,8)@0 - assign exp_x_uid9_fpToFxPTest_b = a[30:23]; - - // excZ_x_uid11_fpToFxPTest(LOGICAL,10)@0 + 1 - assign excZ_x_uid11_fpToFxPTest_qi = exp_x_uid9_fpToFxPTest_b == cstAllZWE_uid8_fpToFxPTest_q ? 1'b1 : 1'b0; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - excZ_x_uid11_fpToFxPTest_delay ( .xin(excZ_x_uid11_fpToFxPTest_qi), .xout(excZ_x_uid11_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // invExcXZ_uid22_fpToFxPTest(LOGICAL,21)@1 - assign invExcXZ_uid22_fpToFxPTest_q = ~ (excZ_x_uid11_fpToFxPTest_q); - - // frac_x_uid10_fpToFxPTest(BITSELECT,9)@0 - assign frac_x_uid10_fpToFxPTest_b = a[22:0]; - - // redist8_frac_x_uid10_fpToFxPTest_b_1(DELAY,94) - dspba_delay_ver #( .width(23), .depth(1), .reset_kind("ASYNC") ) - redist8_frac_x_uid10_fpToFxPTest_b_1 ( .xin(frac_x_uid10_fpToFxPTest_b), .xout(redist8_frac_x_uid10_fpToFxPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // oFracX_uid23_fpToFxPTest(BITJOIN,22)@1 - assign oFracX_uid23_fpToFxPTest_q = {invExcXZ_uid22_fpToFxPTest_q, redist8_frac_x_uid10_fpToFxPTest_b_1_q}; - - // shifterIn_uid37_fpToFxPTest(BITJOIN,36)@1 - assign shifterIn_uid37_fpToFxPTest_q = {oFracX_uid23_fpToFxPTest_q, cstAllZWE_uid8_fpToFxPTest_q}; - - // rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest(MUX,61)@1 - assign rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_s = rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select_b; - always @(rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_s or en or shifterIn_uid37_fpToFxPTest_q or rightShiftStage0Idx1_uid58_rightShiferNoStickyOut_uid38_fpToFxPTest_q or maxNegValueU_uid51_fpToFxPTest_q) - begin - unique case (rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_s) - 2'b00 : rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q = shifterIn_uid37_fpToFxPTest_q; - 2'b01 : rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q = rightShiftStage0Idx1_uid58_rightShiferNoStickyOut_uid38_fpToFxPTest_q; - 2'b10 : rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q = maxNegValueU_uid51_fpToFxPTest_q; - 2'b11 : rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q = maxNegValueU_uid51_fpToFxPTest_q; - default : rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q = 32'b0; - endcase - end - - // rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest(MUX,72)@1 - assign rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_s = rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select_c; - always @(rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_s or en or rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q or rightShiftStage1Idx1_uid65_rightShiferNoStickyOut_uid38_fpToFxPTest_q or rightShiftStage1Idx2_uid68_rightShiferNoStickyOut_uid38_fpToFxPTest_q or rightShiftStage1Idx3_uid71_rightShiferNoStickyOut_uid38_fpToFxPTest_q) - begin - unique case (rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_s) - 2'b00 : rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_q = rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q; - 2'b01 : rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_q = rightShiftStage1Idx1_uid65_rightShiferNoStickyOut_uid38_fpToFxPTest_q; - 2'b10 : rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_q = rightShiftStage1Idx2_uid68_rightShiferNoStickyOut_uid38_fpToFxPTest_q; - 2'b11 : rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_q = rightShiftStage1Idx3_uid71_rightShiferNoStickyOut_uid38_fpToFxPTest_q; - default : rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_q = 32'b0; - endcase - end - - // maxShiftCst_uid33_fpToFxPTest(CONSTANT,32) - assign maxShiftCst_uid33_fpToFxPTest_q = 6'b100000; - - // ovfExpVal_uid30_fpToFxPTest(CONSTANT,29) - assign ovfExpVal_uid30_fpToFxPTest_q = 9'b010011101; - - // shiftValE_uid31_fpToFxPTest(SUB,30)@0 - assign shiftValE_uid31_fpToFxPTest_a = {{2{ovfExpVal_uid30_fpToFxPTest_q[8]}}, ovfExpVal_uid30_fpToFxPTest_q}; - assign shiftValE_uid31_fpToFxPTest_b = {3'b000, exp_x_uid9_fpToFxPTest_b}; - assign shiftValE_uid31_fpToFxPTest_o = $signed(shiftValE_uid31_fpToFxPTest_a) - $signed(shiftValE_uid31_fpToFxPTest_b); - assign shiftValE_uid31_fpToFxPTest_q = shiftValE_uid31_fpToFxPTest_o[9:0]; - - // shiftValRaw_uid32_fpToFxPTest(BITSELECT,31)@0 - assign shiftValRaw_uid32_fpToFxPTest_in = shiftValE_uid31_fpToFxPTest_q[5:0]; - assign shiftValRaw_uid32_fpToFxPTest_b = shiftValRaw_uid32_fpToFxPTest_in[5:0]; - - // redist1_shiftValRaw_uid32_fpToFxPTest_b_1(DELAY,87) - dspba_delay_ver #( .width(6), .depth(1), .reset_kind("ASYNC") ) - redist1_shiftValRaw_uid32_fpToFxPTest_b_1 ( .xin(shiftValRaw_uid32_fpToFxPTest_b), .xout(redist1_shiftValRaw_uid32_fpToFxPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // shiftOutOfRange_uid34_fpToFxPTest(COMPARE,33)@0 + 1 - assign shiftOutOfRange_uid34_fpToFxPTest_a = {{2{shiftValE_uid31_fpToFxPTest_q[9]}}, shiftValE_uid31_fpToFxPTest_q}; - assign shiftOutOfRange_uid34_fpToFxPTest_b = {6'b000000, maxShiftCst_uid33_fpToFxPTest_q}; - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - shiftOutOfRange_uid34_fpToFxPTest_o <= 12'b0; - end - else if (en == 1'b1) - begin - shiftOutOfRange_uid34_fpToFxPTest_o <= $signed(shiftOutOfRange_uid34_fpToFxPTest_a) - $signed(shiftOutOfRange_uid34_fpToFxPTest_b); - end - end - assign shiftOutOfRange_uid34_fpToFxPTest_n[0] = ~ (shiftOutOfRange_uid34_fpToFxPTest_o[11]); - - // shiftVal_uid35_fpToFxPTest(MUX,34)@1 - assign shiftVal_uid35_fpToFxPTest_s = shiftOutOfRange_uid34_fpToFxPTest_n; - always @(shiftVal_uid35_fpToFxPTest_s or en or redist1_shiftValRaw_uid32_fpToFxPTest_b_1_q or maxShiftCst_uid33_fpToFxPTest_q) - begin - unique case (shiftVal_uid35_fpToFxPTest_s) - 1'b0 : shiftVal_uid35_fpToFxPTest_q = redist1_shiftValRaw_uid32_fpToFxPTest_b_1_q; - 1'b1 : shiftVal_uid35_fpToFxPTest_q = maxShiftCst_uid33_fpToFxPTest_q; - default : shiftVal_uid35_fpToFxPTest_q = 6'b0; - endcase - end - - // rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select(BITSELECT,85)@1 - assign rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select_b = shiftVal_uid35_fpToFxPTest_q[5:4]; - assign rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select_c = shiftVal_uid35_fpToFxPTest_q[3:2]; - assign rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select_d = shiftVal_uid35_fpToFxPTest_q[1:0]; - - // rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest(MUX,83)@1 + 1 - assign rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_s = rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select_d; - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_q <= 32'b0; - end - else if (en == 1'b1) - begin - unique case (rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_s) - 2'b00 : rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_q <= rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_q; - 2'b01 : rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_q <= rightShiftStage2Idx1_uid76_rightShiferNoStickyOut_uid38_fpToFxPTest_q; - 2'b10 : rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_q <= rightShiftStage2Idx2_uid79_rightShiferNoStickyOut_uid38_fpToFxPTest_q; - 2'b11 : rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_q <= rightShiftStage2Idx3_uid82_rightShiferNoStickyOut_uid38_fpToFxPTest_q; - default : rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_q <= 32'b0; - endcase - end - end - - // zRightShiferNoStickyOut_uid41_fpToFxPTest(BITJOIN,40)@2 - assign zRightShiferNoStickyOut_uid41_fpToFxPTest_q = {GND_q, rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_q}; - - // xXorSignE_uid42_fpToFxPTest(LOGICAL,41)@2 - assign xXorSignE_uid42_fpToFxPTest_b = {{32{redist4_signX_uid25_fpToFxPTest_b_2_q[0]}}, redist4_signX_uid25_fpToFxPTest_b_2_q}; - assign xXorSignE_uid42_fpToFxPTest_q = zRightShiferNoStickyOut_uid41_fpToFxPTest_q ^ xXorSignE_uid42_fpToFxPTest_b; - - // sPostRndFull_uid44_fpToFxPTest(ADD,43)@2 - assign sPostRndFull_uid44_fpToFxPTest_a = {{1{xXorSignE_uid42_fpToFxPTest_q[32]}}, xXorSignE_uid42_fpToFxPTest_q}; - assign sPostRndFull_uid44_fpToFxPTest_b = {{31{d0_uid43_fpToFxPTest_q[2]}}, d0_uid43_fpToFxPTest_q}; - assign sPostRndFull_uid44_fpToFxPTest_o = $signed(sPostRndFull_uid44_fpToFxPTest_a) + $signed(sPostRndFull_uid44_fpToFxPTest_b); - assign sPostRndFull_uid44_fpToFxPTest_q = sPostRndFull_uid44_fpToFxPTest_o[33:0]; - - // sPostRnd_uid45_fpToFxPTest(BITSELECT,44)@2 - assign sPostRnd_uid45_fpToFxPTest_in = sPostRndFull_uid44_fpToFxPTest_q[32:0]; - assign sPostRnd_uid45_fpToFxPTest_b = sPostRnd_uid45_fpToFxPTest_in[32:1]; - - // redist0_sPostRnd_uid45_fpToFxPTest_b_1(DELAY,86) - dspba_delay_ver #( .width(32), .depth(1), .reset_kind("ASYNC") ) - redist0_sPostRnd_uid45_fpToFxPTest_b_1 ( .xin(sPostRnd_uid45_fpToFxPTest_b), .xout(redist0_sPostRnd_uid45_fpToFxPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist5_signX_uid25_fpToFxPTest_b_3(DELAY,91) - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - redist5_signX_uid25_fpToFxPTest_b_3 ( .xin(redist4_signX_uid25_fpToFxPTest_b_2_q), .xout(redist5_signX_uid25_fpToFxPTest_b_3_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // udfExpVal_uid28_fpToFxPTest(CONSTANT,27) - assign udfExpVal_uid28_fpToFxPTest_q = 8'b01111101; - - // udf_uid29_fpToFxPTest(COMPARE,28)@0 + 1 - assign udf_uid29_fpToFxPTest_a = {{3{udfExpVal_uid28_fpToFxPTest_q[7]}}, udfExpVal_uid28_fpToFxPTest_q}; - assign udf_uid29_fpToFxPTest_b = {3'b000, exp_x_uid9_fpToFxPTest_b}; - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - udf_uid29_fpToFxPTest_o <= 11'b0; - end - else if (en == 1'b1) - begin - udf_uid29_fpToFxPTest_o <= $signed(udf_uid29_fpToFxPTest_a) - $signed(udf_uid29_fpToFxPTest_b); - end - end - assign udf_uid29_fpToFxPTest_n[0] = ~ (udf_uid29_fpToFxPTest_o[10]); - - // redist2_udf_uid29_fpToFxPTest_n_3(DELAY,88) - dspba_delay_ver #( .width(1), .depth(2), .reset_kind("ASYNC") ) - redist2_udf_uid29_fpToFxPTest_n_3 ( .xin(udf_uid29_fpToFxPTest_n), .xout(redist2_udf_uid29_fpToFxPTest_n_3_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // sPostRnd_uid46_fpToFxPTest(BITSELECT,45)@2 - assign sPostRnd_uid46_fpToFxPTest_in = {{1{sPostRndFull_uid44_fpToFxPTest_q[33]}}, sPostRndFull_uid44_fpToFxPTest_q}; - assign sPostRnd_uid46_fpToFxPTest_b = sPostRnd_uid46_fpToFxPTest_in[34:1]; - - // rndOvfPos_uid47_fpToFxPTest(COMPARE,46)@2 + 1 - assign rndOvfPos_uid47_fpToFxPTest_a = {4'b0000, maxPosValueS_uid39_fpToFxPTest_q}; - assign rndOvfPos_uid47_fpToFxPTest_b = {{2{sPostRnd_uid46_fpToFxPTest_b[33]}}, sPostRnd_uid46_fpToFxPTest_b}; - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - rndOvfPos_uid47_fpToFxPTest_o <= 36'b0; - end - else if (en == 1'b1) - begin - rndOvfPos_uid47_fpToFxPTest_o <= $signed(rndOvfPos_uid47_fpToFxPTest_a) - $signed(rndOvfPos_uid47_fpToFxPTest_b); - end - end - assign rndOvfPos_uid47_fpToFxPTest_c[0] = rndOvfPos_uid47_fpToFxPTest_o[35]; - - // ovfExpVal_uid26_fpToFxPTest(CONSTANT,25) - assign ovfExpVal_uid26_fpToFxPTest_q = 9'b010011110; - - // ovfExpRange_uid27_fpToFxPTest(COMPARE,26)@0 + 1 - assign ovfExpRange_uid27_fpToFxPTest_a = {3'b000, exp_x_uid9_fpToFxPTest_b}; - assign ovfExpRange_uid27_fpToFxPTest_b = {{2{ovfExpVal_uid26_fpToFxPTest_q[8]}}, ovfExpVal_uid26_fpToFxPTest_q}; - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - ovfExpRange_uid27_fpToFxPTest_o <= 11'b0; - end - else if (en == 1'b1) - begin - ovfExpRange_uid27_fpToFxPTest_o <= $signed(ovfExpRange_uid27_fpToFxPTest_a) - $signed(ovfExpRange_uid27_fpToFxPTest_b); - end - end - assign ovfExpRange_uid27_fpToFxPTest_n[0] = ~ (ovfExpRange_uid27_fpToFxPTest_o[10]); - - // redist3_ovfExpRange_uid27_fpToFxPTest_n_3(DELAY,89) - dspba_delay_ver #( .width(1), .depth(2), .reset_kind("ASYNC") ) - redist3_ovfExpRange_uid27_fpToFxPTest_n_3 ( .xin(ovfExpRange_uid27_fpToFxPTest_n), .xout(redist3_ovfExpRange_uid27_fpToFxPTest_n_3_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // cstZeroWF_uid7_fpToFxPTest(CONSTANT,6) - assign cstZeroWF_uid7_fpToFxPTest_q = 23'b00000000000000000000000; - - // fracXIsZero_uid13_fpToFxPTest(LOGICAL,12)@1 + 1 - assign fracXIsZero_uid13_fpToFxPTest_qi = cstZeroWF_uid7_fpToFxPTest_q == redist8_frac_x_uid10_fpToFxPTest_b_1_q ? 1'b1 : 1'b0; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - fracXIsZero_uid13_fpToFxPTest_delay ( .xin(fracXIsZero_uid13_fpToFxPTest_qi), .xout(fracXIsZero_uid13_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist6_fracXIsZero_uid13_fpToFxPTest_q_2(DELAY,92) - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - redist6_fracXIsZero_uid13_fpToFxPTest_q_2 ( .xin(fracXIsZero_uid13_fpToFxPTest_q), .xout(redist6_fracXIsZero_uid13_fpToFxPTest_q_2_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // cstAllOWE_uid6_fpToFxPTest(CONSTANT,5) - assign cstAllOWE_uid6_fpToFxPTest_q = 8'b11111111; - - // expXIsMax_uid12_fpToFxPTest(LOGICAL,11)@0 + 1 - assign expXIsMax_uid12_fpToFxPTest_qi = exp_x_uid9_fpToFxPTest_b == cstAllOWE_uid6_fpToFxPTest_q ? 1'b1 : 1'b0; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - expXIsMax_uid12_fpToFxPTest_delay ( .xin(expXIsMax_uid12_fpToFxPTest_qi), .xout(expXIsMax_uid12_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist7_expXIsMax_uid12_fpToFxPTest_q_3(DELAY,93) - dspba_delay_ver #( .width(1), .depth(2), .reset_kind("ASYNC") ) - redist7_expXIsMax_uid12_fpToFxPTest_q_3 ( .xin(expXIsMax_uid12_fpToFxPTest_q), .xout(redist7_expXIsMax_uid12_fpToFxPTest_q_3_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // excI_x_uid15_fpToFxPTest(LOGICAL,14)@3 - assign excI_x_uid15_fpToFxPTest_q = redist7_expXIsMax_uid12_fpToFxPTest_q_3_q & redist6_fracXIsZero_uid13_fpToFxPTest_q_2_q; - - // fracXIsNotZero_uid14_fpToFxPTest(LOGICAL,13)@3 - assign fracXIsNotZero_uid14_fpToFxPTest_q = ~ (redist6_fracXIsZero_uid13_fpToFxPTest_q_2_q); - - // excN_x_uid16_fpToFxPTest(LOGICAL,15)@3 - assign excN_x_uid16_fpToFxPTest_q = redist7_expXIsMax_uid12_fpToFxPTest_q_3_q & fracXIsNotZero_uid14_fpToFxPTest_q; - - // ovfPostRnd_uid48_fpToFxPTest(LOGICAL,47)@3 - assign ovfPostRnd_uid48_fpToFxPTest_q = excN_x_uid16_fpToFxPTest_q | excI_x_uid15_fpToFxPTest_q | redist3_ovfExpRange_uid27_fpToFxPTest_n_3_q | rndOvfPos_uid47_fpToFxPTest_c; - - // muxSelConc_uid49_fpToFxPTest(BITJOIN,48)@3 - assign muxSelConc_uid49_fpToFxPTest_q = {redist5_signX_uid25_fpToFxPTest_b_3_q, redist2_udf_uid29_fpToFxPTest_n_3_q, ovfPostRnd_uid48_fpToFxPTest_q}; - - // muxSel_uid50_fpToFxPTest(LOOKUP,49)@3 - always @(muxSelConc_uid49_fpToFxPTest_q) - begin - // Begin reserved scope level - unique case (muxSelConc_uid49_fpToFxPTest_q) - 3'b000 : muxSel_uid50_fpToFxPTest_q = 2'b00; - 3'b001 : muxSel_uid50_fpToFxPTest_q = 2'b01; - 3'b010 : muxSel_uid50_fpToFxPTest_q = 2'b11; - 3'b011 : muxSel_uid50_fpToFxPTest_q = 2'b11; - 3'b100 : muxSel_uid50_fpToFxPTest_q = 2'b00; - 3'b101 : muxSel_uid50_fpToFxPTest_q = 2'b10; - 3'b110 : muxSel_uid50_fpToFxPTest_q = 2'b11; - 3'b111 : muxSel_uid50_fpToFxPTest_q = 2'b11; - default : begin - // unreachable - muxSel_uid50_fpToFxPTest_q = 2'bxx; - end - endcase - // End reserved scope level - end - - // finalOut_uid52_fpToFxPTest(MUX,51)@3 - assign finalOut_uid52_fpToFxPTest_s = muxSel_uid50_fpToFxPTest_q; - always @(finalOut_uid52_fpToFxPTest_s or en or redist0_sPostRnd_uid45_fpToFxPTest_b_1_q or maxPosValueS_uid39_fpToFxPTest_q or maxNegValueS_uid40_fpToFxPTest_q or maxNegValueU_uid51_fpToFxPTest_q) - begin - unique case (finalOut_uid52_fpToFxPTest_s) - 2'b00 : finalOut_uid52_fpToFxPTest_q = redist0_sPostRnd_uid45_fpToFxPTest_b_1_q; - 2'b01 : finalOut_uid52_fpToFxPTest_q = maxPosValueS_uid39_fpToFxPTest_q; - 2'b10 : finalOut_uid52_fpToFxPTest_q = maxNegValueS_uid40_fpToFxPTest_q; - 2'b11 : finalOut_uid52_fpToFxPTest_q = maxNegValueU_uid51_fpToFxPTest_q; - default : finalOut_uid52_fpToFxPTest_q = 32'b0; - endcase - end - - // xOut(GPOUT,4)@3 - assign q = finalOut_uid52_fpToFxPTest_q; - -endmodule diff --git a/hw/rtl/fp_cores/altera/arria10/acl_ftou.sv b/hw/rtl/fp_cores/altera/arria10/acl_ftou.sv deleted file mode 100644 index 65a973d3..00000000 --- a/hw/rtl/fp_cores/altera/arria10/acl_ftou.sv +++ /dev/null @@ -1,493 +0,0 @@ -// ------------------------------------------------------------------------- -// High Level Design Compiler for Intel(R) FPGAs Version 17.1 (Release Build #273) -// Quartus Prime development tool and MATLAB/Simulink Interface -// -// Legal Notice: Copyright 2017 Intel Corporation. All rights reserved. -// Your use of Intel Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly -// subject to the terms and conditions of the Intel FPGA Software License -// Agreement, Intel MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for -// the sole purpose of programming logic devices manufactured by Intel -// and sold by Intel or its authorized distributors. Please refer to the -// applicable agreement for further details. -// --------------------------------------------------------------------------- - -// SystemVerilog created from acl_ftou -// SystemVerilog created on Sun Dec 27 09:47:21 2020 - - -(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) -module acl_ftou ( - input wire [31:0] a, - input wire [0:0] en, - output wire [31:0] q, - input wire clk, - input wire areset - ); - - wire [0:0] GND_q; - wire [0:0] VCC_q; - wire [7:0] cstAllOWE_uid6_fpToFxPTest_q; - wire [22:0] cstZeroWF_uid7_fpToFxPTest_q; - wire [7:0] cstAllZWE_uid8_fpToFxPTest_q; - wire [7:0] exp_x_uid9_fpToFxPTest_b; - wire [22:0] frac_x_uid10_fpToFxPTest_b; - wire [0:0] excZ_x_uid11_fpToFxPTest_qi; - reg [0:0] excZ_x_uid11_fpToFxPTest_q; - wire [0:0] expXIsMax_uid12_fpToFxPTest_qi; - reg [0:0] expXIsMax_uid12_fpToFxPTest_q; - wire [0:0] fracXIsZero_uid13_fpToFxPTest_qi; - reg [0:0] fracXIsZero_uid13_fpToFxPTest_q; - wire [0:0] fracXIsNotZero_uid14_fpToFxPTest_q; - wire [0:0] excI_x_uid15_fpToFxPTest_q; - wire [0:0] excN_x_uid16_fpToFxPTest_q; - wire [0:0] invExcXZ_uid22_fpToFxPTest_q; - wire [23:0] oFracX_uid23_fpToFxPTest_q; - wire [0:0] signX_uid25_fpToFxPTest_b; - wire [8:0] ovfExpVal_uid26_fpToFxPTest_q; - wire [10:0] ovf_uid27_fpToFxPTest_a; - wire [10:0] ovf_uid27_fpToFxPTest_b; - logic [10:0] ovf_uid27_fpToFxPTest_o; - wire [0:0] ovf_uid27_fpToFxPTest_n; - wire [0:0] negOrOvf_uid28_fpToFxPTest_q; - wire [7:0] udfExpVal_uid29_fpToFxPTest_q; - wire [10:0] udf_uid30_fpToFxPTest_a; - wire [10:0] udf_uid30_fpToFxPTest_b; - logic [10:0] udf_uid30_fpToFxPTest_o; - wire [0:0] udf_uid30_fpToFxPTest_n; - wire [8:0] ovfExpVal_uid31_fpToFxPTest_q; - wire [10:0] shiftValE_uid32_fpToFxPTest_a; - wire [10:0] shiftValE_uid32_fpToFxPTest_b; - logic [10:0] shiftValE_uid32_fpToFxPTest_o; - wire [9:0] shiftValE_uid32_fpToFxPTest_q; - wire [5:0] shiftValRaw_uid33_fpToFxPTest_in; - wire [5:0] shiftValRaw_uid33_fpToFxPTest_b; - wire [5:0] maxShiftCst_uid34_fpToFxPTest_q; - wire [11:0] shiftOutOfRange_uid35_fpToFxPTest_a; - wire [11:0] shiftOutOfRange_uid35_fpToFxPTest_b; - logic [11:0] shiftOutOfRange_uid35_fpToFxPTest_o; - wire [0:0] shiftOutOfRange_uid35_fpToFxPTest_n; - wire [0:0] shiftVal_uid36_fpToFxPTest_s; - reg [5:0] shiftVal_uid36_fpToFxPTest_q; - wire [8:0] zPadd_uid37_fpToFxPTest_q; - wire [32:0] shifterIn_uid38_fpToFxPTest_q; - wire [31:0] maxPosValueU_uid40_fpToFxPTest_q; - wire [31:0] maxNegValueU_uid41_fpToFxPTest_q; - wire [33:0] zRightShiferNoStickyOut_uid43_fpToFxPTest_q; - wire [34:0] sPostRndFull_uid44_fpToFxPTest_a; - wire [34:0] sPostRndFull_uid44_fpToFxPTest_b; - logic [34:0] sPostRndFull_uid44_fpToFxPTest_o; - wire [34:0] sPostRndFull_uid44_fpToFxPTest_q; - wire [32:0] sPostRnd_uid45_fpToFxPTest_in; - wire [31:0] sPostRnd_uid45_fpToFxPTest_b; - wire [33:0] sPostRndFullMSBU_uid46_fpToFxPTest_in; - wire [0:0] sPostRndFullMSBU_uid46_fpToFxPTest_b; - wire [0:0] ovfPostRnd_uid47_fpToFxPTest_q; - wire [2:0] muxSelConc_uid48_fpToFxPTest_q; - reg [1:0] muxSel_uid49_fpToFxPTest_q; - wire [1:0] finalOut_uid51_fpToFxPTest_s; - reg [31:0] finalOut_uid51_fpToFxPTest_q; - wire [16:0] rightShiftStage0Idx1Rng16_uid55_rightShiferNoStickyOut_uid39_fpToFxPTest_b; - wire [15:0] rightShiftStage0Idx1Pad16_uid56_rightShiferNoStickyOut_uid39_fpToFxPTest_q; - wire [32:0] rightShiftStage0Idx1_uid57_rightShiferNoStickyOut_uid39_fpToFxPTest_q; - wire [0:0] rightShiftStage0Idx2Rng32_uid58_rightShiferNoStickyOut_uid39_fpToFxPTest_b; - wire [32:0] rightShiftStage0Idx2_uid60_rightShiferNoStickyOut_uid39_fpToFxPTest_q; - wire [32:0] rightShiftStage0Idx3_uid61_rightShiferNoStickyOut_uid39_fpToFxPTest_q; - wire [1:0] rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_s; - reg [32:0] rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q; - wire [28:0] rightShiftStage1Idx1Rng4_uid64_rightShiferNoStickyOut_uid39_fpToFxPTest_b; - wire [3:0] rightShiftStage1Idx1Pad4_uid65_rightShiferNoStickyOut_uid39_fpToFxPTest_q; - wire [32:0] rightShiftStage1Idx1_uid66_rightShiferNoStickyOut_uid39_fpToFxPTest_q; - wire [24:0] rightShiftStage1Idx2Rng8_uid67_rightShiferNoStickyOut_uid39_fpToFxPTest_b; - wire [32:0] rightShiftStage1Idx2_uid69_rightShiferNoStickyOut_uid39_fpToFxPTest_q; - wire [20:0] rightShiftStage1Idx3Rng12_uid70_rightShiferNoStickyOut_uid39_fpToFxPTest_b; - wire [11:0] rightShiftStage1Idx3Pad12_uid71_rightShiferNoStickyOut_uid39_fpToFxPTest_q; - wire [32:0] rightShiftStage1Idx3_uid72_rightShiferNoStickyOut_uid39_fpToFxPTest_q; - wire [1:0] rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_s; - reg [32:0] rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_q; - wire [31:0] rightShiftStage2Idx1Rng1_uid75_rightShiferNoStickyOut_uid39_fpToFxPTest_b; - wire [32:0] rightShiftStage2Idx1_uid77_rightShiferNoStickyOut_uid39_fpToFxPTest_q; - wire [30:0] rightShiftStage2Idx2Rng2_uid78_rightShiferNoStickyOut_uid39_fpToFxPTest_b; - wire [1:0] rightShiftStage2Idx2Pad2_uid79_rightShiferNoStickyOut_uid39_fpToFxPTest_q; - wire [32:0] rightShiftStage2Idx2_uid80_rightShiferNoStickyOut_uid39_fpToFxPTest_q; - wire [29:0] rightShiftStage2Idx3Rng3_uid81_rightShiferNoStickyOut_uid39_fpToFxPTest_b; - wire [2:0] rightShiftStage2Idx3Pad3_uid82_rightShiferNoStickyOut_uid39_fpToFxPTest_q; - wire [32:0] rightShiftStage2Idx3_uid83_rightShiferNoStickyOut_uid39_fpToFxPTest_q; - wire [1:0] rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_s; - reg [32:0] rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_q; - wire [1:0] rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select_b; - wire [1:0] rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select_c; - wire [1:0] rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select_d; - reg [31:0] redist0_sPostRnd_uid45_fpToFxPTest_b_1_q; - reg [5:0] redist1_shiftValRaw_uid33_fpToFxPTest_b_1_q; - reg [0:0] redist2_udf_uid30_fpToFxPTest_n_2_q; - reg [0:0] redist3_ovf_uid27_fpToFxPTest_n_2_q; - reg [0:0] redist4_signX_uid25_fpToFxPTest_b_2_q; - reg [0:0] redist5_expXIsMax_uid12_fpToFxPTest_q_2_q; - reg [22:0] redist6_frac_x_uid10_fpToFxPTest_b_1_q; - - - // maxNegValueU_uid41_fpToFxPTest(CONSTANT,40) - assign maxNegValueU_uid41_fpToFxPTest_q = 32'b00000000000000000000000000000000; - - // maxPosValueU_uid40_fpToFxPTest(CONSTANT,39) - assign maxPosValueU_uid40_fpToFxPTest_q = 32'b11111111111111111111111111111111; - - // VCC(CONSTANT,1) - assign VCC_q = 1'b1; - - // GND(CONSTANT,0) - assign GND_q = 1'b0; - - // rightShiftStage2Idx3Pad3_uid82_rightShiferNoStickyOut_uid39_fpToFxPTest(CONSTANT,81) - assign rightShiftStage2Idx3Pad3_uid82_rightShiferNoStickyOut_uid39_fpToFxPTest_q = 3'b000; - - // rightShiftStage2Idx3Rng3_uid81_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,80)@1 - assign rightShiftStage2Idx3Rng3_uid81_rightShiferNoStickyOut_uid39_fpToFxPTest_b = rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_q[32:3]; - - // rightShiftStage2Idx3_uid83_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,82)@1 - assign rightShiftStage2Idx3_uid83_rightShiferNoStickyOut_uid39_fpToFxPTest_q = {rightShiftStage2Idx3Pad3_uid82_rightShiferNoStickyOut_uid39_fpToFxPTest_q, rightShiftStage2Idx3Rng3_uid81_rightShiferNoStickyOut_uid39_fpToFxPTest_b}; - - // rightShiftStage2Idx2Pad2_uid79_rightShiferNoStickyOut_uid39_fpToFxPTest(CONSTANT,78) - assign rightShiftStage2Idx2Pad2_uid79_rightShiferNoStickyOut_uid39_fpToFxPTest_q = 2'b00; - - // rightShiftStage2Idx2Rng2_uid78_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,77)@1 - assign rightShiftStage2Idx2Rng2_uid78_rightShiferNoStickyOut_uid39_fpToFxPTest_b = rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_q[32:2]; - - // rightShiftStage2Idx2_uid80_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,79)@1 - assign rightShiftStage2Idx2_uid80_rightShiferNoStickyOut_uid39_fpToFxPTest_q = {rightShiftStage2Idx2Pad2_uid79_rightShiferNoStickyOut_uid39_fpToFxPTest_q, rightShiftStage2Idx2Rng2_uid78_rightShiferNoStickyOut_uid39_fpToFxPTest_b}; - - // rightShiftStage2Idx1Rng1_uid75_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,74)@1 - assign rightShiftStage2Idx1Rng1_uid75_rightShiferNoStickyOut_uid39_fpToFxPTest_b = rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_q[32:1]; - - // rightShiftStage2Idx1_uid77_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,76)@1 - assign rightShiftStage2Idx1_uid77_rightShiferNoStickyOut_uid39_fpToFxPTest_q = {GND_q, rightShiftStage2Idx1Rng1_uid75_rightShiferNoStickyOut_uid39_fpToFxPTest_b}; - - // rightShiftStage1Idx3Pad12_uid71_rightShiferNoStickyOut_uid39_fpToFxPTest(CONSTANT,70) - assign rightShiftStage1Idx3Pad12_uid71_rightShiferNoStickyOut_uid39_fpToFxPTest_q = 12'b000000000000; - - // rightShiftStage1Idx3Rng12_uid70_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,69)@1 - assign rightShiftStage1Idx3Rng12_uid70_rightShiferNoStickyOut_uid39_fpToFxPTest_b = rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q[32:12]; - - // rightShiftStage1Idx3_uid72_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,71)@1 - assign rightShiftStage1Idx3_uid72_rightShiferNoStickyOut_uid39_fpToFxPTest_q = {rightShiftStage1Idx3Pad12_uid71_rightShiferNoStickyOut_uid39_fpToFxPTest_q, rightShiftStage1Idx3Rng12_uid70_rightShiferNoStickyOut_uid39_fpToFxPTest_b}; - - // cstAllZWE_uid8_fpToFxPTest(CONSTANT,7) - assign cstAllZWE_uid8_fpToFxPTest_q = 8'b00000000; - - // rightShiftStage1Idx2Rng8_uid67_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,66)@1 - assign rightShiftStage1Idx2Rng8_uid67_rightShiferNoStickyOut_uid39_fpToFxPTest_b = rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q[32:8]; - - // rightShiftStage1Idx2_uid69_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,68)@1 - assign rightShiftStage1Idx2_uid69_rightShiferNoStickyOut_uid39_fpToFxPTest_q = {cstAllZWE_uid8_fpToFxPTest_q, rightShiftStage1Idx2Rng8_uid67_rightShiferNoStickyOut_uid39_fpToFxPTest_b}; - - // rightShiftStage1Idx1Pad4_uid65_rightShiferNoStickyOut_uid39_fpToFxPTest(CONSTANT,64) - assign rightShiftStage1Idx1Pad4_uid65_rightShiferNoStickyOut_uid39_fpToFxPTest_q = 4'b0000; - - // rightShiftStage1Idx1Rng4_uid64_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,63)@1 - assign rightShiftStage1Idx1Rng4_uid64_rightShiferNoStickyOut_uid39_fpToFxPTest_b = rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q[32:4]; - - // rightShiftStage1Idx1_uid66_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,65)@1 - assign rightShiftStage1Idx1_uid66_rightShiferNoStickyOut_uid39_fpToFxPTest_q = {rightShiftStage1Idx1Pad4_uid65_rightShiferNoStickyOut_uid39_fpToFxPTest_q, rightShiftStage1Idx1Rng4_uid64_rightShiferNoStickyOut_uid39_fpToFxPTest_b}; - - // rightShiftStage0Idx3_uid61_rightShiferNoStickyOut_uid39_fpToFxPTest(CONSTANT,60) - assign rightShiftStage0Idx3_uid61_rightShiferNoStickyOut_uid39_fpToFxPTest_q = 33'b000000000000000000000000000000000; - - // rightShiftStage0Idx2Rng32_uid58_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,57)@1 - assign rightShiftStage0Idx2Rng32_uid58_rightShiferNoStickyOut_uid39_fpToFxPTest_b = shifterIn_uid38_fpToFxPTest_q[32:32]; - - // rightShiftStage0Idx2_uid60_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,59)@1 - assign rightShiftStage0Idx2_uid60_rightShiferNoStickyOut_uid39_fpToFxPTest_q = {maxNegValueU_uid41_fpToFxPTest_q, rightShiftStage0Idx2Rng32_uid58_rightShiferNoStickyOut_uid39_fpToFxPTest_b}; - - // rightShiftStage0Idx1Pad16_uid56_rightShiferNoStickyOut_uid39_fpToFxPTest(CONSTANT,55) - assign rightShiftStage0Idx1Pad16_uid56_rightShiferNoStickyOut_uid39_fpToFxPTest_q = 16'b0000000000000000; - - // rightShiftStage0Idx1Rng16_uid55_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,54)@1 - assign rightShiftStage0Idx1Rng16_uid55_rightShiferNoStickyOut_uid39_fpToFxPTest_b = shifterIn_uid38_fpToFxPTest_q[32:16]; - - // rightShiftStage0Idx1_uid57_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,56)@1 - assign rightShiftStage0Idx1_uid57_rightShiferNoStickyOut_uid39_fpToFxPTest_q = {rightShiftStage0Idx1Pad16_uid56_rightShiferNoStickyOut_uid39_fpToFxPTest_q, rightShiftStage0Idx1Rng16_uid55_rightShiferNoStickyOut_uid39_fpToFxPTest_b}; - - // exp_x_uid9_fpToFxPTest(BITSELECT,8)@0 - assign exp_x_uid9_fpToFxPTest_b = a[30:23]; - - // excZ_x_uid11_fpToFxPTest(LOGICAL,10)@0 + 1 - assign excZ_x_uid11_fpToFxPTest_qi = exp_x_uid9_fpToFxPTest_b == cstAllZWE_uid8_fpToFxPTest_q ? 1'b1 : 1'b0; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - excZ_x_uid11_fpToFxPTest_delay ( .xin(excZ_x_uid11_fpToFxPTest_qi), .xout(excZ_x_uid11_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // invExcXZ_uid22_fpToFxPTest(LOGICAL,21)@1 - assign invExcXZ_uid22_fpToFxPTest_q = ~ (excZ_x_uid11_fpToFxPTest_q); - - // frac_x_uid10_fpToFxPTest(BITSELECT,9)@0 - assign frac_x_uid10_fpToFxPTest_b = a[22:0]; - - // redist6_frac_x_uid10_fpToFxPTest_b_1(DELAY,93) - dspba_delay_ver #( .width(23), .depth(1), .reset_kind("ASYNC") ) - redist6_frac_x_uid10_fpToFxPTest_b_1 ( .xin(frac_x_uid10_fpToFxPTest_b), .xout(redist6_frac_x_uid10_fpToFxPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // oFracX_uid23_fpToFxPTest(BITJOIN,22)@1 - assign oFracX_uid23_fpToFxPTest_q = {invExcXZ_uid22_fpToFxPTest_q, redist6_frac_x_uid10_fpToFxPTest_b_1_q}; - - // zPadd_uid37_fpToFxPTest(CONSTANT,36) - assign zPadd_uid37_fpToFxPTest_q = 9'b000000000; - - // shifterIn_uid38_fpToFxPTest(BITJOIN,37)@1 - assign shifterIn_uid38_fpToFxPTest_q = {oFracX_uid23_fpToFxPTest_q, zPadd_uid37_fpToFxPTest_q}; - - // rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest(MUX,62)@1 - assign rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_s = rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select_b; - always @(rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_s or en or shifterIn_uid38_fpToFxPTest_q or rightShiftStage0Idx1_uid57_rightShiferNoStickyOut_uid39_fpToFxPTest_q or rightShiftStage0Idx2_uid60_rightShiferNoStickyOut_uid39_fpToFxPTest_q or rightShiftStage0Idx3_uid61_rightShiferNoStickyOut_uid39_fpToFxPTest_q) - begin - unique case (rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_s) - 2'b00 : rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q = shifterIn_uid38_fpToFxPTest_q; - 2'b01 : rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q = rightShiftStage0Idx1_uid57_rightShiferNoStickyOut_uid39_fpToFxPTest_q; - 2'b10 : rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q = rightShiftStage0Idx2_uid60_rightShiferNoStickyOut_uid39_fpToFxPTest_q; - 2'b11 : rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q = rightShiftStage0Idx3_uid61_rightShiferNoStickyOut_uid39_fpToFxPTest_q; - default : rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q = 33'b0; - endcase - end - - // rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest(MUX,73)@1 - assign rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_s = rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select_c; - always @(rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_s or en or rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q or rightShiftStage1Idx1_uid66_rightShiferNoStickyOut_uid39_fpToFxPTest_q or rightShiftStage1Idx2_uid69_rightShiferNoStickyOut_uid39_fpToFxPTest_q or rightShiftStage1Idx3_uid72_rightShiferNoStickyOut_uid39_fpToFxPTest_q) - begin - unique case (rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_s) - 2'b00 : rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_q = rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q; - 2'b01 : rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_q = rightShiftStage1Idx1_uid66_rightShiferNoStickyOut_uid39_fpToFxPTest_q; - 2'b10 : rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_q = rightShiftStage1Idx2_uid69_rightShiferNoStickyOut_uid39_fpToFxPTest_q; - 2'b11 : rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_q = rightShiftStage1Idx3_uid72_rightShiferNoStickyOut_uid39_fpToFxPTest_q; - default : rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_q = 33'b0; - endcase - end - - // maxShiftCst_uid34_fpToFxPTest(CONSTANT,33) - assign maxShiftCst_uid34_fpToFxPTest_q = 6'b100001; - - // ovfExpVal_uid31_fpToFxPTest(CONSTANT,30) - assign ovfExpVal_uid31_fpToFxPTest_q = 9'b010011110; - - // shiftValE_uid32_fpToFxPTest(SUB,31)@0 - assign shiftValE_uid32_fpToFxPTest_a = {{2{ovfExpVal_uid31_fpToFxPTest_q[8]}}, ovfExpVal_uid31_fpToFxPTest_q}; - assign shiftValE_uid32_fpToFxPTest_b = {3'b000, exp_x_uid9_fpToFxPTest_b}; - assign shiftValE_uid32_fpToFxPTest_o = $signed(shiftValE_uid32_fpToFxPTest_a) - $signed(shiftValE_uid32_fpToFxPTest_b); - assign shiftValE_uid32_fpToFxPTest_q = shiftValE_uid32_fpToFxPTest_o[9:0]; - - // shiftValRaw_uid33_fpToFxPTest(BITSELECT,32)@0 - assign shiftValRaw_uid33_fpToFxPTest_in = shiftValE_uid32_fpToFxPTest_q[5:0]; - assign shiftValRaw_uid33_fpToFxPTest_b = shiftValRaw_uid33_fpToFxPTest_in[5:0]; - - // redist1_shiftValRaw_uid33_fpToFxPTest_b_1(DELAY,88) - dspba_delay_ver #( .width(6), .depth(1), .reset_kind("ASYNC") ) - redist1_shiftValRaw_uid33_fpToFxPTest_b_1 ( .xin(shiftValRaw_uid33_fpToFxPTest_b), .xout(redist1_shiftValRaw_uid33_fpToFxPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // shiftOutOfRange_uid35_fpToFxPTest(COMPARE,34)@0 + 1 - assign shiftOutOfRange_uid35_fpToFxPTest_a = {{2{shiftValE_uid32_fpToFxPTest_q[9]}}, shiftValE_uid32_fpToFxPTest_q}; - assign shiftOutOfRange_uid35_fpToFxPTest_b = {6'b000000, maxShiftCst_uid34_fpToFxPTest_q}; - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - shiftOutOfRange_uid35_fpToFxPTest_o <= 12'b0; - end - else if (en == 1'b1) - begin - shiftOutOfRange_uid35_fpToFxPTest_o <= $signed(shiftOutOfRange_uid35_fpToFxPTest_a) - $signed(shiftOutOfRange_uid35_fpToFxPTest_b); - end - end - assign shiftOutOfRange_uid35_fpToFxPTest_n[0] = ~ (shiftOutOfRange_uid35_fpToFxPTest_o[11]); - - // shiftVal_uid36_fpToFxPTest(MUX,35)@1 - assign shiftVal_uid36_fpToFxPTest_s = shiftOutOfRange_uid35_fpToFxPTest_n; - always @(shiftVal_uid36_fpToFxPTest_s or en or redist1_shiftValRaw_uid33_fpToFxPTest_b_1_q or maxShiftCst_uid34_fpToFxPTest_q) - begin - unique case (shiftVal_uid36_fpToFxPTest_s) - 1'b0 : shiftVal_uid36_fpToFxPTest_q = redist1_shiftValRaw_uid33_fpToFxPTest_b_1_q; - 1'b1 : shiftVal_uid36_fpToFxPTest_q = maxShiftCst_uid34_fpToFxPTest_q; - default : shiftVal_uid36_fpToFxPTest_q = 6'b0; - endcase - end - - // rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select(BITSELECT,86)@1 - assign rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select_b = shiftVal_uid36_fpToFxPTest_q[5:4]; - assign rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select_c = shiftVal_uid36_fpToFxPTest_q[3:2]; - assign rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select_d = shiftVal_uid36_fpToFxPTest_q[1:0]; - - // rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest(MUX,84)@1 + 1 - assign rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_s = rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select_d; - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_q <= 33'b0; - end - else if (en == 1'b1) - begin - unique case (rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_s) - 2'b00 : rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_q <= rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_q; - 2'b01 : rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_q <= rightShiftStage2Idx1_uid77_rightShiferNoStickyOut_uid39_fpToFxPTest_q; - 2'b10 : rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_q <= rightShiftStage2Idx2_uid80_rightShiferNoStickyOut_uid39_fpToFxPTest_q; - 2'b11 : rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_q <= rightShiftStage2Idx3_uid83_rightShiferNoStickyOut_uid39_fpToFxPTest_q; - default : rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_q <= 33'b0; - endcase - end - end - - // zRightShiferNoStickyOut_uid43_fpToFxPTest(BITJOIN,42)@2 - assign zRightShiferNoStickyOut_uid43_fpToFxPTest_q = {GND_q, rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_q}; - - // sPostRndFull_uid44_fpToFxPTest(ADD,43)@2 - assign sPostRndFull_uid44_fpToFxPTest_a = {1'b0, zRightShiferNoStickyOut_uid43_fpToFxPTest_q}; - assign sPostRndFull_uid44_fpToFxPTest_b = {34'b0000000000000000000000000000000000, VCC_q}; - assign sPostRndFull_uid44_fpToFxPTest_o = $unsigned(sPostRndFull_uid44_fpToFxPTest_a) + $unsigned(sPostRndFull_uid44_fpToFxPTest_b); - assign sPostRndFull_uid44_fpToFxPTest_q = sPostRndFull_uid44_fpToFxPTest_o[34:0]; - - // sPostRnd_uid45_fpToFxPTest(BITSELECT,44)@2 - assign sPostRnd_uid45_fpToFxPTest_in = sPostRndFull_uid44_fpToFxPTest_q[32:0]; - assign sPostRnd_uid45_fpToFxPTest_b = sPostRnd_uid45_fpToFxPTest_in[32:1]; - - // redist0_sPostRnd_uid45_fpToFxPTest_b_1(DELAY,87) - dspba_delay_ver #( .width(32), .depth(1), .reset_kind("ASYNC") ) - redist0_sPostRnd_uid45_fpToFxPTest_b_1 ( .xin(sPostRnd_uid45_fpToFxPTest_b), .xout(redist0_sPostRnd_uid45_fpToFxPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // signX_uid25_fpToFxPTest(BITSELECT,24)@0 - assign signX_uid25_fpToFxPTest_b = a[31:31]; - - // redist4_signX_uid25_fpToFxPTest_b_2(DELAY,91) - dspba_delay_ver #( .width(1), .depth(2), .reset_kind("ASYNC") ) - redist4_signX_uid25_fpToFxPTest_b_2 ( .xin(signX_uid25_fpToFxPTest_b), .xout(redist4_signX_uid25_fpToFxPTest_b_2_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // udfExpVal_uid29_fpToFxPTest(CONSTANT,28) - assign udfExpVal_uid29_fpToFxPTest_q = 8'b01111101; - - // udf_uid30_fpToFxPTest(COMPARE,29)@0 + 1 - assign udf_uid30_fpToFxPTest_a = {{3{udfExpVal_uid29_fpToFxPTest_q[7]}}, udfExpVal_uid29_fpToFxPTest_q}; - assign udf_uid30_fpToFxPTest_b = {3'b000, exp_x_uid9_fpToFxPTest_b}; - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - udf_uid30_fpToFxPTest_o <= 11'b0; - end - else if (en == 1'b1) - begin - udf_uid30_fpToFxPTest_o <= $signed(udf_uid30_fpToFxPTest_a) - $signed(udf_uid30_fpToFxPTest_b); - end - end - assign udf_uid30_fpToFxPTest_n[0] = ~ (udf_uid30_fpToFxPTest_o[10]); - - // redist2_udf_uid30_fpToFxPTest_n_2(DELAY,89) - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - redist2_udf_uid30_fpToFxPTest_n_2 ( .xin(udf_uid30_fpToFxPTest_n), .xout(redist2_udf_uid30_fpToFxPTest_n_2_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // sPostRndFullMSBU_uid46_fpToFxPTest(BITSELECT,45)@2 - assign sPostRndFullMSBU_uid46_fpToFxPTest_in = sPostRndFull_uid44_fpToFxPTest_q[33:0]; - assign sPostRndFullMSBU_uid46_fpToFxPTest_b = sPostRndFullMSBU_uid46_fpToFxPTest_in[33:33]; - - // ovfExpVal_uid26_fpToFxPTest(CONSTANT,25) - assign ovfExpVal_uid26_fpToFxPTest_q = 9'b010011111; - - // ovf_uid27_fpToFxPTest(COMPARE,26)@0 + 1 - assign ovf_uid27_fpToFxPTest_a = {3'b000, exp_x_uid9_fpToFxPTest_b}; - assign ovf_uid27_fpToFxPTest_b = {{2{ovfExpVal_uid26_fpToFxPTest_q[8]}}, ovfExpVal_uid26_fpToFxPTest_q}; - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - ovf_uid27_fpToFxPTest_o <= 11'b0; - end - else if (en == 1'b1) - begin - ovf_uid27_fpToFxPTest_o <= $signed(ovf_uid27_fpToFxPTest_a) - $signed(ovf_uid27_fpToFxPTest_b); - end - end - assign ovf_uid27_fpToFxPTest_n[0] = ~ (ovf_uid27_fpToFxPTest_o[10]); - - // redist3_ovf_uid27_fpToFxPTest_n_2(DELAY,90) - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - redist3_ovf_uid27_fpToFxPTest_n_2 ( .xin(ovf_uid27_fpToFxPTest_n), .xout(redist3_ovf_uid27_fpToFxPTest_n_2_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // negOrOvf_uid28_fpToFxPTest(LOGICAL,27)@2 - assign negOrOvf_uid28_fpToFxPTest_q = redist4_signX_uid25_fpToFxPTest_b_2_q | redist3_ovf_uid27_fpToFxPTest_n_2_q; - - // cstZeroWF_uid7_fpToFxPTest(CONSTANT,6) - assign cstZeroWF_uid7_fpToFxPTest_q = 23'b00000000000000000000000; - - // fracXIsZero_uid13_fpToFxPTest(LOGICAL,12)@1 + 1 - assign fracXIsZero_uid13_fpToFxPTest_qi = cstZeroWF_uid7_fpToFxPTest_q == redist6_frac_x_uid10_fpToFxPTest_b_1_q ? 1'b1 : 1'b0; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - fracXIsZero_uid13_fpToFxPTest_delay ( .xin(fracXIsZero_uid13_fpToFxPTest_qi), .xout(fracXIsZero_uid13_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // cstAllOWE_uid6_fpToFxPTest(CONSTANT,5) - assign cstAllOWE_uid6_fpToFxPTest_q = 8'b11111111; - - // expXIsMax_uid12_fpToFxPTest(LOGICAL,11)@0 + 1 - assign expXIsMax_uid12_fpToFxPTest_qi = exp_x_uid9_fpToFxPTest_b == cstAllOWE_uid6_fpToFxPTest_q ? 1'b1 : 1'b0; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - expXIsMax_uid12_fpToFxPTest_delay ( .xin(expXIsMax_uid12_fpToFxPTest_qi), .xout(expXIsMax_uid12_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist5_expXIsMax_uid12_fpToFxPTest_q_2(DELAY,92) - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - redist5_expXIsMax_uid12_fpToFxPTest_q_2 ( .xin(expXIsMax_uid12_fpToFxPTest_q), .xout(redist5_expXIsMax_uid12_fpToFxPTest_q_2_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // excI_x_uid15_fpToFxPTest(LOGICAL,14)@2 - assign excI_x_uid15_fpToFxPTest_q = redist5_expXIsMax_uid12_fpToFxPTest_q_2_q & fracXIsZero_uid13_fpToFxPTest_q; - - // fracXIsNotZero_uid14_fpToFxPTest(LOGICAL,13)@2 - assign fracXIsNotZero_uid14_fpToFxPTest_q = ~ (fracXIsZero_uid13_fpToFxPTest_q); - - // excN_x_uid16_fpToFxPTest(LOGICAL,15)@2 - assign excN_x_uid16_fpToFxPTest_q = redist5_expXIsMax_uid12_fpToFxPTest_q_2_q & fracXIsNotZero_uid14_fpToFxPTest_q; - - // ovfPostRnd_uid47_fpToFxPTest(LOGICAL,46)@2 - assign ovfPostRnd_uid47_fpToFxPTest_q = excN_x_uid16_fpToFxPTest_q | excI_x_uid15_fpToFxPTest_q | negOrOvf_uid28_fpToFxPTest_q | sPostRndFullMSBU_uid46_fpToFxPTest_b; - - // muxSelConc_uid48_fpToFxPTest(BITJOIN,47)@2 - assign muxSelConc_uid48_fpToFxPTest_q = {redist4_signX_uid25_fpToFxPTest_b_2_q, redist2_udf_uid30_fpToFxPTest_n_2_q, ovfPostRnd_uid47_fpToFxPTest_q}; - - // muxSel_uid49_fpToFxPTest(LOOKUP,48)@2 + 1 - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - muxSel_uid49_fpToFxPTest_q <= 2'b00; - end - else if (en == 1'b1) - begin - unique case (muxSelConc_uid48_fpToFxPTest_q) - 3'b000 : muxSel_uid49_fpToFxPTest_q <= 2'b00; - 3'b001 : muxSel_uid49_fpToFxPTest_q <= 2'b01; - 3'b010 : muxSel_uid49_fpToFxPTest_q <= 2'b11; - 3'b011 : muxSel_uid49_fpToFxPTest_q <= 2'b00; - 3'b100 : muxSel_uid49_fpToFxPTest_q <= 2'b10; - 3'b101 : muxSel_uid49_fpToFxPTest_q <= 2'b10; - 3'b110 : muxSel_uid49_fpToFxPTest_q <= 2'b10; - 3'b111 : muxSel_uid49_fpToFxPTest_q <= 2'b10; - default : begin - // unreachable - muxSel_uid49_fpToFxPTest_q <= 2'bxx; - end - endcase - end - end - - // finalOut_uid51_fpToFxPTest(MUX,50)@3 - assign finalOut_uid51_fpToFxPTest_s = muxSel_uid49_fpToFxPTest_q; - always @(finalOut_uid51_fpToFxPTest_s or en or redist0_sPostRnd_uid45_fpToFxPTest_b_1_q or maxPosValueU_uid40_fpToFxPTest_q or maxNegValueU_uid41_fpToFxPTest_q) - begin - unique case (finalOut_uid51_fpToFxPTest_s) - 2'b00 : finalOut_uid51_fpToFxPTest_q = redist0_sPostRnd_uid45_fpToFxPTest_b_1_q; - 2'b01 : finalOut_uid51_fpToFxPTest_q = maxPosValueU_uid40_fpToFxPTest_q; - 2'b10 : finalOut_uid51_fpToFxPTest_q = maxNegValueU_uid41_fpToFxPTest_q; - 2'b11 : finalOut_uid51_fpToFxPTest_q = maxNegValueU_uid41_fpToFxPTest_q; - default : finalOut_uid51_fpToFxPTest_q = 32'b0; - endcase - end - - // xOut(GPOUT,4)@3 - assign q = finalOut_uid51_fpToFxPTest_q; - -endmodule diff --git a/hw/rtl/fp_cores/altera/arria10/acl_gen.sh b/hw/rtl/fp_cores/altera/arria10/acl_gen.sh index 36302666..5eb811b9 100755 --- a/hw/rtl/fp_cores/altera/arria10/acl_gen.sh +++ b/hw/rtl/fp_cores/altera/arria10/acl_gen.sh @@ -18,13 +18,16 @@ FBITS="f$(($EXP_BITS + $MAN_BITS + 1))" echo Generating IP cores for $FBITS { + #$CMD -name "$PREFIX"_fadd -frequency 250 FPAdd $EXP_BITS $MAN_BITS + #$CMD -name "$PREFIX"_fsub -frequency 250 FPSub $EXP_BITS $MAN_BITS + #$CMD -name "$PREFIX"_fmul -frequency 250 FPMul $EXP_BITS $MAN_BITS $CMD -name "$PREFIX"_fmadd -frequency 250 FPMultAdd $EXP_BITS $MAN_BITS $CMD -name "$PREFIX"_fdiv -frequency 250 FPDiv $EXP_BITS $MAN_BITS 0 $CMD -name "$PREFIX"_fsqrt -frequency 250 FPSqrt $EXP_BITS $MAN_BITS - $CMD -name "$PREFIX"_ftoi -frequency 250 FPToFXP $EXP_BITS $MAN_BITS 32 0 1 - $CMD -name "$PREFIX"_ftou -frequency 250 FPToFXP $EXP_BITS $MAN_BITS 32 0 0 - $CMD -name "$PREFIX"_itof -frequency 250 FXPToFP 32 0 1 $EXP_BITS $MAN_BITS - $CMD -name "$PREFIX"_utof -frequency 300 FXPToFP 32 0 0 $EXP_BITS $MAN_BITS + #$CMD -name "$PREFIX"_ftoi -frequency 250 FPToFXP $EXP_BITS $MAN_BITS 32 0 1 + #$CMD -name "$PREFIX"_ftou -frequency 250 FPToFXP $EXP_BITS $MAN_BITS 32 0 0 + #$CMD -name "$PREFIX"_itof -frequency 250 FXPToFP 32 0 1 $EXP_BITS $MAN_BITS + #$CMD -name "$PREFIX"_utof -frequency 300 FXPToFP 32 0 0 $EXP_BITS $MAN_BITS } > acl_gen.log 2>&1 #cp $QUARTUS_HOME/dspba/backend/Libraries/sv/base/dspba_library_ver.sv . \ No newline at end of file diff --git a/hw/rtl/fp_cores/altera/arria10/acl_itof.sv b/hw/rtl/fp_cores/altera/arria10/acl_itof.sv deleted file mode 100644 index 78316263..00000000 --- a/hw/rtl/fp_cores/altera/arria10/acl_itof.sv +++ /dev/null @@ -1,520 +0,0 @@ -// ------------------------------------------------------------------------- -// High Level Design Compiler for Intel(R) FPGAs Version 17.1 (Release Build #273) -// Quartus Prime development tool and MATLAB/Simulink Interface -// -// Legal Notice: Copyright 2017 Intel Corporation. All rights reserved. -// Your use of Intel Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly -// subject to the terms and conditions of the Intel FPGA Software License -// Agreement, Intel MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for -// the sole purpose of programming logic devices manufactured by Intel -// and sold by Intel or its authorized distributors. Please refer to the -// applicable agreement for further details. -// --------------------------------------------------------------------------- - -// SystemVerilog created from acl_itof -// SystemVerilog created on Sun Dec 27 09:47:21 2020 - - -(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) -module acl_itof ( - input wire [31:0] a, - input wire [0:0] en, - output wire [31:0] q, - input wire clk, - input wire areset - ); - - wire [0:0] GND_q; - wire [0:0] signX_uid6_fxpToFPTest_b; - wire [31:0] xXorSign_uid7_fxpToFPTest_b; - wire [31:0] xXorSign_uid7_fxpToFPTest_qi; - reg [31:0] xXorSign_uid7_fxpToFPTest_q; - wire [32:0] yE_uid8_fxpToFPTest_a; - wire [32:0] yE_uid8_fxpToFPTest_b; - logic [32:0] yE_uid8_fxpToFPTest_o; - wire [32:0] yE_uid8_fxpToFPTest_q; - wire [31:0] y_uid9_fxpToFPTest_in; - wire [31:0] y_uid9_fxpToFPTest_b; - wire [5:0] maxCount_uid11_fxpToFPTest_q; - wire [0:0] inIsZero_uid12_fxpToFPTest_qi; - reg [0:0] inIsZero_uid12_fxpToFPTest_q; - wire [7:0] msbIn_uid13_fxpToFPTest_q; - wire [8:0] expPreRnd_uid14_fxpToFPTest_a; - wire [8:0] expPreRnd_uid14_fxpToFPTest_b; - logic [8:0] expPreRnd_uid14_fxpToFPTest_o; - wire [8:0] expPreRnd_uid14_fxpToFPTest_q; - wire [32:0] expFracRnd_uid16_fxpToFPTest_q; - wire [0:0] sticky_uid20_fxpToFPTest_qi; - reg [0:0] sticky_uid20_fxpToFPTest_q; - wire [0:0] nr_uid21_fxpToFPTest_q; - wire [0:0] rnd_uid22_fxpToFPTest_q; - wire [34:0] expFracR_uid24_fxpToFPTest_a; - wire [34:0] expFracR_uid24_fxpToFPTest_b; - logic [34:0] expFracR_uid24_fxpToFPTest_o; - wire [33:0] expFracR_uid24_fxpToFPTest_q; - wire [23:0] fracR_uid25_fxpToFPTest_in; - wire [22:0] fracR_uid25_fxpToFPTest_b; - wire [9:0] expR_uid26_fxpToFPTest_b; - wire [11:0] udf_uid27_fxpToFPTest_a; - wire [11:0] udf_uid27_fxpToFPTest_b; - logic [11:0] udf_uid27_fxpToFPTest_o; - wire [0:0] udf_uid27_fxpToFPTest_n; - wire [7:0] expInf_uid28_fxpToFPTest_q; - wire [11:0] ovf_uid29_fxpToFPTest_a; - wire [11:0] ovf_uid29_fxpToFPTest_b; - logic [11:0] ovf_uid29_fxpToFPTest_o; - wire [0:0] ovf_uid29_fxpToFPTest_n; - wire [0:0] excSelector_uid30_fxpToFPTest_q; - wire [22:0] fracZ_uid31_fxpToFPTest_q; - wire [0:0] fracRPostExc_uid32_fxpToFPTest_s; - reg [22:0] fracRPostExc_uid32_fxpToFPTest_q; - wire [0:0] udfOrInZero_uid33_fxpToFPTest_q; - wire [1:0] excSelector_uid34_fxpToFPTest_q; - wire [7:0] expZ_uid37_fxpToFPTest_q; - wire [7:0] expR_uid38_fxpToFPTest_in; - wire [7:0] expR_uid38_fxpToFPTest_b; - wire [1:0] expRPostExc_uid39_fxpToFPTest_s; - reg [7:0] expRPostExc_uid39_fxpToFPTest_q; - wire [31:0] outRes_uid40_fxpToFPTest_q; - wire [31:0] zs_uid42_lzcShifterZ1_uid10_fxpToFPTest_q; - wire [0:0] vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_qi; - reg [0:0] vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q; - wire [0:0] vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_s; - reg [31:0] vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q; - wire [15:0] zs_uid47_lzcShifterZ1_uid10_fxpToFPTest_q; - wire [0:0] vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q; - wire [31:0] cStage_uid52_lzcShifterZ1_uid10_fxpToFPTest_q; - wire [0:0] vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_s; - reg [31:0] vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q; - wire [0:0] vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q; - wire [31:0] cStage_uid59_lzcShifterZ1_uid10_fxpToFPTest_q; - wire [0:0] vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_s; - reg [31:0] vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q; - wire [3:0] zs_uid61_lzcShifterZ1_uid10_fxpToFPTest_q; - wire [0:0] vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q; - wire [31:0] cStage_uid66_lzcShifterZ1_uid10_fxpToFPTest_q; - wire [0:0] vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_s; - reg [31:0] vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q; - wire [1:0] zs_uid68_lzcShifterZ1_uid10_fxpToFPTest_q; - wire [0:0] vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q; - wire [31:0] cStage_uid73_lzcShifterZ1_uid10_fxpToFPTest_q; - wire [0:0] vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_s; - reg [31:0] vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q; - wire [0:0] vCount_uid77_lzcShifterZ1_uid10_fxpToFPTest_q; - wire [31:0] cStage_uid80_lzcShifterZ1_uid10_fxpToFPTest_q; - wire [0:0] vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_s; - reg [31:0] vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_q; - wire [5:0] vCount_uid82_lzcShifterZ1_uid10_fxpToFPTest_q; - wire [7:0] vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_a; - wire [7:0] vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_b; - logic [7:0] vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_o; - wire [0:0] vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_c; - wire [0:0] vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_s; - reg [5:0] vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q; - wire [1:0] l_uid17_fxpToFPTest_merged_bit_select_in; - wire [0:0] l_uid17_fxpToFPTest_merged_bit_select_b; - wire [0:0] l_uid17_fxpToFPTest_merged_bit_select_c; - wire [15:0] rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b; - wire [15:0] rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c; - wire [7:0] rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b; - wire [23:0] rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c; - wire [3:0] rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b; - wire [27:0] rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c; - wire [1:0] rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b; - wire [29:0] rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c; - wire [0:0] rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b; - wire [30:0] rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c; - wire [30:0] fracRnd_uid15_fxpToFPTest_merged_bit_select_in; - wire [23:0] fracRnd_uid15_fxpToFPTest_merged_bit_select_b; - wire [6:0] fracRnd_uid15_fxpToFPTest_merged_bit_select_c; - reg [23:0] redist0_fracRnd_uid15_fxpToFPTest_merged_bit_select_b_2_q; - reg [0:0] redist1_vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q_1_q; - reg [0:0] redist2_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_1_q; - reg [0:0] redist3_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_2_q; - reg [0:0] redist4_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_3_q; - reg [9:0] redist5_expR_uid26_fxpToFPTest_b_1_q; - reg [22:0] redist6_fracR_uid25_fxpToFPTest_b_1_q; - reg [0:0] redist7_sticky_uid20_fxpToFPTest_q_2_q; - reg [0:0] redist8_inIsZero_uid12_fxpToFPTest_q_2_q; - reg [31:0] redist9_y_uid9_fxpToFPTest_b_1_q; - reg [0:0] redist10_signX_uid6_fxpToFPTest_b_1_q; - reg [0:0] redist11_signX_uid6_fxpToFPTest_b_7_q; - - - // signX_uid6_fxpToFPTest(BITSELECT,5)@0 - assign signX_uid6_fxpToFPTest_b = a[31:31]; - - // redist10_signX_uid6_fxpToFPTest_b_1(DELAY,105) - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - redist10_signX_uid6_fxpToFPTest_b_1 ( .xin(signX_uid6_fxpToFPTest_b), .xout(redist10_signX_uid6_fxpToFPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist11_signX_uid6_fxpToFPTest_b_7(DELAY,106) - dspba_delay_ver #( .width(1), .depth(6), .reset_kind("ASYNC") ) - redist11_signX_uid6_fxpToFPTest_b_7 ( .xin(redist10_signX_uid6_fxpToFPTest_b_1_q), .xout(redist11_signX_uid6_fxpToFPTest_b_7_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // expInf_uid28_fxpToFPTest(CONSTANT,27) - assign expInf_uid28_fxpToFPTest_q = 8'b11111111; - - // expZ_uid37_fxpToFPTest(CONSTANT,36) - assign expZ_uid37_fxpToFPTest_q = 8'b00000000; - - // rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select(BITSELECT,93)@4 - assign rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b = vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q[31:31]; - assign rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c = vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q[30:0]; - - // GND(CONSTANT,0) - assign GND_q = 1'b0; - - // cStage_uid80_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,79)@4 - assign cStage_uid80_lzcShifterZ1_uid10_fxpToFPTest_q = {rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c, GND_q}; - - // rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select(BITSELECT,92)@4 - assign rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b = vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q[31:30]; - assign rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c = vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q[29:0]; - - // zs_uid68_lzcShifterZ1_uid10_fxpToFPTest(CONSTANT,67) - assign zs_uid68_lzcShifterZ1_uid10_fxpToFPTest_q = 2'b00; - - // cStage_uid73_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,72)@4 - assign cStage_uid73_lzcShifterZ1_uid10_fxpToFPTest_q = {rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c, zs_uid68_lzcShifterZ1_uid10_fxpToFPTest_q}; - - // rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select(BITSELECT,91)@3 - assign rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b = vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q[31:28]; - assign rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c = vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q[27:0]; - - // zs_uid61_lzcShifterZ1_uid10_fxpToFPTest(CONSTANT,60) - assign zs_uid61_lzcShifterZ1_uid10_fxpToFPTest_q = 4'b0000; - - // cStage_uid66_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,65)@3 - assign cStage_uid66_lzcShifterZ1_uid10_fxpToFPTest_q = {rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c, zs_uid61_lzcShifterZ1_uid10_fxpToFPTest_q}; - - // rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select(BITSELECT,90)@3 - assign rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b = vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q[31:24]; - assign rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c = vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q[23:0]; - - // cStage_uid59_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,58)@3 - assign cStage_uid59_lzcShifterZ1_uid10_fxpToFPTest_q = {rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c, expZ_uid37_fxpToFPTest_q}; - - // rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select(BITSELECT,89)@2 - assign rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b = vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q[31:16]; - assign rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c = vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q[15:0]; - - // zs_uid47_lzcShifterZ1_uid10_fxpToFPTest(CONSTANT,46) - assign zs_uid47_lzcShifterZ1_uid10_fxpToFPTest_q = 16'b0000000000000000; - - // cStage_uid52_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,51)@2 - assign cStage_uid52_lzcShifterZ1_uid10_fxpToFPTest_q = {rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c, zs_uid47_lzcShifterZ1_uid10_fxpToFPTest_q}; - - // zs_uid42_lzcShifterZ1_uid10_fxpToFPTest(CONSTANT,41) - assign zs_uid42_lzcShifterZ1_uid10_fxpToFPTest_q = 32'b00000000000000000000000000000000; - - // xXorSign_uid7_fxpToFPTest(LOGICAL,6)@0 + 1 - assign xXorSign_uid7_fxpToFPTest_b = {{31{signX_uid6_fxpToFPTest_b[0]}}, signX_uid6_fxpToFPTest_b}; - assign xXorSign_uid7_fxpToFPTest_qi = a ^ xXorSign_uid7_fxpToFPTest_b; - dspba_delay_ver #( .width(32), .depth(1), .reset_kind("ASYNC") ) - xXorSign_uid7_fxpToFPTest_delay ( .xin(xXorSign_uid7_fxpToFPTest_qi), .xout(xXorSign_uid7_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // yE_uid8_fxpToFPTest(ADD,7)@1 - assign yE_uid8_fxpToFPTest_a = {1'b0, xXorSign_uid7_fxpToFPTest_q}; - assign yE_uid8_fxpToFPTest_b = {32'b00000000000000000000000000000000, redist10_signX_uid6_fxpToFPTest_b_1_q}; - assign yE_uid8_fxpToFPTest_o = $unsigned(yE_uid8_fxpToFPTest_a) + $unsigned(yE_uid8_fxpToFPTest_b); - assign yE_uid8_fxpToFPTest_q = yE_uid8_fxpToFPTest_o[32:0]; - - // y_uid9_fxpToFPTest(BITSELECT,8)@1 - assign y_uid9_fxpToFPTest_in = yE_uid8_fxpToFPTest_q[31:0]; - assign y_uid9_fxpToFPTest_b = y_uid9_fxpToFPTest_in[31:0]; - - // redist9_y_uid9_fxpToFPTest_b_1(DELAY,104) - dspba_delay_ver #( .width(32), .depth(1), .reset_kind("ASYNC") ) - redist9_y_uid9_fxpToFPTest_b_1 ( .xin(y_uid9_fxpToFPTest_b), .xout(redist9_y_uid9_fxpToFPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,43)@1 + 1 - assign vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_qi = y_uid9_fxpToFPTest_b == zs_uid42_lzcShifterZ1_uid10_fxpToFPTest_q ? 1'b1 : 1'b0; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_delay ( .xin(vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_qi), .xout(vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest(MUX,45)@2 - assign vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q; - always @(vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_s or en or redist9_y_uid9_fxpToFPTest_b_1_q or zs_uid42_lzcShifterZ1_uid10_fxpToFPTest_q) - begin - unique case (vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_s) - 1'b0 : vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q = redist9_y_uid9_fxpToFPTest_b_1_q; - 1'b1 : vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q = zs_uid42_lzcShifterZ1_uid10_fxpToFPTest_q; - default : vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q = 32'b0; - endcase - end - - // vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,48)@2 - assign vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q = rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b == zs_uid47_lzcShifterZ1_uid10_fxpToFPTest_q ? 1'b1 : 1'b0; - - // vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest(MUX,52)@2 + 1 - assign vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q; - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q <= 32'b0; - end - else if (en == 1'b1) - begin - unique case (vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_s) - 1'b0 : vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q <= vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q; - 1'b1 : vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q <= cStage_uid52_lzcShifterZ1_uid10_fxpToFPTest_q; - default : vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q <= 32'b0; - endcase - end - end - - // vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,55)@3 - assign vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q = rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b == expZ_uid37_fxpToFPTest_q ? 1'b1 : 1'b0; - - // vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest(MUX,59)@3 - assign vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q; - always @(vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_s or en or vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q or cStage_uid59_lzcShifterZ1_uid10_fxpToFPTest_q) - begin - unique case (vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_s) - 1'b0 : vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q = vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q; - 1'b1 : vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q = cStage_uid59_lzcShifterZ1_uid10_fxpToFPTest_q; - default : vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q = 32'b0; - endcase - end - - // vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,62)@3 - assign vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q = rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b == zs_uid61_lzcShifterZ1_uid10_fxpToFPTest_q ? 1'b1 : 1'b0; - - // vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest(MUX,66)@3 + 1 - assign vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q; - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q <= 32'b0; - end - else if (en == 1'b1) - begin - unique case (vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_s) - 1'b0 : vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q <= vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q; - 1'b1 : vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q <= cStage_uid66_lzcShifterZ1_uid10_fxpToFPTest_q; - default : vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q <= 32'b0; - endcase - end - end - - // vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,69)@4 - assign vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q = rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b == zs_uid68_lzcShifterZ1_uid10_fxpToFPTest_q ? 1'b1 : 1'b0; - - // vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest(MUX,73)@4 - assign vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q; - always @(vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_s or en or vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q or cStage_uid73_lzcShifterZ1_uid10_fxpToFPTest_q) - begin - unique case (vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_s) - 1'b0 : vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q = vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q; - 1'b1 : vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q = cStage_uid73_lzcShifterZ1_uid10_fxpToFPTest_q; - default : vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q = 32'b0; - endcase - end - - // vCount_uid77_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,76)@4 - assign vCount_uid77_lzcShifterZ1_uid10_fxpToFPTest_q = rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b == GND_q ? 1'b1 : 1'b0; - - // vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest(MUX,80)@4 - assign vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid77_lzcShifterZ1_uid10_fxpToFPTest_q; - always @(vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_s or en or vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q or cStage_uid80_lzcShifterZ1_uid10_fxpToFPTest_q) - begin - unique case (vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_s) - 1'b0 : vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_q = vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q; - 1'b1 : vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_q = cStage_uid80_lzcShifterZ1_uid10_fxpToFPTest_q; - default : vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_q = 32'b0; - endcase - end - - // fracRnd_uid15_fxpToFPTest_merged_bit_select(BITSELECT,94)@4 - assign fracRnd_uid15_fxpToFPTest_merged_bit_select_in = vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_q[30:0]; - assign fracRnd_uid15_fxpToFPTest_merged_bit_select_b = fracRnd_uid15_fxpToFPTest_merged_bit_select_in[30:7]; - assign fracRnd_uid15_fxpToFPTest_merged_bit_select_c = fracRnd_uid15_fxpToFPTest_merged_bit_select_in[6:0]; - - // sticky_uid20_fxpToFPTest(LOGICAL,19)@4 + 1 - assign sticky_uid20_fxpToFPTest_qi = fracRnd_uid15_fxpToFPTest_merged_bit_select_c != 7'b0000000 ? 1'b1 : 1'b0; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - sticky_uid20_fxpToFPTest_delay ( .xin(sticky_uid20_fxpToFPTest_qi), .xout(sticky_uid20_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist7_sticky_uid20_fxpToFPTest_q_2(DELAY,102) - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - redist7_sticky_uid20_fxpToFPTest_q_2 ( .xin(sticky_uid20_fxpToFPTest_q), .xout(redist7_sticky_uid20_fxpToFPTest_q_2_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // nr_uid21_fxpToFPTest(LOGICAL,20)@6 - assign nr_uid21_fxpToFPTest_q = ~ (l_uid17_fxpToFPTest_merged_bit_select_c); - - // l_uid17_fxpToFPTest_merged_bit_select(BITSELECT,88)@6 - assign l_uid17_fxpToFPTest_merged_bit_select_in = expFracRnd_uid16_fxpToFPTest_q[1:0]; - assign l_uid17_fxpToFPTest_merged_bit_select_b = l_uid17_fxpToFPTest_merged_bit_select_in[1:1]; - assign l_uid17_fxpToFPTest_merged_bit_select_c = l_uid17_fxpToFPTest_merged_bit_select_in[0:0]; - - // rnd_uid22_fxpToFPTest(LOGICAL,21)@6 - assign rnd_uid22_fxpToFPTest_q = l_uid17_fxpToFPTest_merged_bit_select_b | nr_uid21_fxpToFPTest_q | redist7_sticky_uid20_fxpToFPTest_q_2_q; - - // maxCount_uid11_fxpToFPTest(CONSTANT,10) - assign maxCount_uid11_fxpToFPTest_q = 6'b100000; - - // redist4_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_3(DELAY,99) - dspba_delay_ver #( .width(1), .depth(2), .reset_kind("ASYNC") ) - redist4_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_3 ( .xin(vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q), .xout(redist4_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_3_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist3_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_2(DELAY,98) - dspba_delay_ver #( .width(1), .depth(2), .reset_kind("ASYNC") ) - redist3_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_2 ( .xin(vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q), .xout(redist3_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_2_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist2_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_1(DELAY,97) - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - redist2_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_1 ( .xin(vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q), .xout(redist2_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist1_vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q_1(DELAY,96) - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - redist1_vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q_1 ( .xin(vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q), .xout(redist1_vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // vCount_uid82_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,81)@4 - assign vCount_uid82_lzcShifterZ1_uid10_fxpToFPTest_q = {redist4_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_3_q, redist3_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_2_q, redist2_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_1_q, redist1_vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q_1_q, vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q, vCount_uid77_lzcShifterZ1_uid10_fxpToFPTest_q}; - - // vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest(COMPARE,83)@4 - assign vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_a = {2'b00, maxCount_uid11_fxpToFPTest_q}; - assign vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_b = {2'b00, vCount_uid82_lzcShifterZ1_uid10_fxpToFPTest_q}; - assign vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_o = $unsigned(vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_a) - $unsigned(vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_b); - assign vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_c[0] = vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_o[7]; - - // vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest(MUX,85)@4 + 1 - assign vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_s = vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_c; - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q <= 6'b0; - end - else if (en == 1'b1) - begin - unique case (vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_s) - 1'b0 : vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q <= vCount_uid82_lzcShifterZ1_uid10_fxpToFPTest_q; - 1'b1 : vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q <= maxCount_uid11_fxpToFPTest_q; - default : vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q <= 6'b0; - endcase - end - end - - // msbIn_uid13_fxpToFPTest(CONSTANT,12) - assign msbIn_uid13_fxpToFPTest_q = 8'b10011110; - - // expPreRnd_uid14_fxpToFPTest(SUB,13)@5 + 1 - assign expPreRnd_uid14_fxpToFPTest_a = {1'b0, msbIn_uid13_fxpToFPTest_q}; - assign expPreRnd_uid14_fxpToFPTest_b = {3'b000, vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q}; - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - expPreRnd_uid14_fxpToFPTest_o <= 9'b0; - end - else if (en == 1'b1) - begin - expPreRnd_uid14_fxpToFPTest_o <= $unsigned(expPreRnd_uid14_fxpToFPTest_a) - $unsigned(expPreRnd_uid14_fxpToFPTest_b); - end - end - assign expPreRnd_uid14_fxpToFPTest_q = expPreRnd_uid14_fxpToFPTest_o[8:0]; - - // redist0_fracRnd_uid15_fxpToFPTest_merged_bit_select_b_2(DELAY,95) - dspba_delay_ver #( .width(24), .depth(2), .reset_kind("ASYNC") ) - redist0_fracRnd_uid15_fxpToFPTest_merged_bit_select_b_2 ( .xin(fracRnd_uid15_fxpToFPTest_merged_bit_select_b), .xout(redist0_fracRnd_uid15_fxpToFPTest_merged_bit_select_b_2_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // expFracRnd_uid16_fxpToFPTest(BITJOIN,15)@6 - assign expFracRnd_uid16_fxpToFPTest_q = {expPreRnd_uid14_fxpToFPTest_q, redist0_fracRnd_uid15_fxpToFPTest_merged_bit_select_b_2_q}; - - // expFracR_uid24_fxpToFPTest(ADD,23)@6 - assign expFracR_uid24_fxpToFPTest_a = {{2{expFracRnd_uid16_fxpToFPTest_q[32]}}, expFracRnd_uid16_fxpToFPTest_q}; - assign expFracR_uid24_fxpToFPTest_b = {34'b0000000000000000000000000000000000, rnd_uid22_fxpToFPTest_q}; - assign expFracR_uid24_fxpToFPTest_o = $signed(expFracR_uid24_fxpToFPTest_a) + $signed(expFracR_uid24_fxpToFPTest_b); - assign expFracR_uid24_fxpToFPTest_q = expFracR_uid24_fxpToFPTest_o[33:0]; - - // expR_uid26_fxpToFPTest(BITSELECT,25)@6 - assign expR_uid26_fxpToFPTest_b = expFracR_uid24_fxpToFPTest_q[33:24]; - - // redist5_expR_uid26_fxpToFPTest_b_1(DELAY,100) - dspba_delay_ver #( .width(10), .depth(1), .reset_kind("ASYNC") ) - redist5_expR_uid26_fxpToFPTest_b_1 ( .xin(expR_uid26_fxpToFPTest_b), .xout(redist5_expR_uid26_fxpToFPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // expR_uid38_fxpToFPTest(BITSELECT,37)@7 - assign expR_uid38_fxpToFPTest_in = redist5_expR_uid26_fxpToFPTest_b_1_q[7:0]; - assign expR_uid38_fxpToFPTest_b = expR_uid38_fxpToFPTest_in[7:0]; - - // ovf_uid29_fxpToFPTest(COMPARE,28)@7 - assign ovf_uid29_fxpToFPTest_a = {{2{redist5_expR_uid26_fxpToFPTest_b_1_q[9]}}, redist5_expR_uid26_fxpToFPTest_b_1_q}; - assign ovf_uid29_fxpToFPTest_b = {4'b0000, expInf_uid28_fxpToFPTest_q}; - assign ovf_uid29_fxpToFPTest_o = $signed(ovf_uid29_fxpToFPTest_a) - $signed(ovf_uid29_fxpToFPTest_b); - assign ovf_uid29_fxpToFPTest_n[0] = ~ (ovf_uid29_fxpToFPTest_o[11]); - - // inIsZero_uid12_fxpToFPTest(LOGICAL,11)@5 + 1 - assign inIsZero_uid12_fxpToFPTest_qi = vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q == maxCount_uid11_fxpToFPTest_q ? 1'b1 : 1'b0; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - inIsZero_uid12_fxpToFPTest_delay ( .xin(inIsZero_uid12_fxpToFPTest_qi), .xout(inIsZero_uid12_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist8_inIsZero_uid12_fxpToFPTest_q_2(DELAY,103) - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - redist8_inIsZero_uid12_fxpToFPTest_q_2 ( .xin(inIsZero_uid12_fxpToFPTest_q), .xout(redist8_inIsZero_uid12_fxpToFPTest_q_2_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // udf_uid27_fxpToFPTest(COMPARE,26)@7 - assign udf_uid27_fxpToFPTest_a = {11'b00000000000, GND_q}; - assign udf_uid27_fxpToFPTest_b = {{2{redist5_expR_uid26_fxpToFPTest_b_1_q[9]}}, redist5_expR_uid26_fxpToFPTest_b_1_q}; - assign udf_uid27_fxpToFPTest_o = $signed(udf_uid27_fxpToFPTest_a) - $signed(udf_uid27_fxpToFPTest_b); - assign udf_uid27_fxpToFPTest_n[0] = ~ (udf_uid27_fxpToFPTest_o[11]); - - // udfOrInZero_uid33_fxpToFPTest(LOGICAL,32)@7 - assign udfOrInZero_uid33_fxpToFPTest_q = udf_uid27_fxpToFPTest_n | redist8_inIsZero_uid12_fxpToFPTest_q_2_q; - - // excSelector_uid34_fxpToFPTest(BITJOIN,33)@7 - assign excSelector_uid34_fxpToFPTest_q = {ovf_uid29_fxpToFPTest_n, udfOrInZero_uid33_fxpToFPTest_q}; - - // expRPostExc_uid39_fxpToFPTest(MUX,38)@7 - assign expRPostExc_uid39_fxpToFPTest_s = excSelector_uid34_fxpToFPTest_q; - always @(expRPostExc_uid39_fxpToFPTest_s or en or expR_uid38_fxpToFPTest_b or expZ_uid37_fxpToFPTest_q or expInf_uid28_fxpToFPTest_q) - begin - unique case (expRPostExc_uid39_fxpToFPTest_s) - 2'b00 : expRPostExc_uid39_fxpToFPTest_q = expR_uid38_fxpToFPTest_b; - 2'b01 : expRPostExc_uid39_fxpToFPTest_q = expZ_uid37_fxpToFPTest_q; - 2'b10 : expRPostExc_uid39_fxpToFPTest_q = expInf_uid28_fxpToFPTest_q; - 2'b11 : expRPostExc_uid39_fxpToFPTest_q = expInf_uid28_fxpToFPTest_q; - default : expRPostExc_uid39_fxpToFPTest_q = 8'b0; - endcase - end - - // fracZ_uid31_fxpToFPTest(CONSTANT,30) - assign fracZ_uid31_fxpToFPTest_q = 23'b00000000000000000000000; - - // fracR_uid25_fxpToFPTest(BITSELECT,24)@6 - assign fracR_uid25_fxpToFPTest_in = expFracR_uid24_fxpToFPTest_q[23:0]; - assign fracR_uid25_fxpToFPTest_b = fracR_uid25_fxpToFPTest_in[23:1]; - - // redist6_fracR_uid25_fxpToFPTest_b_1(DELAY,101) - dspba_delay_ver #( .width(23), .depth(1), .reset_kind("ASYNC") ) - redist6_fracR_uid25_fxpToFPTest_b_1 ( .xin(fracR_uid25_fxpToFPTest_b), .xout(redist6_fracR_uid25_fxpToFPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // excSelector_uid30_fxpToFPTest(LOGICAL,29)@7 - assign excSelector_uid30_fxpToFPTest_q = redist8_inIsZero_uid12_fxpToFPTest_q_2_q | ovf_uid29_fxpToFPTest_n | udf_uid27_fxpToFPTest_n; - - // fracRPostExc_uid32_fxpToFPTest(MUX,31)@7 - assign fracRPostExc_uid32_fxpToFPTest_s = excSelector_uid30_fxpToFPTest_q; - always @(fracRPostExc_uid32_fxpToFPTest_s or en or redist6_fracR_uid25_fxpToFPTest_b_1_q or fracZ_uid31_fxpToFPTest_q) - begin - unique case (fracRPostExc_uid32_fxpToFPTest_s) - 1'b0 : fracRPostExc_uid32_fxpToFPTest_q = redist6_fracR_uid25_fxpToFPTest_b_1_q; - 1'b1 : fracRPostExc_uid32_fxpToFPTest_q = fracZ_uid31_fxpToFPTest_q; - default : fracRPostExc_uid32_fxpToFPTest_q = 23'b0; - endcase - end - - // outRes_uid40_fxpToFPTest(BITJOIN,39)@7 - assign outRes_uid40_fxpToFPTest_q = {redist11_signX_uid6_fxpToFPTest_b_7_q, expRPostExc_uid39_fxpToFPTest_q, fracRPostExc_uid32_fxpToFPTest_q}; - - // xOut(GPOUT,4)@7 - assign q = outRes_uid40_fxpToFPTest_q; - -endmodule diff --git a/hw/rtl/fp_cores/altera/arria10/acl_utof.sv b/hw/rtl/fp_cores/altera/arria10/acl_utof.sv deleted file mode 100644 index 086bab11..00000000 --- a/hw/rtl/fp_cores/altera/arria10/acl_utof.sv +++ /dev/null @@ -1,486 +0,0 @@ -// ------------------------------------------------------------------------- -// High Level Design Compiler for Intel(R) FPGAs Version 17.1 (Release Build #273) -// Quartus Prime development tool and MATLAB/Simulink Interface -// -// Legal Notice: Copyright 2017 Intel Corporation. All rights reserved. -// Your use of Intel Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly -// subject to the terms and conditions of the Intel FPGA Software License -// Agreement, Intel MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for -// the sole purpose of programming logic devices manufactured by Intel -// and sold by Intel or its authorized distributors. Please refer to the -// applicable agreement for further details. -// --------------------------------------------------------------------------- - -// SystemVerilog created from acl_utof -// SystemVerilog created on Sun Dec 27 09:47:21 2020 - - -(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) -module acl_utof ( - input wire [31:0] a, - input wire [0:0] en, - output wire [31:0] q, - input wire clk, - input wire areset - ); - - wire [0:0] GND_q; - wire [5:0] maxCount_uid7_fxpToFPTest_q; - wire [0:0] inIsZero_uid8_fxpToFPTest_qi; - reg [0:0] inIsZero_uid8_fxpToFPTest_q; - wire [7:0] msbIn_uid9_fxpToFPTest_q; - wire [8:0] expPreRnd_uid10_fxpToFPTest_a; - wire [8:0] expPreRnd_uid10_fxpToFPTest_b; - logic [8:0] expPreRnd_uid10_fxpToFPTest_o; - wire [8:0] expPreRnd_uid10_fxpToFPTest_q; - wire [32:0] expFracRnd_uid12_fxpToFPTest_q; - wire [0:0] sticky_uid16_fxpToFPTest_qi; - reg [0:0] sticky_uid16_fxpToFPTest_q; - wire [0:0] nr_uid17_fxpToFPTest_q; - wire [0:0] rnd_uid18_fxpToFPTest_qi; - reg [0:0] rnd_uid18_fxpToFPTest_q; - wire [34:0] expFracR_uid20_fxpToFPTest_a; - wire [34:0] expFracR_uid20_fxpToFPTest_b; - logic [34:0] expFracR_uid20_fxpToFPTest_o; - wire [33:0] expFracR_uid20_fxpToFPTest_q; - wire [23:0] fracR_uid21_fxpToFPTest_in; - wire [22:0] fracR_uid21_fxpToFPTest_b; - wire [9:0] expR_uid22_fxpToFPTest_b; - wire [11:0] udf_uid23_fxpToFPTest_a; - wire [11:0] udf_uid23_fxpToFPTest_b; - logic [11:0] udf_uid23_fxpToFPTest_o; - wire [0:0] udf_uid23_fxpToFPTest_n; - wire [7:0] expInf_uid24_fxpToFPTest_q; - wire [11:0] ovf_uid25_fxpToFPTest_a; - wire [11:0] ovf_uid25_fxpToFPTest_b; - logic [11:0] ovf_uid25_fxpToFPTest_o; - wire [0:0] ovf_uid25_fxpToFPTest_n; - wire [0:0] excSelector_uid26_fxpToFPTest_q; - wire [22:0] fracZ_uid27_fxpToFPTest_q; - wire [0:0] fracRPostExc_uid28_fxpToFPTest_s; - reg [22:0] fracRPostExc_uid28_fxpToFPTest_q; - wire [0:0] udfOrInZero_uid29_fxpToFPTest_q; - wire [1:0] excSelector_uid30_fxpToFPTest_q; - wire [7:0] expZ_uid33_fxpToFPTest_q; - wire [7:0] expR_uid34_fxpToFPTest_in; - wire [7:0] expR_uid34_fxpToFPTest_b; - wire [1:0] expRPostExc_uid35_fxpToFPTest_s; - reg [7:0] expRPostExc_uid35_fxpToFPTest_q; - wire [31:0] outRes_uid36_fxpToFPTest_q; - wire [31:0] zs_uid38_lzcShifterZ1_uid6_fxpToFPTest_q; - wire [0:0] vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_qi; - reg [0:0] vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q; - wire [0:0] vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_s; - reg [31:0] vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q; - wire [15:0] zs_uid43_lzcShifterZ1_uid6_fxpToFPTest_q; - wire [0:0] vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q; - wire [31:0] cStage_uid48_lzcShifterZ1_uid6_fxpToFPTest_q; - wire [0:0] vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_s; - reg [31:0] vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q; - wire [0:0] vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q; - wire [31:0] cStage_uid55_lzcShifterZ1_uid6_fxpToFPTest_q; - wire [0:0] vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_s; - reg [31:0] vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q; - wire [3:0] zs_uid57_lzcShifterZ1_uid6_fxpToFPTest_q; - wire [0:0] vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q; - wire [31:0] cStage_uid62_lzcShifterZ1_uid6_fxpToFPTest_q; - wire [0:0] vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_s; - reg [31:0] vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q; - wire [1:0] zs_uid64_lzcShifterZ1_uid6_fxpToFPTest_q; - wire [0:0] vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q; - wire [31:0] cStage_uid69_lzcShifterZ1_uid6_fxpToFPTest_q; - wire [0:0] vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_s; - reg [31:0] vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q; - wire [0:0] vCount_uid73_lzcShifterZ1_uid6_fxpToFPTest_q; - wire [31:0] cStage_uid76_lzcShifterZ1_uid6_fxpToFPTest_q; - wire [0:0] vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_s; - reg [31:0] vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_q; - wire [5:0] vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q; - wire [7:0] vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_a; - wire [7:0] vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_b; - logic [7:0] vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_o; - wire [0:0] vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_c; - wire [0:0] vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_s; - reg [5:0] vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q; - wire [1:0] l_uid13_fxpToFPTest_merged_bit_select_in; - wire [0:0] l_uid13_fxpToFPTest_merged_bit_select_b; - wire [0:0] l_uid13_fxpToFPTest_merged_bit_select_c; - wire [15:0] rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b; - wire [15:0] rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c; - wire [7:0] rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b; - wire [23:0] rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c; - wire [3:0] rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b; - wire [27:0] rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c; - wire [1:0] rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b; - wire [29:0] rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c; - wire [0:0] rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b; - wire [30:0] rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c; - wire [30:0] fracRnd_uid11_fxpToFPTest_merged_bit_select_in; - wire [23:0] fracRnd_uid11_fxpToFPTest_merged_bit_select_b; - wire [6:0] fracRnd_uid11_fxpToFPTest_merged_bit_select_c; - reg [23:0] redist0_fracRnd_uid11_fxpToFPTest_merged_bit_select_b_1_q; - reg [0:0] redist1_vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q_1_q; - reg [0:0] redist2_vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q_1_q; - reg [0:0] redist3_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2_q; - reg [0:0] redist4_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_q; - reg [0:0] redist5_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_q; - reg [9:0] redist6_expR_uid22_fxpToFPTest_b_1_q; - reg [22:0] redist7_fracR_uid21_fxpToFPTest_b_1_q; - reg [32:0] redist8_expFracRnd_uid12_fxpToFPTest_q_1_q; - reg [0:0] redist9_inIsZero_uid8_fxpToFPTest_q_2_q; - reg [31:0] redist10_xIn_a_1_q; - - - // GND(CONSTANT,0) - assign GND_q = 1'b0; - - // expInf_uid24_fxpToFPTest(CONSTANT,23) - assign expInf_uid24_fxpToFPTest_q = 8'b11111111; - - // expZ_uid33_fxpToFPTest(CONSTANT,32) - assign expZ_uid33_fxpToFPTest_q = 8'b00000000; - - // rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select(BITSELECT,89)@4 - assign rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b = vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q[31:31]; - assign rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c = vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q[30:0]; - - // cStage_uid76_lzcShifterZ1_uid6_fxpToFPTest(BITJOIN,75)@4 - assign cStage_uid76_lzcShifterZ1_uid6_fxpToFPTest_q = {rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c, GND_q}; - - // rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select(BITSELECT,88)@3 - assign rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b = vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q[31:30]; - assign rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c = vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q[29:0]; - - // zs_uid64_lzcShifterZ1_uid6_fxpToFPTest(CONSTANT,63) - assign zs_uid64_lzcShifterZ1_uid6_fxpToFPTest_q = 2'b00; - - // cStage_uid69_lzcShifterZ1_uid6_fxpToFPTest(BITJOIN,68)@3 - assign cStage_uid69_lzcShifterZ1_uid6_fxpToFPTest_q = {rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c, zs_uid64_lzcShifterZ1_uid6_fxpToFPTest_q}; - - // rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select(BITSELECT,87)@3 - assign rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b = vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q[31:28]; - assign rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c = vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q[27:0]; - - // zs_uid57_lzcShifterZ1_uid6_fxpToFPTest(CONSTANT,56) - assign zs_uid57_lzcShifterZ1_uid6_fxpToFPTest_q = 4'b0000; - - // cStage_uid62_lzcShifterZ1_uid6_fxpToFPTest(BITJOIN,61)@3 - assign cStage_uid62_lzcShifterZ1_uid6_fxpToFPTest_q = {rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c, zs_uid57_lzcShifterZ1_uid6_fxpToFPTest_q}; - - // rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select(BITSELECT,86)@2 - assign rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b = vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q[31:24]; - assign rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c = vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q[23:0]; - - // cStage_uid55_lzcShifterZ1_uid6_fxpToFPTest(BITJOIN,54)@2 - assign cStage_uid55_lzcShifterZ1_uid6_fxpToFPTest_q = {rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c, expZ_uid33_fxpToFPTest_q}; - - // rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select(BITSELECT,85)@1 - assign rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b = vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q[31:16]; - assign rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c = vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q[15:0]; - - // zs_uid43_lzcShifterZ1_uid6_fxpToFPTest(CONSTANT,42) - assign zs_uid43_lzcShifterZ1_uid6_fxpToFPTest_q = 16'b0000000000000000; - - // cStage_uid48_lzcShifterZ1_uid6_fxpToFPTest(BITJOIN,47)@1 - assign cStage_uid48_lzcShifterZ1_uid6_fxpToFPTest_q = {rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c, zs_uid43_lzcShifterZ1_uid6_fxpToFPTest_q}; - - // zs_uid38_lzcShifterZ1_uid6_fxpToFPTest(CONSTANT,37) - assign zs_uid38_lzcShifterZ1_uid6_fxpToFPTest_q = 32'b00000000000000000000000000000000; - - // redist10_xIn_a_1(DELAY,101) - dspba_delay_ver #( .width(32), .depth(1), .reset_kind("ASYNC") ) - redist10_xIn_a_1 ( .xin(a), .xout(redist10_xIn_a_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest(LOGICAL,39)@0 + 1 - assign vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_qi = a == zs_uid38_lzcShifterZ1_uid6_fxpToFPTest_q ? 1'b1 : 1'b0; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_delay ( .xin(vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_qi), .xout(vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest(MUX,41)@1 - assign vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_s = vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q; - always @(vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_s or en or redist10_xIn_a_1_q or zs_uid38_lzcShifterZ1_uid6_fxpToFPTest_q) - begin - unique case (vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_s) - 1'b0 : vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q = redist10_xIn_a_1_q; - 1'b1 : vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q = zs_uid38_lzcShifterZ1_uid6_fxpToFPTest_q; - default : vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q = 32'b0; - endcase - end - - // vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest(LOGICAL,44)@1 - assign vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q = rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b == zs_uid43_lzcShifterZ1_uid6_fxpToFPTest_q ? 1'b1 : 1'b0; - - // vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest(MUX,48)@1 + 1 - assign vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_s = vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q; - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0; - end - else if (en == 1'b1) - begin - unique case (vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_s) - 1'b0 : vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q <= vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q; - 1'b1 : vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q <= cStage_uid48_lzcShifterZ1_uid6_fxpToFPTest_q; - default : vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0; - endcase - end - end - - // vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest(LOGICAL,51)@2 - assign vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q = rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b == expZ_uid33_fxpToFPTest_q ? 1'b1 : 1'b0; - - // vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest(MUX,55)@2 + 1 - assign vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_s = vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q; - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0; - end - else if (en == 1'b1) - begin - unique case (vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_s) - 1'b0 : vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q <= vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q; - 1'b1 : vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q <= cStage_uid55_lzcShifterZ1_uid6_fxpToFPTest_q; - default : vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0; - endcase - end - end - - // vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest(LOGICAL,58)@3 - assign vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q = rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b == zs_uid57_lzcShifterZ1_uid6_fxpToFPTest_q ? 1'b1 : 1'b0; - - // vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest(MUX,62)@3 - assign vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_s = vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q; - always @(vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_s or en or vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q or cStage_uid62_lzcShifterZ1_uid6_fxpToFPTest_q) - begin - unique case (vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_s) - 1'b0 : vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q = vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q; - 1'b1 : vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q = cStage_uid62_lzcShifterZ1_uid6_fxpToFPTest_q; - default : vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q = 32'b0; - endcase - end - - // vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest(LOGICAL,65)@3 - assign vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q = rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b == zs_uid64_lzcShifterZ1_uid6_fxpToFPTest_q ? 1'b1 : 1'b0; - - // vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest(MUX,69)@3 + 1 - assign vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_s = vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q; - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0; - end - else if (en == 1'b1) - begin - unique case (vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_s) - 1'b0 : vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q <= vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q; - 1'b1 : vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q <= cStage_uid69_lzcShifterZ1_uid6_fxpToFPTest_q; - default : vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0; - endcase - end - end - - // vCount_uid73_lzcShifterZ1_uid6_fxpToFPTest(LOGICAL,72)@4 - assign vCount_uid73_lzcShifterZ1_uid6_fxpToFPTest_q = rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b == GND_q ? 1'b1 : 1'b0; - - // vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest(MUX,76)@4 - assign vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_s = vCount_uid73_lzcShifterZ1_uid6_fxpToFPTest_q; - always @(vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_s or en or vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q or cStage_uid76_lzcShifterZ1_uid6_fxpToFPTest_q) - begin - unique case (vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_s) - 1'b0 : vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_q = vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q; - 1'b1 : vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_q = cStage_uid76_lzcShifterZ1_uid6_fxpToFPTest_q; - default : vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_q = 32'b0; - endcase - end - - // fracRnd_uid11_fxpToFPTest_merged_bit_select(BITSELECT,90)@4 - assign fracRnd_uid11_fxpToFPTest_merged_bit_select_in = vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_q[30:0]; - assign fracRnd_uid11_fxpToFPTest_merged_bit_select_b = fracRnd_uid11_fxpToFPTest_merged_bit_select_in[30:7]; - assign fracRnd_uid11_fxpToFPTest_merged_bit_select_c = fracRnd_uid11_fxpToFPTest_merged_bit_select_in[6:0]; - - // sticky_uid16_fxpToFPTest(LOGICAL,15)@4 + 1 - assign sticky_uid16_fxpToFPTest_qi = fracRnd_uid11_fxpToFPTest_merged_bit_select_c != 7'b0000000 ? 1'b1 : 1'b0; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - sticky_uid16_fxpToFPTest_delay ( .xin(sticky_uid16_fxpToFPTest_qi), .xout(sticky_uid16_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // nr_uid17_fxpToFPTest(LOGICAL,16)@5 - assign nr_uid17_fxpToFPTest_q = ~ (l_uid13_fxpToFPTest_merged_bit_select_c); - - // maxCount_uid7_fxpToFPTest(CONSTANT,6) - assign maxCount_uid7_fxpToFPTest_q = 6'b100000; - - // redist5_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4(DELAY,96) - dspba_delay_ver #( .width(1), .depth(3), .reset_kind("ASYNC") ) - redist5_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4 ( .xin(vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q), .xout(redist5_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist4_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3(DELAY,95) - dspba_delay_ver #( .width(1), .depth(3), .reset_kind("ASYNC") ) - redist4_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3 ( .xin(vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q), .xout(redist4_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist3_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2(DELAY,94) - dspba_delay_ver #( .width(1), .depth(2), .reset_kind("ASYNC") ) - redist3_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2 ( .xin(vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q), .xout(redist3_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist2_vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q_1(DELAY,93) - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - redist2_vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q_1 ( .xin(vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q), .xout(redist2_vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist1_vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q_1(DELAY,92) - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - redist1_vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q_1 ( .xin(vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q), .xout(redist1_vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest(BITJOIN,77)@4 - assign vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q = {redist5_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_q, redist4_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_q, redist3_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2_q, redist2_vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q_1_q, redist1_vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q_1_q, vCount_uid73_lzcShifterZ1_uid6_fxpToFPTest_q}; - - // vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest(COMPARE,79)@4 - assign vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_a = {2'b00, maxCount_uid7_fxpToFPTest_q}; - assign vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_b = {2'b00, vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q}; - assign vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_o = $unsigned(vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_a) - $unsigned(vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_b); - assign vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_c[0] = vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_o[7]; - - // vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest(MUX,81)@4 + 1 - assign vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_s = vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_c; - always @ (posedge clk or posedge areset) - begin - if (areset) - begin - vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q <= 6'b0; - end - else if (en == 1'b1) - begin - unique case (vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_s) - 1'b0 : vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q <= vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q; - 1'b1 : vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q <= maxCount_uid7_fxpToFPTest_q; - default : vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q <= 6'b0; - endcase - end - end - - // msbIn_uid9_fxpToFPTest(CONSTANT,8) - assign msbIn_uid9_fxpToFPTest_q = 8'b10011110; - - // expPreRnd_uid10_fxpToFPTest(SUB,9)@5 - assign expPreRnd_uid10_fxpToFPTest_a = {1'b0, msbIn_uid9_fxpToFPTest_q}; - assign expPreRnd_uid10_fxpToFPTest_b = {3'b000, vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q}; - assign expPreRnd_uid10_fxpToFPTest_o = $unsigned(expPreRnd_uid10_fxpToFPTest_a) - $unsigned(expPreRnd_uid10_fxpToFPTest_b); - assign expPreRnd_uid10_fxpToFPTest_q = expPreRnd_uid10_fxpToFPTest_o[8:0]; - - // redist0_fracRnd_uid11_fxpToFPTest_merged_bit_select_b_1(DELAY,91) - dspba_delay_ver #( .width(24), .depth(1), .reset_kind("ASYNC") ) - redist0_fracRnd_uid11_fxpToFPTest_merged_bit_select_b_1 ( .xin(fracRnd_uid11_fxpToFPTest_merged_bit_select_b), .xout(redist0_fracRnd_uid11_fxpToFPTest_merged_bit_select_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // expFracRnd_uid12_fxpToFPTest(BITJOIN,11)@5 - assign expFracRnd_uid12_fxpToFPTest_q = {expPreRnd_uid10_fxpToFPTest_q, redist0_fracRnd_uid11_fxpToFPTest_merged_bit_select_b_1_q}; - - // l_uid13_fxpToFPTest_merged_bit_select(BITSELECT,84)@5 - assign l_uid13_fxpToFPTest_merged_bit_select_in = expFracRnd_uid12_fxpToFPTest_q[1:0]; - assign l_uid13_fxpToFPTest_merged_bit_select_b = l_uid13_fxpToFPTest_merged_bit_select_in[1:1]; - assign l_uid13_fxpToFPTest_merged_bit_select_c = l_uid13_fxpToFPTest_merged_bit_select_in[0:0]; - - // rnd_uid18_fxpToFPTest(LOGICAL,17)@5 + 1 - assign rnd_uid18_fxpToFPTest_qi = l_uid13_fxpToFPTest_merged_bit_select_b | nr_uid17_fxpToFPTest_q | sticky_uid16_fxpToFPTest_q; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - rnd_uid18_fxpToFPTest_delay ( .xin(rnd_uid18_fxpToFPTest_qi), .xout(rnd_uid18_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist8_expFracRnd_uid12_fxpToFPTest_q_1(DELAY,99) - dspba_delay_ver #( .width(33), .depth(1), .reset_kind("ASYNC") ) - redist8_expFracRnd_uid12_fxpToFPTest_q_1 ( .xin(expFracRnd_uid12_fxpToFPTest_q), .xout(redist8_expFracRnd_uid12_fxpToFPTest_q_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // expFracR_uid20_fxpToFPTest(ADD,19)@6 - assign expFracR_uid20_fxpToFPTest_a = {{2{redist8_expFracRnd_uid12_fxpToFPTest_q_1_q[32]}}, redist8_expFracRnd_uid12_fxpToFPTest_q_1_q}; - assign expFracR_uid20_fxpToFPTest_b = {34'b0000000000000000000000000000000000, rnd_uid18_fxpToFPTest_q}; - assign expFracR_uid20_fxpToFPTest_o = $signed(expFracR_uid20_fxpToFPTest_a) + $signed(expFracR_uid20_fxpToFPTest_b); - assign expFracR_uid20_fxpToFPTest_q = expFracR_uid20_fxpToFPTest_o[33:0]; - - // expR_uid22_fxpToFPTest(BITSELECT,21)@6 - assign expR_uid22_fxpToFPTest_b = expFracR_uid20_fxpToFPTest_q[33:24]; - - // redist6_expR_uid22_fxpToFPTest_b_1(DELAY,97) - dspba_delay_ver #( .width(10), .depth(1), .reset_kind("ASYNC") ) - redist6_expR_uid22_fxpToFPTest_b_1 ( .xin(expR_uid22_fxpToFPTest_b), .xout(redist6_expR_uid22_fxpToFPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // expR_uid34_fxpToFPTest(BITSELECT,33)@7 - assign expR_uid34_fxpToFPTest_in = redist6_expR_uid22_fxpToFPTest_b_1_q[7:0]; - assign expR_uid34_fxpToFPTest_b = expR_uid34_fxpToFPTest_in[7:0]; - - // ovf_uid25_fxpToFPTest(COMPARE,24)@7 - assign ovf_uid25_fxpToFPTest_a = {{2{redist6_expR_uid22_fxpToFPTest_b_1_q[9]}}, redist6_expR_uid22_fxpToFPTest_b_1_q}; - assign ovf_uid25_fxpToFPTest_b = {4'b0000, expInf_uid24_fxpToFPTest_q}; - assign ovf_uid25_fxpToFPTest_o = $signed(ovf_uid25_fxpToFPTest_a) - $signed(ovf_uid25_fxpToFPTest_b); - assign ovf_uid25_fxpToFPTest_n[0] = ~ (ovf_uid25_fxpToFPTest_o[11]); - - // inIsZero_uid8_fxpToFPTest(LOGICAL,7)@5 + 1 - assign inIsZero_uid8_fxpToFPTest_qi = vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q == maxCount_uid7_fxpToFPTest_q ? 1'b1 : 1'b0; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - inIsZero_uid8_fxpToFPTest_delay ( .xin(inIsZero_uid8_fxpToFPTest_qi), .xout(inIsZero_uid8_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist9_inIsZero_uid8_fxpToFPTest_q_2(DELAY,100) - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) - redist9_inIsZero_uid8_fxpToFPTest_q_2 ( .xin(inIsZero_uid8_fxpToFPTest_q), .xout(redist9_inIsZero_uid8_fxpToFPTest_q_2_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // udf_uid23_fxpToFPTest(COMPARE,22)@7 - assign udf_uid23_fxpToFPTest_a = {11'b00000000000, GND_q}; - assign udf_uid23_fxpToFPTest_b = {{2{redist6_expR_uid22_fxpToFPTest_b_1_q[9]}}, redist6_expR_uid22_fxpToFPTest_b_1_q}; - assign udf_uid23_fxpToFPTest_o = $signed(udf_uid23_fxpToFPTest_a) - $signed(udf_uid23_fxpToFPTest_b); - assign udf_uid23_fxpToFPTest_n[0] = ~ (udf_uid23_fxpToFPTest_o[11]); - - // udfOrInZero_uid29_fxpToFPTest(LOGICAL,28)@7 - assign udfOrInZero_uid29_fxpToFPTest_q = udf_uid23_fxpToFPTest_n | redist9_inIsZero_uid8_fxpToFPTest_q_2_q; - - // excSelector_uid30_fxpToFPTest(BITJOIN,29)@7 - assign excSelector_uid30_fxpToFPTest_q = {ovf_uid25_fxpToFPTest_n, udfOrInZero_uid29_fxpToFPTest_q}; - - // expRPostExc_uid35_fxpToFPTest(MUX,34)@7 - assign expRPostExc_uid35_fxpToFPTest_s = excSelector_uid30_fxpToFPTest_q; - always @(expRPostExc_uid35_fxpToFPTest_s or en or expR_uid34_fxpToFPTest_b or expZ_uid33_fxpToFPTest_q or expInf_uid24_fxpToFPTest_q) - begin - unique case (expRPostExc_uid35_fxpToFPTest_s) - 2'b00 : expRPostExc_uid35_fxpToFPTest_q = expR_uid34_fxpToFPTest_b; - 2'b01 : expRPostExc_uid35_fxpToFPTest_q = expZ_uid33_fxpToFPTest_q; - 2'b10 : expRPostExc_uid35_fxpToFPTest_q = expInf_uid24_fxpToFPTest_q; - 2'b11 : expRPostExc_uid35_fxpToFPTest_q = expInf_uid24_fxpToFPTest_q; - default : expRPostExc_uid35_fxpToFPTest_q = 8'b0; - endcase - end - - // fracZ_uid27_fxpToFPTest(CONSTANT,26) - assign fracZ_uid27_fxpToFPTest_q = 23'b00000000000000000000000; - - // fracR_uid21_fxpToFPTest(BITSELECT,20)@6 - assign fracR_uid21_fxpToFPTest_in = expFracR_uid20_fxpToFPTest_q[23:0]; - assign fracR_uid21_fxpToFPTest_b = fracR_uid21_fxpToFPTest_in[23:1]; - - // redist7_fracR_uid21_fxpToFPTest_b_1(DELAY,98) - dspba_delay_ver #( .width(23), .depth(1), .reset_kind("ASYNC") ) - redist7_fracR_uid21_fxpToFPTest_b_1 ( .xin(fracR_uid21_fxpToFPTest_b), .xout(redist7_fracR_uid21_fxpToFPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // excSelector_uid26_fxpToFPTest(LOGICAL,25)@7 - assign excSelector_uid26_fxpToFPTest_q = redist9_inIsZero_uid8_fxpToFPTest_q_2_q | ovf_uid25_fxpToFPTest_n | udf_uid23_fxpToFPTest_n; - - // fracRPostExc_uid28_fxpToFPTest(MUX,27)@7 - assign fracRPostExc_uid28_fxpToFPTest_s = excSelector_uid26_fxpToFPTest_q; - always @(fracRPostExc_uid28_fxpToFPTest_s or en or redist7_fracR_uid21_fxpToFPTest_b_1_q or fracZ_uid27_fxpToFPTest_q) - begin - unique case (fracRPostExc_uid28_fxpToFPTest_s) - 1'b0 : fracRPostExc_uid28_fxpToFPTest_q = redist7_fracR_uid21_fxpToFPTest_b_1_q; - 1'b1 : fracRPostExc_uid28_fxpToFPTest_q = fracZ_uid27_fxpToFPTest_q; - default : fracRPostExc_uid28_fxpToFPTest_q = 23'b0; - endcase - end - - // outRes_uid36_fxpToFPTest(BITJOIN,35)@7 - assign outRes_uid36_fxpToFPTest_q = {GND_q, expRPostExc_uid35_fxpToFPTest_q, fracRPostExc_uid28_fxpToFPTest_q}; - - // xOut(GPOUT,4)@7 - assign q = outRes_uid36_fxpToFPTest_q; - -endmodule diff --git a/hw/rtl/fp_cores/altera/stratix10/acl_ftoi.sv b/hw/rtl/fp_cores/altera/stratix10/acl_ftoi.sv deleted file mode 100644 index 01b08c53..00000000 --- a/hw/rtl/fp_cores/altera/stratix10/acl_ftoi.sv +++ /dev/null @@ -1,586 +0,0 @@ -// ------------------------------------------------------------------------- -// High Level Design Compiler for Intel(R) FPGAs Version 18.1 (Release Build #277) -// Quartus Prime development tool and MATLAB/Simulink Interface -// -// Legal Notice: Copyright 2019 Intel Corporation. All rights reserved. -// Your use of Intel Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly -// subject to the terms and conditions of the Intel FPGA Software License -// Agreement, Intel MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for -// the sole purpose of programming logic devices manufactured by Intel -// and sold by Intel or its authorized distributors. Please refer to the -// applicable agreement for further details. -// --------------------------------------------------------------------------- - -// SystemVerilog created from acl_ftoi -// SystemVerilog created on Sun Dec 27 09:48:58 2020 - - -(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) -module acl_ftoi ( - input wire [31:0] a, - input wire [0:0] en, - output wire [31:0] q, - input wire clk, - input wire areset - ); - - wire [0:0] GND_q; - wire [7:0] cstAllOWE_uid6_fpToFxPTest_q; - wire [22:0] cstZeroWF_uid7_fpToFxPTest_q; - wire [7:0] cstAllZWE_uid8_fpToFxPTest_q; - wire [7:0] exp_x_uid9_fpToFxPTest_b; - wire [22:0] frac_x_uid10_fpToFxPTest_b; - wire [0:0] excZ_x_uid11_fpToFxPTest_q; - wire [0:0] expXIsMax_uid12_fpToFxPTest_q; - wire [0:0] fracXIsZero_uid13_fpToFxPTest_q; - wire [0:0] fracXIsNotZero_uid14_fpToFxPTest_q; - wire [0:0] excI_x_uid15_fpToFxPTest_qi; - reg [0:0] excI_x_uid15_fpToFxPTest_q; - wire [0:0] excN_x_uid16_fpToFxPTest_q; - wire [0:0] fracPostZ_uid23_fpToFxPTest_s; - reg [22:0] fracPostZ_uid23_fpToFxPTest_q; - wire [0:0] invExcXZ_uid24_fpToFxPTest_qi; - reg [0:0] invExcXZ_uid24_fpToFxPTest_q; - wire [23:0] oFracX_uid25_fpToFxPTest_q; - wire [0:0] signX_uid27_fpToFxPTest_b; - wire [0:0] notNan_uid28_fpToFxPTest_q; - wire [0:0] signX_uid29_fpToFxPTest_qi; - reg [0:0] signX_uid29_fpToFxPTest_q; - wire [8:0] ovfExpVal_uid30_fpToFxPTest_q; - wire [10:0] ovfExpRange_uid31_fpToFxPTest_a; - wire [10:0] ovfExpRange_uid31_fpToFxPTest_b; - logic [10:0] ovfExpRange_uid31_fpToFxPTest_o; - wire [0:0] ovfExpRange_uid31_fpToFxPTest_n; - wire [7:0] udfExpVal_uid32_fpToFxPTest_q; - wire [10:0] udf_uid33_fpToFxPTest_a; - wire [10:0] udf_uid33_fpToFxPTest_b; - logic [10:0] udf_uid33_fpToFxPTest_o; - wire [0:0] udf_uid33_fpToFxPTest_n; - wire [8:0] ovfExpVal_uid34_fpToFxPTest_q; - wire [10:0] shiftValE_uid35_fpToFxPTest_a; - wire [10:0] shiftValE_uid35_fpToFxPTest_b; - logic [10:0] shiftValE_uid35_fpToFxPTest_o; - wire [9:0] shiftValE_uid35_fpToFxPTest_q; - wire [5:0] shiftValRaw_uid36_fpToFxPTest_in; - wire [5:0] shiftValRaw_uid36_fpToFxPTest_b; - wire [5:0] maxShiftCst_uid37_fpToFxPTest_q; - wire [11:0] shiftOutOfRange_uid38_fpToFxPTest_a; - wire [11:0] shiftOutOfRange_uid38_fpToFxPTest_b; - logic [11:0] shiftOutOfRange_uid38_fpToFxPTest_o; - wire [0:0] shiftOutOfRange_uid38_fpToFxPTest_n; - wire [0:0] shiftVal_uid39_fpToFxPTest_s; - reg [5:0] shiftVal_uid39_fpToFxPTest_q; - wire [31:0] shifterIn_uid41_fpToFxPTest_q; - wire [31:0] maxPosValueS_uid43_fpToFxPTest_q; - wire [31:0] maxNegValueS_uid44_fpToFxPTest_q; - wire [32:0] zRightShiferNoStickyOut_uid45_fpToFxPTest_q; - wire [32:0] xXorSignE_uid46_fpToFxPTest_b; - wire [32:0] xXorSignE_uid46_fpToFxPTest_qi; - reg [32:0] xXorSignE_uid46_fpToFxPTest_q; - wire [2:0] d0_uid47_fpToFxPTest_q; - wire [33:0] sPostRndFull_uid48_fpToFxPTest_a; - wire [33:0] sPostRndFull_uid48_fpToFxPTest_b; - logic [33:0] sPostRndFull_uid48_fpToFxPTest_o; - wire [33:0] sPostRndFull_uid48_fpToFxPTest_q; - wire [32:0] sPostRnd_uid49_fpToFxPTest_in; - wire [31:0] sPostRnd_uid49_fpToFxPTest_b; - wire [34:0] sPostRnd_uid50_fpToFxPTest_in; - wire [33:0] sPostRnd_uid50_fpToFxPTest_b; - wire [35:0] rndOvfPos_uid51_fpToFxPTest_a; - wire [35:0] rndOvfPos_uid51_fpToFxPTest_b; - logic [35:0] rndOvfPos_uid51_fpToFxPTest_o; - wire [0:0] rndOvfPos_uid51_fpToFxPTest_c; - wire [0:0] ovfPostRnd_uid52_fpToFxPTest_q; - wire [2:0] muxSelConc_uid53_fpToFxPTest_q; - reg [1:0] muxSel_uid54_fpToFxPTest_q; - wire [31:0] maxNegValueU_uid55_fpToFxPTest_q; - wire [1:0] finalOut_uid56_fpToFxPTest_s; - reg [31:0] finalOut_uid56_fpToFxPTest_q; - wire [30:0] rightShiftStage0Idx1Rng1_uid60_rightShiferNoStickyOut_uid42_fpToFxPTest_b; - wire [31:0] rightShiftStage0Idx1_uid62_rightShiferNoStickyOut_uid42_fpToFxPTest_q; - wire [29:0] rightShiftStage0Idx2Rng2_uid63_rightShiferNoStickyOut_uid42_fpToFxPTest_b; - wire [1:0] rightShiftStage0Idx2Pad2_uid64_rightShiferNoStickyOut_uid42_fpToFxPTest_q; - wire [31:0] rightShiftStage0Idx2_uid65_rightShiferNoStickyOut_uid42_fpToFxPTest_q; - wire [28:0] rightShiftStage0Idx3Rng3_uid66_rightShiferNoStickyOut_uid42_fpToFxPTest_b; - wire [2:0] rightShiftStage0Idx3Pad3_uid67_rightShiferNoStickyOut_uid42_fpToFxPTest_q; - wire [31:0] rightShiftStage0Idx3_uid68_rightShiferNoStickyOut_uid42_fpToFxPTest_q; - wire [1:0] rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_s; - reg [31:0] rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_q; - wire [27:0] rightShiftStage1Idx1Rng4_uid71_rightShiferNoStickyOut_uid42_fpToFxPTest_b; - wire [3:0] rightShiftStage1Idx1Pad4_uid72_rightShiferNoStickyOut_uid42_fpToFxPTest_q; - wire [31:0] rightShiftStage1Idx1_uid73_rightShiferNoStickyOut_uid42_fpToFxPTest_q; - wire [23:0] rightShiftStage1Idx2Rng8_uid74_rightShiferNoStickyOut_uid42_fpToFxPTest_b; - wire [31:0] rightShiftStage1Idx2_uid76_rightShiferNoStickyOut_uid42_fpToFxPTest_q; - wire [19:0] rightShiftStage1Idx3Rng12_uid77_rightShiferNoStickyOut_uid42_fpToFxPTest_b; - wire [11:0] rightShiftStage1Idx3Pad12_uid78_rightShiferNoStickyOut_uid42_fpToFxPTest_q; - wire [31:0] rightShiftStage1Idx3_uid79_rightShiferNoStickyOut_uid42_fpToFxPTest_q; - wire [1:0] rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest_s; - reg [31:0] rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest_q; - wire [15:0] rightShiftStage2Idx1Rng16_uid82_rightShiferNoStickyOut_uid42_fpToFxPTest_b; - wire [15:0] rightShiftStage2Idx1Pad16_uid83_rightShiferNoStickyOut_uid42_fpToFxPTest_q; - wire [31:0] rightShiftStage2Idx1_uid84_rightShiferNoStickyOut_uid42_fpToFxPTest_q; - wire [1:0] rightShiftStage2_uid88_rightShiferNoStickyOut_uid42_fpToFxPTest_s; - reg [31:0] rightShiftStage2_uid88_rightShiferNoStickyOut_uid42_fpToFxPTest_q; - wire [1:0] rightShiftStageSel0Dto0_uid69_rightShiferNoStickyOut_uid42_fpToFxPTest_merged_bit_select_b; - wire [1:0] rightShiftStageSel0Dto0_uid69_rightShiferNoStickyOut_uid42_fpToFxPTest_merged_bit_select_c; - wire [1:0] rightShiftStageSel0Dto0_uid69_rightShiferNoStickyOut_uid42_fpToFxPTest_merged_bit_select_d; - reg [31:0] redist0_sPostRnd_uid49_fpToFxPTest_b_1_q; - reg [0:0] redist1_udf_uid33_fpToFxPTest_n_3_q; - reg [0:0] redist1_udf_uid33_fpToFxPTest_n_3_delay_0; - reg [0:0] redist2_ovfExpRange_uid31_fpToFxPTest_n_3_q; - reg [0:0] redist2_ovfExpRange_uid31_fpToFxPTest_n_3_delay_0; - reg [0:0] redist3_signX_uid29_fpToFxPTest_q_3_q; - reg [0:0] redist3_signX_uid29_fpToFxPTest_q_3_delay_0; - reg [0:0] redist4_excN_x_uid16_fpToFxPTest_q_3_q; - reg [0:0] redist4_excN_x_uid16_fpToFxPTest_q_3_delay_0; - reg [0:0] redist4_excN_x_uid16_fpToFxPTest_q_3_delay_1; - reg [0:0] redist5_excI_x_uid15_fpToFxPTest_q_3_q; - reg [0:0] redist5_excI_x_uid15_fpToFxPTest_q_3_delay_0; - - - // maxNegValueU_uid55_fpToFxPTest(CONSTANT,54) - assign maxNegValueU_uid55_fpToFxPTest_q = 32'b00000000000000000000000000000000; - - // maxNegValueS_uid44_fpToFxPTest(CONSTANT,43) - assign maxNegValueS_uid44_fpToFxPTest_q = 32'b10000000000000000000000000000000; - - // maxPosValueS_uid43_fpToFxPTest(CONSTANT,42) - assign maxPosValueS_uid43_fpToFxPTest_q = 32'b01111111111111111111111111111111; - - // d0_uid47_fpToFxPTest(CONSTANT,46) - assign d0_uid47_fpToFxPTest_q = 3'b001; - - // signX_uid27_fpToFxPTest(BITSELECT,26)@0 - assign signX_uid27_fpToFxPTest_b = a[31:31]; - - // frac_x_uid10_fpToFxPTest(BITSELECT,9)@0 - assign frac_x_uid10_fpToFxPTest_b = a[22:0]; - - // cstZeroWF_uid7_fpToFxPTest(CONSTANT,6) - assign cstZeroWF_uid7_fpToFxPTest_q = 23'b00000000000000000000000; - - // fracXIsZero_uid13_fpToFxPTest(LOGICAL,12)@0 - assign fracXIsZero_uid13_fpToFxPTest_q = cstZeroWF_uid7_fpToFxPTest_q == frac_x_uid10_fpToFxPTest_b ? 1'b1 : 1'b0; - - // fracXIsNotZero_uid14_fpToFxPTest(LOGICAL,13)@0 - assign fracXIsNotZero_uid14_fpToFxPTest_q = ~ (fracXIsZero_uid13_fpToFxPTest_q); - - // cstAllOWE_uid6_fpToFxPTest(CONSTANT,5) - assign cstAllOWE_uid6_fpToFxPTest_q = 8'b11111111; - - // exp_x_uid9_fpToFxPTest(BITSELECT,8)@0 - assign exp_x_uid9_fpToFxPTest_b = a[30:23]; - - // expXIsMax_uid12_fpToFxPTest(LOGICAL,11)@0 - assign expXIsMax_uid12_fpToFxPTest_q = exp_x_uid9_fpToFxPTest_b == cstAllOWE_uid6_fpToFxPTest_q ? 1'b1 : 1'b0; - - // excN_x_uid16_fpToFxPTest(LOGICAL,15)@0 - assign excN_x_uid16_fpToFxPTest_q = expXIsMax_uid12_fpToFxPTest_q & fracXIsNotZero_uid14_fpToFxPTest_q; - - // notNan_uid28_fpToFxPTest(LOGICAL,27)@0 - assign notNan_uid28_fpToFxPTest_q = ~ (excN_x_uid16_fpToFxPTest_q); - - // signX_uid29_fpToFxPTest(LOGICAL,28)@0 + 1 - assign signX_uid29_fpToFxPTest_qi = notNan_uid28_fpToFxPTest_q & signX_uid27_fpToFxPTest_b; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) ) - signX_uid29_fpToFxPTest_delay ( .xin(signX_uid29_fpToFxPTest_qi), .xout(signX_uid29_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // GND(CONSTANT,0) - assign GND_q = 1'b0; - - // rightShiftStage2Idx1Pad16_uid83_rightShiferNoStickyOut_uid42_fpToFxPTest(CONSTANT,82) - assign rightShiftStage2Idx1Pad16_uid83_rightShiferNoStickyOut_uid42_fpToFxPTest_q = 16'b0000000000000000; - - // rightShiftStage2Idx1Rng16_uid82_rightShiferNoStickyOut_uid42_fpToFxPTest(BITSELECT,81)@1 - assign rightShiftStage2Idx1Rng16_uid82_rightShiferNoStickyOut_uid42_fpToFxPTest_b = rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest_q[31:16]; - - // rightShiftStage2Idx1_uid84_rightShiferNoStickyOut_uid42_fpToFxPTest(BITJOIN,83)@1 - assign rightShiftStage2Idx1_uid84_rightShiferNoStickyOut_uid42_fpToFxPTest_q = {rightShiftStage2Idx1Pad16_uid83_rightShiferNoStickyOut_uid42_fpToFxPTest_q, rightShiftStage2Idx1Rng16_uid82_rightShiferNoStickyOut_uid42_fpToFxPTest_b}; - - // rightShiftStage1Idx3Pad12_uid78_rightShiferNoStickyOut_uid42_fpToFxPTest(CONSTANT,77) - assign rightShiftStage1Idx3Pad12_uid78_rightShiferNoStickyOut_uid42_fpToFxPTest_q = 12'b000000000000; - - // rightShiftStage1Idx3Rng12_uid77_rightShiferNoStickyOut_uid42_fpToFxPTest(BITSELECT,76)@1 - assign rightShiftStage1Idx3Rng12_uid77_rightShiferNoStickyOut_uid42_fpToFxPTest_b = rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_q[31:12]; - - // rightShiftStage1Idx3_uid79_rightShiferNoStickyOut_uid42_fpToFxPTest(BITJOIN,78)@1 - assign rightShiftStage1Idx3_uid79_rightShiferNoStickyOut_uid42_fpToFxPTest_q = {rightShiftStage1Idx3Pad12_uid78_rightShiferNoStickyOut_uid42_fpToFxPTest_q, rightShiftStage1Idx3Rng12_uid77_rightShiferNoStickyOut_uid42_fpToFxPTest_b}; - - // cstAllZWE_uid8_fpToFxPTest(CONSTANT,7) - assign cstAllZWE_uid8_fpToFxPTest_q = 8'b00000000; - - // rightShiftStage1Idx2Rng8_uid74_rightShiferNoStickyOut_uid42_fpToFxPTest(BITSELECT,73)@1 - assign rightShiftStage1Idx2Rng8_uid74_rightShiferNoStickyOut_uid42_fpToFxPTest_b = rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_q[31:8]; - - // rightShiftStage1Idx2_uid76_rightShiferNoStickyOut_uid42_fpToFxPTest(BITJOIN,75)@1 - assign rightShiftStage1Idx2_uid76_rightShiferNoStickyOut_uid42_fpToFxPTest_q = {cstAllZWE_uid8_fpToFxPTest_q, rightShiftStage1Idx2Rng8_uid74_rightShiferNoStickyOut_uid42_fpToFxPTest_b}; - - // rightShiftStage1Idx1Pad4_uid72_rightShiferNoStickyOut_uid42_fpToFxPTest(CONSTANT,71) - assign rightShiftStage1Idx1Pad4_uid72_rightShiferNoStickyOut_uid42_fpToFxPTest_q = 4'b0000; - - // rightShiftStage1Idx1Rng4_uid71_rightShiferNoStickyOut_uid42_fpToFxPTest(BITSELECT,70)@1 - assign rightShiftStage1Idx1Rng4_uid71_rightShiferNoStickyOut_uid42_fpToFxPTest_b = rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_q[31:4]; - - // rightShiftStage1Idx1_uid73_rightShiferNoStickyOut_uid42_fpToFxPTest(BITJOIN,72)@1 - assign rightShiftStage1Idx1_uid73_rightShiferNoStickyOut_uid42_fpToFxPTest_q = {rightShiftStage1Idx1Pad4_uid72_rightShiferNoStickyOut_uid42_fpToFxPTest_q, rightShiftStage1Idx1Rng4_uid71_rightShiferNoStickyOut_uid42_fpToFxPTest_b}; - - // rightShiftStage0Idx3Pad3_uid67_rightShiferNoStickyOut_uid42_fpToFxPTest(CONSTANT,66) - assign rightShiftStage0Idx3Pad3_uid67_rightShiferNoStickyOut_uid42_fpToFxPTest_q = 3'b000; - - // rightShiftStage0Idx3Rng3_uid66_rightShiferNoStickyOut_uid42_fpToFxPTest(BITSELECT,65)@1 - assign rightShiftStage0Idx3Rng3_uid66_rightShiferNoStickyOut_uid42_fpToFxPTest_b = shifterIn_uid41_fpToFxPTest_q[31:3]; - - // rightShiftStage0Idx3_uid68_rightShiferNoStickyOut_uid42_fpToFxPTest(BITJOIN,67)@1 - assign rightShiftStage0Idx3_uid68_rightShiferNoStickyOut_uid42_fpToFxPTest_q = {rightShiftStage0Idx3Pad3_uid67_rightShiferNoStickyOut_uid42_fpToFxPTest_q, rightShiftStage0Idx3Rng3_uid66_rightShiferNoStickyOut_uid42_fpToFxPTest_b}; - - // rightShiftStage0Idx2Pad2_uid64_rightShiferNoStickyOut_uid42_fpToFxPTest(CONSTANT,63) - assign rightShiftStage0Idx2Pad2_uid64_rightShiferNoStickyOut_uid42_fpToFxPTest_q = 2'b00; - - // rightShiftStage0Idx2Rng2_uid63_rightShiferNoStickyOut_uid42_fpToFxPTest(BITSELECT,62)@1 - assign rightShiftStage0Idx2Rng2_uid63_rightShiferNoStickyOut_uid42_fpToFxPTest_b = shifterIn_uid41_fpToFxPTest_q[31:2]; - - // rightShiftStage0Idx2_uid65_rightShiferNoStickyOut_uid42_fpToFxPTest(BITJOIN,64)@1 - assign rightShiftStage0Idx2_uid65_rightShiferNoStickyOut_uid42_fpToFxPTest_q = {rightShiftStage0Idx2Pad2_uid64_rightShiferNoStickyOut_uid42_fpToFxPTest_q, rightShiftStage0Idx2Rng2_uid63_rightShiferNoStickyOut_uid42_fpToFxPTest_b}; - - // rightShiftStage0Idx1Rng1_uid60_rightShiferNoStickyOut_uid42_fpToFxPTest(BITSELECT,59)@1 - assign rightShiftStage0Idx1Rng1_uid60_rightShiferNoStickyOut_uid42_fpToFxPTest_b = shifterIn_uid41_fpToFxPTest_q[31:1]; - - // rightShiftStage0Idx1_uid62_rightShiferNoStickyOut_uid42_fpToFxPTest(BITJOIN,61)@1 - assign rightShiftStage0Idx1_uid62_rightShiferNoStickyOut_uid42_fpToFxPTest_q = {GND_q, rightShiftStage0Idx1Rng1_uid60_rightShiferNoStickyOut_uid42_fpToFxPTest_b}; - - // excZ_x_uid11_fpToFxPTest(LOGICAL,10)@0 - assign excZ_x_uid11_fpToFxPTest_q = exp_x_uid9_fpToFxPTest_b == cstAllZWE_uid8_fpToFxPTest_q ? 1'b1 : 1'b0; - - // invExcXZ_uid24_fpToFxPTest(LOGICAL,23)@0 + 1 - assign invExcXZ_uid24_fpToFxPTest_qi = ~ (excZ_x_uid11_fpToFxPTest_q); - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) ) - invExcXZ_uid24_fpToFxPTest_delay ( .xin(invExcXZ_uid24_fpToFxPTest_qi), .xout(invExcXZ_uid24_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // fracPostZ_uid23_fpToFxPTest(MUX,22)@0 + 1 - assign fracPostZ_uid23_fpToFxPTest_s = excZ_x_uid11_fpToFxPTest_q; - always @ (posedge clk) - begin - if (areset) - begin - fracPostZ_uid23_fpToFxPTest_q <= 23'b0; - end - else if (en == 1'b1) - begin - unique case (fracPostZ_uid23_fpToFxPTest_s) - 1'b0 : fracPostZ_uid23_fpToFxPTest_q <= frac_x_uid10_fpToFxPTest_b; - 1'b1 : fracPostZ_uid23_fpToFxPTest_q <= cstZeroWF_uid7_fpToFxPTest_q; - default : fracPostZ_uid23_fpToFxPTest_q <= 23'b0; - endcase - end - end - - // oFracX_uid25_fpToFxPTest(BITJOIN,24)@1 - assign oFracX_uid25_fpToFxPTest_q = {invExcXZ_uid24_fpToFxPTest_q, fracPostZ_uid23_fpToFxPTest_q}; - - // shifterIn_uid41_fpToFxPTest(BITJOIN,40)@1 - assign shifterIn_uid41_fpToFxPTest_q = {oFracX_uid25_fpToFxPTest_q, cstAllZWE_uid8_fpToFxPTest_q}; - - // rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest(MUX,69)@1 - assign rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_s = rightShiftStageSel0Dto0_uid69_rightShiferNoStickyOut_uid42_fpToFxPTest_merged_bit_select_b; - always @(rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_s or en or shifterIn_uid41_fpToFxPTest_q or rightShiftStage0Idx1_uid62_rightShiferNoStickyOut_uid42_fpToFxPTest_q or rightShiftStage0Idx2_uid65_rightShiferNoStickyOut_uid42_fpToFxPTest_q or rightShiftStage0Idx3_uid68_rightShiferNoStickyOut_uid42_fpToFxPTest_q) - begin - unique case (rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_s) - 2'b00 : rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_q = shifterIn_uid41_fpToFxPTest_q; - 2'b01 : rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_q = rightShiftStage0Idx1_uid62_rightShiferNoStickyOut_uid42_fpToFxPTest_q; - 2'b10 : rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_q = rightShiftStage0Idx2_uid65_rightShiferNoStickyOut_uid42_fpToFxPTest_q; - 2'b11 : rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_q = rightShiftStage0Idx3_uid68_rightShiferNoStickyOut_uid42_fpToFxPTest_q; - default : rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_q = 32'b0; - endcase - end - - // rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest(MUX,80)@1 - assign rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest_s = rightShiftStageSel0Dto0_uid69_rightShiferNoStickyOut_uid42_fpToFxPTest_merged_bit_select_c; - always @(rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest_s or en or rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_q or rightShiftStage1Idx1_uid73_rightShiferNoStickyOut_uid42_fpToFxPTest_q or rightShiftStage1Idx2_uid76_rightShiferNoStickyOut_uid42_fpToFxPTest_q or rightShiftStage1Idx3_uid79_rightShiferNoStickyOut_uid42_fpToFxPTest_q) - begin - unique case (rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest_s) - 2'b00 : rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest_q = rightShiftStage0_uid70_rightShiferNoStickyOut_uid42_fpToFxPTest_q; - 2'b01 : rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest_q = rightShiftStage1Idx1_uid73_rightShiferNoStickyOut_uid42_fpToFxPTest_q; - 2'b10 : rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest_q = rightShiftStage1Idx2_uid76_rightShiferNoStickyOut_uid42_fpToFxPTest_q; - 2'b11 : rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest_q = rightShiftStage1Idx3_uid79_rightShiferNoStickyOut_uid42_fpToFxPTest_q; - default : rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest_q = 32'b0; - endcase - end - - // maxShiftCst_uid37_fpToFxPTest(CONSTANT,36) - assign maxShiftCst_uid37_fpToFxPTest_q = 6'b100000; - - // ovfExpVal_uid34_fpToFxPTest(CONSTANT,33) - assign ovfExpVal_uid34_fpToFxPTest_q = 9'b010011101; - - // shiftValE_uid35_fpToFxPTest(SUB,34)@0 - assign shiftValE_uid35_fpToFxPTest_a = {{2{ovfExpVal_uid34_fpToFxPTest_q[8]}}, ovfExpVal_uid34_fpToFxPTest_q}; - assign shiftValE_uid35_fpToFxPTest_b = {3'b000, exp_x_uid9_fpToFxPTest_b}; - assign shiftValE_uid35_fpToFxPTest_o = $signed(shiftValE_uid35_fpToFxPTest_a) - $signed(shiftValE_uid35_fpToFxPTest_b); - assign shiftValE_uid35_fpToFxPTest_q = shiftValE_uid35_fpToFxPTest_o[9:0]; - - // shiftValRaw_uid36_fpToFxPTest(BITSELECT,35)@0 - assign shiftValRaw_uid36_fpToFxPTest_in = shiftValE_uid35_fpToFxPTest_q[5:0]; - assign shiftValRaw_uid36_fpToFxPTest_b = shiftValRaw_uid36_fpToFxPTest_in[5:0]; - - // shiftOutOfRange_uid38_fpToFxPTest(COMPARE,37)@0 - assign shiftOutOfRange_uid38_fpToFxPTest_a = {{2{shiftValE_uid35_fpToFxPTest_q[9]}}, shiftValE_uid35_fpToFxPTest_q}; - assign shiftOutOfRange_uid38_fpToFxPTest_b = {6'b000000, maxShiftCst_uid37_fpToFxPTest_q}; - assign shiftOutOfRange_uid38_fpToFxPTest_o = $signed(shiftOutOfRange_uid38_fpToFxPTest_a) - $signed(shiftOutOfRange_uid38_fpToFxPTest_b); - assign shiftOutOfRange_uid38_fpToFxPTest_n[0] = ~ (shiftOutOfRange_uid38_fpToFxPTest_o[11]); - - // shiftVal_uid39_fpToFxPTest(MUX,38)@0 + 1 - assign shiftVal_uid39_fpToFxPTest_s = shiftOutOfRange_uid38_fpToFxPTest_n; - always @ (posedge clk) - begin - if (areset) - begin - shiftVal_uid39_fpToFxPTest_q <= 6'b0; - end - else if (en == 1'b1) - begin - unique case (shiftVal_uid39_fpToFxPTest_s) - 1'b0 : shiftVal_uid39_fpToFxPTest_q <= shiftValRaw_uid36_fpToFxPTest_b; - 1'b1 : shiftVal_uid39_fpToFxPTest_q <= maxShiftCst_uid37_fpToFxPTest_q; - default : shiftVal_uid39_fpToFxPTest_q <= 6'b0; - endcase - end - end - - // rightShiftStageSel0Dto0_uid69_rightShiferNoStickyOut_uid42_fpToFxPTest_merged_bit_select(BITSELECT,89)@1 - assign rightShiftStageSel0Dto0_uid69_rightShiferNoStickyOut_uid42_fpToFxPTest_merged_bit_select_b = shiftVal_uid39_fpToFxPTest_q[1:0]; - assign rightShiftStageSel0Dto0_uid69_rightShiferNoStickyOut_uid42_fpToFxPTest_merged_bit_select_c = shiftVal_uid39_fpToFxPTest_q[3:2]; - assign rightShiftStageSel0Dto0_uid69_rightShiferNoStickyOut_uid42_fpToFxPTest_merged_bit_select_d = shiftVal_uid39_fpToFxPTest_q[5:4]; - - // rightShiftStage2_uid88_rightShiferNoStickyOut_uid42_fpToFxPTest(MUX,87)@1 - assign rightShiftStage2_uid88_rightShiferNoStickyOut_uid42_fpToFxPTest_s = rightShiftStageSel0Dto0_uid69_rightShiferNoStickyOut_uid42_fpToFxPTest_merged_bit_select_d; - always @(rightShiftStage2_uid88_rightShiferNoStickyOut_uid42_fpToFxPTest_s or en or rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest_q or rightShiftStage2Idx1_uid84_rightShiferNoStickyOut_uid42_fpToFxPTest_q or maxNegValueU_uid55_fpToFxPTest_q) - begin - unique case (rightShiftStage2_uid88_rightShiferNoStickyOut_uid42_fpToFxPTest_s) - 2'b00 : rightShiftStage2_uid88_rightShiferNoStickyOut_uid42_fpToFxPTest_q = rightShiftStage1_uid81_rightShiferNoStickyOut_uid42_fpToFxPTest_q; - 2'b01 : rightShiftStage2_uid88_rightShiferNoStickyOut_uid42_fpToFxPTest_q = rightShiftStage2Idx1_uid84_rightShiferNoStickyOut_uid42_fpToFxPTest_q; - 2'b10 : rightShiftStage2_uid88_rightShiferNoStickyOut_uid42_fpToFxPTest_q = maxNegValueU_uid55_fpToFxPTest_q; - 2'b11 : rightShiftStage2_uid88_rightShiferNoStickyOut_uid42_fpToFxPTest_q = maxNegValueU_uid55_fpToFxPTest_q; - default : rightShiftStage2_uid88_rightShiferNoStickyOut_uid42_fpToFxPTest_q = 32'b0; - endcase - end - - // zRightShiferNoStickyOut_uid45_fpToFxPTest(BITJOIN,44)@1 - assign zRightShiferNoStickyOut_uid45_fpToFxPTest_q = {GND_q, rightShiftStage2_uid88_rightShiferNoStickyOut_uid42_fpToFxPTest_q}; - - // xXorSignE_uid46_fpToFxPTest(LOGICAL,45)@1 + 1 - assign xXorSignE_uid46_fpToFxPTest_b = {{32{signX_uid29_fpToFxPTest_q[0]}}, signX_uid29_fpToFxPTest_q}; - assign xXorSignE_uid46_fpToFxPTest_qi = zRightShiferNoStickyOut_uid45_fpToFxPTest_q ^ xXorSignE_uid46_fpToFxPTest_b; - dspba_delay_ver #( .width(33), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) ) - xXorSignE_uid46_fpToFxPTest_delay ( .xin(xXorSignE_uid46_fpToFxPTest_qi), .xout(xXorSignE_uid46_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // sPostRndFull_uid48_fpToFxPTest(ADD,47)@2 - assign sPostRndFull_uid48_fpToFxPTest_a = {{1{xXorSignE_uid46_fpToFxPTest_q[32]}}, xXorSignE_uid46_fpToFxPTest_q}; - assign sPostRndFull_uid48_fpToFxPTest_b = {{31{d0_uid47_fpToFxPTest_q[2]}}, d0_uid47_fpToFxPTest_q}; - assign sPostRndFull_uid48_fpToFxPTest_o = $signed(sPostRndFull_uid48_fpToFxPTest_a) + $signed(sPostRndFull_uid48_fpToFxPTest_b); - assign sPostRndFull_uid48_fpToFxPTest_q = sPostRndFull_uid48_fpToFxPTest_o[33:0]; - - // sPostRnd_uid49_fpToFxPTest(BITSELECT,48)@2 - assign sPostRnd_uid49_fpToFxPTest_in = sPostRndFull_uid48_fpToFxPTest_q[32:0]; - assign sPostRnd_uid49_fpToFxPTest_b = sPostRnd_uid49_fpToFxPTest_in[32:1]; - - // redist0_sPostRnd_uid49_fpToFxPTest_b_1(DELAY,90) - always @ (posedge clk) - begin - if (areset) - begin - redist0_sPostRnd_uid49_fpToFxPTest_b_1_q <= '0; - end - else if (en == 1'b1) - begin - redist0_sPostRnd_uid49_fpToFxPTest_b_1_q <= sPostRnd_uid49_fpToFxPTest_b; - end - end - - // redist3_signX_uid29_fpToFxPTest_q_3(DELAY,93) - always @ (posedge clk) - begin - if (areset) - begin - redist3_signX_uid29_fpToFxPTest_q_3_delay_0 <= '0; - redist3_signX_uid29_fpToFxPTest_q_3_q <= '0; - end - else if (en == 1'b1) - begin - redist3_signX_uid29_fpToFxPTest_q_3_delay_0 <= signX_uid29_fpToFxPTest_q; - redist3_signX_uid29_fpToFxPTest_q_3_q <= redist3_signX_uid29_fpToFxPTest_q_3_delay_0; - end - end - - // udfExpVal_uid32_fpToFxPTest(CONSTANT,31) - assign udfExpVal_uid32_fpToFxPTest_q = 8'b01111101; - - // udf_uid33_fpToFxPTest(COMPARE,32)@0 + 1 - assign udf_uid33_fpToFxPTest_a = {{3{udfExpVal_uid32_fpToFxPTest_q[7]}}, udfExpVal_uid32_fpToFxPTest_q}; - assign udf_uid33_fpToFxPTest_b = {3'b000, exp_x_uid9_fpToFxPTest_b}; - always @ (posedge clk) - begin - if (areset) - begin - udf_uid33_fpToFxPTest_o <= 11'b0; - end - else if (en == 1'b1) - begin - udf_uid33_fpToFxPTest_o <= $signed(udf_uid33_fpToFxPTest_a) - $signed(udf_uid33_fpToFxPTest_b); - end - end - assign udf_uid33_fpToFxPTest_n[0] = ~ (udf_uid33_fpToFxPTest_o[10]); - - // redist1_udf_uid33_fpToFxPTest_n_3(DELAY,91) - always @ (posedge clk) - begin - if (areset) - begin - redist1_udf_uid33_fpToFxPTest_n_3_delay_0 <= '0; - redist1_udf_uid33_fpToFxPTest_n_3_q <= '0; - end - else if (en == 1'b1) - begin - redist1_udf_uid33_fpToFxPTest_n_3_delay_0 <= udf_uid33_fpToFxPTest_n; - redist1_udf_uid33_fpToFxPTest_n_3_q <= redist1_udf_uid33_fpToFxPTest_n_3_delay_0; - end - end - - // sPostRnd_uid50_fpToFxPTest(BITSELECT,49)@2 - assign sPostRnd_uid50_fpToFxPTest_in = {{1{sPostRndFull_uid48_fpToFxPTest_q[33]}}, sPostRndFull_uid48_fpToFxPTest_q}; - assign sPostRnd_uid50_fpToFxPTest_b = sPostRnd_uid50_fpToFxPTest_in[34:1]; - - // rndOvfPos_uid51_fpToFxPTest(COMPARE,50)@2 + 1 - assign rndOvfPos_uid51_fpToFxPTest_a = {4'b0000, maxPosValueS_uid43_fpToFxPTest_q}; - assign rndOvfPos_uid51_fpToFxPTest_b = {{2{sPostRnd_uid50_fpToFxPTest_b[33]}}, sPostRnd_uid50_fpToFxPTest_b}; - always @ (posedge clk) - begin - if (areset) - begin - rndOvfPos_uid51_fpToFxPTest_o <= 36'b0; - end - else if (en == 1'b1) - begin - rndOvfPos_uid51_fpToFxPTest_o <= $signed(rndOvfPos_uid51_fpToFxPTest_a) - $signed(rndOvfPos_uid51_fpToFxPTest_b); - end - end - assign rndOvfPos_uid51_fpToFxPTest_c[0] = rndOvfPos_uid51_fpToFxPTest_o[35]; - - // ovfExpVal_uid30_fpToFxPTest(CONSTANT,29) - assign ovfExpVal_uid30_fpToFxPTest_q = 9'b010011110; - - // ovfExpRange_uid31_fpToFxPTest(COMPARE,30)@0 + 1 - assign ovfExpRange_uid31_fpToFxPTest_a = {3'b000, exp_x_uid9_fpToFxPTest_b}; - assign ovfExpRange_uid31_fpToFxPTest_b = {{2{ovfExpVal_uid30_fpToFxPTest_q[8]}}, ovfExpVal_uid30_fpToFxPTest_q}; - always @ (posedge clk) - begin - if (areset) - begin - ovfExpRange_uid31_fpToFxPTest_o <= 11'b0; - end - else if (en == 1'b1) - begin - ovfExpRange_uid31_fpToFxPTest_o <= $signed(ovfExpRange_uid31_fpToFxPTest_a) - $signed(ovfExpRange_uid31_fpToFxPTest_b); - end - end - assign ovfExpRange_uid31_fpToFxPTest_n[0] = ~ (ovfExpRange_uid31_fpToFxPTest_o[10]); - - // redist2_ovfExpRange_uid31_fpToFxPTest_n_3(DELAY,92) - always @ (posedge clk) - begin - if (areset) - begin - redist2_ovfExpRange_uid31_fpToFxPTest_n_3_delay_0 <= '0; - redist2_ovfExpRange_uid31_fpToFxPTest_n_3_q <= '0; - end - else if (en == 1'b1) - begin - redist2_ovfExpRange_uid31_fpToFxPTest_n_3_delay_0 <= ovfExpRange_uid31_fpToFxPTest_n; - redist2_ovfExpRange_uid31_fpToFxPTest_n_3_q <= redist2_ovfExpRange_uid31_fpToFxPTest_n_3_delay_0; - end - end - - // excI_x_uid15_fpToFxPTest(LOGICAL,14)@0 + 1 - assign excI_x_uid15_fpToFxPTest_qi = expXIsMax_uid12_fpToFxPTest_q & fracXIsZero_uid13_fpToFxPTest_q; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) ) - excI_x_uid15_fpToFxPTest_delay ( .xin(excI_x_uid15_fpToFxPTest_qi), .xout(excI_x_uid15_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist5_excI_x_uid15_fpToFxPTest_q_3(DELAY,95) - always @ (posedge clk) - begin - if (areset) - begin - redist5_excI_x_uid15_fpToFxPTest_q_3_delay_0 <= '0; - redist5_excI_x_uid15_fpToFxPTest_q_3_q <= '0; - end - else if (en == 1'b1) - begin - redist5_excI_x_uid15_fpToFxPTest_q_3_delay_0 <= excI_x_uid15_fpToFxPTest_q; - redist5_excI_x_uid15_fpToFxPTest_q_3_q <= redist5_excI_x_uid15_fpToFxPTest_q_3_delay_0; - end - end - - // redist4_excN_x_uid16_fpToFxPTest_q_3(DELAY,94) - always @ (posedge clk) - begin - if (areset) - begin - redist4_excN_x_uid16_fpToFxPTest_q_3_delay_0 <= '0; - redist4_excN_x_uid16_fpToFxPTest_q_3_delay_1 <= '0; - redist4_excN_x_uid16_fpToFxPTest_q_3_q <= '0; - end - else if (en == 1'b1) - begin - redist4_excN_x_uid16_fpToFxPTest_q_3_delay_0 <= excN_x_uid16_fpToFxPTest_q; - redist4_excN_x_uid16_fpToFxPTest_q_3_delay_1 <= redist4_excN_x_uid16_fpToFxPTest_q_3_delay_0; - redist4_excN_x_uid16_fpToFxPTest_q_3_q <= redist4_excN_x_uid16_fpToFxPTest_q_3_delay_1; - end - end - - // ovfPostRnd_uid52_fpToFxPTest(LOGICAL,51)@3 - assign ovfPostRnd_uid52_fpToFxPTest_q = redist4_excN_x_uid16_fpToFxPTest_q_3_q | redist5_excI_x_uid15_fpToFxPTest_q_3_q | redist2_ovfExpRange_uid31_fpToFxPTest_n_3_q | rndOvfPos_uid51_fpToFxPTest_c; - - // muxSelConc_uid53_fpToFxPTest(BITJOIN,52)@3 - assign muxSelConc_uid53_fpToFxPTest_q = {redist3_signX_uid29_fpToFxPTest_q_3_q, redist1_udf_uid33_fpToFxPTest_n_3_q, ovfPostRnd_uid52_fpToFxPTest_q}; - - // muxSel_uid54_fpToFxPTest(LOOKUP,53)@3 - always @(muxSelConc_uid53_fpToFxPTest_q) - begin - // Begin reserved scope level - unique case (muxSelConc_uid53_fpToFxPTest_q) - 3'b000 : muxSel_uid54_fpToFxPTest_q = 2'b00; - 3'b001 : muxSel_uid54_fpToFxPTest_q = 2'b01; - 3'b010 : muxSel_uid54_fpToFxPTest_q = 2'b11; - 3'b011 : muxSel_uid54_fpToFxPTest_q = 2'b11; - 3'b100 : muxSel_uid54_fpToFxPTest_q = 2'b00; - 3'b101 : muxSel_uid54_fpToFxPTest_q = 2'b10; - 3'b110 : muxSel_uid54_fpToFxPTest_q = 2'b11; - 3'b111 : muxSel_uid54_fpToFxPTest_q = 2'b11; - default : begin - // unreachable - muxSel_uid54_fpToFxPTest_q = 2'bxx; - end - endcase - // End reserved scope level - end - - // finalOut_uid56_fpToFxPTest(MUX,55)@3 - assign finalOut_uid56_fpToFxPTest_s = muxSel_uid54_fpToFxPTest_q; - always @(finalOut_uid56_fpToFxPTest_s or en or redist0_sPostRnd_uid49_fpToFxPTest_b_1_q or maxPosValueS_uid43_fpToFxPTest_q or maxNegValueS_uid44_fpToFxPTest_q or maxNegValueU_uid55_fpToFxPTest_q) - begin - unique case (finalOut_uid56_fpToFxPTest_s) - 2'b00 : finalOut_uid56_fpToFxPTest_q = redist0_sPostRnd_uid49_fpToFxPTest_b_1_q; - 2'b01 : finalOut_uid56_fpToFxPTest_q = maxPosValueS_uid43_fpToFxPTest_q; - 2'b10 : finalOut_uid56_fpToFxPTest_q = maxNegValueS_uid44_fpToFxPTest_q; - 2'b11 : finalOut_uid56_fpToFxPTest_q = maxNegValueU_uid55_fpToFxPTest_q; - default : finalOut_uid56_fpToFxPTest_q = 32'b0; - endcase - end - - // xOut(GPOUT,4)@3 - assign q = finalOut_uid56_fpToFxPTest_q; - -endmodule diff --git a/hw/rtl/fp_cores/altera/stratix10/acl_ftou.sv b/hw/rtl/fp_cores/altera/stratix10/acl_ftou.sv deleted file mode 100644 index cb93a84f..00000000 --- a/hw/rtl/fp_cores/altera/stratix10/acl_ftou.sv +++ /dev/null @@ -1,563 +0,0 @@ -// ------------------------------------------------------------------------- -// High Level Design Compiler for Intel(R) FPGAs Version 18.1 (Release Build #277) -// Quartus Prime development tool and MATLAB/Simulink Interface -// -// Legal Notice: Copyright 2019 Intel Corporation. All rights reserved. -// Your use of Intel Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly -// subject to the terms and conditions of the Intel FPGA Software License -// Agreement, Intel MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for -// the sole purpose of programming logic devices manufactured by Intel -// and sold by Intel or its authorized distributors. Please refer to the -// applicable agreement for further details. -// --------------------------------------------------------------------------- - -// SystemVerilog created from acl_ftou -// SystemVerilog created on Sun Dec 27 09:48:58 2020 - - -(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) -module acl_ftou ( - input wire [31:0] a, - input wire [0:0] en, - output wire [31:0] q, - input wire clk, - input wire areset - ); - - wire [0:0] GND_q; - wire [0:0] VCC_q; - wire [7:0] cstAllOWE_uid6_fpToFxPTest_q; - wire [22:0] cstZeroWF_uid7_fpToFxPTest_q; - wire [7:0] cstAllZWE_uid8_fpToFxPTest_q; - wire [7:0] exp_x_uid9_fpToFxPTest_b; - wire [22:0] frac_x_uid10_fpToFxPTest_b; - wire [0:0] excZ_x_uid11_fpToFxPTest_qi; - reg [0:0] excZ_x_uid11_fpToFxPTest_q; - wire [0:0] expXIsMax_uid12_fpToFxPTest_qi; - reg [0:0] expXIsMax_uid12_fpToFxPTest_q; - wire [0:0] fracXIsZero_uid13_fpToFxPTest_q; - wire [0:0] fracXIsNotZero_uid14_fpToFxPTest_q; - wire [0:0] excI_x_uid15_fpToFxPTest_qi; - reg [0:0] excI_x_uid15_fpToFxPTest_q; - wire [0:0] excN_x_uid16_fpToFxPTest_q; - wire [0:0] fracPostZ_uid23_fpToFxPTest_s; - reg [22:0] fracPostZ_uid23_fpToFxPTest_q; - wire [0:0] invExcXZ_uid24_fpToFxPTest_q; - wire [23:0] oFracX_uid25_fpToFxPTest_q; - wire [0:0] signX_uid27_fpToFxPTest_b; - wire [0:0] notNan_uid28_fpToFxPTest_q; - wire [0:0] signX_uid29_fpToFxPTest_qi; - reg [0:0] signX_uid29_fpToFxPTest_q; - wire [8:0] ovfExpVal_uid30_fpToFxPTest_q; - wire [10:0] ovf_uid31_fpToFxPTest_a; - wire [10:0] ovf_uid31_fpToFxPTest_b; - logic [10:0] ovf_uid31_fpToFxPTest_o; - wire [0:0] ovf_uid31_fpToFxPTest_n; - wire [0:0] negOrOvf_uid32_fpToFxPTest_q; - wire [7:0] udfExpVal_uid33_fpToFxPTest_q; - wire [10:0] udf_uid34_fpToFxPTest_a; - wire [10:0] udf_uid34_fpToFxPTest_b; - logic [10:0] udf_uid34_fpToFxPTest_o; - wire [0:0] udf_uid34_fpToFxPTest_n; - wire [8:0] ovfExpVal_uid35_fpToFxPTest_q; - wire [10:0] shiftValE_uid36_fpToFxPTest_a; - wire [10:0] shiftValE_uid36_fpToFxPTest_b; - logic [10:0] shiftValE_uid36_fpToFxPTest_o; - wire [9:0] shiftValE_uid36_fpToFxPTest_q; - wire [5:0] shiftValRaw_uid37_fpToFxPTest_in; - wire [5:0] shiftValRaw_uid37_fpToFxPTest_b; - wire [5:0] maxShiftCst_uid38_fpToFxPTest_q; - wire [11:0] shiftOutOfRange_uid39_fpToFxPTest_a; - wire [11:0] shiftOutOfRange_uid39_fpToFxPTest_b; - logic [11:0] shiftOutOfRange_uid39_fpToFxPTest_o; - wire [0:0] shiftOutOfRange_uid39_fpToFxPTest_n; - wire [0:0] shiftVal_uid40_fpToFxPTest_s; - reg [5:0] shiftVal_uid40_fpToFxPTest_q; - wire [8:0] zPadd_uid41_fpToFxPTest_q; - wire [32:0] shifterIn_uid42_fpToFxPTest_q; - wire [31:0] maxPosValueU_uid44_fpToFxPTest_q; - wire [31:0] maxNegValueU_uid45_fpToFxPTest_q; - wire [33:0] zRightShiferNoStickyOut_uid47_fpToFxPTest_q; - wire [34:0] sPostRndFull_uid48_fpToFxPTest_a; - wire [34:0] sPostRndFull_uid48_fpToFxPTest_b; - logic [34:0] sPostRndFull_uid48_fpToFxPTest_o; - wire [34:0] sPostRndFull_uid48_fpToFxPTest_q; - wire [32:0] sPostRnd_uid49_fpToFxPTest_in; - wire [31:0] sPostRnd_uid49_fpToFxPTest_b; - wire [33:0] sPostRndFullMSBU_uid50_fpToFxPTest_in; - wire [0:0] sPostRndFullMSBU_uid50_fpToFxPTest_b; - wire [0:0] ovfPostRnd_uid51_fpToFxPTest_q; - wire [2:0] muxSelConc_uid52_fpToFxPTest_q; - reg [1:0] muxSel_uid53_fpToFxPTest_q; - wire [1:0] finalOut_uid55_fpToFxPTest_s; - reg [31:0] finalOut_uid55_fpToFxPTest_q; - wire [31:0] rightShiftStage0Idx1Rng1_uid59_rightShiferNoStickyOut_uid43_fpToFxPTest_b; - wire [32:0] rightShiftStage0Idx1_uid61_rightShiferNoStickyOut_uid43_fpToFxPTest_q; - wire [30:0] rightShiftStage0Idx2Rng2_uid62_rightShiferNoStickyOut_uid43_fpToFxPTest_b; - wire [1:0] rightShiftStage0Idx2Pad2_uid63_rightShiferNoStickyOut_uid43_fpToFxPTest_q; - wire [32:0] rightShiftStage0Idx2_uid64_rightShiferNoStickyOut_uid43_fpToFxPTest_q; - wire [29:0] rightShiftStage0Idx3Rng3_uid65_rightShiferNoStickyOut_uid43_fpToFxPTest_b; - wire [2:0] rightShiftStage0Idx3Pad3_uid66_rightShiferNoStickyOut_uid43_fpToFxPTest_q; - wire [32:0] rightShiftStage0Idx3_uid67_rightShiferNoStickyOut_uid43_fpToFxPTest_q; - wire [1:0] rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_s; - reg [32:0] rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_q; - wire [28:0] rightShiftStage1Idx1Rng4_uid70_rightShiferNoStickyOut_uid43_fpToFxPTest_b; - wire [3:0] rightShiftStage1Idx1Pad4_uid71_rightShiferNoStickyOut_uid43_fpToFxPTest_q; - wire [32:0] rightShiftStage1Idx1_uid72_rightShiferNoStickyOut_uid43_fpToFxPTest_q; - wire [24:0] rightShiftStage1Idx2Rng8_uid73_rightShiferNoStickyOut_uid43_fpToFxPTest_b; - wire [32:0] rightShiftStage1Idx2_uid75_rightShiferNoStickyOut_uid43_fpToFxPTest_q; - wire [20:0] rightShiftStage1Idx3Rng12_uid76_rightShiferNoStickyOut_uid43_fpToFxPTest_b; - wire [11:0] rightShiftStage1Idx3Pad12_uid77_rightShiferNoStickyOut_uid43_fpToFxPTest_q; - wire [32:0] rightShiftStage1Idx3_uid78_rightShiferNoStickyOut_uid43_fpToFxPTest_q; - wire [1:0] rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest_s; - reg [32:0] rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest_q; - wire [16:0] rightShiftStage2Idx1Rng16_uid81_rightShiferNoStickyOut_uid43_fpToFxPTest_b; - wire [15:0] rightShiftStage2Idx1Pad16_uid82_rightShiferNoStickyOut_uid43_fpToFxPTest_q; - wire [32:0] rightShiftStage2Idx1_uid83_rightShiferNoStickyOut_uid43_fpToFxPTest_q; - wire [0:0] rightShiftStage2Idx2Rng32_uid84_rightShiferNoStickyOut_uid43_fpToFxPTest_b; - wire [32:0] rightShiftStage2Idx2_uid86_rightShiferNoStickyOut_uid43_fpToFxPTest_q; - wire [32:0] rightShiftStage2Idx3_uid87_rightShiferNoStickyOut_uid43_fpToFxPTest_q; - wire [1:0] rightShiftStage2_uid89_rightShiferNoStickyOut_uid43_fpToFxPTest_s; - reg [32:0] rightShiftStage2_uid89_rightShiferNoStickyOut_uid43_fpToFxPTest_q; - wire [1:0] rightShiftStageSel0Dto0_uid68_rightShiferNoStickyOut_uid43_fpToFxPTest_merged_bit_select_b; - wire [1:0] rightShiftStageSel0Dto0_uid68_rightShiferNoStickyOut_uid43_fpToFxPTest_merged_bit_select_c; - wire [1:0] rightShiftStageSel0Dto0_uid68_rightShiferNoStickyOut_uid43_fpToFxPTest_merged_bit_select_d; - reg [31:0] redist0_sPostRnd_uid49_fpToFxPTest_b_1_q; - reg [0:0] redist1_udf_uid34_fpToFxPTest_n_2_q; - reg [0:0] redist2_ovf_uid31_fpToFxPTest_n_2_q; - reg [0:0] redist3_signX_uid27_fpToFxPTest_b_1_q; - reg [0:0] redist4_excN_x_uid16_fpToFxPTest_q_1_q; - reg [22:0] redist5_frac_x_uid10_fpToFxPTest_b_1_q; - - - // maxNegValueU_uid45_fpToFxPTest(CONSTANT,44) - assign maxNegValueU_uid45_fpToFxPTest_q = 32'b00000000000000000000000000000000; - - // maxPosValueU_uid44_fpToFxPTest(CONSTANT,43) - assign maxPosValueU_uid44_fpToFxPTest_q = 32'b11111111111111111111111111111111; - - // VCC(CONSTANT,1) - assign VCC_q = 1'b1; - - // GND(CONSTANT,0) - assign GND_q = 1'b0; - - // rightShiftStage2Idx3_uid87_rightShiferNoStickyOut_uid43_fpToFxPTest(CONSTANT,86) - assign rightShiftStage2Idx3_uid87_rightShiferNoStickyOut_uid43_fpToFxPTest_q = 33'b000000000000000000000000000000000; - - // rightShiftStage2Idx2Rng32_uid84_rightShiferNoStickyOut_uid43_fpToFxPTest(BITSELECT,83)@1 - assign rightShiftStage2Idx2Rng32_uid84_rightShiferNoStickyOut_uid43_fpToFxPTest_b = rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest_q[32:32]; - - // rightShiftStage2Idx2_uid86_rightShiferNoStickyOut_uid43_fpToFxPTest(BITJOIN,85)@1 - assign rightShiftStage2Idx2_uid86_rightShiferNoStickyOut_uid43_fpToFxPTest_q = {maxNegValueU_uid45_fpToFxPTest_q, rightShiftStage2Idx2Rng32_uid84_rightShiferNoStickyOut_uid43_fpToFxPTest_b}; - - // rightShiftStage2Idx1Pad16_uid82_rightShiferNoStickyOut_uid43_fpToFxPTest(CONSTANT,81) - assign rightShiftStage2Idx1Pad16_uid82_rightShiferNoStickyOut_uid43_fpToFxPTest_q = 16'b0000000000000000; - - // rightShiftStage2Idx1Rng16_uid81_rightShiferNoStickyOut_uid43_fpToFxPTest(BITSELECT,80)@1 - assign rightShiftStage2Idx1Rng16_uid81_rightShiferNoStickyOut_uid43_fpToFxPTest_b = rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest_q[32:16]; - - // rightShiftStage2Idx1_uid83_rightShiferNoStickyOut_uid43_fpToFxPTest(BITJOIN,82)@1 - assign rightShiftStage2Idx1_uid83_rightShiferNoStickyOut_uid43_fpToFxPTest_q = {rightShiftStage2Idx1Pad16_uid82_rightShiferNoStickyOut_uid43_fpToFxPTest_q, rightShiftStage2Idx1Rng16_uid81_rightShiferNoStickyOut_uid43_fpToFxPTest_b}; - - // rightShiftStage1Idx3Pad12_uid77_rightShiferNoStickyOut_uid43_fpToFxPTest(CONSTANT,76) - assign rightShiftStage1Idx3Pad12_uid77_rightShiferNoStickyOut_uid43_fpToFxPTest_q = 12'b000000000000; - - // rightShiftStage1Idx3Rng12_uid76_rightShiferNoStickyOut_uid43_fpToFxPTest(BITSELECT,75)@1 - assign rightShiftStage1Idx3Rng12_uid76_rightShiferNoStickyOut_uid43_fpToFxPTest_b = rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_q[32:12]; - - // rightShiftStage1Idx3_uid78_rightShiferNoStickyOut_uid43_fpToFxPTest(BITJOIN,77)@1 - assign rightShiftStage1Idx3_uid78_rightShiferNoStickyOut_uid43_fpToFxPTest_q = {rightShiftStage1Idx3Pad12_uid77_rightShiferNoStickyOut_uid43_fpToFxPTest_q, rightShiftStage1Idx3Rng12_uid76_rightShiferNoStickyOut_uid43_fpToFxPTest_b}; - - // cstAllZWE_uid8_fpToFxPTest(CONSTANT,7) - assign cstAllZWE_uid8_fpToFxPTest_q = 8'b00000000; - - // rightShiftStage1Idx2Rng8_uid73_rightShiferNoStickyOut_uid43_fpToFxPTest(BITSELECT,72)@1 - assign rightShiftStage1Idx2Rng8_uid73_rightShiferNoStickyOut_uid43_fpToFxPTest_b = rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_q[32:8]; - - // rightShiftStage1Idx2_uid75_rightShiferNoStickyOut_uid43_fpToFxPTest(BITJOIN,74)@1 - assign rightShiftStage1Idx2_uid75_rightShiferNoStickyOut_uid43_fpToFxPTest_q = {cstAllZWE_uid8_fpToFxPTest_q, rightShiftStage1Idx2Rng8_uid73_rightShiferNoStickyOut_uid43_fpToFxPTest_b}; - - // rightShiftStage1Idx1Pad4_uid71_rightShiferNoStickyOut_uid43_fpToFxPTest(CONSTANT,70) - assign rightShiftStage1Idx1Pad4_uid71_rightShiferNoStickyOut_uid43_fpToFxPTest_q = 4'b0000; - - // rightShiftStage1Idx1Rng4_uid70_rightShiferNoStickyOut_uid43_fpToFxPTest(BITSELECT,69)@1 - assign rightShiftStage1Idx1Rng4_uid70_rightShiferNoStickyOut_uid43_fpToFxPTest_b = rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_q[32:4]; - - // rightShiftStage1Idx1_uid72_rightShiferNoStickyOut_uid43_fpToFxPTest(BITJOIN,71)@1 - assign rightShiftStage1Idx1_uid72_rightShiferNoStickyOut_uid43_fpToFxPTest_q = {rightShiftStage1Idx1Pad4_uid71_rightShiferNoStickyOut_uid43_fpToFxPTest_q, rightShiftStage1Idx1Rng4_uid70_rightShiferNoStickyOut_uid43_fpToFxPTest_b}; - - // rightShiftStage0Idx3Pad3_uid66_rightShiferNoStickyOut_uid43_fpToFxPTest(CONSTANT,65) - assign rightShiftStage0Idx3Pad3_uid66_rightShiferNoStickyOut_uid43_fpToFxPTest_q = 3'b000; - - // rightShiftStage0Idx3Rng3_uid65_rightShiferNoStickyOut_uid43_fpToFxPTest(BITSELECT,64)@1 - assign rightShiftStage0Idx3Rng3_uid65_rightShiferNoStickyOut_uid43_fpToFxPTest_b = shifterIn_uid42_fpToFxPTest_q[32:3]; - - // rightShiftStage0Idx3_uid67_rightShiferNoStickyOut_uid43_fpToFxPTest(BITJOIN,66)@1 - assign rightShiftStage0Idx3_uid67_rightShiferNoStickyOut_uid43_fpToFxPTest_q = {rightShiftStage0Idx3Pad3_uid66_rightShiferNoStickyOut_uid43_fpToFxPTest_q, rightShiftStage0Idx3Rng3_uid65_rightShiferNoStickyOut_uid43_fpToFxPTest_b}; - - // rightShiftStage0Idx2Pad2_uid63_rightShiferNoStickyOut_uid43_fpToFxPTest(CONSTANT,62) - assign rightShiftStage0Idx2Pad2_uid63_rightShiferNoStickyOut_uid43_fpToFxPTest_q = 2'b00; - - // rightShiftStage0Idx2Rng2_uid62_rightShiferNoStickyOut_uid43_fpToFxPTest(BITSELECT,61)@1 - assign rightShiftStage0Idx2Rng2_uid62_rightShiferNoStickyOut_uid43_fpToFxPTest_b = shifterIn_uid42_fpToFxPTest_q[32:2]; - - // rightShiftStage0Idx2_uid64_rightShiferNoStickyOut_uid43_fpToFxPTest(BITJOIN,63)@1 - assign rightShiftStage0Idx2_uid64_rightShiferNoStickyOut_uid43_fpToFxPTest_q = {rightShiftStage0Idx2Pad2_uid63_rightShiferNoStickyOut_uid43_fpToFxPTest_q, rightShiftStage0Idx2Rng2_uid62_rightShiferNoStickyOut_uid43_fpToFxPTest_b}; - - // rightShiftStage0Idx1Rng1_uid59_rightShiferNoStickyOut_uid43_fpToFxPTest(BITSELECT,58)@1 - assign rightShiftStage0Idx1Rng1_uid59_rightShiferNoStickyOut_uid43_fpToFxPTest_b = shifterIn_uid42_fpToFxPTest_q[32:1]; - - // rightShiftStage0Idx1_uid61_rightShiferNoStickyOut_uid43_fpToFxPTest(BITJOIN,60)@1 - assign rightShiftStage0Idx1_uid61_rightShiferNoStickyOut_uid43_fpToFxPTest_q = {GND_q, rightShiftStage0Idx1Rng1_uid59_rightShiferNoStickyOut_uid43_fpToFxPTest_b}; - - // exp_x_uid9_fpToFxPTest(BITSELECT,8)@0 - assign exp_x_uid9_fpToFxPTest_b = a[30:23]; - - // excZ_x_uid11_fpToFxPTest(LOGICAL,10)@0 + 1 - assign excZ_x_uid11_fpToFxPTest_qi = exp_x_uid9_fpToFxPTest_b == cstAllZWE_uid8_fpToFxPTest_q ? 1'b1 : 1'b0; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) ) - excZ_x_uid11_fpToFxPTest_delay ( .xin(excZ_x_uid11_fpToFxPTest_qi), .xout(excZ_x_uid11_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // invExcXZ_uid24_fpToFxPTest(LOGICAL,23)@1 - assign invExcXZ_uid24_fpToFxPTest_q = ~ (excZ_x_uid11_fpToFxPTest_q); - - // cstZeroWF_uid7_fpToFxPTest(CONSTANT,6) - assign cstZeroWF_uid7_fpToFxPTest_q = 23'b00000000000000000000000; - - // frac_x_uid10_fpToFxPTest(BITSELECT,9)@0 - assign frac_x_uid10_fpToFxPTest_b = a[22:0]; - - // redist5_frac_x_uid10_fpToFxPTest_b_1(DELAY,96) - always @ (posedge clk) - begin - if (areset) - begin - redist5_frac_x_uid10_fpToFxPTest_b_1_q <= '0; - end - else if (en == 1'b1) - begin - redist5_frac_x_uid10_fpToFxPTest_b_1_q <= frac_x_uid10_fpToFxPTest_b; - end - end - - // fracPostZ_uid23_fpToFxPTest(MUX,22)@1 - assign fracPostZ_uid23_fpToFxPTest_s = excZ_x_uid11_fpToFxPTest_q; - always @(fracPostZ_uid23_fpToFxPTest_s or en or redist5_frac_x_uid10_fpToFxPTest_b_1_q or cstZeroWF_uid7_fpToFxPTest_q) - begin - unique case (fracPostZ_uid23_fpToFxPTest_s) - 1'b0 : fracPostZ_uid23_fpToFxPTest_q = redist5_frac_x_uid10_fpToFxPTest_b_1_q; - 1'b1 : fracPostZ_uid23_fpToFxPTest_q = cstZeroWF_uid7_fpToFxPTest_q; - default : fracPostZ_uid23_fpToFxPTest_q = 23'b0; - endcase - end - - // oFracX_uid25_fpToFxPTest(BITJOIN,24)@1 - assign oFracX_uid25_fpToFxPTest_q = {invExcXZ_uid24_fpToFxPTest_q, fracPostZ_uid23_fpToFxPTest_q}; - - // zPadd_uid41_fpToFxPTest(CONSTANT,40) - assign zPadd_uid41_fpToFxPTest_q = 9'b000000000; - - // shifterIn_uid42_fpToFxPTest(BITJOIN,41)@1 - assign shifterIn_uid42_fpToFxPTest_q = {oFracX_uid25_fpToFxPTest_q, zPadd_uid41_fpToFxPTest_q}; - - // rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest(MUX,68)@1 - assign rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_s = rightShiftStageSel0Dto0_uid68_rightShiferNoStickyOut_uid43_fpToFxPTest_merged_bit_select_b; - always @(rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_s or en or shifterIn_uid42_fpToFxPTest_q or rightShiftStage0Idx1_uid61_rightShiferNoStickyOut_uid43_fpToFxPTest_q or rightShiftStage0Idx2_uid64_rightShiferNoStickyOut_uid43_fpToFxPTest_q or rightShiftStage0Idx3_uid67_rightShiferNoStickyOut_uid43_fpToFxPTest_q) - begin - unique case (rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_s) - 2'b00 : rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_q = shifterIn_uid42_fpToFxPTest_q; - 2'b01 : rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_q = rightShiftStage0Idx1_uid61_rightShiferNoStickyOut_uid43_fpToFxPTest_q; - 2'b10 : rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_q = rightShiftStage0Idx2_uid64_rightShiferNoStickyOut_uid43_fpToFxPTest_q; - 2'b11 : rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_q = rightShiftStage0Idx3_uid67_rightShiferNoStickyOut_uid43_fpToFxPTest_q; - default : rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_q = 33'b0; - endcase - end - - // rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest(MUX,79)@1 - assign rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest_s = rightShiftStageSel0Dto0_uid68_rightShiferNoStickyOut_uid43_fpToFxPTest_merged_bit_select_c; - always @(rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest_s or en or rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_q or rightShiftStage1Idx1_uid72_rightShiferNoStickyOut_uid43_fpToFxPTest_q or rightShiftStage1Idx2_uid75_rightShiferNoStickyOut_uid43_fpToFxPTest_q or rightShiftStage1Idx3_uid78_rightShiferNoStickyOut_uid43_fpToFxPTest_q) - begin - unique case (rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest_s) - 2'b00 : rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest_q = rightShiftStage0_uid69_rightShiferNoStickyOut_uid43_fpToFxPTest_q; - 2'b01 : rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest_q = rightShiftStage1Idx1_uid72_rightShiferNoStickyOut_uid43_fpToFxPTest_q; - 2'b10 : rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest_q = rightShiftStage1Idx2_uid75_rightShiferNoStickyOut_uid43_fpToFxPTest_q; - 2'b11 : rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest_q = rightShiftStage1Idx3_uid78_rightShiferNoStickyOut_uid43_fpToFxPTest_q; - default : rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest_q = 33'b0; - endcase - end - - // maxShiftCst_uid38_fpToFxPTest(CONSTANT,37) - assign maxShiftCst_uid38_fpToFxPTest_q = 6'b100001; - - // ovfExpVal_uid35_fpToFxPTest(CONSTANT,34) - assign ovfExpVal_uid35_fpToFxPTest_q = 9'b010011110; - - // shiftValE_uid36_fpToFxPTest(SUB,35)@0 - assign shiftValE_uid36_fpToFxPTest_a = {{2{ovfExpVal_uid35_fpToFxPTest_q[8]}}, ovfExpVal_uid35_fpToFxPTest_q}; - assign shiftValE_uid36_fpToFxPTest_b = {3'b000, exp_x_uid9_fpToFxPTest_b}; - assign shiftValE_uid36_fpToFxPTest_o = $signed(shiftValE_uid36_fpToFxPTest_a) - $signed(shiftValE_uid36_fpToFxPTest_b); - assign shiftValE_uid36_fpToFxPTest_q = shiftValE_uid36_fpToFxPTest_o[9:0]; - - // shiftValRaw_uid37_fpToFxPTest(BITSELECT,36)@0 - assign shiftValRaw_uid37_fpToFxPTest_in = shiftValE_uid36_fpToFxPTest_q[5:0]; - assign shiftValRaw_uid37_fpToFxPTest_b = shiftValRaw_uid37_fpToFxPTest_in[5:0]; - - // shiftOutOfRange_uid39_fpToFxPTest(COMPARE,38)@0 - assign shiftOutOfRange_uid39_fpToFxPTest_a = {{2{shiftValE_uid36_fpToFxPTest_q[9]}}, shiftValE_uid36_fpToFxPTest_q}; - assign shiftOutOfRange_uid39_fpToFxPTest_b = {6'b000000, maxShiftCst_uid38_fpToFxPTest_q}; - assign shiftOutOfRange_uid39_fpToFxPTest_o = $signed(shiftOutOfRange_uid39_fpToFxPTest_a) - $signed(shiftOutOfRange_uid39_fpToFxPTest_b); - assign shiftOutOfRange_uid39_fpToFxPTest_n[0] = ~ (shiftOutOfRange_uid39_fpToFxPTest_o[11]); - - // shiftVal_uid40_fpToFxPTest(MUX,39)@0 + 1 - assign shiftVal_uid40_fpToFxPTest_s = shiftOutOfRange_uid39_fpToFxPTest_n; - always @ (posedge clk) - begin - if (areset) - begin - shiftVal_uid40_fpToFxPTest_q <= 6'b0; - end - else if (en == 1'b1) - begin - unique case (shiftVal_uid40_fpToFxPTest_s) - 1'b0 : shiftVal_uid40_fpToFxPTest_q <= shiftValRaw_uid37_fpToFxPTest_b; - 1'b1 : shiftVal_uid40_fpToFxPTest_q <= maxShiftCst_uid38_fpToFxPTest_q; - default : shiftVal_uid40_fpToFxPTest_q <= 6'b0; - endcase - end - end - - // rightShiftStageSel0Dto0_uid68_rightShiferNoStickyOut_uid43_fpToFxPTest_merged_bit_select(BITSELECT,90)@1 - assign rightShiftStageSel0Dto0_uid68_rightShiferNoStickyOut_uid43_fpToFxPTest_merged_bit_select_b = shiftVal_uid40_fpToFxPTest_q[1:0]; - assign rightShiftStageSel0Dto0_uid68_rightShiferNoStickyOut_uid43_fpToFxPTest_merged_bit_select_c = shiftVal_uid40_fpToFxPTest_q[3:2]; - assign rightShiftStageSel0Dto0_uid68_rightShiferNoStickyOut_uid43_fpToFxPTest_merged_bit_select_d = shiftVal_uid40_fpToFxPTest_q[5:4]; - - // rightShiftStage2_uid89_rightShiferNoStickyOut_uid43_fpToFxPTest(MUX,88)@1 + 1 - assign rightShiftStage2_uid89_rightShiferNoStickyOut_uid43_fpToFxPTest_s = rightShiftStageSel0Dto0_uid68_rightShiferNoStickyOut_uid43_fpToFxPTest_merged_bit_select_d; - always @ (posedge clk) - begin - if (areset) - begin - rightShiftStage2_uid89_rightShiferNoStickyOut_uid43_fpToFxPTest_q <= 33'b0; - end - else if (en == 1'b1) - begin - unique case (rightShiftStage2_uid89_rightShiferNoStickyOut_uid43_fpToFxPTest_s) - 2'b00 : rightShiftStage2_uid89_rightShiferNoStickyOut_uid43_fpToFxPTest_q <= rightShiftStage1_uid80_rightShiferNoStickyOut_uid43_fpToFxPTest_q; - 2'b01 : rightShiftStage2_uid89_rightShiferNoStickyOut_uid43_fpToFxPTest_q <= rightShiftStage2Idx1_uid83_rightShiferNoStickyOut_uid43_fpToFxPTest_q; - 2'b10 : rightShiftStage2_uid89_rightShiferNoStickyOut_uid43_fpToFxPTest_q <= rightShiftStage2Idx2_uid86_rightShiferNoStickyOut_uid43_fpToFxPTest_q; - 2'b11 : rightShiftStage2_uid89_rightShiferNoStickyOut_uid43_fpToFxPTest_q <= rightShiftStage2Idx3_uid87_rightShiferNoStickyOut_uid43_fpToFxPTest_q; - default : rightShiftStage2_uid89_rightShiferNoStickyOut_uid43_fpToFxPTest_q <= 33'b0; - endcase - end - end - - // zRightShiferNoStickyOut_uid47_fpToFxPTest(BITJOIN,46)@2 - assign zRightShiferNoStickyOut_uid47_fpToFxPTest_q = {GND_q, rightShiftStage2_uid89_rightShiferNoStickyOut_uid43_fpToFxPTest_q}; - - // sPostRndFull_uid48_fpToFxPTest(ADD,47)@2 - assign sPostRndFull_uid48_fpToFxPTest_a = {1'b0, zRightShiferNoStickyOut_uid47_fpToFxPTest_q}; - assign sPostRndFull_uid48_fpToFxPTest_b = {34'b0000000000000000000000000000000000, VCC_q}; - assign sPostRndFull_uid48_fpToFxPTest_o = $unsigned(sPostRndFull_uid48_fpToFxPTest_a) + $unsigned(sPostRndFull_uid48_fpToFxPTest_b); - assign sPostRndFull_uid48_fpToFxPTest_q = sPostRndFull_uid48_fpToFxPTest_o[34:0]; - - // sPostRnd_uid49_fpToFxPTest(BITSELECT,48)@2 - assign sPostRnd_uid49_fpToFxPTest_in = sPostRndFull_uid48_fpToFxPTest_q[32:0]; - assign sPostRnd_uid49_fpToFxPTest_b = sPostRnd_uid49_fpToFxPTest_in[32:1]; - - // redist0_sPostRnd_uid49_fpToFxPTest_b_1(DELAY,91) - always @ (posedge clk) - begin - if (areset) - begin - redist0_sPostRnd_uid49_fpToFxPTest_b_1_q <= '0; - end - else if (en == 1'b1) - begin - redist0_sPostRnd_uid49_fpToFxPTest_b_1_q <= sPostRnd_uid49_fpToFxPTest_b; - end - end - - // signX_uid27_fpToFxPTest(BITSELECT,26)@0 - assign signX_uid27_fpToFxPTest_b = a[31:31]; - - // redist3_signX_uid27_fpToFxPTest_b_1(DELAY,94) - always @ (posedge clk) - begin - if (areset) - begin - redist3_signX_uid27_fpToFxPTest_b_1_q <= '0; - end - else if (en == 1'b1) - begin - redist3_signX_uid27_fpToFxPTest_b_1_q <= signX_uid27_fpToFxPTest_b; - end - end - - // fracXIsZero_uid13_fpToFxPTest(LOGICAL,12)@1 - assign fracXIsZero_uid13_fpToFxPTest_q = cstZeroWF_uid7_fpToFxPTest_q == redist5_frac_x_uid10_fpToFxPTest_b_1_q ? 1'b1 : 1'b0; - - // fracXIsNotZero_uid14_fpToFxPTest(LOGICAL,13)@1 - assign fracXIsNotZero_uid14_fpToFxPTest_q = ~ (fracXIsZero_uid13_fpToFxPTest_q); - - // cstAllOWE_uid6_fpToFxPTest(CONSTANT,5) - assign cstAllOWE_uid6_fpToFxPTest_q = 8'b11111111; - - // expXIsMax_uid12_fpToFxPTest(LOGICAL,11)@0 + 1 - assign expXIsMax_uid12_fpToFxPTest_qi = exp_x_uid9_fpToFxPTest_b == cstAllOWE_uid6_fpToFxPTest_q ? 1'b1 : 1'b0; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) ) - expXIsMax_uid12_fpToFxPTest_delay ( .xin(expXIsMax_uid12_fpToFxPTest_qi), .xout(expXIsMax_uid12_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // excN_x_uid16_fpToFxPTest(LOGICAL,15)@1 - assign excN_x_uid16_fpToFxPTest_q = expXIsMax_uid12_fpToFxPTest_q & fracXIsNotZero_uid14_fpToFxPTest_q; - - // notNan_uid28_fpToFxPTest(LOGICAL,27)@1 - assign notNan_uid28_fpToFxPTest_q = ~ (excN_x_uid16_fpToFxPTest_q); - - // signX_uid29_fpToFxPTest(LOGICAL,28)@1 + 1 - assign signX_uid29_fpToFxPTest_qi = notNan_uid28_fpToFxPTest_q & redist3_signX_uid27_fpToFxPTest_b_1_q; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) ) - signX_uid29_fpToFxPTest_delay ( .xin(signX_uid29_fpToFxPTest_qi), .xout(signX_uid29_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // udfExpVal_uid33_fpToFxPTest(CONSTANT,32) - assign udfExpVal_uid33_fpToFxPTest_q = 8'b01111101; - - // udf_uid34_fpToFxPTest(COMPARE,33)@0 + 1 - assign udf_uid34_fpToFxPTest_a = {{3{udfExpVal_uid33_fpToFxPTest_q[7]}}, udfExpVal_uid33_fpToFxPTest_q}; - assign udf_uid34_fpToFxPTest_b = {3'b000, exp_x_uid9_fpToFxPTest_b}; - always @ (posedge clk) - begin - if (areset) - begin - udf_uid34_fpToFxPTest_o <= 11'b0; - end - else if (en == 1'b1) - begin - udf_uid34_fpToFxPTest_o <= $signed(udf_uid34_fpToFxPTest_a) - $signed(udf_uid34_fpToFxPTest_b); - end - end - assign udf_uid34_fpToFxPTest_n[0] = ~ (udf_uid34_fpToFxPTest_o[10]); - - // redist1_udf_uid34_fpToFxPTest_n_2(DELAY,92) - always @ (posedge clk) - begin - if (areset) - begin - redist1_udf_uid34_fpToFxPTest_n_2_q <= '0; - end - else if (en == 1'b1) - begin - redist1_udf_uid34_fpToFxPTest_n_2_q <= udf_uid34_fpToFxPTest_n; - end - end - - // sPostRndFullMSBU_uid50_fpToFxPTest(BITSELECT,49)@2 - assign sPostRndFullMSBU_uid50_fpToFxPTest_in = sPostRndFull_uid48_fpToFxPTest_q[33:0]; - assign sPostRndFullMSBU_uid50_fpToFxPTest_b = sPostRndFullMSBU_uid50_fpToFxPTest_in[33:33]; - - // ovfExpVal_uid30_fpToFxPTest(CONSTANT,29) - assign ovfExpVal_uid30_fpToFxPTest_q = 9'b010011111; - - // ovf_uid31_fpToFxPTest(COMPARE,30)@0 + 1 - assign ovf_uid31_fpToFxPTest_a = {3'b000, exp_x_uid9_fpToFxPTest_b}; - assign ovf_uid31_fpToFxPTest_b = {{2{ovfExpVal_uid30_fpToFxPTest_q[8]}}, ovfExpVal_uid30_fpToFxPTest_q}; - always @ (posedge clk) - begin - if (areset) - begin - ovf_uid31_fpToFxPTest_o <= 11'b0; - end - else if (en == 1'b1) - begin - ovf_uid31_fpToFxPTest_o <= $signed(ovf_uid31_fpToFxPTest_a) - $signed(ovf_uid31_fpToFxPTest_b); - end - end - assign ovf_uid31_fpToFxPTest_n[0] = ~ (ovf_uid31_fpToFxPTest_o[10]); - - // redist2_ovf_uid31_fpToFxPTest_n_2(DELAY,93) - always @ (posedge clk) - begin - if (areset) - begin - redist2_ovf_uid31_fpToFxPTest_n_2_q <= '0; - end - else if (en == 1'b1) - begin - redist2_ovf_uid31_fpToFxPTest_n_2_q <= ovf_uid31_fpToFxPTest_n; - end - end - - // negOrOvf_uid32_fpToFxPTest(LOGICAL,31)@2 - assign negOrOvf_uid32_fpToFxPTest_q = signX_uid29_fpToFxPTest_q | redist2_ovf_uid31_fpToFxPTest_n_2_q; - - // excI_x_uid15_fpToFxPTest(LOGICAL,14)@1 + 1 - assign excI_x_uid15_fpToFxPTest_qi = expXIsMax_uid12_fpToFxPTest_q & fracXIsZero_uid13_fpToFxPTest_q; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) ) - excI_x_uid15_fpToFxPTest_delay ( .xin(excI_x_uid15_fpToFxPTest_qi), .xout(excI_x_uid15_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist4_excN_x_uid16_fpToFxPTest_q_1(DELAY,95) - always @ (posedge clk) - begin - if (areset) - begin - redist4_excN_x_uid16_fpToFxPTest_q_1_q <= '0; - end - else if (en == 1'b1) - begin - redist4_excN_x_uid16_fpToFxPTest_q_1_q <= excN_x_uid16_fpToFxPTest_q; - end - end - - // ovfPostRnd_uid51_fpToFxPTest(LOGICAL,50)@2 - assign ovfPostRnd_uid51_fpToFxPTest_q = redist4_excN_x_uid16_fpToFxPTest_q_1_q | excI_x_uid15_fpToFxPTest_q | negOrOvf_uid32_fpToFxPTest_q | sPostRndFullMSBU_uid50_fpToFxPTest_b; - - // muxSelConc_uid52_fpToFxPTest(BITJOIN,51)@2 - assign muxSelConc_uid52_fpToFxPTest_q = {signX_uid29_fpToFxPTest_q, redist1_udf_uid34_fpToFxPTest_n_2_q, ovfPostRnd_uid51_fpToFxPTest_q}; - - // muxSel_uid53_fpToFxPTest(LOOKUP,52)@2 + 1 - always @ (posedge clk) - begin - if (areset) - begin - muxSel_uid53_fpToFxPTest_q <= 2'b00; - end - else if (en == 1'b1) - begin - unique case (muxSelConc_uid52_fpToFxPTest_q) - 3'b000 : muxSel_uid53_fpToFxPTest_q <= 2'b00; - 3'b001 : muxSel_uid53_fpToFxPTest_q <= 2'b01; - 3'b010 : muxSel_uid53_fpToFxPTest_q <= 2'b11; - 3'b011 : muxSel_uid53_fpToFxPTest_q <= 2'b00; - 3'b100 : muxSel_uid53_fpToFxPTest_q <= 2'b10; - 3'b101 : muxSel_uid53_fpToFxPTest_q <= 2'b10; - 3'b110 : muxSel_uid53_fpToFxPTest_q <= 2'b10; - 3'b111 : muxSel_uid53_fpToFxPTest_q <= 2'b10; - default : begin - // unreachable - muxSel_uid53_fpToFxPTest_q <= 2'bxx; - end - endcase - end - end - - // finalOut_uid55_fpToFxPTest(MUX,54)@3 - assign finalOut_uid55_fpToFxPTest_s = muxSel_uid53_fpToFxPTest_q; - always @(finalOut_uid55_fpToFxPTest_s or en or redist0_sPostRnd_uid49_fpToFxPTest_b_1_q or maxPosValueU_uid44_fpToFxPTest_q or maxNegValueU_uid45_fpToFxPTest_q) - begin - unique case (finalOut_uid55_fpToFxPTest_s) - 2'b00 : finalOut_uid55_fpToFxPTest_q = redist0_sPostRnd_uid49_fpToFxPTest_b_1_q; - 2'b01 : finalOut_uid55_fpToFxPTest_q = maxPosValueU_uid44_fpToFxPTest_q; - 2'b10 : finalOut_uid55_fpToFxPTest_q = maxNegValueU_uid45_fpToFxPTest_q; - 2'b11 : finalOut_uid55_fpToFxPTest_q = maxNegValueU_uid45_fpToFxPTest_q; - default : finalOut_uid55_fpToFxPTest_q = 32'b0; - endcase - end - - // xOut(GPOUT,4)@3 - assign q = finalOut_uid55_fpToFxPTest_q; - -endmodule diff --git a/hw/rtl/fp_cores/altera/stratix10/acl_gen.sh b/hw/rtl/fp_cores/altera/stratix10/acl_gen.sh index 483a5333..6bba5c3a 100755 --- a/hw/rtl/fp_cores/altera/stratix10/acl_gen.sh +++ b/hw/rtl/fp_cores/altera/stratix10/acl_gen.sh @@ -18,13 +18,16 @@ FBITS="f$(($EXP_BITS + $MAN_BITS + 1))" echo Generating IP cores for $FBITS { + #$CMD -name "$PREFIX"_fadd -frequency 250 FPAdd $EXP_BITS $MAN_BITS + #$CMD -name "$PREFIX"_fsub -frequency 250 FPSub $EXP_BITS $MAN_BITS + #$CMD -name "$PREFIX"_fmul -frequency 250 FPMul $EXP_BITS $MAN_BITS $CMD -name "$PREFIX"_fmadd -frequency 250 FPMultAdd $EXP_BITS $MAN_BITS $CMD -name "$PREFIX"_fdiv -frequency 250 FPDiv $EXP_BITS $MAN_BITS 0 $CMD -name "$PREFIX"_fsqrt -frequency 250 FPSqrt $EXP_BITS $MAN_BITS - $CMD -name "$PREFIX"_ftoi -frequency 250 FPToFXP $EXP_BITS $MAN_BITS 32 0 1 - $CMD -name "$PREFIX"_ftou -frequency 250 FPToFXP $EXP_BITS $MAN_BITS 32 0 0 - $CMD -name "$PREFIX"_itof -frequency 250 FXPToFP 32 0 1 $EXP_BITS $MAN_BITS - $CMD -name "$PREFIX"_utof -frequency 300 FXPToFP 32 0 0 $EXP_BITS $MAN_BITS + #$CMD -name "$PREFIX"_ftoi -frequency 250 FPToFXP $EXP_BITS $MAN_BITS 32 0 1 + #$CMD -name "$PREFIX"_ftou -frequency 250 FPToFXP $EXP_BITS $MAN_BITS 32 0 0 + #$CMD -name "$PREFIX"_itof -frequency 250 FXPToFP 32 0 1 $EXP_BITS $MAN_BITS + #$CMD -name "$PREFIX"_utof -frequency 300 FXPToFP 32 0 0 $EXP_BITS $MAN_BITS } > acl_gen.log 2>&1 #cp $QUARTUS_HOME/dspba/backend/Libraries/sv/base/dspba_library_ver.sv . \ No newline at end of file diff --git a/hw/rtl/fp_cores/altera/stratix10/acl_itof.sv b/hw/rtl/fp_cores/altera/stratix10/acl_itof.sv deleted file mode 100644 index 6c9458ef..00000000 --- a/hw/rtl/fp_cores/altera/stratix10/acl_itof.sv +++ /dev/null @@ -1,631 +0,0 @@ -// ------------------------------------------------------------------------- -// High Level Design Compiler for Intel(R) FPGAs Version 18.1 (Release Build #277) -// Quartus Prime development tool and MATLAB/Simulink Interface -// -// Legal Notice: Copyright 2019 Intel Corporation. All rights reserved. -// Your use of Intel Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly -// subject to the terms and conditions of the Intel FPGA Software License -// Agreement, Intel MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for -// the sole purpose of programming logic devices manufactured by Intel -// and sold by Intel or its authorized distributors. Please refer to the -// applicable agreement for further details. -// --------------------------------------------------------------------------- - -// SystemVerilog created from acl_itof -// SystemVerilog created on Sun Dec 27 09:48:58 2020 - - -(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) -module acl_itof ( - input wire [31:0] a, - input wire [0:0] en, - output wire [31:0] q, - input wire clk, - input wire areset - ); - - wire [0:0] GND_q; - wire [0:0] signX_uid6_fxpToFPTest_b; - wire [31:0] xXorSign_uid7_fxpToFPTest_b; - wire [31:0] xXorSign_uid7_fxpToFPTest_q; - wire [32:0] yE_uid8_fxpToFPTest_a; - wire [32:0] yE_uid8_fxpToFPTest_b; - logic [32:0] yE_uid8_fxpToFPTest_o; - wire [32:0] yE_uid8_fxpToFPTest_q; - wire [31:0] y_uid9_fxpToFPTest_in; - wire [31:0] y_uid9_fxpToFPTest_b; - wire [5:0] maxCount_uid11_fxpToFPTest_q; - wire [0:0] inIsZero_uid12_fxpToFPTest_qi; - reg [0:0] inIsZero_uid12_fxpToFPTest_q; - wire [7:0] msbIn_uid13_fxpToFPTest_q; - wire [8:0] expPreRnd_uid14_fxpToFPTest_a; - wire [8:0] expPreRnd_uid14_fxpToFPTest_b; - logic [8:0] expPreRnd_uid14_fxpToFPTest_o; - wire [8:0] expPreRnd_uid14_fxpToFPTest_q; - wire [32:0] expFracRnd_uid16_fxpToFPTest_q; - wire [0:0] sticky_uid20_fxpToFPTest_qi; - reg [0:0] sticky_uid20_fxpToFPTest_q; - wire [0:0] nr_uid21_fxpToFPTest_q; - wire [0:0] rnd_uid22_fxpToFPTest_q; - wire [34:0] expFracR_uid24_fxpToFPTest_a; - wire [34:0] expFracR_uid24_fxpToFPTest_b; - logic [34:0] expFracR_uid24_fxpToFPTest_o; - wire [33:0] expFracR_uid24_fxpToFPTest_q; - wire [23:0] fracR_uid25_fxpToFPTest_in; - wire [22:0] fracR_uid25_fxpToFPTest_b; - wire [9:0] expR_uid26_fxpToFPTest_b; - wire [11:0] udf_uid27_fxpToFPTest_a; - wire [11:0] udf_uid27_fxpToFPTest_b; - logic [11:0] udf_uid27_fxpToFPTest_o; - wire [0:0] udf_uid27_fxpToFPTest_n; - wire [7:0] expInf_uid28_fxpToFPTest_q; - wire [11:0] ovf_uid29_fxpToFPTest_a; - wire [11:0] ovf_uid29_fxpToFPTest_b; - logic [11:0] ovf_uid29_fxpToFPTest_o; - wire [0:0] ovf_uid29_fxpToFPTest_n; - wire [0:0] excSelector_uid30_fxpToFPTest_q; - wire [22:0] fracZ_uid31_fxpToFPTest_q; - wire [0:0] fracRPostExc_uid32_fxpToFPTest_s; - reg [22:0] fracRPostExc_uid32_fxpToFPTest_q; - wire [0:0] udfOrInZero_uid33_fxpToFPTest_q; - wire [1:0] excSelector_uid34_fxpToFPTest_q; - wire [7:0] expZ_uid37_fxpToFPTest_q; - wire [7:0] expR_uid38_fxpToFPTest_in; - wire [7:0] expR_uid38_fxpToFPTest_b; - wire [1:0] expRPostExc_uid39_fxpToFPTest_s; - reg [7:0] expRPostExc_uid39_fxpToFPTest_q; - wire [31:0] outRes_uid40_fxpToFPTest_q; - wire [31:0] zs_uid42_lzcShifterZ1_uid10_fxpToFPTest_q; - wire [0:0] vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_qi; - reg [0:0] vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q; - wire [0:0] vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_s; - reg [31:0] vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q; - wire [15:0] zs_uid47_lzcShifterZ1_uid10_fxpToFPTest_q; - wire [0:0] vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q; - wire [31:0] cStage_uid52_lzcShifterZ1_uid10_fxpToFPTest_q; - wire [0:0] vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_s; - reg [31:0] vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q; - wire [0:0] vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q; - wire [31:0] cStage_uid59_lzcShifterZ1_uid10_fxpToFPTest_q; - wire [0:0] vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_s; - reg [31:0] vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q; - wire [3:0] zs_uid61_lzcShifterZ1_uid10_fxpToFPTest_q; - wire [0:0] vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q; - wire [31:0] cStage_uid66_lzcShifterZ1_uid10_fxpToFPTest_q; - wire [0:0] vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_s; - reg [31:0] vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q; - wire [1:0] zs_uid68_lzcShifterZ1_uid10_fxpToFPTest_q; - wire [0:0] vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q; - wire [31:0] cStage_uid73_lzcShifterZ1_uid10_fxpToFPTest_q; - wire [0:0] vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_s; - reg [31:0] vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q; - wire [0:0] vCount_uid77_lzcShifterZ1_uid10_fxpToFPTest_q; - wire [31:0] cStage_uid80_lzcShifterZ1_uid10_fxpToFPTest_q; - wire [0:0] vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_s; - reg [31:0] vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_q; - wire [5:0] vCount_uid82_lzcShifterZ1_uid10_fxpToFPTest_q; - wire [7:0] vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_a; - wire [7:0] vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_b; - logic [7:0] vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_o; - wire [0:0] vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_c; - wire [0:0] vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_s; - reg [5:0] vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q; - wire [1:0] l_uid17_fxpToFPTest_merged_bit_select_in; - wire [0:0] l_uid17_fxpToFPTest_merged_bit_select_b; - wire [0:0] l_uid17_fxpToFPTest_merged_bit_select_c; - wire [15:0] rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b; - wire [15:0] rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c; - wire [7:0] rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b; - wire [23:0] rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c; - wire [3:0] rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b; - wire [27:0] rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c; - wire [1:0] rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b; - wire [29:0] rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c; - wire [0:0] rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b; - wire [30:0] rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c; - wire [30:0] fracRnd_uid15_fxpToFPTest_merged_bit_select_in; - wire [23:0] fracRnd_uid15_fxpToFPTest_merged_bit_select_b; - wire [6:0] fracRnd_uid15_fxpToFPTest_merged_bit_select_c; - reg [23:0] redist0_fracRnd_uid15_fxpToFPTest_merged_bit_select_b_1_q; - reg [0:0] redist1_vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q_1_q; - reg [0:0] redist2_vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q_1_q; - reg [0:0] redist3_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_2_q; - reg [0:0] redist3_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_2_delay_0; - reg [0:0] redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3_q; - reg [0:0] redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3_delay_0; - reg [0:0] redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3_delay_1; - reg [0:0] redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4_q; - reg [0:0] redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4_delay_0; - reg [0:0] redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4_delay_1; - reg [9:0] redist6_expR_uid26_fxpToFPTest_b_1_q; - reg [22:0] redist7_fracR_uid25_fxpToFPTest_b_1_q; - reg [0:0] redist8_inIsZero_uid12_fxpToFPTest_q_2_q; - reg [31:0] redist9_y_uid9_fxpToFPTest_b_1_q; - reg [31:0] redist10_y_uid9_fxpToFPTest_b_2_q; - reg [0:0] redist11_signX_uid6_fxpToFPTest_b_7_q; - - - // signX_uid6_fxpToFPTest(BITSELECT,5)@0 - assign signX_uid6_fxpToFPTest_b = a[31:31]; - - // redist11_signX_uid6_fxpToFPTest_b_7(DELAY,106) - dspba_delay_ver #( .width(1), .depth(7), .reset_kind("SYNC"), .phase(0), .modulus(1) ) - redist11_signX_uid6_fxpToFPTest_b_7 ( .xin(signX_uid6_fxpToFPTest_b), .xout(redist11_signX_uid6_fxpToFPTest_b_7_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // expInf_uid28_fxpToFPTest(CONSTANT,27) - assign expInf_uid28_fxpToFPTest_q = 8'b11111111; - - // expZ_uid37_fxpToFPTest(CONSTANT,36) - assign expZ_uid37_fxpToFPTest_q = 8'b00000000; - - // rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select(BITSELECT,93)@5 - assign rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b = vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q[31:31]; - assign rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c = vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q[30:0]; - - // GND(CONSTANT,0) - assign GND_q = 1'b0; - - // cStage_uid80_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,79)@5 - assign cStage_uid80_lzcShifterZ1_uid10_fxpToFPTest_q = {rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c, GND_q}; - - // rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select(BITSELECT,92)@4 - assign rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b = vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q[31:30]; - assign rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c = vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q[29:0]; - - // zs_uid68_lzcShifterZ1_uid10_fxpToFPTest(CONSTANT,67) - assign zs_uid68_lzcShifterZ1_uid10_fxpToFPTest_q = 2'b00; - - // cStage_uid73_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,72)@4 - assign cStage_uid73_lzcShifterZ1_uid10_fxpToFPTest_q = {rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c, zs_uid68_lzcShifterZ1_uid10_fxpToFPTest_q}; - - // rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select(BITSELECT,91)@4 - assign rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b = vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q[31:28]; - assign rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c = vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q[27:0]; - - // zs_uid61_lzcShifterZ1_uid10_fxpToFPTest(CONSTANT,60) - assign zs_uid61_lzcShifterZ1_uid10_fxpToFPTest_q = 4'b0000; - - // cStage_uid66_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,65)@4 - assign cStage_uid66_lzcShifterZ1_uid10_fxpToFPTest_q = {rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c, zs_uid61_lzcShifterZ1_uid10_fxpToFPTest_q}; - - // rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select(BITSELECT,90)@3 - assign rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b = vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q[31:24]; - assign rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c = vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q[23:0]; - - // cStage_uid59_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,58)@3 - assign cStage_uid59_lzcShifterZ1_uid10_fxpToFPTest_q = {rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c, expZ_uid37_fxpToFPTest_q}; - - // rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select(BITSELECT,89)@2 - assign rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b = vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q[31:16]; - assign rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c = vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q[15:0]; - - // zs_uid47_lzcShifterZ1_uid10_fxpToFPTest(CONSTANT,46) - assign zs_uid47_lzcShifterZ1_uid10_fxpToFPTest_q = 16'b0000000000000000; - - // cStage_uid52_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,51)@2 - assign cStage_uid52_lzcShifterZ1_uid10_fxpToFPTest_q = {rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c, zs_uid47_lzcShifterZ1_uid10_fxpToFPTest_q}; - - // zs_uid42_lzcShifterZ1_uid10_fxpToFPTest(CONSTANT,41) - assign zs_uid42_lzcShifterZ1_uid10_fxpToFPTest_q = 32'b00000000000000000000000000000000; - - // xXorSign_uid7_fxpToFPTest(LOGICAL,6)@0 - assign xXorSign_uid7_fxpToFPTest_b = {{31{signX_uid6_fxpToFPTest_b[0]}}, signX_uid6_fxpToFPTest_b}; - assign xXorSign_uid7_fxpToFPTest_q = a ^ xXorSign_uid7_fxpToFPTest_b; - - // yE_uid8_fxpToFPTest(ADD,7)@0 - assign yE_uid8_fxpToFPTest_a = {1'b0, xXorSign_uid7_fxpToFPTest_q}; - assign yE_uid8_fxpToFPTest_b = {32'b00000000000000000000000000000000, signX_uid6_fxpToFPTest_b}; - assign yE_uid8_fxpToFPTest_o = $unsigned(yE_uid8_fxpToFPTest_a) + $unsigned(yE_uid8_fxpToFPTest_b); - assign yE_uid8_fxpToFPTest_q = yE_uid8_fxpToFPTest_o[32:0]; - - // y_uid9_fxpToFPTest(BITSELECT,8)@0 - assign y_uid9_fxpToFPTest_in = yE_uid8_fxpToFPTest_q[31:0]; - assign y_uid9_fxpToFPTest_b = y_uid9_fxpToFPTest_in[31:0]; - - // redist9_y_uid9_fxpToFPTest_b_1(DELAY,104) - always @ (posedge clk) - begin - if (areset) - begin - redist9_y_uid9_fxpToFPTest_b_1_q <= '0; - end - else if (en == 1'b1) - begin - redist9_y_uid9_fxpToFPTest_b_1_q <= y_uid9_fxpToFPTest_b; - end - end - - // redist10_y_uid9_fxpToFPTest_b_2(DELAY,105) - always @ (posedge clk) - begin - if (areset) - begin - redist10_y_uid9_fxpToFPTest_b_2_q <= '0; - end - else if (en == 1'b1) - begin - redist10_y_uid9_fxpToFPTest_b_2_q <= redist9_y_uid9_fxpToFPTest_b_1_q; - end - end - - // vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,43)@1 + 1 - assign vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_qi = redist9_y_uid9_fxpToFPTest_b_1_q == zs_uid42_lzcShifterZ1_uid10_fxpToFPTest_q ? 1'b1 : 1'b0; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) ) - vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_delay ( .xin(vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_qi), .xout(vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest(MUX,45)@2 - assign vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q; - always @(vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_s or en or redist10_y_uid9_fxpToFPTest_b_2_q or zs_uid42_lzcShifterZ1_uid10_fxpToFPTest_q) - begin - unique case (vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_s) - 1'b0 : vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q = redist10_y_uid9_fxpToFPTest_b_2_q; - 1'b1 : vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q = zs_uid42_lzcShifterZ1_uid10_fxpToFPTest_q; - default : vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q = 32'b0; - endcase - end - - // vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,48)@2 - assign vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q = rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b == zs_uid47_lzcShifterZ1_uid10_fxpToFPTest_q ? 1'b1 : 1'b0; - - // vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest(MUX,52)@2 + 1 - assign vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q; - always @ (posedge clk) - begin - if (areset) - begin - vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q <= 32'b0; - end - else if (en == 1'b1) - begin - unique case (vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_s) - 1'b0 : vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q <= vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q; - 1'b1 : vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q <= cStage_uid52_lzcShifterZ1_uid10_fxpToFPTest_q; - default : vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q <= 32'b0; - endcase - end - end - - // vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,55)@3 - assign vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q = rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b == expZ_uid37_fxpToFPTest_q ? 1'b1 : 1'b0; - - // vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest(MUX,59)@3 + 1 - assign vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q; - always @ (posedge clk) - begin - if (areset) - begin - vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q <= 32'b0; - end - else if (en == 1'b1) - begin - unique case (vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_s) - 1'b0 : vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q <= vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q; - 1'b1 : vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q <= cStage_uid59_lzcShifterZ1_uid10_fxpToFPTest_q; - default : vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q <= 32'b0; - endcase - end - end - - // vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,62)@4 - assign vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q = rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b == zs_uid61_lzcShifterZ1_uid10_fxpToFPTest_q ? 1'b1 : 1'b0; - - // vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest(MUX,66)@4 - assign vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q; - always @(vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_s or en or vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q or cStage_uid66_lzcShifterZ1_uid10_fxpToFPTest_q) - begin - unique case (vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_s) - 1'b0 : vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q = vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q; - 1'b1 : vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q = cStage_uid66_lzcShifterZ1_uid10_fxpToFPTest_q; - default : vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q = 32'b0; - endcase - end - - // vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,69)@4 - assign vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q = rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b == zs_uid68_lzcShifterZ1_uid10_fxpToFPTest_q ? 1'b1 : 1'b0; - - // vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest(MUX,73)@4 + 1 - assign vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q; - always @ (posedge clk) - begin - if (areset) - begin - vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q <= 32'b0; - end - else if (en == 1'b1) - begin - unique case (vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_s) - 1'b0 : vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q <= vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q; - 1'b1 : vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q <= cStage_uid73_lzcShifterZ1_uid10_fxpToFPTest_q; - default : vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q <= 32'b0; - endcase - end - end - - // vCount_uid77_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,76)@5 - assign vCount_uid77_lzcShifterZ1_uid10_fxpToFPTest_q = rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b == GND_q ? 1'b1 : 1'b0; - - // vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest(MUX,80)@5 - assign vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid77_lzcShifterZ1_uid10_fxpToFPTest_q; - always @(vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_s or en or vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q or cStage_uid80_lzcShifterZ1_uid10_fxpToFPTest_q) - begin - unique case (vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_s) - 1'b0 : vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_q = vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q; - 1'b1 : vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_q = cStage_uid80_lzcShifterZ1_uid10_fxpToFPTest_q; - default : vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_q = 32'b0; - endcase - end - - // fracRnd_uid15_fxpToFPTest_merged_bit_select(BITSELECT,94)@5 - assign fracRnd_uid15_fxpToFPTest_merged_bit_select_in = vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_q[30:0]; - assign fracRnd_uid15_fxpToFPTest_merged_bit_select_b = fracRnd_uid15_fxpToFPTest_merged_bit_select_in[30:7]; - assign fracRnd_uid15_fxpToFPTest_merged_bit_select_c = fracRnd_uid15_fxpToFPTest_merged_bit_select_in[6:0]; - - // sticky_uid20_fxpToFPTest(LOGICAL,19)@5 + 1 - assign sticky_uid20_fxpToFPTest_qi = fracRnd_uid15_fxpToFPTest_merged_bit_select_c != 7'b0000000 ? 1'b1 : 1'b0; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) ) - sticky_uid20_fxpToFPTest_delay ( .xin(sticky_uid20_fxpToFPTest_qi), .xout(sticky_uid20_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // nr_uid21_fxpToFPTest(LOGICAL,20)@6 - assign nr_uid21_fxpToFPTest_q = ~ (l_uid17_fxpToFPTest_merged_bit_select_c); - - // l_uid17_fxpToFPTest_merged_bit_select(BITSELECT,88)@6 - assign l_uid17_fxpToFPTest_merged_bit_select_in = expFracRnd_uid16_fxpToFPTest_q[1:0]; - assign l_uid17_fxpToFPTest_merged_bit_select_b = l_uid17_fxpToFPTest_merged_bit_select_in[1:1]; - assign l_uid17_fxpToFPTest_merged_bit_select_c = l_uid17_fxpToFPTest_merged_bit_select_in[0:0]; - - // rnd_uid22_fxpToFPTest(LOGICAL,21)@6 - assign rnd_uid22_fxpToFPTest_q = l_uid17_fxpToFPTest_merged_bit_select_b | nr_uid21_fxpToFPTest_q | sticky_uid20_fxpToFPTest_q; - - // maxCount_uid11_fxpToFPTest(CONSTANT,10) - assign maxCount_uid11_fxpToFPTest_q = 6'b100000; - - // redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4(DELAY,100) - always @ (posedge clk) - begin - if (areset) - begin - redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4_delay_0 <= '0; - redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4_delay_1 <= '0; - redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4_q <= '0; - end - else if (en == 1'b1) - begin - redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4_delay_0 <= vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q; - redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4_delay_1 <= redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4_delay_0; - redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4_q <= redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4_delay_1; - end - end - - // redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3(DELAY,99) - always @ (posedge clk) - begin - if (areset) - begin - redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3_delay_0 <= '0; - redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3_delay_1 <= '0; - redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3_q <= '0; - end - else if (en == 1'b1) - begin - redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3_delay_0 <= vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q; - redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3_delay_1 <= redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3_delay_0; - redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3_q <= redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3_delay_1; - end - end - - // redist3_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_2(DELAY,98) - always @ (posedge clk) - begin - if (areset) - begin - redist3_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_2_delay_0 <= '0; - redist3_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_2_q <= '0; - end - else if (en == 1'b1) - begin - redist3_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_2_delay_0 <= vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q; - redist3_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_2_q <= redist3_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_2_delay_0; - end - end - - // redist2_vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q_1(DELAY,97) - always @ (posedge clk) - begin - if (areset) - begin - redist2_vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q_1_q <= '0; - end - else if (en == 1'b1) - begin - redist2_vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q_1_q <= vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q; - end - end - - // redist1_vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q_1(DELAY,96) - always @ (posedge clk) - begin - if (areset) - begin - redist1_vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q_1_q <= '0; - end - else if (en == 1'b1) - begin - redist1_vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q_1_q <= vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q; - end - end - - // vCount_uid82_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,81)@5 - assign vCount_uid82_lzcShifterZ1_uid10_fxpToFPTest_q = {redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4_q, redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3_q, redist3_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_2_q, redist2_vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q_1_q, redist1_vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q_1_q, vCount_uid77_lzcShifterZ1_uid10_fxpToFPTest_q}; - - // vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest(COMPARE,83)@5 - assign vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_a = {2'b00, maxCount_uid11_fxpToFPTest_q}; - assign vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_b = {2'b00, vCount_uid82_lzcShifterZ1_uid10_fxpToFPTest_q}; - assign vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_o = $unsigned(vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_a) - $unsigned(vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_b); - assign vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_c[0] = vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_o[7]; - - // vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest(MUX,85)@5 - assign vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_s = vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_c; - always @(vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_s or en or vCount_uid82_lzcShifterZ1_uid10_fxpToFPTest_q or maxCount_uid11_fxpToFPTest_q) - begin - unique case (vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_s) - 1'b0 : vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q = vCount_uid82_lzcShifterZ1_uid10_fxpToFPTest_q; - 1'b1 : vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q = maxCount_uid11_fxpToFPTest_q; - default : vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q = 6'b0; - endcase - end - - // msbIn_uid13_fxpToFPTest(CONSTANT,12) - assign msbIn_uid13_fxpToFPTest_q = 8'b10011110; - - // expPreRnd_uid14_fxpToFPTest(SUB,13)@5 + 1 - assign expPreRnd_uid14_fxpToFPTest_a = {1'b0, msbIn_uid13_fxpToFPTest_q}; - assign expPreRnd_uid14_fxpToFPTest_b = {3'b000, vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q}; - always @ (posedge clk) - begin - if (areset) - begin - expPreRnd_uid14_fxpToFPTest_o <= 9'b0; - end - else if (en == 1'b1) - begin - expPreRnd_uid14_fxpToFPTest_o <= $unsigned(expPreRnd_uid14_fxpToFPTest_a) - $unsigned(expPreRnd_uid14_fxpToFPTest_b); - end - end - assign expPreRnd_uid14_fxpToFPTest_q = expPreRnd_uid14_fxpToFPTest_o[8:0]; - - // redist0_fracRnd_uid15_fxpToFPTest_merged_bit_select_b_1(DELAY,95) - always @ (posedge clk) - begin - if (areset) - begin - redist0_fracRnd_uid15_fxpToFPTest_merged_bit_select_b_1_q <= '0; - end - else if (en == 1'b1) - begin - redist0_fracRnd_uid15_fxpToFPTest_merged_bit_select_b_1_q <= fracRnd_uid15_fxpToFPTest_merged_bit_select_b; - end - end - - // expFracRnd_uid16_fxpToFPTest(BITJOIN,15)@6 - assign expFracRnd_uid16_fxpToFPTest_q = {expPreRnd_uid14_fxpToFPTest_q, redist0_fracRnd_uid15_fxpToFPTest_merged_bit_select_b_1_q}; - - // expFracR_uid24_fxpToFPTest(ADD,23)@6 - assign expFracR_uid24_fxpToFPTest_a = {{2{expFracRnd_uid16_fxpToFPTest_q[32]}}, expFracRnd_uid16_fxpToFPTest_q}; - assign expFracR_uid24_fxpToFPTest_b = {34'b0000000000000000000000000000000000, rnd_uid22_fxpToFPTest_q}; - assign expFracR_uid24_fxpToFPTest_o = $signed(expFracR_uid24_fxpToFPTest_a) + $signed(expFracR_uid24_fxpToFPTest_b); - assign expFracR_uid24_fxpToFPTest_q = expFracR_uid24_fxpToFPTest_o[33:0]; - - // expR_uid26_fxpToFPTest(BITSELECT,25)@6 - assign expR_uid26_fxpToFPTest_b = expFracR_uid24_fxpToFPTest_q[33:24]; - - // redist6_expR_uid26_fxpToFPTest_b_1(DELAY,101) - always @ (posedge clk) - begin - if (areset) - begin - redist6_expR_uid26_fxpToFPTest_b_1_q <= '0; - end - else if (en == 1'b1) - begin - redist6_expR_uid26_fxpToFPTest_b_1_q <= expR_uid26_fxpToFPTest_b; - end - end - - // expR_uid38_fxpToFPTest(BITSELECT,37)@7 - assign expR_uid38_fxpToFPTest_in = redist6_expR_uid26_fxpToFPTest_b_1_q[7:0]; - assign expR_uid38_fxpToFPTest_b = expR_uid38_fxpToFPTest_in[7:0]; - - // ovf_uid29_fxpToFPTest(COMPARE,28)@7 - assign ovf_uid29_fxpToFPTest_a = {{2{redist6_expR_uid26_fxpToFPTest_b_1_q[9]}}, redist6_expR_uid26_fxpToFPTest_b_1_q}; - assign ovf_uid29_fxpToFPTest_b = {4'b0000, expInf_uid28_fxpToFPTest_q}; - assign ovf_uid29_fxpToFPTest_o = $signed(ovf_uid29_fxpToFPTest_a) - $signed(ovf_uid29_fxpToFPTest_b); - assign ovf_uid29_fxpToFPTest_n[0] = ~ (ovf_uid29_fxpToFPTest_o[11]); - - // inIsZero_uid12_fxpToFPTest(LOGICAL,11)@5 + 1 - assign inIsZero_uid12_fxpToFPTest_qi = vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q == maxCount_uid11_fxpToFPTest_q ? 1'b1 : 1'b0; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) ) - inIsZero_uid12_fxpToFPTest_delay ( .xin(inIsZero_uid12_fxpToFPTest_qi), .xout(inIsZero_uid12_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist8_inIsZero_uid12_fxpToFPTest_q_2(DELAY,103) - always @ (posedge clk) - begin - if (areset) - begin - redist8_inIsZero_uid12_fxpToFPTest_q_2_q <= '0; - end - else if (en == 1'b1) - begin - redist8_inIsZero_uid12_fxpToFPTest_q_2_q <= inIsZero_uid12_fxpToFPTest_q; - end - end - - // udf_uid27_fxpToFPTest(COMPARE,26)@7 - assign udf_uid27_fxpToFPTest_a = {11'b00000000000, GND_q}; - assign udf_uid27_fxpToFPTest_b = {{2{redist6_expR_uid26_fxpToFPTest_b_1_q[9]}}, redist6_expR_uid26_fxpToFPTest_b_1_q}; - assign udf_uid27_fxpToFPTest_o = $signed(udf_uid27_fxpToFPTest_a) - $signed(udf_uid27_fxpToFPTest_b); - assign udf_uid27_fxpToFPTest_n[0] = ~ (udf_uid27_fxpToFPTest_o[11]); - - // udfOrInZero_uid33_fxpToFPTest(LOGICAL,32)@7 - assign udfOrInZero_uid33_fxpToFPTest_q = udf_uid27_fxpToFPTest_n | redist8_inIsZero_uid12_fxpToFPTest_q_2_q; - - // excSelector_uid34_fxpToFPTest(BITJOIN,33)@7 - assign excSelector_uid34_fxpToFPTest_q = {ovf_uid29_fxpToFPTest_n, udfOrInZero_uid33_fxpToFPTest_q}; - - // expRPostExc_uid39_fxpToFPTest(MUX,38)@7 - assign expRPostExc_uid39_fxpToFPTest_s = excSelector_uid34_fxpToFPTest_q; - always @(expRPostExc_uid39_fxpToFPTest_s or en or expR_uid38_fxpToFPTest_b or expZ_uid37_fxpToFPTest_q or expInf_uid28_fxpToFPTest_q) - begin - unique case (expRPostExc_uid39_fxpToFPTest_s) - 2'b00 : expRPostExc_uid39_fxpToFPTest_q = expR_uid38_fxpToFPTest_b; - 2'b01 : expRPostExc_uid39_fxpToFPTest_q = expZ_uid37_fxpToFPTest_q; - 2'b10 : expRPostExc_uid39_fxpToFPTest_q = expInf_uid28_fxpToFPTest_q; - 2'b11 : expRPostExc_uid39_fxpToFPTest_q = expInf_uid28_fxpToFPTest_q; - default : expRPostExc_uid39_fxpToFPTest_q = 8'b0; - endcase - end - - // fracZ_uid31_fxpToFPTest(CONSTANT,30) - assign fracZ_uid31_fxpToFPTest_q = 23'b00000000000000000000000; - - // fracR_uid25_fxpToFPTest(BITSELECT,24)@6 - assign fracR_uid25_fxpToFPTest_in = expFracR_uid24_fxpToFPTest_q[23:0]; - assign fracR_uid25_fxpToFPTest_b = fracR_uid25_fxpToFPTest_in[23:1]; - - // redist7_fracR_uid25_fxpToFPTest_b_1(DELAY,102) - always @ (posedge clk) - begin - if (areset) - begin - redist7_fracR_uid25_fxpToFPTest_b_1_q <= '0; - end - else if (en == 1'b1) - begin - redist7_fracR_uid25_fxpToFPTest_b_1_q <= fracR_uid25_fxpToFPTest_b; - end - end - - // excSelector_uid30_fxpToFPTest(LOGICAL,29)@7 - assign excSelector_uid30_fxpToFPTest_q = redist8_inIsZero_uid12_fxpToFPTest_q_2_q | ovf_uid29_fxpToFPTest_n | udf_uid27_fxpToFPTest_n; - - // fracRPostExc_uid32_fxpToFPTest(MUX,31)@7 - assign fracRPostExc_uid32_fxpToFPTest_s = excSelector_uid30_fxpToFPTest_q; - always @(fracRPostExc_uid32_fxpToFPTest_s or en or redist7_fracR_uid25_fxpToFPTest_b_1_q or fracZ_uid31_fxpToFPTest_q) - begin - unique case (fracRPostExc_uid32_fxpToFPTest_s) - 1'b0 : fracRPostExc_uid32_fxpToFPTest_q = redist7_fracR_uid25_fxpToFPTest_b_1_q; - 1'b1 : fracRPostExc_uid32_fxpToFPTest_q = fracZ_uid31_fxpToFPTest_q; - default : fracRPostExc_uid32_fxpToFPTest_q = 23'b0; - endcase - end - - // outRes_uid40_fxpToFPTest(BITJOIN,39)@7 - assign outRes_uid40_fxpToFPTest_q = {redist11_signX_uid6_fxpToFPTest_b_7_q, expRPostExc_uid39_fxpToFPTest_q, fracRPostExc_uid32_fxpToFPTest_q}; - - // xOut(GPOUT,4)@7 - assign q = outRes_uid40_fxpToFPTest_q; - -endmodule diff --git a/hw/rtl/fp_cores/altera/stratix10/acl_utof.sv b/hw/rtl/fp_cores/altera/stratix10/acl_utof.sv deleted file mode 100644 index f8b4897a..00000000 --- a/hw/rtl/fp_cores/altera/stratix10/acl_utof.sv +++ /dev/null @@ -1,607 +0,0 @@ -// ------------------------------------------------------------------------- -// High Level Design Compiler for Intel(R) FPGAs Version 18.1 (Release Build #277) -// Quartus Prime development tool and MATLAB/Simulink Interface -// -// Legal Notice: Copyright 2019 Intel Corporation. All rights reserved. -// Your use of Intel Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly -// subject to the terms and conditions of the Intel FPGA Software License -// Agreement, Intel MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for -// the sole purpose of programming logic devices manufactured by Intel -// and sold by Intel or its authorized distributors. Please refer to the -// applicable agreement for further details. -// --------------------------------------------------------------------------- - -// SystemVerilog created from acl_utof -// SystemVerilog created on Sun Dec 27 09:48:58 2020 - - -(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) -module acl_utof ( - input wire [31:0] a, - input wire [0:0] en, - output wire [31:0] q, - input wire clk, - input wire areset - ); - - wire [0:0] GND_q; - wire [5:0] maxCount_uid7_fxpToFPTest_q; - wire [0:0] inIsZero_uid8_fxpToFPTest_qi; - reg [0:0] inIsZero_uid8_fxpToFPTest_q; - wire [7:0] msbIn_uid9_fxpToFPTest_q; - wire [8:0] expPreRnd_uid10_fxpToFPTest_a; - wire [8:0] expPreRnd_uid10_fxpToFPTest_b; - logic [8:0] expPreRnd_uid10_fxpToFPTest_o; - wire [8:0] expPreRnd_uid10_fxpToFPTest_q; - wire [32:0] expFracRnd_uid12_fxpToFPTest_q; - wire [0:0] sticky_uid16_fxpToFPTest_q; - wire [0:0] nr_uid17_fxpToFPTest_q; - wire [0:0] rnd_uid18_fxpToFPTest_qi; - reg [0:0] rnd_uid18_fxpToFPTest_q; - wire [34:0] expFracR_uid20_fxpToFPTest_a; - wire [34:0] expFracR_uid20_fxpToFPTest_b; - logic [34:0] expFracR_uid20_fxpToFPTest_o; - wire [33:0] expFracR_uid20_fxpToFPTest_q; - wire [23:0] fracR_uid21_fxpToFPTest_in; - wire [22:0] fracR_uid21_fxpToFPTest_b; - wire [9:0] expR_uid22_fxpToFPTest_b; - wire [11:0] udf_uid23_fxpToFPTest_a; - wire [11:0] udf_uid23_fxpToFPTest_b; - logic [11:0] udf_uid23_fxpToFPTest_o; - wire [0:0] udf_uid23_fxpToFPTest_n; - wire [7:0] expInf_uid24_fxpToFPTest_q; - wire [11:0] ovf_uid25_fxpToFPTest_a; - wire [11:0] ovf_uid25_fxpToFPTest_b; - logic [11:0] ovf_uid25_fxpToFPTest_o; - wire [0:0] ovf_uid25_fxpToFPTest_n; - wire [0:0] excSelector_uid26_fxpToFPTest_q; - wire [22:0] fracZ_uid27_fxpToFPTest_q; - wire [0:0] fracRPostExc_uid28_fxpToFPTest_s; - reg [22:0] fracRPostExc_uid28_fxpToFPTest_q; - wire [0:0] udfOrInZero_uid29_fxpToFPTest_q; - wire [1:0] excSelector_uid30_fxpToFPTest_q; - wire [7:0] expZ_uid33_fxpToFPTest_q; - wire [7:0] expR_uid34_fxpToFPTest_in; - wire [7:0] expR_uid34_fxpToFPTest_b; - wire [1:0] expRPostExc_uid35_fxpToFPTest_s; - reg [7:0] expRPostExc_uid35_fxpToFPTest_q; - wire [31:0] outRes_uid36_fxpToFPTest_q; - wire [31:0] zs_uid38_lzcShifterZ1_uid6_fxpToFPTest_q; - wire [0:0] vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q; - wire [0:0] vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_s; - reg [31:0] vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q; - wire [15:0] zs_uid43_lzcShifterZ1_uid6_fxpToFPTest_q; - wire [0:0] vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q; - wire [31:0] cStage_uid48_lzcShifterZ1_uid6_fxpToFPTest_q; - wire [0:0] vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_s; - reg [31:0] vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q; - wire [0:0] vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q; - wire [31:0] cStage_uid55_lzcShifterZ1_uid6_fxpToFPTest_q; - wire [0:0] vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_s; - reg [31:0] vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q; - wire [3:0] zs_uid57_lzcShifterZ1_uid6_fxpToFPTest_q; - wire [0:0] vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q; - wire [31:0] cStage_uid62_lzcShifterZ1_uid6_fxpToFPTest_q; - wire [0:0] vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_s; - reg [31:0] vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q; - wire [1:0] zs_uid64_lzcShifterZ1_uid6_fxpToFPTest_q; - wire [0:0] vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q; - wire [31:0] cStage_uid69_lzcShifterZ1_uid6_fxpToFPTest_q; - wire [0:0] vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_s; - reg [31:0] vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q; - wire [0:0] vCount_uid73_lzcShifterZ1_uid6_fxpToFPTest_q; - wire [31:0] cStage_uid76_lzcShifterZ1_uid6_fxpToFPTest_q; - wire [0:0] vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_s; - reg [31:0] vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_q; - wire [5:0] vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q; - wire [7:0] vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_a; - wire [7:0] vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_b; - logic [7:0] vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_o; - wire [0:0] vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_c; - wire [0:0] vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_s; - reg [5:0] vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q; - wire [1:0] l_uid13_fxpToFPTest_merged_bit_select_in; - wire [0:0] l_uid13_fxpToFPTest_merged_bit_select_b; - wire [0:0] l_uid13_fxpToFPTest_merged_bit_select_c; - wire [15:0] rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b; - wire [15:0] rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c; - wire [7:0] rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b; - wire [23:0] rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c; - wire [3:0] rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b; - wire [27:0] rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c; - wire [1:0] rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b; - wire [29:0] rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c; - wire [0:0] rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b; - wire [30:0] rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c; - wire [30:0] fracRnd_uid11_fxpToFPTest_merged_bit_select_in; - wire [23:0] fracRnd_uid11_fxpToFPTest_merged_bit_select_b; - wire [6:0] fracRnd_uid11_fxpToFPTest_merged_bit_select_c; - reg [23:0] redist0_fracRnd_uid11_fxpToFPTest_merged_bit_select_b_1_q; - reg [6:0] redist1_fracRnd_uid11_fxpToFPTest_merged_bit_select_c_1_q; - reg [5:0] redist2_vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q_1_q; - reg [0:0] redist3_vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q_1_q; - reg [0:0] redist4_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2_q; - reg [0:0] redist4_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2_delay_0; - reg [0:0] redist5_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_q; - reg [0:0] redist5_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_delay_0; - reg [0:0] redist5_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_delay_1; - reg [0:0] redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_q; - reg [0:0] redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_delay_0; - reg [0:0] redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_delay_1; - reg [0:0] redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_delay_2; - reg [9:0] redist7_expR_uid22_fxpToFPTest_b_1_q; - reg [22:0] redist8_fracR_uid21_fxpToFPTest_b_1_q; - reg [32:0] redist9_expFracRnd_uid12_fxpToFPTest_q_1_q; - reg [0:0] redist10_inIsZero_uid8_fxpToFPTest_q_2_q; - - - // GND(CONSTANT,0) - assign GND_q = 1'b0; - - // expInf_uid24_fxpToFPTest(CONSTANT,23) - assign expInf_uid24_fxpToFPTest_q = 8'b11111111; - - // expZ_uid33_fxpToFPTest(CONSTANT,32) - assign expZ_uid33_fxpToFPTest_q = 8'b00000000; - - // rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select(BITSELECT,89)@4 - assign rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b = vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q[31:31]; - assign rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c = vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q[30:0]; - - // cStage_uid76_lzcShifterZ1_uid6_fxpToFPTest(BITJOIN,75)@4 - assign cStage_uid76_lzcShifterZ1_uid6_fxpToFPTest_q = {rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c, GND_q}; - - // rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select(BITSELECT,88)@4 - assign rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b = vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q[31:30]; - assign rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c = vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q[29:0]; - - // zs_uid64_lzcShifterZ1_uid6_fxpToFPTest(CONSTANT,63) - assign zs_uid64_lzcShifterZ1_uid6_fxpToFPTest_q = 2'b00; - - // cStage_uid69_lzcShifterZ1_uid6_fxpToFPTest(BITJOIN,68)@4 - assign cStage_uid69_lzcShifterZ1_uid6_fxpToFPTest_q = {rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c, zs_uid64_lzcShifterZ1_uid6_fxpToFPTest_q}; - - // rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select(BITSELECT,87)@3 - assign rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b = vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q[31:28]; - assign rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c = vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q[27:0]; - - // zs_uid57_lzcShifterZ1_uid6_fxpToFPTest(CONSTANT,56) - assign zs_uid57_lzcShifterZ1_uid6_fxpToFPTest_q = 4'b0000; - - // cStage_uid62_lzcShifterZ1_uid6_fxpToFPTest(BITJOIN,61)@3 - assign cStage_uid62_lzcShifterZ1_uid6_fxpToFPTest_q = {rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c, zs_uid57_lzcShifterZ1_uid6_fxpToFPTest_q}; - - // rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select(BITSELECT,86)@2 - assign rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b = vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q[31:24]; - assign rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c = vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q[23:0]; - - // cStage_uid55_lzcShifterZ1_uid6_fxpToFPTest(BITJOIN,54)@2 - assign cStage_uid55_lzcShifterZ1_uid6_fxpToFPTest_q = {rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c, expZ_uid33_fxpToFPTest_q}; - - // rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select(BITSELECT,85)@1 - assign rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b = vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q[31:16]; - assign rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c = vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q[15:0]; - - // zs_uid43_lzcShifterZ1_uid6_fxpToFPTest(CONSTANT,42) - assign zs_uid43_lzcShifterZ1_uid6_fxpToFPTest_q = 16'b0000000000000000; - - // cStage_uid48_lzcShifterZ1_uid6_fxpToFPTest(BITJOIN,47)@1 - assign cStage_uid48_lzcShifterZ1_uid6_fxpToFPTest_q = {rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c, zs_uid43_lzcShifterZ1_uid6_fxpToFPTest_q}; - - // zs_uid38_lzcShifterZ1_uid6_fxpToFPTest(CONSTANT,37) - assign zs_uid38_lzcShifterZ1_uid6_fxpToFPTest_q = 32'b00000000000000000000000000000000; - - // vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest(LOGICAL,39)@0 - assign vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q = a == zs_uid38_lzcShifterZ1_uid6_fxpToFPTest_q ? 1'b1 : 1'b0; - - // vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest(MUX,41)@0 + 1 - assign vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_s = vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q; - always @ (posedge clk) - begin - if (areset) - begin - vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0; - end - else if (en == 1'b1) - begin - unique case (vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_s) - 1'b0 : vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q <= a; - 1'b1 : vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q <= zs_uid38_lzcShifterZ1_uid6_fxpToFPTest_q; - default : vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0; - endcase - end - end - - // vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest(LOGICAL,44)@1 - assign vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q = rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b == zs_uid43_lzcShifterZ1_uid6_fxpToFPTest_q ? 1'b1 : 1'b0; - - // vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest(MUX,48)@1 + 1 - assign vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_s = vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q; - always @ (posedge clk) - begin - if (areset) - begin - vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0; - end - else if (en == 1'b1) - begin - unique case (vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_s) - 1'b0 : vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q <= vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q; - 1'b1 : vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q <= cStage_uid48_lzcShifterZ1_uid6_fxpToFPTest_q; - default : vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0; - endcase - end - end - - // vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest(LOGICAL,51)@2 - assign vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q = rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b == expZ_uid33_fxpToFPTest_q ? 1'b1 : 1'b0; - - // vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest(MUX,55)@2 + 1 - assign vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_s = vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q; - always @ (posedge clk) - begin - if (areset) - begin - vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0; - end - else if (en == 1'b1) - begin - unique case (vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_s) - 1'b0 : vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q <= vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q; - 1'b1 : vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q <= cStage_uid55_lzcShifterZ1_uid6_fxpToFPTest_q; - default : vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0; - endcase - end - end - - // vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest(LOGICAL,58)@3 - assign vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q = rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b == zs_uid57_lzcShifterZ1_uid6_fxpToFPTest_q ? 1'b1 : 1'b0; - - // vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest(MUX,62)@3 + 1 - assign vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_s = vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q; - always @ (posedge clk) - begin - if (areset) - begin - vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0; - end - else if (en == 1'b1) - begin - unique case (vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_s) - 1'b0 : vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q <= vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q; - 1'b1 : vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q <= cStage_uid62_lzcShifterZ1_uid6_fxpToFPTest_q; - default : vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0; - endcase - end - end - - // vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest(LOGICAL,65)@4 - assign vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q = rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b == zs_uid64_lzcShifterZ1_uid6_fxpToFPTest_q ? 1'b1 : 1'b0; - - // vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest(MUX,69)@4 - assign vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_s = vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q; - always @(vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_s or en or vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q or cStage_uid69_lzcShifterZ1_uid6_fxpToFPTest_q) - begin - unique case (vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_s) - 1'b0 : vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q = vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q; - 1'b1 : vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q = cStage_uid69_lzcShifterZ1_uid6_fxpToFPTest_q; - default : vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q = 32'b0; - endcase - end - - // vCount_uid73_lzcShifterZ1_uid6_fxpToFPTest(LOGICAL,72)@4 - assign vCount_uid73_lzcShifterZ1_uid6_fxpToFPTest_q = rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b == GND_q ? 1'b1 : 1'b0; - - // vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest(MUX,76)@4 - assign vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_s = vCount_uid73_lzcShifterZ1_uid6_fxpToFPTest_q; - always @(vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_s or en or vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q or cStage_uid76_lzcShifterZ1_uid6_fxpToFPTest_q) - begin - unique case (vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_s) - 1'b0 : vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_q = vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q; - 1'b1 : vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_q = cStage_uid76_lzcShifterZ1_uid6_fxpToFPTest_q; - default : vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_q = 32'b0; - endcase - end - - // fracRnd_uid11_fxpToFPTest_merged_bit_select(BITSELECT,90)@4 - assign fracRnd_uid11_fxpToFPTest_merged_bit_select_in = vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_q[30:0]; - assign fracRnd_uid11_fxpToFPTest_merged_bit_select_b = fracRnd_uid11_fxpToFPTest_merged_bit_select_in[30:7]; - assign fracRnd_uid11_fxpToFPTest_merged_bit_select_c = fracRnd_uid11_fxpToFPTest_merged_bit_select_in[6:0]; - - // redist1_fracRnd_uid11_fxpToFPTest_merged_bit_select_c_1(DELAY,92) - always @ (posedge clk) - begin - if (areset) - begin - redist1_fracRnd_uid11_fxpToFPTest_merged_bit_select_c_1_q <= '0; - end - else if (en == 1'b1) - begin - redist1_fracRnd_uid11_fxpToFPTest_merged_bit_select_c_1_q <= fracRnd_uid11_fxpToFPTest_merged_bit_select_c; - end - end - - // sticky_uid16_fxpToFPTest(LOGICAL,15)@5 - assign sticky_uid16_fxpToFPTest_q = redist1_fracRnd_uid11_fxpToFPTest_merged_bit_select_c_1_q != 7'b0000000 ? 1'b1 : 1'b0; - - // nr_uid17_fxpToFPTest(LOGICAL,16)@5 - assign nr_uid17_fxpToFPTest_q = ~ (l_uid13_fxpToFPTest_merged_bit_select_c); - - // maxCount_uid7_fxpToFPTest(CONSTANT,6) - assign maxCount_uid7_fxpToFPTest_q = 6'b100000; - - // redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4(DELAY,97) - always @ (posedge clk) - begin - if (areset) - begin - redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_delay_0 <= '0; - redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_delay_1 <= '0; - redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_delay_2 <= '0; - redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_q <= '0; - end - else if (en == 1'b1) - begin - redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_delay_0 <= vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q; - redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_delay_1 <= redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_delay_0; - redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_delay_2 <= redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_delay_1; - redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_q <= redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_delay_2; - end - end - - // redist5_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3(DELAY,96) - always @ (posedge clk) - begin - if (areset) - begin - redist5_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_delay_0 <= '0; - redist5_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_delay_1 <= '0; - redist5_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_q <= '0; - end - else if (en == 1'b1) - begin - redist5_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_delay_0 <= vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q; - redist5_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_delay_1 <= redist5_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_delay_0; - redist5_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_q <= redist5_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_delay_1; - end - end - - // redist4_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2(DELAY,95) - always @ (posedge clk) - begin - if (areset) - begin - redist4_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2_delay_0 <= '0; - redist4_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2_q <= '0; - end - else if (en == 1'b1) - begin - redist4_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2_delay_0 <= vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q; - redist4_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2_q <= redist4_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2_delay_0; - end - end - - // redist3_vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q_1(DELAY,94) - always @ (posedge clk) - begin - if (areset) - begin - redist3_vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q_1_q <= '0; - end - else if (en == 1'b1) - begin - redist3_vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q_1_q <= vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q; - end - end - - // vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest(BITJOIN,77)@4 - assign vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q = {redist6_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_q, redist5_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_q, redist4_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2_q, redist3_vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q_1_q, vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q, vCount_uid73_lzcShifterZ1_uid6_fxpToFPTest_q}; - - // redist2_vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q_1(DELAY,93) - always @ (posedge clk) - begin - if (areset) - begin - redist2_vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q_1_q <= '0; - end - else if (en == 1'b1) - begin - redist2_vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q_1_q <= vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q; - end - end - - // vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest(COMPARE,79)@4 + 1 - assign vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_a = {2'b00, maxCount_uid7_fxpToFPTest_q}; - assign vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_b = {2'b00, vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q}; - always @ (posedge clk) - begin - if (areset) - begin - vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_o <= 8'b0; - end - else if (en == 1'b1) - begin - vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_o <= $unsigned(vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_a) - $unsigned(vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_b); - end - end - assign vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_c[0] = vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_o[7]; - - // vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest(MUX,81)@5 - assign vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_s = vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_c; - always @(vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_s or en or redist2_vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q_1_q or maxCount_uid7_fxpToFPTest_q) - begin - unique case (vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_s) - 1'b0 : vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q = redist2_vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q_1_q; - 1'b1 : vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q = maxCount_uid7_fxpToFPTest_q; - default : vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q = 6'b0; - endcase - end - - // msbIn_uid9_fxpToFPTest(CONSTANT,8) - assign msbIn_uid9_fxpToFPTest_q = 8'b10011110; - - // expPreRnd_uid10_fxpToFPTest(SUB,9)@5 - assign expPreRnd_uid10_fxpToFPTest_a = {1'b0, msbIn_uid9_fxpToFPTest_q}; - assign expPreRnd_uid10_fxpToFPTest_b = {3'b000, vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q}; - assign expPreRnd_uid10_fxpToFPTest_o = $unsigned(expPreRnd_uid10_fxpToFPTest_a) - $unsigned(expPreRnd_uid10_fxpToFPTest_b); - assign expPreRnd_uid10_fxpToFPTest_q = expPreRnd_uid10_fxpToFPTest_o[8:0]; - - // redist0_fracRnd_uid11_fxpToFPTest_merged_bit_select_b_1(DELAY,91) - always @ (posedge clk) - begin - if (areset) - begin - redist0_fracRnd_uid11_fxpToFPTest_merged_bit_select_b_1_q <= '0; - end - else if (en == 1'b1) - begin - redist0_fracRnd_uid11_fxpToFPTest_merged_bit_select_b_1_q <= fracRnd_uid11_fxpToFPTest_merged_bit_select_b; - end - end - - // expFracRnd_uid12_fxpToFPTest(BITJOIN,11)@5 - assign expFracRnd_uid12_fxpToFPTest_q = {expPreRnd_uid10_fxpToFPTest_q, redist0_fracRnd_uid11_fxpToFPTest_merged_bit_select_b_1_q}; - - // l_uid13_fxpToFPTest_merged_bit_select(BITSELECT,84)@5 - assign l_uid13_fxpToFPTest_merged_bit_select_in = expFracRnd_uid12_fxpToFPTest_q[1:0]; - assign l_uid13_fxpToFPTest_merged_bit_select_b = l_uid13_fxpToFPTest_merged_bit_select_in[1:1]; - assign l_uid13_fxpToFPTest_merged_bit_select_c = l_uid13_fxpToFPTest_merged_bit_select_in[0:0]; - - // rnd_uid18_fxpToFPTest(LOGICAL,17)@5 + 1 - assign rnd_uid18_fxpToFPTest_qi = l_uid13_fxpToFPTest_merged_bit_select_b | nr_uid17_fxpToFPTest_q | sticky_uid16_fxpToFPTest_q; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) ) - rnd_uid18_fxpToFPTest_delay ( .xin(rnd_uid18_fxpToFPTest_qi), .xout(rnd_uid18_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist9_expFracRnd_uid12_fxpToFPTest_q_1(DELAY,100) - always @ (posedge clk) - begin - if (areset) - begin - redist9_expFracRnd_uid12_fxpToFPTest_q_1_q <= '0; - end - else if (en == 1'b1) - begin - redist9_expFracRnd_uid12_fxpToFPTest_q_1_q <= expFracRnd_uid12_fxpToFPTest_q; - end - end - - // expFracR_uid20_fxpToFPTest(ADD,19)@6 - assign expFracR_uid20_fxpToFPTest_a = {{2{redist9_expFracRnd_uid12_fxpToFPTest_q_1_q[32]}}, redist9_expFracRnd_uid12_fxpToFPTest_q_1_q}; - assign expFracR_uid20_fxpToFPTest_b = {34'b0000000000000000000000000000000000, rnd_uid18_fxpToFPTest_q}; - assign expFracR_uid20_fxpToFPTest_o = $signed(expFracR_uid20_fxpToFPTest_a) + $signed(expFracR_uid20_fxpToFPTest_b); - assign expFracR_uid20_fxpToFPTest_q = expFracR_uid20_fxpToFPTest_o[33:0]; - - // expR_uid22_fxpToFPTest(BITSELECT,21)@6 - assign expR_uid22_fxpToFPTest_b = expFracR_uid20_fxpToFPTest_q[33:24]; - - // redist7_expR_uid22_fxpToFPTest_b_1(DELAY,98) - always @ (posedge clk) - begin - if (areset) - begin - redist7_expR_uid22_fxpToFPTest_b_1_q <= '0; - end - else if (en == 1'b1) - begin - redist7_expR_uid22_fxpToFPTest_b_1_q <= expR_uid22_fxpToFPTest_b; - end - end - - // expR_uid34_fxpToFPTest(BITSELECT,33)@7 - assign expR_uid34_fxpToFPTest_in = redist7_expR_uid22_fxpToFPTest_b_1_q[7:0]; - assign expR_uid34_fxpToFPTest_b = expR_uid34_fxpToFPTest_in[7:0]; - - // ovf_uid25_fxpToFPTest(COMPARE,24)@7 - assign ovf_uid25_fxpToFPTest_a = {{2{redist7_expR_uid22_fxpToFPTest_b_1_q[9]}}, redist7_expR_uid22_fxpToFPTest_b_1_q}; - assign ovf_uid25_fxpToFPTest_b = {4'b0000, expInf_uid24_fxpToFPTest_q}; - assign ovf_uid25_fxpToFPTest_o = $signed(ovf_uid25_fxpToFPTest_a) - $signed(ovf_uid25_fxpToFPTest_b); - assign ovf_uid25_fxpToFPTest_n[0] = ~ (ovf_uid25_fxpToFPTest_o[11]); - - // inIsZero_uid8_fxpToFPTest(LOGICAL,7)@5 + 1 - assign inIsZero_uid8_fxpToFPTest_qi = vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q == maxCount_uid7_fxpToFPTest_q ? 1'b1 : 1'b0; - dspba_delay_ver #( .width(1), .depth(1), .reset_kind("SYNC"), .phase(0), .modulus(1) ) - inIsZero_uid8_fxpToFPTest_delay ( .xin(inIsZero_uid8_fxpToFPTest_qi), .xout(inIsZero_uid8_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); - - // redist10_inIsZero_uid8_fxpToFPTest_q_2(DELAY,101) - always @ (posedge clk) - begin - if (areset) - begin - redist10_inIsZero_uid8_fxpToFPTest_q_2_q <= '0; - end - else if (en == 1'b1) - begin - redist10_inIsZero_uid8_fxpToFPTest_q_2_q <= inIsZero_uid8_fxpToFPTest_q; - end - end - - // udf_uid23_fxpToFPTest(COMPARE,22)@7 - assign udf_uid23_fxpToFPTest_a = {11'b00000000000, GND_q}; - assign udf_uid23_fxpToFPTest_b = {{2{redist7_expR_uid22_fxpToFPTest_b_1_q[9]}}, redist7_expR_uid22_fxpToFPTest_b_1_q}; - assign udf_uid23_fxpToFPTest_o = $signed(udf_uid23_fxpToFPTest_a) - $signed(udf_uid23_fxpToFPTest_b); - assign udf_uid23_fxpToFPTest_n[0] = ~ (udf_uid23_fxpToFPTest_o[11]); - - // udfOrInZero_uid29_fxpToFPTest(LOGICAL,28)@7 - assign udfOrInZero_uid29_fxpToFPTest_q = udf_uid23_fxpToFPTest_n | redist10_inIsZero_uid8_fxpToFPTest_q_2_q; - - // excSelector_uid30_fxpToFPTest(BITJOIN,29)@7 - assign excSelector_uid30_fxpToFPTest_q = {ovf_uid25_fxpToFPTest_n, udfOrInZero_uid29_fxpToFPTest_q}; - - // expRPostExc_uid35_fxpToFPTest(MUX,34)@7 - assign expRPostExc_uid35_fxpToFPTest_s = excSelector_uid30_fxpToFPTest_q; - always @(expRPostExc_uid35_fxpToFPTest_s or en or expR_uid34_fxpToFPTest_b or expZ_uid33_fxpToFPTest_q or expInf_uid24_fxpToFPTest_q) - begin - unique case (expRPostExc_uid35_fxpToFPTest_s) - 2'b00 : expRPostExc_uid35_fxpToFPTest_q = expR_uid34_fxpToFPTest_b; - 2'b01 : expRPostExc_uid35_fxpToFPTest_q = expZ_uid33_fxpToFPTest_q; - 2'b10 : expRPostExc_uid35_fxpToFPTest_q = expInf_uid24_fxpToFPTest_q; - 2'b11 : expRPostExc_uid35_fxpToFPTest_q = expInf_uid24_fxpToFPTest_q; - default : expRPostExc_uid35_fxpToFPTest_q = 8'b0; - endcase - end - - // fracZ_uid27_fxpToFPTest(CONSTANT,26) - assign fracZ_uid27_fxpToFPTest_q = 23'b00000000000000000000000; - - // fracR_uid21_fxpToFPTest(BITSELECT,20)@6 - assign fracR_uid21_fxpToFPTest_in = expFracR_uid20_fxpToFPTest_q[23:0]; - assign fracR_uid21_fxpToFPTest_b = fracR_uid21_fxpToFPTest_in[23:1]; - - // redist8_fracR_uid21_fxpToFPTest_b_1(DELAY,99) - always @ (posedge clk) - begin - if (areset) - begin - redist8_fracR_uid21_fxpToFPTest_b_1_q <= '0; - end - else if (en == 1'b1) - begin - redist8_fracR_uid21_fxpToFPTest_b_1_q <= fracR_uid21_fxpToFPTest_b; - end - end - - // excSelector_uid26_fxpToFPTest(LOGICAL,25)@7 - assign excSelector_uid26_fxpToFPTest_q = redist10_inIsZero_uid8_fxpToFPTest_q_2_q | ovf_uid25_fxpToFPTest_n | udf_uid23_fxpToFPTest_n; - - // fracRPostExc_uid28_fxpToFPTest(MUX,27)@7 - assign fracRPostExc_uid28_fxpToFPTest_s = excSelector_uid26_fxpToFPTest_q; - always @(fracRPostExc_uid28_fxpToFPTest_s or en or redist8_fracR_uid21_fxpToFPTest_b_1_q or fracZ_uid27_fxpToFPTest_q) - begin - unique case (fracRPostExc_uid28_fxpToFPTest_s) - 1'b0 : fracRPostExc_uid28_fxpToFPTest_q = redist8_fracR_uid21_fxpToFPTest_b_1_q; - 1'b1 : fracRPostExc_uid28_fxpToFPTest_q = fracZ_uid27_fxpToFPTest_q; - default : fracRPostExc_uid28_fxpToFPTest_q = 23'b0; - endcase - end - - // outRes_uid36_fxpToFPTest(BITJOIN,35)@7 - assign outRes_uid36_fxpToFPTest_q = {GND_q, expRPostExc_uid35_fxpToFPTest_q, fracRPostExc_uid28_fxpToFPTest_q}; - - // xOut(GPOUT,4)@7 - assign q = outRes_uid36_fxpToFPTest_q; - -endmodule diff --git a/hw/rtl/fp_cores/svdpi/float_dpi.cpp b/hw/rtl/fp_cores/svdpi/float_dpi.cpp index 6c9545b6..0bc99c2c 100644 --- a/hw/rtl/fp_cores/svdpi/float_dpi.cpp +++ b/hw/rtl/fp_cores/svdpi/float_dpi.cpp @@ -10,14 +10,17 @@ extern "C" { int dpi_register(); - void dpi_fmadd(int inst, bool enable, int a, int b, int c, int* result); - void dpi_fdiv(int inst, bool enable, int a, int b, int* result); - void dpi_fsqrt(int inst, bool enable, int a, int* result); - void dpi_ftoi(int inst, bool enable, int a, int* result); - void dpi_ftou(int inst, bool enable, int a, int* result); - void dpi_itof(int inst, bool enable, int a, int* result); - void dpi_utof(int inst, bool enable, int a, int* result); - void dpi_delayed_assert(int inst, bool cond); + void dpi_fadd(int inst, bool enable, int a, int b, int delay, int* result); + void dpi_fsub(int inst, bool enable, int a, int b, int delay, int* result); + void dpi_fmul(int inst, bool enable, int a, int b, int delay, int* result); + void dpi_fmadd(int inst, bool enable, int a, int b, int c, int delay, int* result); + void dpi_fdiv(int inst, bool enable, int a, int b, int delay, int* result); + void dpi_fsqrt(int inst, bool enable, int a, int delay, int* result); + void dpi_ftoi(int inst, bool enable, int a, int delay, int* result); + void dpi_ftou(int inst, bool enable, int a, int delay, int* result); + void dpi_itof(int inst, bool enable, int a, int delay, int* result); + void dpi_utof(int inst, bool enable, int a, int delay, int* result); + void dpi_assert(int inst, bool cond, int delay); } class ShiftRegister { @@ -87,7 +90,49 @@ int dpi_register() { return instances.allocate(); } -void dpi_fmadd(int inst, bool enable, int a, int b, int c, int* result) { +void dpi_fadd(int inst, bool enable, int a, int b, int delay, int* result) { + ShiftRegister& sr = instances.get(inst); + + Float_t fa, fb, fr; + + fa.i = a; + fb.i = b; + fr.f = fa.f + fb.f; + + sr.ensure_init(delay); + sr.push(fr.i, enable); + *result = sr.top(); +} + +void dpi_fsub(int inst, bool enable, int a, int b, int delay, int* result) { + ShiftRegister& sr = instances.get(inst); + + Float_t fa, fb, fr; + + fa.i = a; + fb.i = b; + fr.f = fa.f - fb.f; + + sr.ensure_init(delay); + sr.push(fr.i, enable); + *result = sr.top(); +} + +void dpi_fmul(int inst, bool enable, int a, int b, int delay, int* result) { + ShiftRegister& sr = instances.get(inst); + + Float_t fa, fb, fr; + + fa.i = a; + fb.i = b; + fr.f = fa.f * fb.f; + + sr.ensure_init(delay); + sr.push(fr.i, enable); + *result = sr.top(); +} + +void dpi_fmadd(int inst, bool enable, int a, int b, int c, int delay, int* result) { ShiftRegister& sr = instances.get(inst); Float_t fa, fb, fc, fr; @@ -97,12 +142,12 @@ void dpi_fmadd(int inst, bool enable, int a, int b, int c, int* result) { fc.i = c; fr.f = fa.f * fb.f + fc.f; - sr.ensure_init(LATENCY_FMADD); + sr.ensure_init(delay); sr.push(fr.i, enable); *result = sr.top(); } -void dpi_fdiv(int inst, bool enable, int a, int b, int* result) { +void dpi_fdiv(int inst, bool enable, int a, int b, int delay, int* result) { ShiftRegister& sr = instances.get(inst); Float_t fa, fb, fr; @@ -111,12 +156,12 @@ void dpi_fdiv(int inst, bool enable, int a, int b, int* result) { fb.i = b; fr.f = fa.f / fb.f; - sr.ensure_init(LATENCY_FDIV); + sr.ensure_init(delay); sr.push(fr.i, enable); *result = sr.top(); } -void dpi_fsqrt(int inst, bool enable, int a, int* result) { +void dpi_fsqrt(int inst, bool enable, int a, int delay, int* result) { ShiftRegister& sr = instances.get(inst); Float_t fa, fr; @@ -124,12 +169,12 @@ void dpi_fsqrt(int inst, bool enable, int a, int* result) { fa.i = a; fr.f = sqrtf(fa.f); - sr.ensure_init(LATENCY_FSQRT); + sr.ensure_init(delay); sr.push(fr.i, enable); *result = sr.top(); } -void dpi_ftoi(int inst, bool enable, int a, int* result) { +void dpi_ftoi(int inst, bool enable, int a, int delay, int* result) { ShiftRegister& sr = instances.get(inst); Float_t fa, fr; @@ -137,12 +182,12 @@ void dpi_ftoi(int inst, bool enable, int a, int* result) { fa.i = a; fr.i = int(fa.f); - sr.ensure_init(LATENCY_FTOI); + sr.ensure_init(delay); sr.push(fr.i, enable); *result = sr.top(); } -void dpi_ftou(int inst, bool enable, int a, int* result) { +void dpi_ftou(int inst, bool enable, int a, int delay, int* result) { ShiftRegister& sr = instances.get(inst); Float_t fa, fr; @@ -150,24 +195,24 @@ void dpi_ftou(int inst, bool enable, int a, int* result) { fa.i = a; fr.i = unsigned(fa.f); - sr.ensure_init(LATENCY_FTOI); + sr.ensure_init(delay); sr.push(fr.i, enable); *result = sr.top(); } -void dpi_itof(int inst, bool enable, int a, int* result) { +void dpi_itof(int inst, bool enable, int a, int delay, int* result) { ShiftRegister& sr = instances.get(inst); Float_t fa, fr; fr.f = (float)a; - sr.ensure_init(LATENCY_ITOF); + sr.ensure_init(delay); sr.push(fr.i, enable); *result = sr.top(); } -void dpi_utof(int inst, bool enable, int a, int* result) { +void dpi_utof(int inst, bool enable, int a, int delay, int* result) { ShiftRegister& sr = instances.get(inst); Float_t fa, fr; @@ -175,15 +220,15 @@ void dpi_utof(int inst, bool enable, int a, int* result) { unsigned ua = a; fr.f = (float)ua; - sr.ensure_init(LATENCY_ITOF); + sr.ensure_init(delay); sr.push(fr.i, enable); *result = sr.top(); } -void dpi_delayed_assert(int inst, bool cond) { +void dpi_assert(int inst, bool cond, int delay) { ShiftRegister& sr = instances.get(inst); - sr.ensure_init(2); + sr.ensure_init(delay); sr.push(!cond, 1); auto status = sr.top(); diff --git a/hw/rtl/fp_cores/svdpi/float_dpi.vh b/hw/rtl/fp_cores/svdpi/float_dpi.vh index 0131b422..d4500cf9 100644 --- a/hw/rtl/fp_cores/svdpi/float_dpi.vh +++ b/hw/rtl/fp_cores/svdpi/float_dpi.vh @@ -3,18 +3,18 @@ import "DPI-C" context function int dpi_register(); -import "DPI-C" context function void dpi_fadd(int inst, input logic enable, input int a, input int b, output int result); -import "DPI-C" context function void dpi_fsub(int inst, input logic enable, input int a, input int b, output int result); -import "DPI-C" context function void dpi_fmul(int inst, input logic enable, input int a, input int b, output int result); -import "DPI-C" context function void dpi_fmadd(int inst, input logic enable, input int a, input int b, input int c, output int result); -import "DPI-C" context function void dpi_fmsub(int inst, input logic enable, input int a, input int b, input int c, output int result); -import "DPI-C" context function void dpi_fdiv(int inst, input logic enable, input int a, input int b, output int result); -import "DPI-C" context function void dpi_fsqrt(int inst, input logic enable, input int a, output int result); -import "DPI-C" context function void dpi_ftoi(int inst, input logic enable, input int a, output int result); -import "DPI-C" context function void dpi_ftou(int inst, input logic enable, input int a, output int result); -import "DPI-C" context function void dpi_itof(int inst, input logic enable, input int a, output int result); -import "DPI-C" context function void dpi_utof(int inst, input logic enable, input int a, output int result); +import "DPI-C" context function void dpi_fadd(int inst, input logic enable, input int a, input int b, input int delay, output int result); +import "DPI-C" context function void dpi_fsub(int inst, input logic enable, input int a, input int b, input int delay, output int result); +import "DPI-C" context function void dpi_fmul(int inst, input logic enable, input int a, input int b, input int delay, output int result); +import "DPI-C" context function void dpi_fmadd(int inst, input logic enable, input int a, input int b, input int c, input int delay, output int result); +import "DPI-C" context function void dpi_fmsub(int inst, input logic enable, input int a, input int b, input int c, input int delay, output int result); +import "DPI-C" context function void dpi_fdiv(int inst, input logic enable, input int a, input int b, input int delay, output int result); +import "DPI-C" context function void dpi_fsqrt(int inst, input logic enable, input int a, input int delay, output int result); +import "DPI-C" context function void dpi_ftoi(int inst, input logic enable, input int a, input int delay, output int result); +import "DPI-C" context function void dpi_ftou(int inst, input logic enable, input int a, input int delay, output int result); +import "DPI-C" context function void dpi_itof(int inst, input logic enable, input int a, input int delay, output int result); +import "DPI-C" context function void dpi_utof(int inst, input logic enable, input int a, input int delay, output int result); -import "DPI-C" context function void dpi_delayed_assert(int inst, input logic cond); +import "DPI-C" context function void dpi_assert(int inst, input logic cond, input int delay); `endif \ No newline at end of file diff --git a/hw/rtl/libs/VX_elastic_buffer.v b/hw/rtl/libs/VX_elastic_buffer.v index a1fa1b5d..06bfb54b 100644 --- a/hw/rtl/libs/VX_elastic_buffer.v +++ b/hw/rtl/libs/VX_elastic_buffer.v @@ -34,7 +34,7 @@ module VX_elastic_buffer #( wire push = valid_in && ready_in; wire pop = valid_out && ready_out; - VX_generic_queue #( + VX_fifo_queue #( .DATAW (DATAW), .SIZE (SIZE), .BUFFERED (BUFFERED), diff --git a/hw/rtl/libs/VX_generic_queue.v b/hw/rtl/libs/VX_fifo_queue.v similarity index 99% rename from hw/rtl/libs/VX_generic_queue.v rename to hw/rtl/libs/VX_fifo_queue.v index 63698cb6..fabef871 100644 --- a/hw/rtl/libs/VX_generic_queue.v +++ b/hw/rtl/libs/VX_fifo_queue.v @@ -1,6 +1,6 @@ `include "VX_platform.vh" -module VX_generic_queue #( +module VX_fifo_queue #( parameter DATAW = 1, parameter SIZE = 2, parameter ADDRW = $clog2(SIZE), diff --git a/hw/rtl/libs/VX_generic_register.v b/hw/rtl/libs/VX_generic_register.v deleted file mode 100644 index d29ec108..00000000 --- a/hw/rtl/libs/VX_generic_register.v +++ /dev/null @@ -1,45 +0,0 @@ -`include "VX_platform.vh" - -module VX_generic_register #( - parameter N = 1, - parameter R = N, - parameter PASSTHRU = 0 -) ( - input wire clk, - input wire reset, - input wire stall, - input wire flush, - input wire[N-1:0] data_in, - output wire[N-1:0] data_out -); - if (PASSTHRU) begin - `UNUSED_VAR (clk) - `UNUSED_VAR (reset) - `UNUSED_VAR (stall) - assign data_out = flush ? N'(0) : data_in; - end else begin - reg [N-1:0] value; - - if (R != 0) begin - always @(posedge clk) begin - if (~stall) begin - value <= data_in; - end - if (reset || flush) begin - value[N-1:N-R] <= R'(0); - end - end - end else begin - `UNUSED_VAR (reset) - `UNUSED_VAR (flush) - always @(posedge clk) begin - if (~stall) begin - value <= data_in; - end - end - end - - assign data_out = value; - end - -endmodule \ No newline at end of file diff --git a/hw/rtl/libs/VX_index_buffer.v b/hw/rtl/libs/VX_index_buffer.v index 2a28d061..c9f946ad 100644 --- a/hw/rtl/libs/VX_index_buffer.v +++ b/hw/rtl/libs/VX_index_buffer.v @@ -28,7 +28,7 @@ module VX_index_buffer #( wire [ADDRW-1:0] free_index; VX_priority_encoder #( - .N(SIZE) + .DATAW (SIZE) ) free_slots_encoder ( .data_in (free_slots_n), .data_out (free_index), diff --git a/hw/rtl/libs/VX_lzc.v b/hw/rtl/libs/VX_lzc.v new file mode 100644 index 00000000..0baceb17 --- /dev/null +++ b/hw/rtl/libs/VX_lzc.v @@ -0,0 +1,27 @@ +`include "VX_platform.vh" + +module VX_lzc #( + parameter DATAW = 1, + parameter LDATAW = `LOG2UP(DATAW) +) ( + input wire [DATAW-1:0] data_in, + output wire [LDATAW-1:0] data_out, + output wire valid_out +); + + reg [LDATAW-1:0] data_out_r; + + always @(*) begin + data_out_r = 'x; + for (integer i = DATAW-1; i >= 0; --i) begin + if (data_in[i]) begin + data_out_r = LDATAW'(DATAW-1-i); + break; + end + end + end + + assign data_out = data_out_r; + assign valid_out = (| data_in); + +endmodule \ No newline at end of file diff --git a/hw/rtl/libs/VX_pipe_register.v b/hw/rtl/libs/VX_pipe_register.v new file mode 100644 index 00000000..60a52d7c --- /dev/null +++ b/hw/rtl/libs/VX_pipe_register.v @@ -0,0 +1,53 @@ +`include "VX_platform.vh" + +module VX_pipe_register #( + parameter DATAW = 1, + parameter RESETW = DATAW, + parameter DEPTH = 1 +) ( + input wire clk, + input wire reset, + input wire enable, + input wire [DATAW-1:0] data_in, + output wire [DATAW-1:0] data_out +); + + if (DEPTH == 0) begin + `UNUSED_VAR (clk) + `UNUSED_VAR (reset) + `UNUSED_VAR (enable) + assign data_out = data_in; + end else if (DEPTH == 1) begin + reg [DATAW-1:0] value; + if (RESETW != 0) begin + always @(posedge clk) begin + if (reset) begin + value[DATAW-1:DATAW-RESETW] <= RESETW'(0); + end else if (enable) begin + value <= data_in; + end + end + end else begin + `UNUSED_VAR (reset) + always @(posedge clk) begin + if (enable) begin + value <= data_in; + end + end + end + assign data_out = value; + end else begin + VX_shift_register #( + .DATAW (DATAW), + .RESETW (RESETW), + .DEPTH (DEPTH) + ) shift_reg ( + .clk (clk), + .reset (reset), + .enable (enable), + .data_in (data_in), + .data_out (data_out) + ); + end + +endmodule \ No newline at end of file diff --git a/hw/rtl/libs/VX_priority_encoder.v b/hw/rtl/libs/VX_priority_encoder.v index c9b47847..6fa54380 100644 --- a/hw/rtl/libs/VX_priority_encoder.v +++ b/hw/rtl/libs/VX_priority_encoder.v @@ -1,20 +1,20 @@ `include "VX_platform.vh" module VX_priority_encoder #( - parameter N = 1, - parameter LOGN = `LOG2UP(N) + parameter DATAW = 1, + parameter LDATAW = `LOG2UP(DATAW) ) ( - input wire [N-1:0] data_in, - output wire [LOGN-1:0] data_out, - output wire valid_out + input wire [DATAW-1:0] data_in, + output wire [LDATAW-1:0] data_out, + output wire valid_out ); - reg [`LOG2UP(N)-1:0] data_out_r; + reg [LDATAW-1:0] data_out_r; always @(*) begin data_out_r = 'x; - for (integer i = 0; i < N; i++) begin + for (integer i = 0; i < DATAW; i++) begin if (data_in[i]) begin - data_out_r = LOGN'(i); + data_out_r = LDATAW'(i); break; end end diff --git a/hw/rtl/libs/VX_shift_register.v b/hw/rtl/libs/VX_shift_register.v index 9626be58..3493a4b6 100644 --- a/hw/rtl/libs/VX_shift_register.v +++ b/hw/rtl/libs/VX_shift_register.v @@ -76,7 +76,7 @@ endmodule module VX_shift_register #( parameter DATAW = 1, - parameter RESETW = DATAW, + parameter RESETW = 0, parameter DEPTH = 1, parameter NTAPS = 1, parameter DEPTHW = $clog2(DEPTH), diff --git a/hw/rtl/libs/VX_skid_buffer.v b/hw/rtl/libs/VX_skid_buffer.v index 34126bf1..b35abad4 100644 --- a/hw/rtl/libs/VX_skid_buffer.v +++ b/hw/rtl/libs/VX_skid_buffer.v @@ -34,14 +34,13 @@ module VX_skid_buffer #( wire stall = valid_out && ~ready_out; - VX_generic_register #( - .N (1 + DATAW), - .R (1) + VX_pipe_register #( + .DATAW (1 + DATAW), + .RESETW (1) ) pipe_reg ( .clk (clk), .reset (reset), - .stall (stall), - .flush (1'b0), + .enable (!stall), .data_in ({valid_in, data_in}), .data_out ({valid_out, data_out}) ); diff --git a/hw/syn/quartus/pipeline/Makefile b/hw/syn/quartus/pipeline/Makefile index 67941e7f..095e19ce 100644 --- a/hw/syn/quartus/pipeline/Makefile +++ b/hw/syn/quartus/pipeline/Makefile @@ -65,8 +65,11 @@ sta.chg: asm.chg: $(STAMP) asm.chg +timing: $(PROJECT_FILES) + quartus_sh -t ../timing-html.tcl -project $(PROJECT) + program: $(PROJECT).sof quartus_pgm --no_banner --mode=jtag -o "$(PROJECT).sof" - + clean: rm -rf bin *.rpt *.chg *.qsf *.qpf *.qws *.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox diff --git a/hw/unit_tests/generic_queue/testbench.v b/hw/unit_tests/generic_queue/testbench.v index 53d69d06..43381e24 100644 --- a/hw/unit_tests/generic_queue/testbench.v +++ b/hw/unit_tests/generic_queue/testbench.v @@ -1,5 +1,5 @@ `timescale 1ns/1ns -`include "VX_generic_queue.v" +`include "VX_fifo_queue.v" `define check(x, y) if ((x == y) !== 1) if ((x == y) === 0) $error("x=%h, expected=%h", x, y); else $warning("x=%h, expected=%h", x, y) @@ -14,7 +14,7 @@ module testbench(); wire full; wire empty; - VX_generic_queue #( + VX_fifo_queue #( .DATAW(4), .SIZE(4) ) dut (