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adding input buffering to bus arbiters to reduce backpressure delay propagation

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This commit is contained in:
Blaise Tine
2020-12-05 17:31:29 -08:00
parent 13a5370254
commit d0f2a3984d
17 changed files with 480 additions and 338 deletions
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60
hw/rtl/libs/VX_elastic_buffer.v
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@@ -4,7 +4,8 @@ module VX_elastic_buffer #(
parameter DATAW = 1,
parameter SIZE = 2,
parameter BUFFERED = 0,
parameter FASTRAM = 0
parameter FASTRAM = 0,
parameter PASSTHRU = 0
) (
input wire clk,
input wire reset,
@@ -16,30 +17,43 @@ module VX_elastic_buffer #(
output wire [DATAW-1:0] data_out,
input wire ready_out,
output wire valid_out
);
wire empty, full;
);
if (PASSTHRU) begin
wire push = valid_in && ready_in;
wire pop = valid_out && ready_out;
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
VX_generic_queue #(
.DATAW (DATAW),
.SIZE (SIZE),
.BUFFERED (BUFFERED),
.FASTRAM (FASTRAM)
) queue (
.clk (clk),
.reset (reset),
.push (push),
.pop (pop),
.data_in(data_in),
.data_out(data_out),
.empty (empty),
.full (full),
`UNUSED_PIN (size)
);
assign valid_out = valid_in;
assign data_out = data_in;
assign ready_in = ready_out;
assign ready_in = ~full;
assign valid_out = ~empty;
end else begin
wire empty, full;
wire push = valid_in && ready_in;
wire pop = valid_out && ready_out;
VX_generic_queue #(
.DATAW (DATAW),
.SIZE (SIZE),
.BUFFERED (BUFFERED),
.FASTRAM (FASTRAM)
) queue (
.clk (clk),
.reset (reset),
.push (push),
.pop (pop),
.data_in(data_in),
.data_out(data_out),
.empty (empty),
.full (full),
`UNUSED_PIN (size)
);
assign ready_in = ~full;
assign valid_out = ~empty;
end
endmodule

44
hw/rtl/libs/VX_fair_arbiter.v
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@@ -7,8 +7,8 @@ module VX_fair_arbiter #(
) (
input wire clk,
input wire reset,
input wire [NUM_REQS-1:0] requests,
input wire enable,
input wire [NUM_REQS-1:0] requests,
output wire [LOG_NUM_REQS-1:0] grant_index,
output wire [NUM_REQS-1:0] grant_onehot,
output wire grant_valid
@@ -24,12 +24,13 @@ module VX_fair_arbiter #(
end else begin
reg [NUM_REQS-1:0] remaining;
wire [NUM_REQS-1:0] remaining_next;
wire [NUM_REQS-1:0] requests_use;
reg use_buffer;
reg [NUM_REQS-1:0] remaining;
reg use_buffer;
always @(posedge clk) begin
wire [NUM_REQS-1:0] requests_use = use_buffer ? remaining : requests;
wire [NUM_REQS-1:0] remaining_next = requests_use & ~grant_onehot;
always @(posedge clk) begin
if (reset) begin
remaining <= 0;
use_buffer <= 0;
@@ -38,26 +39,19 @@ module VX_fair_arbiter #(
use_buffer <= (remaining_next != 0);
end
end
assign requests_use = use_buffer ? remaining : requests;
VX_priority_encoder #(
.N(NUM_REQS)
) priority_encoder (
.data_in (requests_use),
.data_out (grant_index),
.valid_out (grant_valid)
VX_fixed_arbiter #(
.NUM_REQS(NUM_REQS),
.LOCK_ENABLE(LOCK_ENABLE)
) fixed_arbiter (
.clk (clk),
.reset (reset),
.enable (enable),
.requests (requests_use),
.grant_index (grant_index),
.grant_onehot (grant_onehot),
.grant_valid (grant_valid)
);
reg [NUM_REQS-1:0] grant_onehot_r;
always @(*) begin
grant_onehot_r = NUM_REQS'(0);
grant_onehot_r[grant_index] = 1;
end
assign remaining_next = requests_use & ~grant_onehot_r;
assign grant_onehot = grant_onehot_r;
end
endmodule

27
hw/rtl/libs/VX_fixed_arbiter.v
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@@ -26,21 +26,24 @@ module VX_fixed_arbiter #(
end else begin
VX_priority_encoder # (
.N(NUM_REQS)
) priority_encoder (
.data_in (requests),
.data_out (grant_index),
.valid_out (grant_valid)
);
reg [LOG_NUM_REQS-1:0] grant_index_r;
reg [NUM_REQS-1:0] grant_onehot_r;
always @(*) begin
grant_onehot_r = NUM_REQS'(0);
grant_onehot_r[grant_index] = 1;
end
always @(*) begin
grant_index_r = 'x;
grant_onehot_r = 'x;
for (integer i = 0; i < NUM_REQS; ++i) begin
if (requests[i]) begin
grant_index_r = LOG_NUM_REQS'(i);
grant_onehot_r = NUM_REQS'(1) << i;
break;
end
end
end
assign grant_index = grant_index_r;
assign grant_onehot = grant_onehot_r;
assign grant_valid = (| requests);
end
endmodule

2
hw/rtl/libs/VX_matrix_arbiter.v
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@@ -7,8 +7,8 @@ module VX_matrix_arbiter #(
) (
input wire clk,
input wire reset,
input wire [NUM_REQS-1:0] requests,
input wire enable,
input wire [NUM_REQS-1:0] requests,
output wire [LOG_NUM_REQS-1:0] grant_index,
output wire [NUM_REQS-1:0] grant_onehot,
output wire grant_valid

2
hw/rtl/libs/VX_priority_encoder.v
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@@ -11,7 +11,7 @@ module VX_priority_encoder #(
reg [`LOG2UP(N)-1:0] data_out_r;
always @(*) begin
data_out_r = 0;
data_out_r = 'x;
for (integer i = 0; i < N; i++) begin
if (data_in[i]) begin
data_out_r = LOGN'(i);

4
hw/rtl/libs/VX_rr_arbiter.v
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@@ -6,9 +6,9 @@ module VX_rr_arbiter #(
parameter LOG_NUM_REQS = $clog2(NUM_REQS)
) (
input wire clk,
input wire reset,
input wire [NUM_REQS-1:0] requests,
input wire reset,
input wire enable,
input wire [NUM_REQS-1:0] requests,
output wire [LOG_NUM_REQS-1:0] grant_index,
output wire [NUM_REQS-1:0] grant_onehot,
output wire grant_valid

77
hw/rtl/libs/VX_skid_buffer.v
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@@ -1,7 +1,8 @@
`include "VX_platform.vh"
module VX_skid_buffer #(
parameter DATAW = 1
parameter DATAW = 1,
parameter PASSTHRU = 0
) (
input wire clk,
input wire reset,
@@ -13,42 +14,56 @@ module VX_skid_buffer #(
output wire [DATAW-1:0] data_out,
input wire ready_out,
output wire valid_out
);
reg [DATAW-1:0] data_out_r;
reg [DATAW-1:0] buffer;
reg valid_out_r;
reg use_buffer;
wire push = valid_in && ready_in;
always @(posedge clk) begin
if (reset) begin
valid_out_r <= 0;
use_buffer <= 0;
end else begin
if (ready_out) begin
use_buffer <= 0;
);
if (PASSTHRU) begin
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
assign valid_out = valid_in;
assign data_out = data_in;
assign ready_in = ready_out;
end else begin
reg [DATAW-1:0] data_out_r;
reg [DATAW-1:0] buffer;
reg valid_out_r;
reg use_buffer;
wire push = valid_in && ready_in;
always @(posedge clk) begin
if (reset) begin
valid_out_r <= 0;
use_buffer <= 0;
end else begin
if (ready_out) begin
use_buffer <= 0;
end
if (push && valid_out_r && !ready_out) begin
assert(!use_buffer);
use_buffer <= 1;
end
if (!valid_out_r || ready_out) begin
valid_out_r <= valid_in || use_buffer;
end
end
if (push && valid_out_r && !ready_out) begin
assert(!use_buffer);
use_buffer <= 1;
if (push) begin
buffer <= data_in;
end
if (!valid_out_r || ready_out) begin
valid_out_r <= valid_in || use_buffer;
data_out_r <= use_buffer ? buffer : data_in;
end
end
if (push) begin
buffer <= data_in;
end
if (!valid_out_r || ready_out) begin
data_out_r <= use_buffer ? buffer : data_in;
end
assign ready_in = !use_buffer;
assign valid_out = valid_out_r;
assign data_out = data_out_r;
end
assign ready_in = !use_buffer;
assign valid_out = valid_out_r;
assign data_out = data_out_r;
endmodule