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RTL code refactoring

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This commit is contained in:
Blaise Tine
2020-04-20 23:44:30 -04:00
parent 786817d601
commit cfa8626bf7
18 changed files with 30 additions and 130 deletions
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2
hw/rtl/interfaces/VX_branch_response_if.v → hw/rtl/interfaces/VX_branch_rsp_if.v
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@@ -3,7 +3,7 @@
`include "../VX_define.vh"
interface VX_branch_response_if ();
interface VX_branch_rsp_if ();
wire valid_branch;
wire branch_dir;

16
hw/rtl/interfaces/VX_dcache_request_if.v
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@@ -1,16 +0,0 @@
`ifndef VX_DCACHE_REQ
`define VX_DCACHE_REQ
`include "../VX_define.vh"
interface VX_dcache_request_if ();
wire [`NUM_THREADS-1:0][31:0] out_cache_driver_in_address;
wire [2:0] out_cache_driver_in_mem_read;
wire [2:0] out_cache_driver_in_mem_write;
wire [`NUM_THREADS-1:0] out_cache_driver_in_valid;
wire [`NUM_THREADS-1:0][31:0] out_cache_driver_in_data;
endinterface
`endif

13
hw/rtl/interfaces/VX_dcache_response_if.v
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@@ -1,13 +0,0 @@
`ifndef VX_DCACHE_RSP
`define VX_DCACHE_RSP
`include "../VX_define.vh"
interface VX_dcache_response_if ();
wire [`NUM_THREADS-1:0][31:0] in_cache_driver_out_data;
wire delay;
endinterface
`endif

25
hw/rtl/interfaces/VX_dram_req_rsp_if.v
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@@ -1,25 +0,0 @@
`ifndef VX_DRAM_REQ_RSP_INTER
`define VX_DRAM_REQ_RSP_INTER
`include "../VX_define.vh"
interface VX_dram_req_rsp_if #(
parameter NUM_BANKS = 8,
parameter NUM_WORDS_PER_BLOCK = 4
) ();
// Req
wire [31:0] o_m_evict_addr;
wire [31:0] o_m_read_addr;
wire o_m_valid;
wire [NUM_BANKS - 1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] o_m_writedata;
wire o_m_read_or_write;
// Rsp
wire [NUM_BANKS - 1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata;
wire i_m_ready;
endinterface
`endif

17
hw/rtl/interfaces/VX_icache_request_if.v
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@@ -1,17 +0,0 @@
`ifndef VX_ICACHE_REQ
`define VX_ICACHE_REQ
`include "../VX_define.vh"
interface VX_icache_request_if ();
wire [31:0] pc_address;
wire [2:0] out_cache_driver_in_mem_read;
wire [2:0] out_cache_driver_in_mem_write;
wire out_cache_driver_in_valid;
wire [31:0] out_cache_driver_in_data;
endinterface
`endif

2
hw/rtl/interfaces/VX_icache_response_if.v → hw/rtl/interfaces/VX_icache_rsp_if.v
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@@ -3,7 +3,7 @@
`include "../VX_define.vh"
interface VX_icache_response_if ();
interface VX_icache_rsp_if ();
// wire ready;
// wire stall;

2
hw/rtl/interfaces/VX_jal_response_if.v → hw/rtl/interfaces/VX_jal_rsp_if.v
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@@ -4,7 +4,7 @@
`include "../VX_define.vh"
interface VX_jal_response_if ();
interface VX_jal_rsp_if ();
wire jal;
wire [31:0] jal_dest;

25
hw/rtl/interfaces/VX_mem_req_if.v
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@@ -1,25 +0,0 @@
`ifndef VX_MEM_REQ_IN
`define VX_MEM_REQ_IN
`include "../VX_define.vh"
interface VX_mem_req_if ();
wire [`NUM_THREADS-1:0][31:0] alu_result;
wire [2:0] mem_read;
wire [2:0] mem_write;
wire [4:0] rd;
wire [1:0] wb;
wire [4:0] rs1;
wire [4:0] rs2;
wire [`NUM_THREADS-1:0][31:0] rd2;
wire [31:0] PC_next;
wire [31:0] curr_PC;
wire [31:0] branch_offset;
wire [2:0] branch_type;
wire [`NUM_THREADS-1:0] valid;
wire [`NW_BITS-1:0] warp_num;
endinterface
`endif