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RTL code refactoring

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This commit is contained in:
Blaise Tine
2020-04-20 23:44:30 -04:00
parent 786817d601
commit cfa8626bf7
18 changed files with 30 additions and 130 deletions
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2
hw/opae/sources.txt
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@@ -15,7 +15,7 @@ vortex_afu.json
../rtl/cache/VX_cache_config.vh
../rtl/interfaces/VX_exec_unit_req_if.v
../rtl/interfaces/VX_branch_response_if.v
../rtl/interfaces/VX_branch_rsp_if.v
../rtl/interfaces/VX_inst_meta_if.v
../rtl/interfaces/VX_join_if.v
../rtl/interfaces/VX_icache_response_if.v

6
hw/rtl/VX_back_end.v
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@@ -13,8 +13,8 @@ module VX_back_end #(
output wire mem_delay_o,
output wire exec_delay_o,
output wire gpr_stage_delay,
VX_jal_response_if jal_rsp_if,
VX_branch_response_if branch_rsp_if,
VX_jal_rsp_if jal_rsp_if,
VX_branch_rsp_if branch_rsp_if,
VX_frE_to_bckE_req_if bckE_req_if,
VX_wb_if writeback_if,
@@ -81,7 +81,7 @@ VX_lsu load_store_unit (
.no_slot_mem_i (no_slot_mem)
);
VX_execute_unit execUnit (
VX_exec_unit exec_unit (
.clk (clk),
.reset (reset),
.exec_unit_req_if(exec_unit_req_if),

2
hw/rtl/VX_dmem_controller.v → hw/rtl/VX_dmem_ctrl.v
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@@ -1,6 +1,6 @@
`include "VX_define.vh"
module VX_dmem_controller (
module VX_dmem_ctrl (
input wire clk,
input wire reset,

12
hw/rtl/VX_execute_unit.v → hw/rtl/VX_exec_unit.v
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@@ -1,6 +1,6 @@
`include "VX_define.vh"
module VX_execute_unit (
module VX_exec_unit (
input wire clk,
input wire reset,
// Request
@@ -10,9 +10,9 @@ module VX_execute_unit (
// Writeback
VX_inst_exec_wb_if inst_exec_wb_if,
// JAL Response
VX_jal_response_if jal_rsp_if,
VX_jal_rsp_if jal_rsp_if,
// Branch Response
VX_branch_response_if branch_rsp_if,
VX_branch_rsp_if branch_rsp_if,
input wire no_slot_exec_i,
output wire delay_o
@@ -110,9 +110,9 @@ module VX_execute_unit (
// VX_inst_exec_wb_if inst_exec_wb_temp_if();
// JAL Response
VX_jal_response_if jal_rsp_temp_if();
VX_jal_rsp_if jal_rsp_temp_if();
// Branch Response
VX_branch_response_if branch_rsp_temp_if();
VX_branch_rsp_if branch_rsp_temp_if();
// Actual Writeback
assign inst_exec_wb_if.rd = exec_unit_req_if.rd;
@@ -180,4 +180,4 @@ module VX_execute_unit (
// assign out_is_csr = exec_unit_req_if.is_csr;
// assign out_csr_address = exec_unit_req_if.csr_address;
endmodule : VX_execute_unit
endmodule : VX_exec_unit

6
hw/rtl/VX_fetch.v
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@@ -11,8 +11,8 @@ module VX_fetch (
input wire[`NUM_THREADS-1:0] icache_stage_valids,
output wire ebreak_o,
VX_jal_response_if jal_rsp_if,
VX_branch_response_if branch_rsp_if,
VX_jal_rsp_if jal_rsp_if,
VX_branch_rsp_if branch_rsp_if,
VX_inst_meta_if fe_inst_meta_fi,
VX_warp_ctl_if warp_ctl_if
);
@@ -30,7 +30,7 @@ module VX_fetch (
assign pipe_stall = schedule_delay || icache_stage_delay;
VX_warp_scheduler warp_scheduler(
VX_warp_sched warp_sched (
.clk (clk),
.reset (reset),
.stall (pipe_stall),

4
hw/rtl/VX_front_end.v
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@@ -11,8 +11,8 @@ module VX_front_end (
VX_gpu_dcache_rsp_if icache_rsp_if,
VX_gpu_dcache_req_if icache_req_if,
VX_jal_response_if jal_rsp_if,
VX_branch_response_if branch_rsp_if,
VX_jal_rsp_if jal_rsp_if,
VX_branch_rsp_if branch_rsp_if,
VX_frE_to_bckE_req_if bckE_req_if,

2
hw/rtl/VX_warp_scheduler.v → hw/rtl/VX_warp_sched.v
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@@ -1,6 +1,6 @@
`include "VX_define.vh"
module VX_warp_scheduler (
module VX_warp_sched (
input wire clk, // Clock
input wire reset,
input wire stall,

6
hw/rtl/Vortex.v
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@@ -133,8 +133,8 @@ VX_frE_to_bckE_req_if bckE_req_if(); // New instruction request to EXE/MEM
// Back-end to Front-end
VX_wb_if writeback_if(); // Writeback to GPRs
VX_branch_response_if branch_rsp_if(); // Branch Resolution to Fetch
VX_jal_response_if jal_rsp_if(); // Jump resolution to Fetch
VX_branch_rsp_if branch_rsp_if(); // Branch Resolution to Fetch
VX_jal_rsp_if jal_rsp_if(); // Jump resolution to Fetch
// Warp controls
VX_warp_ctl_if warp_ctl_if();
@@ -189,7 +189,7 @@ VX_back_end #(
.gpr_stage_delay (gpr_stage_delay)
);
VX_dmem_controller dmem_controller (
VX_dmem_ctrl dmem_controller (
.clk (clk),
.reset (reset),

2
hw/rtl/interfaces/VX_branch_response_if.v → hw/rtl/interfaces/VX_branch_rsp_if.v
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@@ -3,7 +3,7 @@
`include "../VX_define.vh"
interface VX_branch_response_if ();
interface VX_branch_rsp_if ();
wire valid_branch;
wire branch_dir;

16
hw/rtl/interfaces/VX_dcache_request_if.v
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@@ -1,16 +0,0 @@
`ifndef VX_DCACHE_REQ
`define VX_DCACHE_REQ
`include "../VX_define.vh"
interface VX_dcache_request_if ();
wire [`NUM_THREADS-1:0][31:0] out_cache_driver_in_address;
wire [2:0] out_cache_driver_in_mem_read;
wire [2:0] out_cache_driver_in_mem_write;
wire [`NUM_THREADS-1:0] out_cache_driver_in_valid;
wire [`NUM_THREADS-1:0][31:0] out_cache_driver_in_data;
endinterface
`endif

13
hw/rtl/interfaces/VX_dcache_response_if.v
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@@ -1,13 +0,0 @@
`ifndef VX_DCACHE_RSP
`define VX_DCACHE_RSP
`include "../VX_define.vh"
interface VX_dcache_response_if ();
wire [`NUM_THREADS-1:0][31:0] in_cache_driver_out_data;
wire delay;
endinterface
`endif

25
hw/rtl/interfaces/VX_dram_req_rsp_if.v
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@@ -1,25 +0,0 @@
`ifndef VX_DRAM_REQ_RSP_INTER
`define VX_DRAM_REQ_RSP_INTER
`include "../VX_define.vh"
interface VX_dram_req_rsp_if #(
parameter NUM_BANKS = 8,
parameter NUM_WORDS_PER_BLOCK = 4
) ();
// Req
wire [31:0] o_m_evict_addr;
wire [31:0] o_m_read_addr;
wire o_m_valid;
wire [NUM_BANKS - 1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] o_m_writedata;
wire o_m_read_or_write;
// Rsp
wire [NUM_BANKS - 1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata;
wire i_m_ready;
endinterface
`endif

17
hw/rtl/interfaces/VX_icache_request_if.v
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@@ -1,17 +0,0 @@
`ifndef VX_ICACHE_REQ
`define VX_ICACHE_REQ
`include "../VX_define.vh"
interface VX_icache_request_if ();
wire [31:0] pc_address;
wire [2:0] out_cache_driver_in_mem_read;
wire [2:0] out_cache_driver_in_mem_write;
wire out_cache_driver_in_valid;
wire [31:0] out_cache_driver_in_data;
endinterface
`endif

2
hw/rtl/interfaces/VX_icache_response_if.v → hw/rtl/interfaces/VX_icache_rsp_if.v
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@@ -3,7 +3,7 @@
`include "../VX_define.vh"
interface VX_icache_response_if ();
interface VX_icache_rsp_if ();
// wire ready;
// wire stall;

2
hw/rtl/interfaces/VX_jal_response_if.v → hw/rtl/interfaces/VX_jal_rsp_if.v
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@@ -4,7 +4,7 @@
`include "../VX_define.vh"
interface VX_jal_response_if ();
interface VX_jal_rsp_if ();
wire jal;
wire [31:0] jal_dest;

25
hw/rtl/interfaces/VX_mem_req_if.v
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@@ -1,25 +0,0 @@
`ifndef VX_MEM_REQ_IN
`define VX_MEM_REQ_IN
`include "../VX_define.vh"
interface VX_mem_req_if ();
wire [`NUM_THREADS-1:0][31:0] alu_result;
wire [2:0] mem_read;
wire [2:0] mem_write;
wire [4:0] rd;
wire [1:0] wb;
wire [4:0] rs1;
wire [4:0] rs2;
wire [`NUM_THREADS-1:0][31:0] rd2;
wire [31:0] PC_next;
wire [31:0] curr_PC;
wire [31:0] branch_offset;
wire [2:0] branch_type;
wire [`NUM_THREADS-1:0] valid;
wire [`NW_BITS-1:0] warp_num;
endinterface
`endif

14
hw/rtl/VX_countones.v → hw/rtl/libs/VX_countones.v
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@@ -1,12 +1,8 @@
module VX_countones
#(
parameter N = 10
)
(
input wire[N-1:0] valids,
output reg[$clog2(N):0] count
module VX_countones #(
parameter N = 10
) (
input wire[N-1:0] valids,
output reg[$clog2(N):0] count
);
integer i;

4
simX/cache_simX.v
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@@ -33,7 +33,7 @@ module cache_simX (
assign VX_icache_req.cache_driver_in_data_o = 0;
VX_icache_response_if VX_icache_rsp;
VX_icache_rsp_if VX_icache_rsp;
assign out_icache_stall = VX_icache_rsp.delay;
@@ -79,7 +79,7 @@ module cache_simX (
assign VX_dram_req_rsp.i_m_ready = dcache_i_m_ready;
VX_dmem_controller dmem_controller (
VX_dmem_ctrl dmem_controller (
.clk (clk),
.reset (reset),
.VX_dram_req_rsp (VX_dram_req_rsp),