wu-arch/vortex
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

removing ebreak signals from public interface

Browse Source
This commit is contained in:
Blaise Tine
2021-06-10 12:57:44 -07:00
parent adf033b0aa
commit cbca7e12c6
6 changed files with 10 additions and 29 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
hw/rtl/VX_cluster.v
View File

@@ -38,8 +38,7 @@ module VX_cluster #(
input wire csr_rsp_ready, input wire csr_rsp_ready,
// Status // Status
output wire busy, output wire busy
output wire ebreak
); );
`STATIC_ASSERT((`L2_ENABLE == 0 || `NUM_CORES > 1), ("invalid parameter")) `STATIC_ASSERT((`L2_ENABLE == 0 || `NUM_CORES > 1), ("invalid parameter"))
@@ -67,7 +66,6 @@ module VX_cluster #(
wire [`NUM_CORES-1:0] per_core_csr_rsp_ready; wire [`NUM_CORES-1:0] per_core_csr_rsp_ready;
wire [`NUM_CORES-1:0] per_core_busy; wire [`NUM_CORES-1:0] per_core_busy;
wire [`NUM_CORES-1:0] per_core_ebreak;
for (genvar i = 0; i < `NUM_CORES; i++) begin for (genvar i = 0; i < `NUM_CORES; i++) begin
@@ -111,8 +109,7 @@ module VX_cluster #(
.csr_rsp_data (per_core_csr_rsp_data [i]), .csr_rsp_data (per_core_csr_rsp_data [i]),
.csr_rsp_ready (per_core_csr_rsp_ready [i]), .csr_rsp_ready (per_core_csr_rsp_ready [i]),
.busy (per_core_busy [i]), .busy (per_core_busy [i])
.ebreak (per_core_ebreak [i])
); );
end end
@@ -154,7 +151,6 @@ module VX_cluster #(
); );
assign busy = (| per_core_busy); assign busy = (| per_core_busy);
assign ebreak = (| per_core_ebreak);
if (`L2_ENABLE) begin if (`L2_ENABLE) begin
`ifdef PERF_ENABLE `ifdef PERF_ENABLE

6
hw/rtl/VX_core.v
View File

@@ -37,8 +37,7 @@ module VX_core #(
input wire csr_rsp_ready, input wire csr_rsp_ready,
// Status // Status
output wire busy, output wire busy
output wire ebreak
); );
`ifdef PERF_ENABLE `ifdef PERF_ENABLE
VX_perf_memsys_if perf_memsys_if(); VX_perf_memsys_if perf_memsys_if();
@@ -143,8 +142,7 @@ module VX_core #(
.csr_rsp_ready (csr_rsp_ready), .csr_rsp_ready (csr_rsp_ready),
// Status // Status
.busy(busy), .busy(busy)
.ebreak(ebreak)
); );
//-- //--

8
hw/rtl/VX_execute.v
View File

@@ -41,8 +41,7 @@ module VX_execute #(
VX_commit_if fpu_commit_if, VX_commit_if fpu_commit_if,
VX_commit_if gpu_commit_if, VX_commit_if gpu_commit_if,
input wire busy, input wire busy
output wire ebreak
); );
VX_fpu_to_csr_if fpu_to_csr_if(); VX_fpu_to_csr_if fpu_to_csr_if();
wire[`NUM_WARPS-1:0] csr_pending; wire[`NUM_WARPS-1:0] csr_pending;
@@ -132,9 +131,4 @@ module VX_execute #(
.gpu_commit_if (gpu_commit_if) .gpu_commit_if (gpu_commit_if)
); );
assign ebreak = alu_req_if.valid
&& `IS_BR_MOD(alu_req_if.op_mod)
&& (`BR_OP(alu_req_if.op_type) == `BR_EBREAK
|| `BR_OP(alu_req_if.op_type) == `BR_ECALL);
endmodule endmodule

6
hw/rtl/VX_pipeline.v
View File

@@ -53,8 +53,7 @@ module VX_pipeline #(
`endif `endif
// Status // Status
output wire busy, output wire busy
output wire ebreak
); );
// //
// Dcache request // Dcache request
@@ -248,8 +247,7 @@ module VX_pipeline #(
.fpu_commit_if (fpu_commit_if), .fpu_commit_if (fpu_commit_if),
.gpu_commit_if (gpu_commit_if), .gpu_commit_if (gpu_commit_if),
.busy (busy), .busy (busy)
.ebreak (ebreak)
); );
VX_commit #( VX_commit #(

8
hw/rtl/Vortex.v
View File

@@ -36,8 +36,7 @@ module Vortex (
input wire csr_rsp_ready, input wire csr_rsp_ready,
// Status // Status
output wire busy, output wire busy
output wire ebreak
); );
`STATIC_ASSERT((`L3_ENABLE == 0 || `NUM_CLUSTERS > 1), ("invalid parameter")) `STATIC_ASSERT((`L3_ENABLE == 0 || `NUM_CLUSTERS > 1), ("invalid parameter"))
@@ -65,7 +64,6 @@ module Vortex (
wire [`NUM_CLUSTERS-1:0] per_cluster_csr_rsp_ready; wire [`NUM_CLUSTERS-1:0] per_cluster_csr_rsp_ready;
wire [`NUM_CLUSTERS-1:0] per_cluster_busy; wire [`NUM_CLUSTERS-1:0] per_cluster_busy;
wire [`NUM_CLUSTERS-1:0] per_cluster_ebreak;
wire [`LOG2UP(`NUM_CLUSTERS)-1:0] csr_cluster_id = `LOG2UP(`NUM_CLUSTERS)'(csr_req_coreid >> `CLOG2(`NUM_CORES)); wire [`LOG2UP(`NUM_CLUSTERS)-1:0] csr_cluster_id = `LOG2UP(`NUM_CLUSTERS)'(csr_req_coreid >> `CLOG2(`NUM_CORES));
wire [`NC_BITS-1:0] csr_core_id = `NC_BITS'(csr_req_coreid); wire [`NC_BITS-1:0] csr_core_id = `NC_BITS'(csr_req_coreid);
@@ -113,8 +111,7 @@ module Vortex (
.csr_rsp_data (per_cluster_csr_rsp_data [i]), .csr_rsp_data (per_cluster_csr_rsp_data [i]),
.csr_rsp_ready (per_cluster_csr_rsp_ready [i]), .csr_rsp_ready (per_cluster_csr_rsp_ready [i]),
.busy (per_cluster_busy [i]), .busy (per_cluster_busy [i])
.ebreak (per_cluster_ebreak [i])
); );
end end
@@ -156,7 +153,6 @@ module Vortex (
); );
assign busy = (| per_cluster_busy); assign busy = (| per_cluster_busy);
assign ebreak = (| per_cluster_ebreak);
if (`L3_ENABLE) begin if (`L3_ENABLE) begin
`ifdef PERF_ENABLE `ifdef PERF_ENABLE

3
hw/rtl/afu/vortex_afu.sv
View File

@@ -999,8 +999,7 @@ Vortex #() vortex (
.csr_rsp_ready (vx_csr_io_rsp_ready), .csr_rsp_ready (vx_csr_io_rsp_ready),
// status // status
.busy (vx_busy), .busy (vx_busy)
`UNUSED_PIN (ebreak)
); );
// SCOPE ////////////////////////////////////////////////////////////////////// // SCOPE //////////////////////////////////////////////////////////////////////