From cbca7e12c6c14b116acbeb7ee8a084e44505016e Mon Sep 17 00:00:00 2001
From: Blaise Tine <tinebp@yahoo.com>
Date: Thu, 10 Jun 2021 12:57:44 -0700
Subject: [PATCH] removing ebreak signals from public interface

---
 hw/rtl/VX_cluster.v      | 8 ++------
 hw/rtl/VX_core.v         | 6 ++----
 hw/rtl/VX_execute.v      | 8 +-------
 hw/rtl/VX_pipeline.v     | 6 ++----
 hw/rtl/Vortex.v          | 8 ++------
 hw/rtl/afu/vortex_afu.sv | 3 +--
 6 files changed, 10 insertions(+), 29 deletions(-)

diff --git a/hw/rtl/VX_cluster.v b/hw/rtl/VX_cluster.v
index c229d16f..ea76d0f2 100644
--- a/hw/rtl/VX_cluster.v
+++ b/hw/rtl/VX_cluster.v
@@ -38,8 +38,7 @@ module VX_cluster #(
     input wire                              csr_rsp_ready,
 
     // Status
-    output wire                             busy, 
-    output wire                             ebreak
+    output wire                             busy
 ); 
     `STATIC_ASSERT((`L2_ENABLE == 0 || `NUM_CORES > 1), ("invalid parameter"))
 
@@ -67,7 +66,6 @@ module VX_cluster #(
     wire [`NUM_CORES-1:0]                       per_core_csr_rsp_ready;
 
     wire [`NUM_CORES-1:0]                       per_core_busy;
-    wire [`NUM_CORES-1:0]                       per_core_ebreak;
 
     for (genvar i = 0; i < `NUM_CORES; i++) begin
         
@@ -111,8 +109,7 @@ module VX_cluster #(
             .csr_rsp_data   (per_core_csr_rsp_data  [i]),
             .csr_rsp_ready  (per_core_csr_rsp_ready [i]),
 
-            .busy           (per_core_busy          [i]),
-            .ebreak         (per_core_ebreak        [i])
+            .busy           (per_core_busy          [i])
         );
     end
 
@@ -154,7 +151,6 @@ module VX_cluster #(
     );
     
     assign busy = (| per_core_busy);
-    assign ebreak = (| per_core_ebreak);
 
     if (`L2_ENABLE) begin
     `ifdef PERF_ENABLE
diff --git a/hw/rtl/VX_core.v b/hw/rtl/VX_core.v
index 36e74097..357302f5 100644
--- a/hw/rtl/VX_core.v
+++ b/hw/rtl/VX_core.v
@@ -37,8 +37,7 @@ module VX_core #(
     input wire                              csr_rsp_ready,
 
     // Status
-    output wire                             busy, 
-    output wire                             ebreak
+    output wire                             busy
 );
 `ifdef PERF_ENABLE
     VX_perf_memsys_if perf_memsys_if();
@@ -143,8 +142,7 @@ module VX_core #(
         .csr_rsp_ready      (csr_rsp_ready),
 
         // Status
-        .busy(busy), 
-        .ebreak(ebreak)
+        .busy(busy)
     );  
 
     //--
diff --git a/hw/rtl/VX_execute.v b/hw/rtl/VX_execute.v
index 81e0b1cc..be6cbcbd 100644
--- a/hw/rtl/VX_execute.v
+++ b/hw/rtl/VX_execute.v
@@ -41,8 +41,7 @@ module VX_execute #(
     VX_commit_if        fpu_commit_if,
     VX_commit_if        gpu_commit_if,
     
-    input wire          busy,
-    output wire         ebreak
+    input wire          busy
 );
     VX_fpu_to_csr_if     fpu_to_csr_if(); 
     wire[`NUM_WARPS-1:0] csr_pending;
@@ -132,9 +131,4 @@ module VX_execute #(
         .gpu_commit_if  (gpu_commit_if)
     );
 
-    assign ebreak = alu_req_if.valid 
-                 && `IS_BR_MOD(alu_req_if.op_mod)
-                 && (`BR_OP(alu_req_if.op_type) == `BR_EBREAK 
-                  || `BR_OP(alu_req_if.op_type) == `BR_ECALL);
-
 endmodule
diff --git a/hw/rtl/VX_pipeline.v b/hw/rtl/VX_pipeline.v
index 91305a4f..720e9ffc 100644
--- a/hw/rtl/VX_pipeline.v
+++ b/hw/rtl/VX_pipeline.v
@@ -53,8 +53,7 @@ module VX_pipeline #(
 `endif
 
     // Status
-    output wire                             busy, 
-    output wire                             ebreak
+    output wire                             busy
 );
     //
     // Dcache request
@@ -248,8 +247,7 @@ module VX_pipeline #(
         .fpu_commit_if  (fpu_commit_if),
         .gpu_commit_if  (gpu_commit_if),        
         
-        .busy           (busy), 
-        .ebreak         (ebreak)
+        .busy           (busy)
     );    
 
     VX_commit #(
diff --git a/hw/rtl/Vortex.v b/hw/rtl/Vortex.v
index f3dd9fa6..c59ba86d 100644
--- a/hw/rtl/Vortex.v
+++ b/hw/rtl/Vortex.v
@@ -36,8 +36,7 @@ module Vortex (
     input wire                              csr_rsp_ready,
 
     // Status
-    output wire                             busy, 
-    output wire                             ebreak
+    output wire                             busy
 );
     `STATIC_ASSERT((`L3_ENABLE == 0 || `NUM_CLUSTERS > 1), ("invalid parameter"))
 
@@ -65,7 +64,6 @@ module Vortex (
     wire [`NUM_CLUSTERS-1:0]                         per_cluster_csr_rsp_ready;
 
     wire [`NUM_CLUSTERS-1:0]                         per_cluster_busy;
-    wire [`NUM_CLUSTERS-1:0]                         per_cluster_ebreak;
 
     wire [`LOG2UP(`NUM_CLUSTERS)-1:0] csr_cluster_id = `LOG2UP(`NUM_CLUSTERS)'(csr_req_coreid >> `CLOG2(`NUM_CORES));
     wire [`NC_BITS-1:0] csr_core_id = `NC_BITS'(csr_req_coreid);
@@ -113,8 +111,7 @@ module Vortex (
             .csr_rsp_data   (per_cluster_csr_rsp_data   [i]),
             .csr_rsp_ready  (per_cluster_csr_rsp_ready  [i]),
 
-            .busy           (per_cluster_busy           [i]),
-            .ebreak         (per_cluster_ebreak         [i])
+            .busy           (per_cluster_busy           [i])
         );
     end
 
@@ -156,7 +153,6 @@ module Vortex (
     );
 
     assign busy   = (| per_cluster_busy);
-    assign ebreak = (| per_cluster_ebreak);
 
     if (`L3_ENABLE) begin
     `ifdef PERF_ENABLE
diff --git a/hw/rtl/afu/vortex_afu.sv b/hw/rtl/afu/vortex_afu.sv
index f5a7e8cf..55ef6712 100644
--- a/hw/rtl/afu/vortex_afu.sv
+++ b/hw/rtl/afu/vortex_afu.sv
@@ -999,8 +999,7 @@ Vortex #() vortex (
   .csr_rsp_ready  (vx_csr_io_rsp_ready),
  
   // status
-  .busy           (vx_busy),
-  `UNUSED_PIN     (ebreak)
+  .busy           (vx_busy)
 );
 
 // SCOPE //////////////////////////////////////////////////////////////////////