Vortex 2.0 changes:
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
This commit is contained in:
Blaise Tine
244
hw/rtl/afu/opae/ccip/ccip_if_pkg.sv
Normal file
244
hw/rtl/afu/opae/ccip/ccip_if_pkg.sv
Normal file
@@ -0,0 +1,244 @@
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// Date: 02/2/2016
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// Compliant with CCI-P spec v0.71
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package ccip_if_pkg;
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//=====================================================================
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// CCI-P interface defines
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//=====================================================================
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parameter CCIP_VERSION_NUMBER = 12'h071;
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parameter CCIP_CLADDR_WIDTH = 42;
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parameter CCIP_CLDATA_WIDTH = 512;
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parameter CCIP_MMIOADDR_WIDTH = 16;
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parameter CCIP_MMIODATA_WIDTH = 64;
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parameter CCIP_TID_WIDTH = 9;
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parameter CCIP_MDATA_WIDTH = 16;
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// Number of requests that can be accepted after almost full is asserted.
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parameter CCIP_TX_ALMOST_FULL_THRESHOLD = 8;
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parameter CCIP_MMIO_RD_TIMEOUT = 512;
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parameter CCIP_SYNC_RESET_POLARITY=1; // Active High Reset
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// Base types
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//----------------------------------------------------------------------
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typedef logic [CCIP_CLADDR_WIDTH-1:0] t_ccip_clAddr;
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typedef logic [CCIP_CLDATA_WIDTH-1:0] t_ccip_clData;
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typedef logic [CCIP_MMIOADDR_WIDTH-1:0] t_ccip_mmioAddr;
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typedef logic [CCIP_MMIODATA_WIDTH-1:0] t_ccip_mmioData;
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typedef logic [CCIP_TID_WIDTH-1:0] t_ccip_tid;
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typedef logic [CCIP_MDATA_WIDTH-1:0] t_ccip_mdata;
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typedef logic [1:0] t_ccip_clNum;
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typedef logic [2:0] t_ccip_qwIdx;
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// Request Type Encodings
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//----------------------------------------------------------------------
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// Channel 0
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typedef enum logic [3:0] {
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eREQ_RDLINE_I = 4'h0, // Memory Read with FPGA Cache Hint=Invalid
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eREQ_RDLINE_S = 4'h1 // Memory Read with FPGA Cache Hint=Shared
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} t_ccip_c0_req;
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// Channel 1
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typedef enum logic [3:0] {
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eREQ_WRLINE_I = 4'h0, // Memory Write with FPGA Cache Hint=Invalid
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eREQ_WRLINE_M = 4'h1, // Memory Write with FPGA Cache Hint=Modified
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eREQ_WRPUSH_I = 4'h2, // Memory Write with DDIO Hint ** NOT SUPPORTED CURRENTLY **
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eREQ_WRFENCE = 4'h4, // Memory Write Fence
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// eREQ_ATOMIC = 4'h5, // Atomic operation: Compare-Exchange for Memory Addr ** NOT SUPPORTED CURRENTELY **
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eREQ_INTR = 4'h6 // Interrupt the CPU ** NOT SUPPORTED CURRENTLY **
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} t_ccip_c1_req;
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// Response Type Encodings
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//----------------------------------------------------------------------
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// Channel 0
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typedef enum logic [3:0] {
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eRSP_RDLINE = 4'h0, // Memory Read
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eRSP_UMSG = 4'h4 // UMsg received
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// eRSP_ATOMIC = 4'h5 // Atomic Operation: Compare-Exchange for Memory Addr
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} t_ccip_c0_rsp;
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// Channel 1
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typedef enum logic [3:0] {
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eRSP_WRLINE = 4'h0, // Memory Write
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eRSP_WRFENCE = 4'h4, // Memory Write Fence
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eRSP_INTR = 4'h6 // Interrupt delivered to the CPU ** NOT SUPPORTED CURRENTLY **
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} t_ccip_c1_rsp;
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//
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// Virtual Channel Select
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//----------------------------------------------------------------------
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typedef enum logic [1:0] {
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eVC_VA = 2'b00,
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eVC_VL0 = 2'b01,
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eVC_VH0 = 2'b10,
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eVC_VH1 = 2'b11
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} t_ccip_vc;
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// Multi-CL Memory Request
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//----------------------------------------------------------------------
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typedef enum logic [1:0] {
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eCL_LEN_1 = 2'b00,
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eCL_LEN_2 = 2'b01,
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eCL_LEN_4 = 2'b11
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} t_ccip_clLen;
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//
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// Structures for Request and Response headers
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//----------------------------------------------------------------------
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typedef struct packed {
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t_ccip_vc vc_sel;
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logic [1:0] rsvd1; // reserved, drive 0
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t_ccip_clLen cl_len;
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t_ccip_c0_req req_type;
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logic [5:0] rsvd0; // reserved, drive 0
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t_ccip_clAddr address;
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t_ccip_mdata mdata;
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} t_ccip_c0_ReqMemHdr;
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parameter CCIP_C0TX_HDR_WIDTH = $bits(t_ccip_c0_ReqMemHdr);
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typedef struct packed {
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logic [5:0] rsvd2;
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t_ccip_vc vc_sel;
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logic sop;
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logic rsvd1; // reserved, drive 0
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t_ccip_clLen cl_len;
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t_ccip_c1_req req_type;
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logic [5:0] rsvd0; // reserved, drive 0
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t_ccip_clAddr address;
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t_ccip_mdata mdata;
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} t_ccip_c1_ReqMemHdr;
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parameter CCIP_C1TX_HDR_WIDTH = $bits(t_ccip_c1_ReqMemHdr);
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typedef struct packed {
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logic [5:0] rsvd2; // reserved, drive 0
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t_ccip_vc vc_sel;
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logic [3:0] rsvd1; // reserved, drive 0
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t_ccip_c1_req req_type;
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logic [47:0] rsvd0; // reserved, drive 0
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t_ccip_mdata mdata;
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}t_ccip_c1_ReqFenceHdr;
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typedef struct packed {
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t_ccip_vc vc_used;
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logic rsvd1; // reserved, don't care
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logic hit_miss;
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logic [1:0] rsvd0; // reserved, don't care
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t_ccip_clNum cl_num;
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t_ccip_c0_rsp resp_type;
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t_ccip_mdata mdata;
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} t_ccip_c0_RspMemHdr;
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parameter CCIP_C0RX_HDR_WIDTH = $bits(t_ccip_c0_RspMemHdr);
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typedef struct packed {
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t_ccip_vc vc_used;
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logic rsvd1; // reserved, don't care
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logic hit_miss;
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logic format;
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logic rsvd0; // reserved, don't care
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t_ccip_clNum cl_num;
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t_ccip_c1_rsp resp_type;
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t_ccip_mdata mdata;
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} t_ccip_c1_RspMemHdr;
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parameter CCIP_C1RX_HDR_WIDTH = $bits(t_ccip_c1_RspMemHdr);
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typedef struct packed {
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logic [7:0] rsvd0; // reserved, don't care
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t_ccip_c1_rsp resp_type;
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t_ccip_mdata mdata;
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} t_ccip_c1_RspFenceHdr;
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// Alternate Channel 0 MMIO request from host :
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// MMIO requests arrive on the same channel as read responses, sharing
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// t_if_ccip_c0_Rx below. When either mmioRdValid or mmioWrValid is set
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// the message is an MMIO request and should be processed by casting
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// t_if_ccip_c0_Rx.hdr to t_ccip_c0_ReqMmioHdr.
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typedef struct packed {
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t_ccip_mmioAddr address; // 4B aligned Mmio address
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logic [1:0] length; // 2'b00- 4B, 2'b01- 8B, 2'b10- 64B
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logic rsvd; // reserved, don't care
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t_ccip_tid tid;
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} t_ccip_c0_ReqMmioHdr;
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typedef struct packed {
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t_ccip_tid tid; // Returned back from ReqMmioHdr
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} t_ccip_c2_RspMmioHdr;
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parameter CCIP_C2TX_HDR_WIDTH = $bits(t_ccip_c2_RspMmioHdr);
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//------------------------------------------------------------------------
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// CCI-P Input & Output bus structures
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//
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// Users are encouraged to use these for AFU development
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//------------------------------------------------------------------------
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// Channel 0 : Memory Reads
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typedef struct packed {
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t_ccip_c0_ReqMemHdr hdr; // Request Header
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logic valid; // Request Valid
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} t_if_ccip_c0_Tx;
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// Channel 1 : Memory Writes, Interrupts, CmpXchg
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typedef struct packed {
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t_ccip_c1_ReqMemHdr hdr; // Request Header
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t_ccip_clData data; // Request Data
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logic valid; // Request Wr Valid
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} t_if_ccip_c1_Tx;
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// Channel 2 : MMIO Read response
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typedef struct packed {
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t_ccip_c2_RspMmioHdr hdr; // Response Header
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logic mmioRdValid; // Response Read Valid
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t_ccip_mmioData data; // Response Data
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} t_if_ccip_c2_Tx;
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// Wrap all Tx channels
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typedef struct packed {
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t_if_ccip_c0_Tx c0;
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t_if_ccip_c1_Tx c1;
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t_if_ccip_c2_Tx c2;
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} t_if_ccip_Tx;
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// Channel 0: Memory Read response, MMIO Request
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typedef struct packed {
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t_ccip_c0_RspMemHdr hdr; // Rd Response/ MMIO req Header
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t_ccip_clData data; // Rd Data / MMIO req Data
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// Only one of valid, mmioRdValid and mmioWrValid may be set
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// in a cycle. When either mmioRdValid or mmioWrValid are true
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// the hdr must be processed specially. See t_ccip_c0_ReqMmioHdr
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// above.
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logic rspValid; // Rd Response Valid
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logic mmioRdValid; // MMIO Read Valid
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logic mmioWrValid; // MMIO Write Valid
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} t_if_ccip_c0_Rx;
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// Channel 1: Memory Writes
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typedef struct packed {
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t_ccip_c1_RspMemHdr hdr; // Response Header
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logic rspValid; // Response Valid
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} t_if_ccip_c1_Rx;
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// Wrap all channels
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typedef struct packed {
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logic c0TxAlmFull; // C0 Request Channel Almost Full
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logic c1TxAlmFull; // C1 Request Channel Almost Full
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t_if_ccip_c0_Rx c0;
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t_if_ccip_c1_Rx c1;
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} t_if_ccip_Rx;
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typedef union packed {
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t_ccip_c0_RspMemHdr rspMemHdr;
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t_ccip_c0_ReqMmioHdr reqMmioHdr;
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} t_if_ccip_c0_RxHdr;
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endpackage
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48
hw/rtl/afu/opae/ccip_interface_reg.sv
Normal file
48
hw/rtl/afu/opae/ccip_interface_reg.sv
Normal file
@@ -0,0 +1,48 @@
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// Code reused from Intel OPAE's 04_local_memory sample program with changes made to fit Vortex
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// Register all interface signals
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import ccip_if_pkg::*;
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module ccip_interface_reg(
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// CCI-P Clocks and Resets
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input logic pClk, // 400MHz - CC-P clock domain. Primary Clock
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input logic pck_cp2af_softReset_T0, // CCI-P ACTIVE HIGH Soft Reset
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input logic [1:0] pck_cp2af_pwrState_T0, // CCI-P AFU Power State
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input logic pck_cp2af_error_T0, // CCI-P Protocol Error Detected
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// Interface structures
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input t_if_ccip_Rx pck_cp2af_sRx_T0, // CCI-P Rx Port
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input t_if_ccip_Tx pck_af2cp_sTx_T0, // CCI-P Tx Port
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output logic pck_cp2af_softReset_T1,
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output logic [1:0] pck_cp2af_pwrState_T1,
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output logic pck_cp2af_error_T1,
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output t_if_ccip_Rx pck_cp2af_sRx_T1,
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output t_if_ccip_Tx pck_af2cp_sTx_T1
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);
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(* preserve *) logic pck_cp2af_softReset_T0_q;
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(* preserve *) logic [1:0] pck_cp2af_pwrState_T0_q;
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(* preserve *) logic pck_cp2af_error_T0_q;
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(* preserve *) t_if_ccip_Rx pck_cp2af_sRx_T0_q;
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(* preserve *) t_if_ccip_Tx pck_af2cp_sTx_T0_q;
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always@(posedge pClk)
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begin
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pck_cp2af_softReset_T0_q <= pck_cp2af_softReset_T0;
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pck_cp2af_pwrState_T0_q <= pck_cp2af_pwrState_T0;
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pck_cp2af_error_T0_q <= pck_cp2af_error_T0;
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pck_cp2af_sRx_T0_q <= pck_cp2af_sRx_T0;
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pck_af2cp_sTx_T0_q <= pck_af2cp_sTx_T0;
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end
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always_comb
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begin
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pck_cp2af_softReset_T1 = pck_cp2af_softReset_T0_q;
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pck_cp2af_pwrState_T1 = pck_cp2af_pwrState_T0_q;
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pck_cp2af_error_T1 = pck_cp2af_error_T0_q;
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pck_cp2af_sRx_T1 = pck_cp2af_sRx_T0_q;
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pck_af2cp_sTx_T1 = pck_af2cp_sTx_T0_q;
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end
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endmodule
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123
hw/rtl/afu/opae/ccip_std_afu.sv
Normal file
123
hw/rtl/afu/opae/ccip_std_afu.sv
Normal file
@@ -0,0 +1,123 @@
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// Code reused from Intel OPAE's 04_local_memory sample program with changes made to fit Vortex
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// Top Level Vortex Driver
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// To be done:
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// Check how to run this with OPAE. Looks like setup issue
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`include "platform_if.vh"
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import local_mem_cfg_pkg::*;
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module ccip_std_afu #(
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parameter NUM_LOCAL_MEM_BANKS = 2
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) (
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// CCI-P Clocks and Resets
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input logic pClk, // Primary CCI-P interface clock.
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input logic pClkDiv2, // Aligned, pClk divided by 2.
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input logic pClkDiv4, // Aligned, pClk divided by 4.
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input logic uClk_usr, // User clock domain. Refer to clock programming guide.
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input logic uClk_usrDiv2, // Aligned, user clock divided by 2.
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input logic pck_cp2af_softReset, // CCI-P ACTIVE HIGH Soft Reset
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input logic [1:0] pck_cp2af_pwrState, // CCI-P AFU Power State
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input logic pck_cp2af_error, // CCI-P Protocol Error Detected
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// CCI-P structures
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input t_if_ccip_Rx pck_cp2af_sRx, // CCI-P Rx Port
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output t_if_ccip_Tx pck_af2cp_sTx, // CCI-P Tx Port
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// Local memory interface
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avalon_mem_if.to_fiu local_mem[NUM_LOCAL_MEM_BANKS]
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);
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// ====================================================================
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// Pick the proper clk and reset, as chosen by the AFU's JSON file
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// ====================================================================
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// The platform may transform the CCI-P clock from pClk to a clock
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// chosen in the AFU's JSON file.
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logic clk;
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assign clk = `PLATFORM_PARAM_CCI_P_CLOCK;
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logic reset;
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assign reset = `PLATFORM_PARAM_CCI_P_RESET;
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// ====================================================================
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// Register signals at interface before consuming them
|
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// ====================================================================
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(* noprune *) logic [1:0] cp2af_pwrState_T1;
|
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(* noprune *) logic cp2af_error_T1;
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logic reset_T1;
|
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t_if_ccip_Rx cp2af_sRx_T1;
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t_if_ccip_Tx af2cp_sTx_T0;
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ccip_interface_reg inst_green_ccip_interface_reg
|
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(
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.pClk (clk),
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.pck_cp2af_softReset_T0 (reset),
|
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.pck_cp2af_pwrState_T0 (pck_cp2af_pwrState),
|
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.pck_cp2af_error_T0 (pck_cp2af_error),
|
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.pck_cp2af_sRx_T0 (pck_cp2af_sRx),
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.pck_af2cp_sTx_T0 (af2cp_sTx_T0),
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.pck_cp2af_softReset_T1 (reset_T1),
|
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.pck_cp2af_pwrState_T1 (cp2af_pwrState_T1),
|
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.pck_cp2af_error_T1 (cp2af_error_T1),
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.pck_cp2af_sRx_T1 (cp2af_sRx_T1),
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.pck_af2cp_sTx_T1 (pck_af2cp_sTx)
|
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);
|
||||
|
||||
|
||||
// ====================================================================
|
||||
// User AFU goes here
|
||||
// ====================================================================
|
||||
|
||||
t_local_mem_byte_mask avs_byteenable [NUM_LOCAL_MEM_BANKS];
|
||||
logic avs_waitrequest [NUM_LOCAL_MEM_BANKS];
|
||||
t_local_mem_data avs_readdata [NUM_LOCAL_MEM_BANKS];
|
||||
logic avs_readdatavalid [NUM_LOCAL_MEM_BANKS];
|
||||
t_local_mem_burst_cnt avs_burstcount [NUM_LOCAL_MEM_BANKS];
|
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t_local_mem_data avs_writedata [NUM_LOCAL_MEM_BANKS];
|
||||
t_local_mem_addr avs_address [NUM_LOCAL_MEM_BANKS];
|
||||
logic avs_write [NUM_LOCAL_MEM_BANKS];
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||||
logic avs_read [NUM_LOCAL_MEM_BANKS];
|
||||
|
||||
for (genvar b = 0; b < NUM_LOCAL_MEM_BANKS; b++) begin
|
||||
assign local_mem[b].burstcount = avs_burstcount[b];
|
||||
assign local_mem[b].writedata = avs_writedata[b];
|
||||
assign local_mem[b].address = avs_address[b];
|
||||
assign local_mem[b].byteenable = avs_byteenable[b];
|
||||
assign local_mem[b].write = avs_write[b];
|
||||
assign local_mem[b].read = avs_read[b];
|
||||
|
||||
assign avs_waitrequest[b] = local_mem[b].waitrequest;
|
||||
assign avs_readdata[b] = local_mem[b].readdata;
|
||||
assign avs_readdatavalid[b] = local_mem[b].readdatavalid;
|
||||
end
|
||||
|
||||
vortex_afu #(
|
||||
.NUM_LOCAL_MEM_BANKS(NUM_LOCAL_MEM_BANKS)
|
||||
) afu (
|
||||
.clk (clk),
|
||||
.reset (reset_T1),
|
||||
|
||||
.cp2af_sRxPort (cp2af_sRx_T1),
|
||||
.af2cp_sTxPort (af2cp_sTx_T0),
|
||||
|
||||
.avs_writedata (avs_writedata),
|
||||
.avs_readdata (avs_readdata),
|
||||
.avs_address (avs_address),
|
||||
.avs_waitrequest (avs_waitrequest),
|
||||
.avs_write (avs_write),
|
||||
.avs_read (avs_read),
|
||||
.avs_byteenable (avs_byteenable),
|
||||
.avs_burstcount (avs_burstcount),
|
||||
.avs_readdatavalid (avs_readdatavalid)
|
||||
);
|
||||
|
||||
endmodule
|
||||
61
hw/rtl/afu/opae/local_mem_cfg_pkg.sv
Normal file
61
hw/rtl/afu/opae/local_mem_cfg_pkg.sv
Normal file
@@ -0,0 +1,61 @@
|
||||
//
|
||||
// Copyright (c) 2017, Intel Corporation
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright notice, this
|
||||
// list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright notice,
|
||||
// this list of conditions and the following disclaimer in the documentation
|
||||
// and/or other materials provided with the distribution.
|
||||
//
|
||||
// Neither the name of the Intel Corporation nor the names of its contributors
|
||||
// may be used to endorse or promote products derived from this software
|
||||
// without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
// POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
//`include "platform_afu_top_config.vh"
|
||||
|
||||
`ifdef PLATFORM_PROVIDES_LOCAL_MEMORY
|
||||
|
||||
package local_mem_cfg_pkg;
|
||||
|
||||
parameter LOCAL_MEM_VERSION_NUMBER = 1;
|
||||
|
||||
parameter LOCAL_MEM_ADDR_WIDTH = `PLATFORM_PARAM_LOCAL_MEMORY_ADDR_WIDTH;
|
||||
parameter LOCAL_MEM_DATA_WIDTH = `PLATFORM_PARAM_LOCAL_MEMORY_DATA_WIDTH;
|
||||
|
||||
parameter LOCAL_MEM_BURST_CNT_WIDTH = `PLATFORM_PARAM_LOCAL_MEMORY_BURST_CNT_WIDTH;
|
||||
|
||||
// Number of bytes in a data line
|
||||
parameter LOCAL_MEM_DATA_N_BYTES = LOCAL_MEM_DATA_WIDTH / 8;
|
||||
|
||||
|
||||
// Base types
|
||||
// --------------------------------------------------------------------
|
||||
|
||||
typedef logic [LOCAL_MEM_ADDR_WIDTH-1:0] t_local_mem_addr;
|
||||
typedef logic [LOCAL_MEM_DATA_WIDTH-1:0] t_local_mem_data;
|
||||
|
||||
typedef logic [LOCAL_MEM_BURST_CNT_WIDTH-1:0] t_local_mem_burst_cnt;
|
||||
|
||||
// Byte-level mask of a data line
|
||||
typedef logic [LOCAL_MEM_DATA_N_BYTES-1:0] t_local_mem_byte_mask;
|
||||
|
||||
endpackage // local_mem_cfg_pkg
|
||||
|
||||
`endif // PLATFORM_PROVIDES_LOCAL_MEMORY
|
||||
1093
hw/rtl/afu/opae/vortex_afu.sv
Normal file
1093
hw/rtl/afu/opae/vortex_afu.sv
Normal file
File diff suppressed because it is too large
Load Diff
39
hw/rtl/afu/opae/vortex_afu.vh
Normal file
39
hw/rtl/afu/opae/vortex_afu.vh
Normal file
@@ -0,0 +1,39 @@
|
||||
// Copyright © 2019-2023
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
`ifndef VORTEX_AFU_VH
|
||||
`define VORTEX_AFU_VH
|
||||
|
||||
`define AFU_ACCEL_NAME "vortex_afu"
|
||||
`define AFU_ACCEL_UUID 128'h35F9452B_25C2_434C_93D5_6F8C60DB361C
|
||||
|
||||
`define AFU_IMAGE_CMD_MEM_READ 1
|
||||
`define AFU_IMAGE_CMD_MEM_WRITE 2
|
||||
`define AFU_IMAGE_CMD_RUN 3
|
||||
`define AFU_IMAGE_CMD_DCR_WRITE 4
|
||||
`define AFU_IMAGE_CMD_MAX_VALUE 4
|
||||
|
||||
`define AFU_IMAGE_MMIO_CMD_TYPE 10
|
||||
`define AFU_IMAGE_MMIO_CMD_ARG0 12
|
||||
`define AFU_IMAGE_MMIO_CMD_ARG1 14
|
||||
`define AFU_IMAGE_MMIO_CMD_ARG2 16
|
||||
`define AFU_IMAGE_MMIO_STATUS 18
|
||||
`define AFU_IMAGE_MMIO_SCOPE_READ 20
|
||||
`define AFU_IMAGE_MMIO_SCOPE_WRITE 22
|
||||
`define AFU_IMAGE_MMIO_DEV_CAPS 24
|
||||
`define AFU_IMAGE_MMIO_ISA_CAPS 26
|
||||
|
||||
`define AFU_IMAGE_POWER 0
|
||||
`define AFU_TOP_IFC "ccip_std_afu_avalon_mm"
|
||||
|
||||
`endif // VORTEX_AFU_VH
|
||||
Reference in New Issue
Block a user