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Add ram async clear port fix for fpga RAM inference

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wgulian3
2020-02-06 13:07:50 -05:00
parent 9c7a9d88cf
commit c1bd731d7f
1 changed files with 6 additions and 2 deletions
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8
rtl/byte_enabled_simple_dual_port_ram.v
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@@ -23,10 +23,14 @@ module byte_enabled_simple_dual_port_ram
// end // end
integer ini; integer ini;
always@(posedge clk, posedge reset) begin always @(posedge clk, posedge reset) begin
// TODO Clearing ram not currently supported on FPGA.
if (reset) begin if (reset) begin
`ifdef ASIC
for (ini = 0; ini < 32; ini = ini + 1) GPR[ini] <= 0; for (ini = 0; ini < 32; ini = ini + 1) GPR[ini] <= 0;
end else if(we) begin `endif
end
else if(we) begin
integer thread_ind; integer thread_ind;
for (thread_ind = 0; thread_ind <= `NT_M1; thread_ind = thread_ind + 1) begin for (thread_ind = 0; thread_ind <= `NT_M1; thread_ind = thread_ind + 1) begin
if(be[thread_ind]) GPR[waddr][thread_ind][0] <= wdata[thread_ind][7:0]; if(be[thread_ind]) GPR[waddr][thread_ind][0] <= wdata[thread_ind][7:0];