From c1bd731d7f8ffa352feec59280648fda3cdbc57f Mon Sep 17 00:00:00 2001 From: wgulian3 Date: Thu, 6 Feb 2020 13:07:50 -0500 Subject: [PATCH] Add ram async clear port fix for fpga RAM inference --- rtl/byte_enabled_simple_dual_port_ram.v | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/rtl/byte_enabled_simple_dual_port_ram.v b/rtl/byte_enabled_simple_dual_port_ram.v index 7a1173d5..bc5f82f1 100644 --- a/rtl/byte_enabled_simple_dual_port_ram.v +++ b/rtl/byte_enabled_simple_dual_port_ram.v @@ -23,10 +23,14 @@ module byte_enabled_simple_dual_port_ram // end integer ini; - always@(posedge clk, posedge reset) begin + always @(posedge clk, posedge reset) begin + // TODO Clearing ram not currently supported on FPGA. if (reset) begin +`ifdef ASIC for (ini = 0; ini < 32; ini = ini + 1) GPR[ini] <= 0; - end else if(we) begin +`endif + end + else if(we) begin integer thread_ind; for (thread_ind = 0; thread_ind <= `NT_M1; thread_ind = thread_ind + 1) begin if(be[thread_ind]) GPR[waddr][thread_ind][0] <= wdata[thread_ind][7:0];