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Merging Emulator Fixes with current main branch

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This commit is contained in:
felsabbagh3
2019-11-06 23:30:20 -05:00
parent 87ae5c8cdf cb1bf65017
commit bf43680b7c
6 changed files with 40 additions and 27 deletions
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8
rtl/VX_define.v
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@@ -12,12 +12,6 @@
// `define SYN 1 // `define SYN 1
`define ASIC 1 `define ASIC 1
`define DCACHE_NUM_BANKS 8
`define DCACHE_NUMBER_BANKS 8
`define DCACHE_NUM_WORDS_PER_BLOCK 4
`define NUM_BARRIERS 4 `define NUM_BARRIERS 4
`define R_INST 7'd51 `define R_INST 7'd51
@@ -139,7 +133,7 @@
// Offset // Offset
`define DCACHE_OFFSET_NB ($clog2(`DCACHE_NUM_WORDS_PER_BLOCK)) `define DCACHE_OFFSET_NB ($clog2(`DCACHE_NUM_WORDS_PER_BLOCK))
`define DCACHE_OFFSET_ST (2+$clog2(`DCACHE_NUMBER_BANKS)) `define DCACHE_OFFSET_ST (2+$clog2(`DCACHE_BANKS))
`define DCACHE_OFFSET_ED (`DCACHE_OFFSET_ST+(`DCACHE_OFFSET_NB)-1) `define DCACHE_OFFSET_ED (`DCACHE_OFFSET_ST+(`DCACHE_OFFSET_NB)-1)

3
rtl/cache/VX_Cache_Bank.v vendored
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@@ -123,6 +123,7 @@ module VX_Cache_Bank
wire lw = (i_p_mem_read == `LW_MEM_READ);
wire lb = (i_p_mem_read == `LB_MEM_READ); wire lb = (i_p_mem_read == `LB_MEM_READ);
wire lh = (i_p_mem_read == `LH_MEM_READ); wire lh = (i_p_mem_read == `LH_MEM_READ);
wire lhu = (i_p_mem_read == `LHU_MEM_READ); wire lhu = (i_p_mem_read == `LHU_MEM_READ);
@@ -137,7 +138,7 @@ module VX_Cache_Bank
wire b2 = (byte_select == 2); wire b2 = (byte_select == 2);
wire b3 = (byte_select == 3); wire b3 = (byte_select == 3);
wire[31:0] data_unQual = b0 ? (data_use[block_offset] ) : wire[31:0] data_unQual = (b0 || lw) ? (data_use[block_offset] ) :
b1 ? (data_use[block_offset] >> 8) : b1 ? (data_use[block_offset] >> 8) :
b2 ? (data_use[block_offset] >> 16) : b2 ? (data_use[block_offset] >> 16) :
(data_use[block_offset] >> 24); (data_use[block_offset] >> 24);

4
rtl/cache/VX_cache_bank_valid.v vendored
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@@ -16,9 +16,9 @@ module VX_cache_bank_valid
thread_track_banks = 0; thread_track_banks = 0;
for (t_id = 0; t_id <= `NT_M1; t_id = t_id + 1) for (t_id = 0; t_id <= `NT_M1; t_id = t_id + 1)
begin begin
thread_track_banks[i_p_addr[t_id][4:2]][t_id] = i_p_valid[t_id]; thread_track_banks[i_p_addr[t_id][2+$clog2(NUMBER_BANKS)-1:2]][t_id] = i_p_valid[t_id];
end end
end end
endgenerate endgenerate
endmodule endmodule

23
rtl/cache/VX_d_cache.v vendored
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@@ -169,17 +169,18 @@ module VX_d_cache
wire[`DCACHE_BANKS - 1 : 0] detect_bank_miss; wire[`DCACHE_BANKS - 1 : 0] detect_bank_miss;
assign threads_serviced_Qual = threads_serviced_per_bank[0] | threads_serviced_per_bank[1] | //assign threads_serviced_Qual = threads_serviced_per_bank[0] | threads_serviced_per_bank[1] |
threads_serviced_per_bank[2] | threads_serviced_per_bank[3] | // threads_serviced_per_bank[2] | threads_serviced_per_bank[3] |
threads_serviced_per_bank[4] | threads_serviced_per_bank[5] | // threads_serviced_per_bank[4] | threads_serviced_per_bank[5] |
threads_serviced_per_bank[6] | threads_serviced_per_bank[7]; // threads_serviced_per_bank[6] | threads_serviced_per_bank[7];
// genvar bbid; integer bbid;
// always @(*) begin always @(*) begin
// for (bbid = 0; bbid < NUMBER_BANKS; bbid=bbid+1) threads_serviced_Qual = 0;
// begin for (bbid = 0; bbid < `DCACHE_BANKS; bbid=bbid+1)
// assign threads_serviced_Qual = threads_serviced_Qual | threads_serviced_per_bank[bbid]; begin
// end threads_serviced_Qual = threads_serviced_Qual | threads_serviced_per_bank[bbid];
// end end
end

4
rtl/interfaces/VX_dram_req_rsp_inter.v
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@@ -11,11 +11,11 @@ interface VX_dram_req_rsp_inter ();
wire [31:0] o_m_evict_addr; wire [31:0] o_m_evict_addr;
wire [31:0] o_m_read_addr; wire [31:0] o_m_read_addr;
wire o_m_valid; wire o_m_valid;
wire[`DCACHE_NUMBER_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0][31:0] o_m_writedata; wire[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0][31:0] o_m_writedata;
wire o_m_read_or_write; wire o_m_read_or_write;
// Rsp // Rsp
wire[`DCACHE_NUMBER_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata; wire[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata;
wire i_m_ready; wire i_m_ready;

25
rtl/modelsim/vortex_dpi.cpp
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@@ -6,6 +6,7 @@
#include <../simulate/ram.h> #include <../simulate/ram.h>
#include <stdio.h> #include <stdio.h>
#include <math.h>
#include "svdpi.h" #include "svdpi.h"
#include "../simulate/VX_define.h" #include "../simulate/VX_define.h"
@@ -27,11 +28,22 @@ unsigned refill_addr;
unsigned num_cycles; unsigned num_cycles;
unsigned getIndex(int, int, int); unsigned getIndex(int, int, int);
unsigned calculate_bits_per_bank_num(int);
unsigned getIndex(int r, int c, int numCols) unsigned getIndex(int r, int c, int numCols)
{ {
return (r * numCols) + c; return (r * numCols) + c;
} }
unsigned calculate_bits_per_bank_num(int num)
{
int shifted_num = 0;
for(int i = 0; i < num; i++){
shifted_num = (shifted_num << 1)| 1 ;
}
return shifted_num;
}
void load_file(char * filename) void load_file(char * filename)
{ {
@@ -69,6 +81,7 @@ void ibus_driver(bool clk, unsigned pc_addr, unsigned * instruction)
} }
void dbus_driver(bool clk, unsigned o_m_read_addr, unsigned o_m_evict_addr, bool o_m_valid, svLogicVecVal * o_m_writedata, bool o_m_read_or_write, svLogicVecVal * i_m_readdata, bool * i_m_ready) void dbus_driver(bool clk, unsigned o_m_read_addr, unsigned o_m_evict_addr, bool o_m_valid, svLogicVecVal * o_m_writedata, bool o_m_read_or_write, svLogicVecVal * i_m_readdata, bool * i_m_ready)
{ {
@@ -116,8 +129,10 @@ void dbus_driver(bool clk, unsigned o_m_read_addr, unsigned o_m_evict_addr, bool
unsigned addr_without_byte = new_addr >> 2; unsigned addr_without_byte = new_addr >> 2;
unsigned bank_num = addr_without_byte & 0x7; unsigned bits_per_bank = (int)log2(CACHE_NUM_BANKS);
unsigned addr_wihtout_bank = addr_without_byte >> 3; unsigned maskbits_per_bank = calculate_bits_per_bank_num(bits_per_bank);
unsigned bank_num = addr_without_byte & maskbits_per_bank;
unsigned addr_wihtout_bank = addr_without_byte >> bits_per_bank;
unsigned offset_num = addr_wihtout_bank & 0x3; unsigned offset_num = addr_wihtout_bank & 0x3;
unsigned value; unsigned value;
@@ -149,8 +164,10 @@ void dbus_driver(bool clk, unsigned o_m_read_addr, unsigned o_m_evict_addr, bool
unsigned addr_without_byte = new_addr >> 2; unsigned addr_without_byte = new_addr >> 2;
unsigned bank_num = addr_without_byte & 0x7; unsigned bits_per_bank = (int)log2(CACHE_NUM_BANKS);
unsigned addr_wihtout_bank = addr_without_byte >> 3; unsigned maskbits_per_bank = calculate_bits_per_bank_num(bits_per_bank);
unsigned bank_num = addr_without_byte & maskbits_per_bank;
unsigned addr_wihtout_bank = addr_without_byte >> bits_per_bank;
unsigned offset_num = addr_wihtout_bank & 0x3; unsigned offset_num = addr_wihtout_bank & 0x3;
unsigned index = getIndex(bank_num,offset_num, CACHE_WORDS_PER_BLOCK); unsigned index = getIndex(bank_num,offset_num, CACHE_WORDS_PER_BLOCK);