diff --git a/rtl/VX_define.v b/rtl/VX_define.v index 04256674..db69c62e 100644 --- a/rtl/VX_define.v +++ b/rtl/VX_define.v @@ -12,12 +12,6 @@ // `define SYN 1 `define ASIC 1 -`define DCACHE_NUM_BANKS 8 - -`define DCACHE_NUMBER_BANKS 8 -`define DCACHE_NUM_WORDS_PER_BLOCK 4 - - `define NUM_BARRIERS 4 `define R_INST 7'd51 @@ -139,7 +133,7 @@ // Offset `define DCACHE_OFFSET_NB ($clog2(`DCACHE_NUM_WORDS_PER_BLOCK)) -`define DCACHE_OFFSET_ST (2+$clog2(`DCACHE_NUMBER_BANKS)) +`define DCACHE_OFFSET_ST (2+$clog2(`DCACHE_BANKS)) `define DCACHE_OFFSET_ED (`DCACHE_OFFSET_ST+(`DCACHE_OFFSET_NB)-1) diff --git a/rtl/cache/VX_Cache_Bank.v b/rtl/cache/VX_Cache_Bank.v index d22cf144..22d6c8b6 100644 --- a/rtl/cache/VX_Cache_Bank.v +++ b/rtl/cache/VX_Cache_Bank.v @@ -123,6 +123,7 @@ module VX_Cache_Bank + wire lw = (i_p_mem_read == `LW_MEM_READ); wire lb = (i_p_mem_read == `LB_MEM_READ); wire lh = (i_p_mem_read == `LH_MEM_READ); wire lhu = (i_p_mem_read == `LHU_MEM_READ); @@ -137,7 +138,7 @@ module VX_Cache_Bank wire b2 = (byte_select == 2); wire b3 = (byte_select == 3); - wire[31:0] data_unQual = b0 ? (data_use[block_offset] ) : + wire[31:0] data_unQual = (b0 || lw) ? (data_use[block_offset] ) : b1 ? (data_use[block_offset] >> 8) : b2 ? (data_use[block_offset] >> 16) : (data_use[block_offset] >> 24); diff --git a/rtl/cache/VX_cache_bank_valid.v b/rtl/cache/VX_cache_bank_valid.v index ff14b299..b7fc94be 100644 --- a/rtl/cache/VX_cache_bank_valid.v +++ b/rtl/cache/VX_cache_bank_valid.v @@ -16,9 +16,9 @@ module VX_cache_bank_valid thread_track_banks = 0; for (t_id = 0; t_id <= `NT_M1; t_id = t_id + 1) begin - thread_track_banks[i_p_addr[t_id][4:2]][t_id] = i_p_valid[t_id]; + thread_track_banks[i_p_addr[t_id][2+$clog2(NUMBER_BANKS)-1:2]][t_id] = i_p_valid[t_id]; end end endgenerate -endmodule \ No newline at end of file +endmodule diff --git a/rtl/cache/VX_d_cache.v b/rtl/cache/VX_d_cache.v index bc88ad05..8bd3e109 100644 --- a/rtl/cache/VX_d_cache.v +++ b/rtl/cache/VX_d_cache.v @@ -169,17 +169,18 @@ module VX_d_cache wire[`DCACHE_BANKS - 1 : 0] detect_bank_miss; - assign threads_serviced_Qual = threads_serviced_per_bank[0] | threads_serviced_per_bank[1] | - threads_serviced_per_bank[2] | threads_serviced_per_bank[3] | - threads_serviced_per_bank[4] | threads_serviced_per_bank[5] | - threads_serviced_per_bank[6] | threads_serviced_per_bank[7]; - // genvar bbid; - // always @(*) begin - // for (bbid = 0; bbid < NUMBER_BANKS; bbid=bbid+1) - // begin - // assign threads_serviced_Qual = threads_serviced_Qual | threads_serviced_per_bank[bbid]; - // end - // end + //assign threads_serviced_Qual = threads_serviced_per_bank[0] | threads_serviced_per_bank[1] | + // threads_serviced_per_bank[2] | threads_serviced_per_bank[3] | + // threads_serviced_per_bank[4] | threads_serviced_per_bank[5] | + // threads_serviced_per_bank[6] | threads_serviced_per_bank[7]; + integer bbid; + always @(*) begin + threads_serviced_Qual = 0; + for (bbid = 0; bbid < `DCACHE_BANKS; bbid=bbid+1) + begin + threads_serviced_Qual = threads_serviced_Qual | threads_serviced_per_bank[bbid]; + end + end diff --git a/rtl/interfaces/VX_dram_req_rsp_inter.v b/rtl/interfaces/VX_dram_req_rsp_inter.v index 5d6d7b5a..23391d82 100644 --- a/rtl/interfaces/VX_dram_req_rsp_inter.v +++ b/rtl/interfaces/VX_dram_req_rsp_inter.v @@ -11,11 +11,11 @@ interface VX_dram_req_rsp_inter (); wire [31:0] o_m_evict_addr; wire [31:0] o_m_read_addr; wire o_m_valid; - wire[`DCACHE_NUMBER_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0][31:0] o_m_writedata; + wire[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0][31:0] o_m_writedata; wire o_m_read_or_write; // Rsp - wire[`DCACHE_NUMBER_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata; + wire[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata; wire i_m_ready; diff --git a/rtl/modelsim/vortex_dpi.cpp b/rtl/modelsim/vortex_dpi.cpp index 5fe66cf6..7eba51b1 100644 --- a/rtl/modelsim/vortex_dpi.cpp +++ b/rtl/modelsim/vortex_dpi.cpp @@ -6,6 +6,7 @@ #include <../simulate/ram.h> #include +#include #include "svdpi.h" #include "../simulate/VX_define.h" @@ -27,11 +28,22 @@ unsigned refill_addr; unsigned num_cycles; unsigned getIndex(int, int, int); +unsigned calculate_bits_per_bank_num(int); + unsigned getIndex(int r, int c, int numCols) { return (r * numCols) + c; } +unsigned calculate_bits_per_bank_num(int num) +{ + int shifted_num = 0; + for(int i = 0; i < num; i++){ + shifted_num = (shifted_num << 1)| 1 ; + } + return shifted_num; +} + void load_file(char * filename) { @@ -69,6 +81,7 @@ void ibus_driver(bool clk, unsigned pc_addr, unsigned * instruction) } + void dbus_driver(bool clk, unsigned o_m_read_addr, unsigned o_m_evict_addr, bool o_m_valid, svLogicVecVal * o_m_writedata, bool o_m_read_or_write, svLogicVecVal * i_m_readdata, bool * i_m_ready) { @@ -116,8 +129,10 @@ void dbus_driver(bool clk, unsigned o_m_read_addr, unsigned o_m_evict_addr, bool unsigned addr_without_byte = new_addr >> 2; - unsigned bank_num = addr_without_byte & 0x7; - unsigned addr_wihtout_bank = addr_without_byte >> 3; + unsigned bits_per_bank = (int)log2(CACHE_NUM_BANKS); + unsigned maskbits_per_bank = calculate_bits_per_bank_num(bits_per_bank); + unsigned bank_num = addr_without_byte & maskbits_per_bank; + unsigned addr_wihtout_bank = addr_without_byte >> bits_per_bank; unsigned offset_num = addr_wihtout_bank & 0x3; unsigned value; @@ -149,8 +164,10 @@ void dbus_driver(bool clk, unsigned o_m_read_addr, unsigned o_m_evict_addr, bool unsigned addr_without_byte = new_addr >> 2; - unsigned bank_num = addr_without_byte & 0x7; - unsigned addr_wihtout_bank = addr_without_byte >> 3; + unsigned bits_per_bank = (int)log2(CACHE_NUM_BANKS); + unsigned maskbits_per_bank = calculate_bits_per_bank_num(bits_per_bank); + unsigned bank_num = addr_without_byte & maskbits_per_bank; + unsigned addr_wihtout_bank = addr_without_byte >> bits_per_bank; unsigned offset_num = addr_wihtout_bank & 0x3; unsigned index = getIndex(bank_num,offset_num, CACHE_WORDS_PER_BLOCK);