yosys synthesis refactoring

2020-07-10 18:56:41 -04:00
parent 77c3b2d45f
commit bdfacf709c
28 changed files with 136 additions and 134 deletions
--- a/hw/rtl/libs/VX_priority_encoder.v
+++ b/hw/rtl/libs/VX_priority_encoder.v
@@ -1,7 +1,7 @@
 `include "VX_define.vh"

 module VX_priority_encoder #( 
-    parameter N
+    parameter N = 1
 ) (
    input  wire [N-1:0]         data_in,
    output reg [`LOG2UP(N)-1:0] data_out,