yosys synthesis refactoring

2020-07-10 18:56:41 -04:00
parent 77c3b2d45f
commit bdfacf709c
28 changed files with 136 additions and 134 deletions
--- a/hw/rtl/libs/VX_indexable_queue.v
+++ b/hw/rtl/libs/VX_indexable_queue.v
@@ -1,8 +1,8 @@
 `include "VX_define.vh"

 module VX_indexable_queue #(
-    parameter DATAW,
-    parameter SIZE
+    parameter DATAW = 1,
+    parameter SIZE = 1
 ) (
    input  wire clk,
    input  wire reset,