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yosys synthesis refactoring

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This commit is contained in:
Blaise Tine
2020-07-10 18:56:41 -04:00
parent 77c3b2d45f
commit bdfacf709c
28 changed files with 136 additions and 134 deletions
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10
hw/rtl/libs/VX_divide.v
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@@ -10,11 +10,11 @@ module VX_divide #(
input wire clk,
input wire reset,
input [WIDTHN-1:0] numer,
input [WIDTHD-1:0] denom,
input wire [WIDTHN-1:0] numer,
input wire [WIDTHD-1:0] denom,
output reg [WIDTHN-1:0] quotient,
output reg [WIDTHD-1:0] remainder
output wire [WIDTHN-1:0] quotient,
output wire [WIDTHD-1:0] remainder
);
`ifdef QUARTUS
@@ -36,7 +36,7 @@ module VX_divide #(
quartus_div.lpm_nrepresentation = NSIGNED ? "SIGNED" : "UNSIGNED",
quartus_div.lpm_drepresentation = DSIGNED ? "SIGNED" : "UNSIGNED",
quartus_div.lpm_hint = "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=FALSE",
quartus_div.lpm_pipeline = PIPELINE;
quartus_div.lpm_pipeline = PIPELINE;
`else