yosys synthesis refactoring

hw/rtl/cache/VX_cache_miss_resrv.v

@@ -66,7 +66,7 @@ module VX_cache_miss_resrv #(
 
     reg [`LOG2UP(MRVQ_SIZE+1)-1:0] size;
 
-    `STATIC_ASSERT(MRVQ_SIZE > 5, "invalid size");
+    `STATIC_ASSERT(MRVQ_SIZE > 5, "invalid size")
 
     assign miss_resrv_full = (size == $bits(size)'(MRVQ_SIZE));
     assign miss_resrv_stop = (size  > $bits(size)'(MRVQ_SIZE-5)); // need to add 5 cycles to prevent pipeline lock

hw/rtl/cache/VX_snp_forwarder.v

@@ -37,7 +37,7 @@ module VX_snp_forwarder #(
     input wire [NUM_REQUESTS-1:0][`LOG2UP(SNRQ_SIZE)-1:0] snp_fwdin_tag,
     output wire [NUM_REQUESTS-1:0]      snp_fwdin_ready
 );
-    `STATIC_ASSERT(NUM_REQUESTS > 1, "invalid value");
+    `STATIC_ASSERT(NUM_REQUESTS > 1, "invalid value")
 
     reg [`REQS_BITS:0] pending_cntrs [SNRQ_SIZE-1:0];