yosys synthesis refactoring
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@@ -34,7 +34,7 @@ TOP = Vortex
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SRCS = vortex.cpp ../common/vx_utils.cpp ../../hw/simulate/simulator.cpp
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RTL_INCLUDE = -I../../hw/rtl -I../../hw/rtl/libs -I../../hw/rtl/interfaces -I../../hw/rtl/pipe_regs -I../../hw/rtl/cache
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RTL_INCLUDE = -I../../hw/rtl -I../../hw/rtl/libs -I../../hw/rtl/interfaces -I../../hw/rtl/cache
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VL_FLAGS += --language 1800-2009 --assert -Wall -Wpedantic $(CONFIGS)
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VL_FLAGS += -Wno-DECLFILENAME
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