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Demo SOC W=8, T=4 Passing

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This commit is contained in:
felsabbagh3
2020-03-30 22:17:38 -07:00
parent 66a837b0df
commit bcf894b581
3 changed files with 6 additions and 2 deletions
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1
rtl/VX_cache/VX_bank.v
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@@ -468,6 +468,7 @@ module VX_bank
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
.stall (stall_bank_pipe), .stall (stall_bank_pipe),
.stall_bank_pipe(stall_bank_pipe),
// Initial Read // Initial Read
.readaddr_st10 (addr_st1[0]), .readaddr_st10 (addr_st1[0]),

4
rtl/VX_cache/VX_tag_data_access.v
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@@ -51,6 +51,7 @@ module VX_tag_data_access
input wire reset, input wire reset,
input wire stall, input wire stall,
input wire is_snp_st1e, input wire is_snp_st1e,
input wire stall_bank_pipe,
// Initial Reading // Initial Reading
input wire[31:0] readaddr_st10, input wire[31:0] readaddr_st10,
@@ -123,6 +124,7 @@ module VX_tag_data_access
( (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
.stall_bank_pipe(stall_bank_pipe),
.read_addr (readaddr_st10), .read_addr (readaddr_st10),
.read_valid (qual_read_valid_st1), .read_valid (qual_read_valid_st1),
@@ -278,7 +280,7 @@ module VX_tag_data_access
wire tags_mismatch = writeaddr_tag != use_read_tag_st1e; wire tags_mismatch = writeaddr_tag != use_read_tag_st1e;
wire tags_match = writeaddr_tag == use_read_tag_st1e; wire tags_match = writeaddr_tag == use_read_tag_st1e;
wire snoop_hit = valid_req_st1e && is_snp_st1e && use_read_valid_st1e && tags_match; wire snoop_hit = valid_req_st1e && is_snp_st1e && use_read_valid_st1e && tags_match && use_read_dirty_st1e;
wire req_invalid = valid_req_st1e && !is_snp_st1e && !use_read_valid_st1e && !writefill_st1e; wire req_invalid = valid_req_st1e && !is_snp_st1e && !use_read_valid_st1e && !writefill_st1e;
wire req_miss = valid_req_st1e && !is_snp_st1e && use_read_valid_st1e && !writefill_st1e && tags_mismatch; wire req_miss = valid_req_st1e && !is_snp_st1e && use_read_valid_st1e && !writefill_st1e && tags_mismatch;

3
rtl/VX_cache/VX_tag_data_structure.v
View File

@@ -49,6 +49,7 @@ module VX_tag_data_structure
( (
input wire clk, input wire clk,
input wire reset, input wire reset,
input wire stall_bank_pipe,
input wire[31:0] read_addr, input wire[31:0] read_addr,
output wire read_valid, output wire read_valid,
@@ -91,7 +92,7 @@ module VX_tag_data_structure
dirty[l] <= 0; dirty[l] <= 0;
data [l] <= 0; data [l] <= 0;
end end
end else begin end else if (!stall_bank_pipe) begin
if (going_to_write) begin if (going_to_write) begin
valid[write_addr[`LINE_SELECT_ADDR_RNG]] <= 1; valid[write_addr[`LINE_SELECT_ADDR_RNG]] <= 1;
tag [write_addr[`LINE_SELECT_ADDR_RNG]] <= write_addr[`TAG_SELECT_ADDR_RNG]; tag [write_addr[`LINE_SELECT_ADDR_RNG]] <= write_addr[`TAG_SELECT_ADDR_RNG];