From bcf894b581fa7e8080edc37bc677d8c028158867 Mon Sep 17 00:00:00 2001 From: felsabbagh3 Date: Mon, 30 Mar 2020 22:17:38 -0700 Subject: [PATCH] Demo SOC W=8, T=4 Passing --- rtl/VX_cache/VX_bank.v | 1 + rtl/VX_cache/VX_tag_data_access.v | 4 +++- rtl/VX_cache/VX_tag_data_structure.v | 3 ++- 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/rtl/VX_cache/VX_bank.v b/rtl/VX_cache/VX_bank.v index f7e6090c..3fc36692 100644 --- a/rtl/VX_cache/VX_bank.v +++ b/rtl/VX_cache/VX_bank.v @@ -468,6 +468,7 @@ module VX_bank .clk (clk), .reset (reset), .stall (stall_bank_pipe), + .stall_bank_pipe(stall_bank_pipe), // Initial Read .readaddr_st10 (addr_st1[0]), diff --git a/rtl/VX_cache/VX_tag_data_access.v b/rtl/VX_cache/VX_tag_data_access.v index 471a0956..39c54ba1 100644 --- a/rtl/VX_cache/VX_tag_data_access.v +++ b/rtl/VX_cache/VX_tag_data_access.v @@ -51,6 +51,7 @@ module VX_tag_data_access input wire reset, input wire stall, input wire is_snp_st1e, + input wire stall_bank_pipe, // Initial Reading input wire[31:0] readaddr_st10, @@ -123,6 +124,7 @@ module VX_tag_data_access ( .clk (clk), .reset (reset), + .stall_bank_pipe(stall_bank_pipe), .read_addr (readaddr_st10), .read_valid (qual_read_valid_st1), @@ -278,7 +280,7 @@ module VX_tag_data_access wire tags_mismatch = writeaddr_tag != use_read_tag_st1e; wire tags_match = writeaddr_tag == use_read_tag_st1e; - wire snoop_hit = valid_req_st1e && is_snp_st1e && use_read_valid_st1e && tags_match; + wire snoop_hit = valid_req_st1e && is_snp_st1e && use_read_valid_st1e && tags_match && use_read_dirty_st1e; wire req_invalid = valid_req_st1e && !is_snp_st1e && !use_read_valid_st1e && !writefill_st1e; wire req_miss = valid_req_st1e && !is_snp_st1e && use_read_valid_st1e && !writefill_st1e && tags_mismatch; diff --git a/rtl/VX_cache/VX_tag_data_structure.v b/rtl/VX_cache/VX_tag_data_structure.v index b13d776e..7ceffcc0 100644 --- a/rtl/VX_cache/VX_tag_data_structure.v +++ b/rtl/VX_cache/VX_tag_data_structure.v @@ -49,6 +49,7 @@ module VX_tag_data_structure ( input wire clk, input wire reset, + input wire stall_bank_pipe, input wire[31:0] read_addr, output wire read_valid, @@ -91,7 +92,7 @@ module VX_tag_data_structure dirty[l] <= 0; data [l] <= 0; end - end else begin + end else if (!stall_bank_pipe) begin if (going_to_write) begin valid[write_addr[`LINE_SELECT_ADDR_RNG]] <= 1; tag [write_addr[`LINE_SELECT_ADDR_RNG]] <= write_addr[`TAG_SELECT_ADDR_RNG];