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RTL code refactoring

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This commit is contained in:
Blaise Tine
2020-04-21 01:03:37 -04:00
parent cfa8626bf7
commit ba4e736782
29 changed files with 332 additions and 563 deletions
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50
simX/cache_simX.v
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@@ -1,4 +1,3 @@
`include "VX_define.vh"
module cache_simX (
@@ -6,36 +5,28 @@ module cache_simX (
input wire reset,
// Icache
input wire[31:0] in_icache_pc_addr,
input wire in_icache_valid_pc_addr,
output wire out_icache_stall,
input wire[31:0] cache_pc_addr,
input wire icache_valid_pc_addr,
output wire icache_stall,
// Dcache
input wire[2:0] in_dcache_mem_read,
input wire[2:0] in_dcache_mem_write,
input wire in_dcache_in_valid[`NT_M1:0],
input wire[31:0] in_dcache_in_address[`NT_M1:0],
output wire out_dcache_stall
input wire[2:0] dcache_mem_read,
input wire[2:0] dcache_mem_write,
input wire dcache_in_valid[`NT_M1:0],
input wire[31:0] dcache_in_addr[`NT_M1:0],
output wire dcache_stall
);
//////////////////// ICACHE ///////////////////
VX_icache_request_if VX_icache_req;
assign VX_icache_req.pc_address = in_icache_pc_addr;
assign VX_icache_req.cache_driver_in_mem_read_o = (in_icache_valid_pc_addr) ? `LW_MEM_READ : `NO_MEM_READ;
assign VX_icache_req.pc_address = cache_pc_addr;
assign VX_icache_req.cache_driver_in_mem_read_o = (icache_valid_pc_addr) ? `LW_MEM_READ : `NO_MEM_READ;
assign VX_icache_req.cache_driver_in_mem_write_o = `NO_MEM_WRITE;
assign VX_icache_req.cache_driver_in_valid_o = in_icache_valid_pc_addr;
assign VX_icache_req.cache_driver_in_valid_o = icache_valid_pc_addr;
assign VX_icache_req.cache_driver_in_data_o = 0;
VX_icache_rsp_if VX_icache_rsp;
assign out_icache_stall = VX_icache_rsp.delay;
assign icache_stall = VX_icache_rsp.delay;
VX_dram_req_rsp_if #(
@@ -48,25 +39,22 @@ module cache_simX (
assign VX_dram_req_rsp_icache.i_m_ready = icache_i_m_ready;
//////////////////// DCACHE ///////////////////
VX_dcache_request_if VX_dcache_req;
assign VX_dcache_req.cache_driver_in_mem_read_o = in_dcache_mem_read;
assign VX_dcache_req.cache_driver_in_mem_write_o = in_dcache_mem_write;
assign VX_dcache_req.cache_driver_in_mem_read_o = dcache_mem_read;
assign VX_dcache_req.cache_driver_in_mem_write_o = dcache_mem_write;
assign VX_dcache_req.cache_driver_in_data_o = 0;
genvar curr_t;
for (curr_t = 0; curr_t < `NT; curr_t=curr_t+1)
begin
assign VX_dcache_req.cache_driver_in_address_o[curr_t] = in_dcache_in_address[curr_t];
assign VX_dcache_req.cache_driver_in_valid_o[curr_t] = in_dcache_in_valid[curr_t];
assign VX_dcache_req.cache_driver_in_address_o[curr_t] = dcache_in_addr[curr_t];
assign VX_dcache_req.cache_driver_in_valid_o[curr_t] = dcache_in_valid[curr_t];
end
VX_dcache_response_if VX_dcache_rsp;
assign out_dcache_stall = VX_dcache_rsp.delay;
assign dcache_stall = VX_dcache_rsp.delay;
VX_dram_req_rsp_if #(
@@ -78,7 +66,6 @@ module cache_simX (
reg dcache_i_m_ready;
assign VX_dram_req_rsp.i_m_ready = dcache_i_m_ready;
VX_dmem_ctrl dmem_controller (
.clk (clk),
.reset (reset),
@@ -118,7 +105,6 @@ module cache_simX (
end
end
endmodule