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RTL code refactoring

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This commit is contained in:
Blaise Tine
2020-04-21 01:03:37 -04:00
parent cfa8626bf7
commit ba4e736782
29 changed files with 332 additions and 563 deletions
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8
hw/rtl/pipe_regs/VX_d_e_reg.v
View File

@@ -3,14 +3,14 @@
module VX_d_e_reg (
input wire clk,
input wire reset,
input wire branch_stall_i,
input wire freeze_i,
input wire branch_stall,
input wire freeze,
VX_frE_to_bckE_req_if frE_to_bckE_req_if,
VX_frE_to_bckE_req_if bckE_req_if
);
wire stall = freeze_i;
wire flush = (branch_stall_i == `STALL);
wire stall = freeze;
wire flush = (branch_stall == `STALL);
VX_generic_register #(
.N(233 + `NW_BITS-1 + 1 + `NUM_THREADS)

4
hw/rtl/pipe_regs/VX_f_d_reg.v
View File

@@ -3,7 +3,7 @@
module VX_f_d_reg (
input wire clk,
input wire reset,
input wire freeze_i,
input wire freeze,
VX_inst_meta_if fe_inst_meta_fd,
VX_inst_meta_if fd_inst_meta_de
@@ -11,7 +11,7 @@ module VX_f_d_reg (
);
wire flush = 1'b0;
wire stall = freeze_i == 1'b1;
wire stall = freeze == 1'b1;
VX_generic_register #(
.N(64+`NW_BITS-1+1+`NUM_THREADS)

4
hw/rtl/pipe_regs/VX_i_d_reg.v
View File

@@ -3,7 +3,7 @@
module VX_i_d_reg (
input wire clk,
input wire reset,
input wire freeze_i,
input wire freeze,
VX_inst_meta_if fe_inst_meta_fd,
VX_inst_meta_if fd_inst_meta_de
@@ -11,7 +11,7 @@ module VX_i_d_reg (
);
wire flush = 1'b0;
wire stall = freeze_i == 1'b1;
wire stall = freeze == 1'b1;
VX_generic_register #(