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RTL code refactoring

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This commit is contained in:
Blaise Tine
2020-04-21 01:03:37 -04:00
parent cfa8626bf7
commit ba4e736782
29 changed files with 332 additions and 563 deletions
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28
hw/rtl/VX_writeback.v
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@@ -12,9 +12,9 @@ module VX_writeback (
// Actual WB to GPR
VX_wb_if writeback_if,
output wire no_slot_mem_o,
output wire no_slot_exec_o,
output wire no_slot_csr_o
output wire no_slot_mem,
output wire no_slot_exec,
output wire no_slot_csr
);
VX_wb_if writeback_tempp_if();
@@ -23,17 +23,15 @@ module VX_writeback (
wire mem_wb = (mem_wb_if.wb != 0) && (|mem_wb_if.wb_valid);
wire csr_wb = (csr_wb_if.wb != 0) && (|csr_wb_if.valid);
assign no_slot_mem_o = mem_wb && (exec_wb || csr_wb);
assign no_slot_csr_o = csr_wb && (exec_wb);
assign no_slot_exec_o = 0;
assign no_slot_mem = mem_wb && (exec_wb || csr_wb);
assign no_slot_csr = csr_wb && (exec_wb);
assign no_slot_exec = 0;
assign writeback_tempp_if.write_data = exec_wb ? inst_exec_wb_if.alu_result :
csr_wb ? csr_wb_if.csr_result :
mem_wb ? mem_wb_if.loaded_data :
0;
assign writeback_tempp_if.wb_valid = exec_wb ? inst_exec_wb_if.wb_valid :
csr_wb ? csr_wb_if.valid :
mem_wb ? mem_wb_if.wb_valid :
@@ -52,9 +50,7 @@ module VX_writeback (
assign writeback_tempp_if.wb_warp_num = exec_wb ? inst_exec_wb_if.wb_warp_num :
csr_wb ? csr_wb_if.warp_num :
mem_wb ? mem_wb_if.wb_warp_num :
0;
0;
assign writeback_tempp_if.wb_pc = exec_wb ? inst_exec_wb_if.exec_wb_pc :
csr_wb ? 32'hdeadbeef :
@@ -63,19 +59,21 @@ module VX_writeback (
wire zero = 0;
wire[`NUM_THREADS-1:0][31:0] use_wb_data;
wire [`NUM_THREADS-1:0][31:0] use_wb_data;
VX_generic_register #(.N(39 + `NW_BITS-1 + 1 + `NUM_THREADS*33)) wb_register(
VX_generic_register #(
.N(39 + `NW_BITS-1 + 1 + `NUM_THREADS*33)
) wb_register (
.clk (clk),
.reset(reset),
.stall(zero),
.flush(zero),
.in ({writeback_tempp_if.write_data, writeback_tempp_if.wb_valid, writeback_tempp_if.rd, writeback_tempp_if.wb, writeback_tempp_if.wb_warp_num, writeback_tempp_if.wb_pc}),
.out ({use_wb_data , writeback_if.wb_valid, writeback_if.rd, writeback_if.wb, writeback_if.wb_warp_num, writeback_if.wb_pc})
);
);
reg [31:0] last_data_wb /* verilator public */;
reg[31:0] last_data_wb /* verilator public */ ;
always @(posedge clk) begin
if ((|writeback_if.wb_valid) && (writeback_if.wb != 0) && (writeback_if.rd == 28)) begin
last_data_wb <= use_wb_data[0];