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minor update

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This commit is contained in:
Blaise Tine
2020-12-26 14:47:41 -08:00
parent 33c431ed44
commit b2b8f190dd
9 changed files with 199 additions and 198 deletions
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19
hw/rtl/fp_cores/VX_fp_addmul.v
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@@ -168,9 +168,9 @@ module VX_fp_addmul #(
fmul_h = dpi_register();
end
always @(posedge clk) begin
dpi_fadd(fadd_h, enable, dataa[i], datab[i], result_add);
dpi_fsub(fsub_h, enable, dataa[i], datab[i], result_sub);
dpi_fmul(fmul_h, enable, dataa[i], datab[i], result_mul);
dpi_fadd (fadd_h, enable, dataa[i], datab[i], result_add);
dpi_fsub (fsub_h, enable, dataa[i], datab[i], result_sub);
dpi_fmul (fmul_h, enable, dataa[i], datab[i], result_mul);
end
`endif
@@ -178,14 +178,15 @@ module VX_fp_addmul #(
end
VX_shift_register #(
.DATAW(1 + TAGW + 1 + 1),
.DEPTH(`LATENCY_FADDMUL)
.DATAW (1 + TAGW + 1 + 1),
.DEPTH (`LATENCY_FADDMUL),
.RESETW (1)
) shift_reg (
.clk(clk),
.reset(reset),
.enable(enable),
.data_in({valid_in, tag_in, do_sub, do_mul}),
.data_out({valid_out, tag_out, do_sub_r, do_mul_r})
.reset (reset),
.enable (enable),
.data_in ({valid_in, tag_in, do_sub, do_mul}),
.data_out ({valid_out, tag_out, do_sub_r, do_mul_r})
);
assign ready_in = enable;

17
hw/rtl/fp_cores/VX_fp_div.v
View File

@@ -44,20 +44,21 @@ module VX_fp_div #(
fdiv_h = dpi_register();
end
always @(posedge clk) begin
dpi_fdiv(fdiv_h, enable, dataa[i], datab[i], result[i]);
dpi_fdiv (fdiv_h, enable, dataa[i], datab[i], result[i]);
end
`endif
end
VX_shift_register #(
.DATAW(1 + TAGW),
.DEPTH(`LATENCY_FDIV)
.DATAW (1 + TAGW),
.DEPTH (`LATENCY_FDIV),
.RESETW (1)
) shift_reg (
.clk(clk),
.reset(reset),
.enable(enable),
.data_in ({valid_in, tag_in}),
.data_out({valid_out, tag_out})
.clk (clk),
.reset (reset),
.enable (enable),
.data_in ({valid_in, tag_in}),
.data_out ({valid_out, tag_out})
);
assign ready_in = enable;

19
hw/rtl/fp_cores/VX_fp_ftoi.v
View File

@@ -59,8 +59,8 @@ module VX_fp_ftoi #(
ftou_h = dpi_register();
end
always @(posedge clk) begin
dpi_ftoi(ftoi_h, enable, dataa[i], result_s);
dpi_ftou(ftou_h, enable, dataa[i], result_u);
dpi_ftoi (ftoi_h, enable, dataa[i], result_s);
dpi_ftou (ftou_h, enable, dataa[i], result_u);
end
`endif
@@ -68,14 +68,15 @@ module VX_fp_ftoi #(
end
VX_shift_register #(
.DATAW(1 + TAGW + 1),
.DEPTH(`LATENCY_FTOI)
.DATAW (1 + TAGW + 1),
.DEPTH (`LATENCY_FTOI),
.RESETW (1)
) shift_reg (
.clk(clk),
.reset(reset),
.enable(enable),
.data_in ({valid_in, tag_in, is_signed}),
.data_out({valid_out, tag_out, is_signed_r})
.clk (clk),
.reset (reset),
.enable (enable),
.data_in ({valid_in, tag_in, is_signed}),
.data_out ({valid_out, tag_out, is_signed_r})
);
assign ready_in = enable;

19
hw/rtl/fp_cores/VX_fp_itof.v
View File

@@ -59,8 +59,8 @@ module VX_fp_itof #(
utof_h = dpi_register();
end
always @(posedge clk) begin
dpi_itof(itof_h, enable, dataa[i], result_s);
dpi_utof(utof_h, enable, dataa[i], result_u);
dpi_itof (itof_h, enable, dataa[i], result_s);
dpi_utof (utof_h, enable, dataa[i], result_u);
end
`endif
@@ -68,14 +68,15 @@ module VX_fp_itof #(
end
VX_shift_register #(
.DATAW(1 + TAGW + 1),
.DEPTH(`LATENCY_ITOF)
.DATAW (1 + TAGW + 1),
.DEPTH (`LATENCY_ITOF),
.RESETW (1)
) shift_reg (
.clk(clk),
.reset(reset),
.enable(enable),
.data_in ({valid_in, tag_in, is_signed}),
.data_out({valid_out, tag_out, is_signed_r})
.clk (clk),
.reset (reset),
.enable (enable),
.data_in ({valid_in, tag_in, is_signed}),
.data_out ({valid_out, tag_out, is_signed_r})
);
assign ready_in = enable;

17
hw/rtl/fp_cores/VX_fp_madd.v
View File

@@ -127,8 +127,8 @@ module VX_fp_madd #(
fmsub_h = dpi_register();
end
always @(posedge clk) begin
dpi_fmadd(fmadd_h, enable, dataa[i], datab[i], datac[i], result_madd);
dpi_fmsub(fmsub_h, enable, dataa[i], datab[i], datac[i], result_msub);
dpi_fmadd (fmadd_h, enable, dataa[i], datab[i], datac[i], result_madd);
dpi_fmsub (fmsub_h, enable, dataa[i], datab[i], datac[i], result_msub);
end
`endif
@@ -138,14 +138,15 @@ module VX_fp_madd #(
end
VX_shift_register #(
.DATAW(1 + TAGW + 1 + 1),
.DEPTH(`LATENCY_FMADD)
.DATAW (1 + TAGW + 1 + 1),
.DEPTH (`LATENCY_FMADD),
.RESETW (1)
) shift_reg (
.clk(clk),
.reset(reset),
.enable(enable),
.data_in({valid_in, tag_in, do_sub, do_neg}),
.data_out({valid_out, tag_out, do_sub_r, do_neg_r})
.reset (reset),
.enable (enable),
.data_in ({valid_in, tag_in, do_sub, do_neg}),
.data_out ({valid_out, tag_out, do_sub_r, do_neg_r})
);
assign ready_in = enable;

17
hw/rtl/fp_cores/VX_fp_sqrt.v
View File

@@ -42,20 +42,21 @@ module VX_fp_sqrt #(
fsqrt_h = dpi_register();
end
always @(posedge clk) begin
dpi_fsqrt(fsqrt_h, enable, dataa[i], result[i]);
dpi_fsqrt (fsqrt_h, enable, dataa[i], result[i]);
end
`endif
end
VX_shift_register #(
.DATAW(1 + TAGW),
.DEPTH(`LATENCY_FSQRT)
.DATAW (1 + TAGW),
.DEPTH (`LATENCY_FSQRT),
.RESETW (1)
) shift_reg (
.clk(clk),
.reset(reset),
.enable(enable),
.data_in ({valid_in, tag_in}),
.data_out({valid_out, tag_out})
.clk (clk),
.reset (reset),
.enable (enable),
.data_in ({valid_in, tag_in}),
.data_out ({valid_out, tag_out})
);
assign ready_in = enable;