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data/dram bus refactoring

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This commit is contained in:
Blaise Tine
2020-12-06 03:37:22 -08:00
parent d0f2a3984d
commit b2652527bb
9 changed files with 624 additions and 573 deletions
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372
hw/rtl/VX_cluster.v
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@@ -68,31 +68,18 @@ module VX_cluster #(
output wire busy,
output wire ebreak
);
wire [`NUM_CORES-1:0] per_core_D_dram_req_valid;
wire [`NUM_CORES-1:0] per_core_D_dram_req_rw;
wire [`NUM_CORES-1:0][`DDRAM_BYTEEN_WIDTH-1:0] per_core_D_dram_req_byteen;
wire [`NUM_CORES-1:0][`DDRAM_ADDR_WIDTH-1:0] per_core_D_dram_req_addr;
wire [`NUM_CORES-1:0][`DDRAM_LINE_WIDTH-1:0] per_core_D_dram_req_data;
wire [`NUM_CORES-1:0][`DDRAM_TAG_WIDTH-1:0] per_core_D_dram_req_tag;
wire [`NUM_CORES-1:0] per_core_D_dram_req_ready;
wire [`NUM_CORES-1:0] per_core_dram_req_valid;
wire [`NUM_CORES-1:0] per_core_dram_req_rw;
wire [`NUM_CORES-1:0][`DDRAM_BYTEEN_WIDTH-1:0] per_core_dram_req_byteen;
wire [`NUM_CORES-1:0][`DDRAM_ADDR_WIDTH-1:0] per_core_dram_req_addr;
wire [`NUM_CORES-1:0][`DDRAM_LINE_WIDTH-1:0] per_core_dram_req_data;
wire [`NUM_CORES-1:0][`XDRAM_TAG_WIDTH-1:0] per_core_dram_req_tag;
wire [`NUM_CORES-1:0] per_core_dram_req_ready;
wire [`NUM_CORES-1:0] per_core_D_dram_rsp_valid;
wire [`NUM_CORES-1:0][`DDRAM_LINE_WIDTH-1:0] per_core_D_dram_rsp_data;
wire [`NUM_CORES-1:0][`DDRAM_TAG_WIDTH-1:0] per_core_D_dram_rsp_tag;
wire [`NUM_CORES-1:0] per_core_D_dram_rsp_ready;
wire [`NUM_CORES-1:0] per_core_I_dram_req_valid;
wire [`NUM_CORES-1:0] per_core_I_dram_req_rw;
wire [`NUM_CORES-1:0][`IDRAM_BYTEEN_WIDTH-1:0] per_core_I_dram_req_byteen;
wire [`NUM_CORES-1:0][`IDRAM_ADDR_WIDTH-1:0] per_core_I_dram_req_addr;
wire [`NUM_CORES-1:0][`IDRAM_LINE_WIDTH-1:0] per_core_I_dram_req_data;
wire [`NUM_CORES-1:0][`IDRAM_TAG_WIDTH-1:0] per_core_I_dram_req_tag;
wire [`NUM_CORES-1:0] per_core_I_dram_req_ready;
wire [`NUM_CORES-1:0] per_core_I_dram_rsp_valid;
wire [`NUM_CORES-1:0][`IDRAM_LINE_WIDTH-1:0] per_core_I_dram_rsp_data;
wire [`NUM_CORES-1:0][`IDRAM_TAG_WIDTH-1:0] per_core_I_dram_rsp_tag;
wire [`NUM_CORES-1:0] per_core_I_dram_rsp_ready;
wire [`NUM_CORES-1:0] per_core_dram_rsp_valid;
wire [`NUM_CORES-1:0][`DDRAM_LINE_WIDTH-1:0] per_core_dram_rsp_data;
wire [`NUM_CORES-1:0][`XDRAM_TAG_WIDTH-1:0] per_core_dram_rsp_tag;
wire [`NUM_CORES-1:0] per_core_dram_rsp_ready;
wire [`NUM_CORES-1:0] per_core_snp_req_valid;
wire [`NUM_CORES-1:0][`DDRAM_ADDR_WIDTH-1:0] per_core_snp_req_addr;
@@ -139,69 +126,58 @@ module VX_cluster #(
.clk (clk),
.reset (reset),
.D_dram_req_valid (per_core_D_dram_req_valid [i]),
.D_dram_req_rw (per_core_D_dram_req_rw [i]),
.D_dram_req_byteen (per_core_D_dram_req_byteen [i]),
.D_dram_req_addr (per_core_D_dram_req_addr [i]),
.D_dram_req_data (per_core_D_dram_req_data [i]),
.D_dram_req_tag (per_core_D_dram_req_tag [i]),
.D_dram_req_ready (per_core_D_dram_req_ready [i]),
.D_dram_rsp_valid (per_core_D_dram_rsp_valid [i]),
.D_dram_rsp_data (per_core_D_dram_rsp_data [i]),
.D_dram_rsp_tag (per_core_D_dram_rsp_tag [i]),
.D_dram_rsp_ready (per_core_D_dram_rsp_ready [i]),
.dram_req_valid (per_core_dram_req_valid [i]),
.dram_req_rw (per_core_dram_req_rw [i]),
.dram_req_byteen (per_core_dram_req_byteen [i]),
.dram_req_addr (per_core_dram_req_addr [i]),
.dram_req_data (per_core_dram_req_data [i]),
.dram_req_tag (per_core_dram_req_tag [i]),
.dram_req_ready (per_core_dram_req_ready [i]),
.dram_rsp_valid (per_core_dram_rsp_valid [i]),
.dram_rsp_data (per_core_dram_rsp_data [i]),
.dram_rsp_tag (per_core_dram_rsp_tag [i]),
.dram_rsp_ready (per_core_dram_rsp_ready [i]),
.I_dram_req_valid (per_core_I_dram_req_valid [i]),
.I_dram_req_rw (per_core_I_dram_req_rw [i]),
.I_dram_req_byteen (per_core_I_dram_req_byteen [i]),
.I_dram_req_addr (per_core_I_dram_req_addr [i]),
.I_dram_req_data (per_core_I_dram_req_data [i]),
.I_dram_req_tag (per_core_I_dram_req_tag [i]),
.I_dram_req_ready (per_core_I_dram_req_ready [i]),
.I_dram_rsp_valid (per_core_I_dram_rsp_valid [i]),
.I_dram_rsp_tag (per_core_I_dram_rsp_tag [i]),
.I_dram_rsp_data (per_core_I_dram_rsp_data [i]),
.I_dram_rsp_ready (per_core_I_dram_rsp_ready [i]),
.snp_req_valid (per_core_snp_req_valid [i]),
.snp_req_addr (per_core_snp_req_addr [i]),
.snp_req_inv (per_core_snp_req_inv [i]),
.snp_req_tag (per_core_snp_req_tag [i]),
.snp_req_ready (per_core_snp_req_ready [i]),
.snp_req_valid (per_core_snp_req_valid [i]),
.snp_req_addr (per_core_snp_req_addr [i]),
.snp_req_inv (per_core_snp_req_inv [i]),
.snp_req_tag (per_core_snp_req_tag [i]),
.snp_req_ready (per_core_snp_req_ready [i]),
.snp_rsp_valid (per_core_snp_rsp_valid [i]),
.snp_rsp_tag (per_core_snp_rsp_tag [i]),
.snp_rsp_ready (per_core_snp_rsp_ready [i]),
.snp_rsp_valid (per_core_snp_rsp_valid [i]),
.snp_rsp_tag (per_core_snp_rsp_tag [i]),
.snp_rsp_ready (per_core_snp_rsp_ready [i]),
.io_req_valid (per_core_io_req_valid [i]),
.io_req_rw (per_core_io_req_rw [i]),
.io_req_byteen (per_core_io_req_byteen [i]),
.io_req_addr (per_core_io_req_addr [i]),
.io_req_data (per_core_io_req_data [i]),
.io_req_tag (per_core_io_req_tag [i]),
.io_req_ready (per_core_io_req_ready [i]),
.io_req_valid (per_core_io_req_valid [i]),
.io_req_rw (per_core_io_req_rw [i]),
.io_req_byteen (per_core_io_req_byteen [i]),
.io_req_addr (per_core_io_req_addr [i]),
.io_req_data (per_core_io_req_data [i]),
.io_req_tag (per_core_io_req_tag [i]),
.io_req_ready (per_core_io_req_ready [i]),
.io_rsp_valid (per_core_io_rsp_valid [i]),
.io_rsp_data (per_core_io_rsp_data [i]),
.io_rsp_tag (per_core_io_rsp_tag [i]),
.io_rsp_ready (per_core_io_rsp_ready [i]),
.io_rsp_valid (per_core_io_rsp_valid [i]),
.io_rsp_data (per_core_io_rsp_data [i]),
.io_rsp_tag (per_core_io_rsp_tag [i]),
.io_rsp_ready (per_core_io_rsp_ready [i]),
.csr_io_req_valid (per_core_csr_io_req_valid[i]),
.csr_io_req_rw (per_core_csr_io_req_rw [i]),
.csr_io_req_addr (per_core_csr_io_req_addr [i]),
.csr_io_req_data (per_core_csr_io_req_data [i]),
.csr_io_req_ready (per_core_csr_io_req_ready[i]),
.csr_io_req_valid (per_core_csr_io_req_valid [i]),
.csr_io_req_rw (per_core_csr_io_req_rw [i]),
.csr_io_req_addr (per_core_csr_io_req_addr [i]),
.csr_io_req_data (per_core_csr_io_req_data [i]),
.csr_io_req_ready (per_core_csr_io_req_ready [i]),
.csr_io_rsp_valid (per_core_csr_io_rsp_valid[i]),
.csr_io_rsp_data (per_core_csr_io_rsp_data [i]),
.csr_io_rsp_ready (per_core_csr_io_rsp_ready[i]),
.csr_io_rsp_valid (per_core_csr_io_rsp_valid [i]),
.csr_io_rsp_data (per_core_csr_io_rsp_data [i]),
.csr_io_rsp_ready (per_core_csr_io_rsp_ready [i]),
.busy (per_core_busy [i]),
.ebreak (per_core_ebreak [i])
.busy (per_core_busy [i]),
.ebreak (per_core_ebreak [i])
);
end
VX_io_arb #(
VX_databus_arb #(
.NUM_REQS (`NUM_CORES),
.WORD_SIZE (4),
.TAG_IN_WIDTH (`DCORE_TAG_WIDTH),
@@ -283,102 +259,76 @@ module VX_cluster #(
// L2 Cache ///////////////////////////////////////////////////////////
wire[`L2NUM_REQUESTS-1:0] core_dram_req_valid;
wire[`L2NUM_REQUESTS-1:0] core_dram_req_rw;
wire[`L2NUM_REQUESTS-1:0][`DDRAM_BYTEEN_WIDTH-1:0] core_dram_req_byteen;
wire[`L2NUM_REQUESTS-1:0][`DDRAM_ADDR_WIDTH-1:0] core_dram_req_addr;
wire[`L2NUM_REQUESTS-1:0][`DDRAM_TAG_WIDTH-1:0] core_dram_req_tag;
wire[`L2NUM_REQUESTS-1:0][`DDRAM_LINE_WIDTH-1:0] core_dram_req_data;
wire core_dram_req_ready;
wire [`NUM_CORES-1:0] core_dram_req_valid;
wire [`NUM_CORES-1:0] core_dram_req_rw;
wire [`NUM_CORES-1:0][`DDRAM_BYTEEN_WIDTH-1:0] core_dram_req_byteen;
wire [`NUM_CORES-1:0][`DDRAM_ADDR_WIDTH-1:0] core_dram_req_addr;
wire [`NUM_CORES-1:0][`XDRAM_TAG_WIDTH-1:0] core_dram_req_tag;
wire [`NUM_CORES-1:0][`DDRAM_LINE_WIDTH-1:0] core_dram_req_data;
wire core_dram_req_ready;
wire[`L2NUM_REQUESTS-1:0] core_dram_rsp_valid;
wire[`L2NUM_REQUESTS-1:0][`DDRAM_LINE_WIDTH-1:0] core_dram_rsp_data;
wire[`L2NUM_REQUESTS-1:0][`DDRAM_TAG_WIDTH-1:0] core_dram_rsp_tag;
wire core_dram_rsp_ready;
wire [`NUM_CORES-1:0] core_dram_rsp_valid;
wire [`NUM_CORES-1:0][`DDRAM_LINE_WIDTH-1:0] core_dram_rsp_data;
wire [`NUM_CORES-1:0][`XDRAM_TAG_WIDTH-1:0] core_dram_rsp_tag;
wire core_dram_rsp_ready;
wire[`NUM_CORES-1:0] core_snp_fwdout_valid;
wire[`NUM_CORES-1:0][`DDRAM_ADDR_WIDTH-1:0] core_snp_fwdout_addr;
wire[`NUM_CORES-1:0] core_snp_fwdout_inv;
wire[`NUM_CORES-1:0][`DSNP_TAG_WIDTH-1:0] core_snp_fwdout_tag;
wire[`NUM_CORES-1:0] core_snp_fwdout_ready;
wire [`NUM_CORES-1:0] core_snp_fwdout_valid;
wire [`NUM_CORES-1:0][`DDRAM_ADDR_WIDTH-1:0] core_snp_fwdout_addr;
wire [`NUM_CORES-1:0] core_snp_fwdout_inv;
wire [`NUM_CORES-1:0][`DSNP_TAG_WIDTH-1:0] core_snp_fwdout_tag;
wire [`NUM_CORES-1:0] core_snp_fwdout_ready;
wire[`NUM_CORES-1:0] core_snp_fwdin_valid;
wire[`NUM_CORES-1:0][`DSNP_TAG_WIDTH-1:0] core_snp_fwdin_tag;
wire[`NUM_CORES-1:0] core_snp_fwdin_ready;
wire [`NUM_CORES-1:0] core_snp_fwdin_valid;
wire [`NUM_CORES-1:0][`DSNP_TAG_WIDTH-1:0] core_snp_fwdin_tag;
wire [`NUM_CORES-1:0] core_snp_fwdin_ready;
wire snp_fwd_rsp_valid;
wire [`L2DRAM_ADDR_WIDTH-1:0] snp_fwd_rsp_addr;
wire snp_fwd_rsp_inv;
wire [`L2SNP_TAG_WIDTH-1:0] snp_fwd_rsp_tag;
wire snp_fwd_rsp_ready;
wire snp_fwd_rsp_valid;
wire [`L2DRAM_ADDR_WIDTH-1:0] snp_fwd_rsp_addr;
wire snp_fwd_rsp_inv;
wire [`L2SNP_TAG_WIDTH-1:0] snp_fwd_rsp_tag;
wire snp_fwd_rsp_ready;
reg [`L2NUM_REQUESTS-1:0] core_dram_rsp_ready_other;
reg core_dram_rsp_ready_all;
for (genvar i = 0; i < `NUM_CORES; i++) begin
assign core_dram_req_valid [i] = per_core_dram_req_valid [i];
assign core_dram_req_rw [i] = per_core_dram_req_rw [i];
assign core_dram_req_byteen [i] = per_core_dram_req_byteen [i];
assign core_dram_req_addr [i] = per_core_dram_req_addr [i];
assign core_dram_req_data [i] = per_core_dram_req_data [i];
assign core_dram_req_tag [i] = per_core_dram_req_tag [i];
assign per_core_dram_req_ready [i] = core_dram_req_ready;
end
reg [`NUM_CORES-1:0] core_dram_rsp_ready_other;
always @(*) begin
core_dram_rsp_ready_other = {`L2NUM_REQUESTS{1'b1}};
core_dram_rsp_ready_all = 1'b1;
for (integer i = 0; i < `L2NUM_REQUESTS; i++) begin
for (integer j = 0; j < `L2NUM_REQUESTS; j++) begin
core_dram_rsp_ready_other = {`NUM_CORES{1'b1}};
for (integer i = 0; i < `NUM_CORES; i++) begin
for (integer j = 0; j < `NUM_CORES; j++) begin
if (i != j) begin
if (0 == (j & 1))
core_dram_rsp_ready_other[i] &= (per_core_D_dram_rsp_ready [(j/2)] | !core_dram_rsp_valid [j]);
else
core_dram_rsp_ready_other[i] &= (per_core_I_dram_rsp_ready [(j/2)] | !core_dram_rsp_valid [j]);
core_dram_rsp_ready_other[i] &= (per_core_dram_rsp_ready [j] | !core_dram_rsp_valid [j]);
end
end
if (0 == (i & 1))
core_dram_rsp_ready_all &= (per_core_D_dram_rsp_ready [(i/2)] | !core_dram_rsp_valid [i]);
else
core_dram_rsp_ready_all &= (per_core_I_dram_rsp_ready [(i/2)] | !core_dram_rsp_valid [i]);
end
end
for (genvar i = 0; i < `L2NUM_REQUESTS; i = i + 2) begin
assign core_dram_req_valid [i] = per_core_D_dram_req_valid [(i/2)];
assign core_dram_req_valid [i+1] = per_core_I_dram_req_valid [(i/2)];
assign core_dram_req_rw [i] = per_core_D_dram_req_rw [(i/2)];
assign core_dram_req_rw [i+1] = per_core_I_dram_req_rw [(i/2)];
assign core_dram_req_byteen [i] = per_core_D_dram_req_byteen [(i/2)];
assign core_dram_req_byteen [i+1] = per_core_I_dram_req_byteen [(i/2)];
assign core_dram_req_addr [i] = per_core_D_dram_req_addr [(i/2)];
assign core_dram_req_addr [i+1] = per_core_I_dram_req_addr [(i/2)];
assign core_dram_req_data [i] = per_core_D_dram_req_data [(i/2)];
assign core_dram_req_data [i+1] = per_core_I_dram_req_data [(i/2)];
assign core_dram_req_tag [i] = per_core_D_dram_req_tag [(i/2)];
assign core_dram_req_tag [i+1] = per_core_I_dram_req_tag [(i/2)];
assign per_core_D_dram_req_ready [(i/2)] = core_dram_req_ready;
assign per_core_I_dram_req_ready [(i/2)] = core_dram_req_ready;
assign per_core_D_dram_rsp_valid [(i/2)] = core_dram_rsp_valid[i] & core_dram_rsp_ready_other [i];
assign per_core_I_dram_rsp_valid [(i/2)] = core_dram_rsp_valid[i+1] & core_dram_rsp_ready_other [i+1];
assign per_core_D_dram_rsp_data [(i/2)] = core_dram_rsp_data[i];
assign per_core_I_dram_rsp_data [(i/2)] = core_dram_rsp_data[i+1];
assign per_core_D_dram_rsp_tag [(i/2)] = core_dram_rsp_tag[i];
assign per_core_I_dram_rsp_tag [(i/2)] = core_dram_rsp_tag[i+1];
assign per_core_snp_req_valid [(i/2)] = core_snp_fwdout_valid [(i/2)];
assign per_core_snp_req_addr [(i/2)] = core_snp_fwdout_addr [(i/2)];
assign per_core_snp_req_inv [(i/2)] = core_snp_fwdout_inv [(i/2)];
assign per_core_snp_req_tag [(i/2)] = core_snp_fwdout_tag [(i/2)];
assign core_snp_fwdout_ready [(i/2)] = per_core_snp_req_ready[(i/2)];
assign core_snp_fwdin_valid [(i/2)] = per_core_snp_rsp_valid [(i/2)];
assign core_snp_fwdin_tag [(i/2)] = per_core_snp_rsp_tag [(i/2)];
assign per_core_snp_rsp_ready [(i/2)] = core_snp_fwdin_ready [(i/2)];
for (genvar i = 0; i < `NUM_CORES; i++) begin
assign per_core_dram_rsp_valid [i] = core_dram_rsp_valid[i] & core_dram_rsp_ready_other [i];
assign per_core_dram_rsp_data [i] = core_dram_rsp_data[i];
assign per_core_dram_rsp_tag [i] = core_dram_rsp_tag[i];
end
assign core_dram_rsp_ready = & (per_core_dram_rsp_ready | ~core_dram_rsp_valid);
assign core_dram_rsp_ready = core_dram_rsp_ready_all;
for (genvar i = 0; i < `NUM_CORES; i++) begin
assign per_core_snp_req_valid [i] = core_snp_fwdout_valid [i];
assign per_core_snp_req_addr [i] = core_snp_fwdout_addr [i];
assign per_core_snp_req_inv [i] = core_snp_fwdout_inv [i];
assign per_core_snp_req_tag [i] = core_snp_fwdout_tag [i];
assign core_snp_fwdout_ready [i] = per_core_snp_req_ready[i];
assign core_snp_fwdin_valid [i] = per_core_snp_rsp_valid [i];
assign core_snp_fwdin_tag [i] = per_core_snp_rsp_tag [i];
assign per_core_snp_rsp_ready [i] = core_snp_fwdin_ready [i];
end
VX_snp_forwarder #(
.CACHE_ID (`L2CACHE_ID),
@@ -420,7 +370,7 @@ module VX_cluster #(
.BANK_LINE_SIZE (`L2BANK_LINE_SIZE),
.NUM_BANKS (`L2NUM_BANKS),
.WORD_SIZE (`L2WORD_SIZE),
.NUM_REQS (`L2NUM_REQUESTS),
.NUM_REQS (`NUM_CORES),
.CREQ_SIZE (`L2CREQ_SIZE),
.MSHR_SIZE (`L2MSHR_SIZE),
.DRFQ_SIZE (`L2DRFQ_SIZE),
@@ -431,7 +381,7 @@ module VX_cluster #(
.DRAM_ENABLE (1),
.FLUSH_ENABLE (1),
.WRITE_ENABLE (1),
.CORE_TAG_WIDTH (`DDRAM_TAG_WIDTH),
.CORE_TAG_WIDTH (`XDRAM_TAG_WIDTH),
.CORE_TAG_ID_BITS (0),
.DRAM_TAG_WIDTH (`L2DRAM_TAG_WIDTH),
.SNP_TAG_WIDTH (`L2SNP_TAG_WIDTH)
@@ -489,72 +439,52 @@ module VX_cluster #(
end else begin
wire[`L2NUM_REQUESTS-1:0] core_dram_req_valid;
wire[`L2NUM_REQUESTS-1:0] core_dram_req_rw;
wire[`L2NUM_REQUESTS-1:0][`DDRAM_BYTEEN_WIDTH-1:0] core_dram_req_byteen;
wire[`L2NUM_REQUESTS-1:0][`DDRAM_ADDR_WIDTH-1:0] core_dram_req_addr;
wire[`L2NUM_REQUESTS-1:0][`DDRAM_TAG_WIDTH-1:0] core_dram_req_tag;
wire[`L2NUM_REQUESTS-1:0][`DDRAM_LINE_WIDTH-1:0] core_dram_req_data;
wire[`L2NUM_REQUESTS-1:0] core_dram_req_ready;
wire[`NUM_CORES-1:0] core_dram_req_valid;
wire[`NUM_CORES-1:0] core_dram_req_rw;
wire[`NUM_CORES-1:0][`DDRAM_BYTEEN_WIDTH-1:0] core_dram_req_byteen;
wire[`NUM_CORES-1:0][`DDRAM_ADDR_WIDTH-1:0] core_dram_req_addr;
wire[`NUM_CORES-1:0][`XDRAM_TAG_WIDTH-1:0] core_dram_req_tag;
wire[`NUM_CORES-1:0][`DDRAM_LINE_WIDTH-1:0] core_dram_req_data;
wire[`NUM_CORES-1:0] core_dram_req_ready;
wire[`L2NUM_REQUESTS-1:0] core_dram_rsp_valid;
wire[`L2NUM_REQUESTS-1:0][`DDRAM_LINE_WIDTH-1:0] core_dram_rsp_data;
wire[`L2NUM_REQUESTS-1:0][`DDRAM_TAG_WIDTH-1:0] core_dram_rsp_tag;
wire[`L2NUM_REQUESTS-1:0] core_dram_rsp_ready;
wire[`NUM_CORES-1:0] core_dram_rsp_valid;
wire[`NUM_CORES-1:0][`DDRAM_LINE_WIDTH-1:0] core_dram_rsp_data;
wire[`NUM_CORES-1:0][`XDRAM_TAG_WIDTH-1:0] core_dram_rsp_tag;
wire[`NUM_CORES-1:0] core_dram_rsp_ready;
wire[`NUM_CORES-1:0] core_snp_fwdout_valid;
wire[`NUM_CORES-1:0][`DDRAM_ADDR_WIDTH-1:0] core_snp_fwdout_addr;
wire[`NUM_CORES-1:0] core_snp_fwdout_inv;
wire[`NUM_CORES-1:0][`DSNP_TAG_WIDTH-1:0] core_snp_fwdout_tag;
wire[`NUM_CORES-1:0] core_snp_fwdout_ready;
wire[`NUM_CORES-1:0] core_snp_fwdout_valid;
wire[`NUM_CORES-1:0][`DDRAM_ADDR_WIDTH-1:0] core_snp_fwdout_addr;
wire[`NUM_CORES-1:0] core_snp_fwdout_inv;
wire[`NUM_CORES-1:0][`DSNP_TAG_WIDTH-1:0] core_snp_fwdout_tag;
wire[`NUM_CORES-1:0] core_snp_fwdout_ready;
wire[`NUM_CORES-1:0] core_snp_fwdin_valid;
wire[`NUM_CORES-1:0][`DSNP_TAG_WIDTH-1:0] core_snp_fwdin_tag;
wire[`NUM_CORES-1:0] core_snp_fwdin_ready;
wire[`NUM_CORES-1:0] core_snp_fwdin_valid;
wire[`NUM_CORES-1:0][`DSNP_TAG_WIDTH-1:0] core_snp_fwdin_tag;
wire[`NUM_CORES-1:0] core_snp_fwdin_ready;
for (genvar i = 0; i < `L2NUM_REQUESTS; i = i + 2) begin
assign core_dram_req_valid [i] = per_core_D_dram_req_valid[(i/2)];
assign core_dram_req_valid [i+1] = per_core_I_dram_req_valid[(i/2)];
for (genvar i = 0; i < `NUM_CORES; i++) begin
assign core_dram_req_valid [i] = per_core_dram_req_valid [i];
assign core_dram_req_rw [i] = per_core_dram_req_rw [i];
assign core_dram_req_byteen [i] = per_core_dram_req_byteen [i];
assign core_dram_req_addr [i] = per_core_dram_req_addr [i];
assign core_dram_req_data [i] = per_core_dram_req_data [i];
assign core_dram_req_tag [i] = per_core_dram_req_tag [i];
assign per_core_dram_req_ready [i] = core_dram_req_ready [i];
assign core_dram_req_rw [i] = per_core_D_dram_req_rw[(i/2)];
assign core_dram_req_rw [i+1] = per_core_I_dram_req_rw[(i/2)];
assign per_core_dram_rsp_valid [i] = core_dram_rsp_valid [i];
assign per_core_dram_rsp_data [i] = core_dram_rsp_data [i];
assign per_core_dram_rsp_tag [i] = core_dram_rsp_tag [i];
assign core_dram_rsp_ready [i] = per_core_dram_rsp_ready [i];
assign core_dram_req_byteen[i] = per_core_D_dram_req_byteen[(i/2)];
assign core_dram_req_byteen[i+1] = per_core_I_dram_req_byteen[(i/2)];
assign per_core_snp_req_valid [i] = core_snp_fwdout_valid [i];
assign per_core_snp_req_addr [i] = core_snp_fwdout_addr [i];
assign per_core_snp_req_inv [i] = core_snp_fwdout_inv [i];
assign per_core_snp_req_tag [i] = core_snp_fwdout_tag [i];
assign core_snp_fwdout_ready [i] = per_core_snp_req_ready [i];
assign core_dram_req_addr [i] = per_core_D_dram_req_addr[(i/2)];
assign core_dram_req_addr [i+1] = per_core_I_dram_req_addr[(i/2)];
assign core_dram_req_data [i] = per_core_D_dram_req_data[(i/2)];
assign core_dram_req_data [i+1] = per_core_I_dram_req_data[(i/2)];
assign core_dram_req_tag [i] = per_core_D_dram_req_tag[(i/2)];
assign core_dram_req_tag [i+1] = per_core_I_dram_req_tag[(i/2)];
assign per_core_D_dram_req_ready [(i/2)] = core_dram_req_ready[i];
assign per_core_I_dram_req_ready [(i/2)] = core_dram_req_ready[i+1];
assign per_core_D_dram_rsp_valid [(i/2)] = core_dram_rsp_valid[i];
assign per_core_I_dram_rsp_valid [(i/2)] = core_dram_rsp_valid[i+1];
assign per_core_D_dram_rsp_data [(i/2)] = core_dram_rsp_data[i];
assign per_core_I_dram_rsp_data [(i/2)] = core_dram_rsp_data[i+1];
assign per_core_D_dram_rsp_tag [(i/2)] = core_dram_rsp_tag[i];
assign per_core_I_dram_rsp_tag [(i/2)] = core_dram_rsp_tag[i+1];
assign core_dram_rsp_ready [i] = per_core_D_dram_rsp_ready[(i/2)];
assign core_dram_rsp_ready [i+1] = per_core_I_dram_rsp_ready[(i/2)];
assign per_core_snp_req_valid [(i/2)] = core_snp_fwdout_valid [(i/2)];
assign per_core_snp_req_addr [(i/2)] = core_snp_fwdout_addr [(i/2)];
assign per_core_snp_req_inv [(i/2)] = core_snp_fwdout_inv [(i/2)];
assign per_core_snp_req_tag [(i/2)] = core_snp_fwdout_tag [(i/2)];
assign core_snp_fwdout_ready [(i/2)] = per_core_snp_req_ready[(i/2)];
assign core_snp_fwdin_valid [(i/2)] = per_core_snp_rsp_valid [(i/2)];
assign core_snp_fwdin_tag [(i/2)] = per_core_snp_rsp_tag [(i/2)];
assign per_core_snp_rsp_ready [(i/2)] = core_snp_fwdin_ready [(i/2)];
assign core_snp_fwdin_valid [i] = per_core_snp_rsp_valid [i];
assign core_snp_fwdin_tag [i] = per_core_snp_rsp_tag [i];
assign per_core_snp_rsp_ready [i] = core_snp_fwdin_ready [i];
end
if (`NUM_CORES > 1) begin
@@ -604,9 +534,9 @@ module VX_cluster #(
end
VX_mem_arb #(
.NUM_REQS (`L2NUM_REQUESTS),
.NUM_REQS (`NUM_CORES),
.DATA_WIDTH (`L2DRAM_LINE_WIDTH),
.TAG_IN_WIDTH (`DDRAM_TAG_WIDTH),
.TAG_IN_WIDTH (`XDRAM_TAG_WIDTH),
.TAG_OUT_WIDTH (`L2DRAM_TAG_WIDTH)
) dram_arb (
.clk (clk),