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tabs cleanup

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This commit is contained in:
Blaise Tine
2020-11-28 17:08:01 -05:00
parent 00d7473268
commit ac1883a13f
21 changed files with 275 additions and 275 deletions
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2
hw/opae/ccip_std_afu.sv
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@@ -113,7 +113,7 @@ module ccip_std_afu #(
.avs_address (avs_address), .avs_address (avs_address),
.avs_waitrequest (avs_waitrequest), .avs_waitrequest (avs_waitrequest),
.avs_write (avs_write), .avs_write (avs_write),
.avs_read (avs_read), .avs_read (avs_read),
.avs_byteenable (avs_byteenable), .avs_byteenable (avs_byteenable),
.avs_burstcount (avs_burstcount), .avs_burstcount (avs_burstcount),
.avs_readdatavalid (avs_readdatavalid), .avs_readdatavalid (avs_readdatavalid),

28
hw/opae/vortex_afu.sv
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@@ -602,7 +602,7 @@ VX_avs_wrapper #(
.avs_address (avs_address), .avs_address (avs_address),
.avs_waitrequest (avs_waitrequest), .avs_waitrequest (avs_waitrequest),
.avs_write (avs_write), .avs_write (avs_write),
.avs_read (avs_read), .avs_read (avs_read),
.avs_byteenable (avs_byteenable), .avs_byteenable (avs_byteenable),
.avs_burstcount (avs_burstcount), .avs_burstcount (avs_burstcount),
.avs_readdatavalid (avs_readdatavalid), .avs_readdatavalid (avs_readdatavalid),
@@ -610,16 +610,16 @@ VX_avs_wrapper #(
// DRAM request // DRAM request
.dram_req_valid (dram_req_valid), .dram_req_valid (dram_req_valid),
.dram_req_rw (dram_req_rw), .dram_req_rw (dram_req_rw),
.dram_req_byteen (dram_req_byteen), .dram_req_byteen (dram_req_byteen),
.dram_req_addr (dram_req_addr), .dram_req_addr (dram_req_addr),
.dram_req_data (dram_req_data), .dram_req_data (dram_req_data),
.dram_req_tag (dram_req_tag), .dram_req_tag (dram_req_tag),
.dram_req_ready (dram_req_ready), .dram_req_ready (dram_req_ready),
// DRAM response // DRAM response
.dram_rsp_valid (dram_rsp_valid), .dram_rsp_valid (dram_rsp_valid),
.dram_rsp_data (dram_rsp_data), .dram_rsp_data (dram_rsp_data),
.dram_rsp_tag (dram_rsp_tag), .dram_rsp_tag (dram_rsp_tag),
.dram_rsp_ready (dram_rsp_ready) .dram_rsp_ready (dram_rsp_ready)
); );
@@ -973,28 +973,28 @@ Vortex #() vortex (
// DRAM request // DRAM request
.dram_req_valid (vx_dram_req_valid), .dram_req_valid (vx_dram_req_valid),
.dram_req_rw (vx_dram_req_rw), .dram_req_rw (vx_dram_req_rw),
.dram_req_byteen (vx_dram_req_byteen), .dram_req_byteen (vx_dram_req_byteen),
.dram_req_addr (vx_dram_req_addr), .dram_req_addr (vx_dram_req_addr),
.dram_req_data (vx_dram_req_data), .dram_req_data (vx_dram_req_data),
.dram_req_tag (vx_dram_req_tag), .dram_req_tag (vx_dram_req_tag),
.dram_req_ready (vx_dram_req_ready), .dram_req_ready (vx_dram_req_ready),
// DRAM response // DRAM response
.dram_rsp_valid (vx_dram_rsp_valid), .dram_rsp_valid (vx_dram_rsp_valid),
.dram_rsp_data (vx_dram_rsp_data), .dram_rsp_data (vx_dram_rsp_data),
.dram_rsp_tag (vx_dram_rsp_tag), .dram_rsp_tag (vx_dram_rsp_tag),
.dram_rsp_ready (vx_dram_rsp_ready), .dram_rsp_ready (vx_dram_rsp_ready),
// Snoop request // Snoop request
.snp_req_valid (vx_snp_req_valid), .snp_req_valid (vx_snp_req_valid),
.snp_req_addr (vx_snp_req_addr), .snp_req_addr (vx_snp_req_addr),
.snp_req_invalidate(vx_snp_req_invalidate), .snp_req_invalidate(vx_snp_req_invalidate),
.snp_req_tag (vx_snp_req_tag), .snp_req_tag (vx_snp_req_tag),
.snp_req_ready (vx_snp_req_ready), .snp_req_ready (vx_snp_req_ready),
// Snoop response // Snoop response
.snp_rsp_valid (vx_snp_rsp_valid), .snp_rsp_valid (vx_snp_rsp_valid),
.snp_rsp_tag (vx_snp_rsp_tag), .snp_rsp_tag (vx_snp_rsp_tag),
.snp_rsp_ready (vx_snp_rsp_ready), .snp_rsp_ready (vx_snp_rsp_ready),
@@ -1027,7 +1027,7 @@ Vortex #() vortex (
.csr_io_rsp_ready (vx_csr_io_rsp_ready), .csr_io_rsp_ready (vx_csr_io_rsp_ready),
// status // status
.busy (vx_busy), .busy (vx_busy),
`UNUSED_PIN (ebreak) `UNUSED_PIN (ebreak)
); );

6
hw/rtl/VX_csr_arb.v
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@@ -19,12 +19,12 @@ module VX_csr_arb (
input wire select_io_rsp input wire select_io_rsp
); );
// requests // requests
assign csr_req_if.valid = (~select_io_req) ? csr_core_req_if.valid : csr_io_req_if.valid; assign csr_req_if.valid = (~select_io_req) ? csr_core_req_if.valid : csr_io_req_if.valid;
assign csr_req_if.wid = (~select_io_req) ? csr_core_req_if.wid : 0; assign csr_req_if.wid = (~select_io_req) ? csr_core_req_if.wid : 0;
assign csr_req_if.tmask = (~select_io_req) ? csr_core_req_if.tmask : 0; assign csr_req_if.tmask = (~select_io_req) ? csr_core_req_if.tmask : 0;
assign csr_req_if.PC = (~select_io_req) ? csr_core_req_if.PC : 0; assign csr_req_if.PC = (~select_io_req) ? csr_core_req_if.PC : 0;
assign csr_req_if.op_type = (~select_io_req) ? csr_core_req_if.op_type : (csr_io_req_if.rw ? `CSR_RW : `CSR_RS); assign csr_req_if.op_type = (~select_io_req) ? csr_core_req_if.op_type : (csr_io_req_if.rw ? `CSR_RW : `CSR_RS);
assign csr_req_if.csr_addr = (~select_io_req) ? csr_core_req_if.csr_addr : csr_io_req_if.addr; assign csr_req_if.csr_addr = (~select_io_req) ? csr_core_req_if.csr_addr : csr_io_req_if.addr;
assign csr_req_if.csr_mask = (~select_io_req) ? csr_core_req_if.csr_mask : (csr_io_req_if.rw ? csr_io_req_if.data : 32'b0); assign csr_req_if.csr_mask = (~select_io_req) ? csr_core_req_if.csr_mask : (csr_io_req_if.rw ? csr_io_req_if.data : 32'b0);
assign csr_req_if.rd = (~select_io_req) ? csr_core_req_if.rd : 0; assign csr_req_if.rd = (~select_io_req) ? csr_core_req_if.rd : 0;
assign csr_req_if.wb = (~select_io_req) ? csr_core_req_if.wb : 0; assign csr_req_if.wb = (~select_io_req) ? csr_core_req_if.wb : 0;

4
hw/rtl/VX_csr_data.v
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@@ -34,8 +34,8 @@ module VX_csr_data #(
reg [63:0] csr_instret; reg [63:0] csr_instret;
reg [`FFG_BITS-1:0] csr_fflags [`NUM_WARPS-1:0]; reg [`FFG_BITS-1:0] csr_fflags [`NUM_WARPS-1:0];
reg [`FRM_BITS-1:0] csr_frm [`NUM_WARPS-1:0]; reg [`FRM_BITS-1:0] csr_frm [`NUM_WARPS-1:0];
reg [`FRM_BITS+`FFG_BITS-1:0] csr_fcsr [`NUM_WARPS-1:0]; // fflags + frm reg [`FRM_BITS+`FFG_BITS-1:0] csr_fcsr [`NUM_WARPS-1:0]; // fflags + frm
reg [31:0] read_data_r; reg [31:0] read_data_r;

12
hw/rtl/VX_fpu_unit.v
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@@ -3,14 +3,14 @@
module VX_fpu_unit #( module VX_fpu_unit #(
parameter CORE_ID = 0 parameter CORE_ID = 0
) ( ) (
// inputs // inputs
input wire clk, input wire clk,
input wire reset, input wire reset,
// inputs // inputs
VX_fpu_req_if fpu_req_if, VX_fpu_req_if fpu_req_if,
// outputs // outputs
VX_fpu_to_csr_if fpu_to_csr_if, VX_fpu_to_csr_if fpu_to_csr_if,
VX_commit_if fpu_commit_if, VX_commit_if fpu_commit_if,

36
hw/rtl/VX_gpr_stage.v
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@@ -38,7 +38,7 @@ module VX_gpr_stage #(
always @(posedge clk) begin always @(posedge clk) begin
if (reset) begin if (reset) begin
rsp_valid <= 0; rsp_valid <= 0;
end else begin end else begin
rsp_valid <= gpr_req_if.valid; rsp_valid <= gpr_req_if.valid;
end end
@@ -47,27 +47,27 @@ module VX_gpr_stage #(
rsp_pc <= gpr_req_if.PC; rsp_pc <= gpr_req_if.PC;
rs1_is_zero <= (0 == gpr_req_if.rs1); rs1_is_zero <= (0 == gpr_req_if.rs1);
rs2_is_zero <= (0 == gpr_req_if.rs2); rs2_is_zero <= (0 == gpr_req_if.rs2);
end end
`ifdef EXT_F_ENABLE `ifdef EXT_F_ENABLE
reg [`NUM_THREADS-1:0][31:0] rs3_data; reg [`NUM_THREADS-1:0][31:0] rs3_data;
reg read_rs3, save_rs3; reg read_rs3, save_rs3;
wire rs3_delay = gpr_req_if.valid && gpr_req_if.use_rs3 && !read_rs3; wire rs3_delay = gpr_req_if.valid && gpr_req_if.use_rs3 && !read_rs3;
wire read_fire = gpr_req_if.valid && gpr_rsp_if.ready; wire read_fire = gpr_req_if.valid && gpr_rsp_if.ready;
always @(posedge clk) begin always @(posedge clk) begin
if (reset) begin if (reset) begin
read_rs3 <= 0; read_rs3 <= 0;
end else begin end else begin
if (rs3_delay) begin if (rs3_delay) begin
read_rs3 <= 1; read_rs3 <= 1;
end else if (read_fire) begin end else if (read_fire) begin
read_rs3 <= 0; read_rs3 <= 0;
end end
assert(!read_rs3 || rsp_wid == gpr_req_if.wid); assert(!read_rs3 || rsp_wid == gpr_req_if.wid);
end end
if (rs3_delay) begin if (rs3_delay) begin
save_rs3 <= 1; save_rs3 <= 1;
@@ -76,11 +76,11 @@ module VX_gpr_stage #(
rs3_data <= rs1_data; rs3_data <= rs1_data;
save_rs3 <= 0; save_rs3 <= 0;
end end
end end
assign raddr1 = {gpr_req_if.wid, (rs3_delay ? gpr_req_if.rs3 : gpr_req_if.rs1)}; assign raddr1 = {gpr_req_if.wid, (rs3_delay ? gpr_req_if.rs3 : gpr_req_if.rs1)};
assign gpr_req_if.ready = ~rs3_delay; assign gpr_req_if.ready = ~rs3_delay;
assign gpr_rsp_if.rs3_data = rs3_data; assign gpr_rsp_if.rs3_data = rs3_data;
`else `else

4
hw/rtl/fp_cores/VX_fp_fpga.v
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@@ -3,8 +3,8 @@
module VX_fp_fpga #( module VX_fp_fpga #(
parameter TAGW = 1 parameter TAGW = 1
) ( ) (
input wire clk, input wire clk,
input wire reset, input wire reset,
input wire valid_in, input wire valid_in,
output wire ready_in, output wire ready_in,

4
hw/rtl/fp_cores/VX_fp_noncomp.v
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@@ -4,8 +4,8 @@ module VX_fp_noncomp #(
parameter TAGW = 1, parameter TAGW = 1,
parameter LANES = 1 parameter LANES = 1
) ( ) (
input wire clk, input wire clk,
input wire reset, input wire reset,
output wire ready_in, output wire ready_in,
input wire valid_in, input wire valid_in,

2
hw/rtl/fp_cores/VX_fp_type.v
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@@ -2,7 +2,7 @@
`include "VX_define.vh" `include "VX_define.vh"
module VX_fp_type ( module VX_fp_type (
// inputs // inputs
input [7:0] exponent, input [7:0] exponent,
input [22:0] mantissa, input [22:0] mantissa,
// outputs // outputs

4
hw/rtl/fp_cores/VX_fpnew.v
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@@ -11,8 +11,8 @@ module VX_fpnew
parameter FNONCOMP = 1, parameter FNONCOMP = 1,
parameter FCONV = 1 parameter FCONV = 1
) ( ) (
input wire clk, input wire clk,
input wire reset, input wire reset,
input wire valid_in, input wire valid_in,
output wire ready_in, output wire ready_in,

10
hw/rtl/interfaces/VX_fpu_to_csr_if.v
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@@ -5,12 +5,12 @@
interface VX_fpu_to_csr_if (); interface VX_fpu_to_csr_if ();
wire write_enable; wire write_enable;
wire [`NW_BITS-1:0] write_wid; wire [`NW_BITS-1:0] write_wid;
fflags_t write_fflags; fflags_t write_fflags;
wire [`NW_BITS-1:0] read_wid; wire [`NW_BITS-1:0] read_wid;
wire [`FRM_BITS-1:0] read_frm; wire [`FRM_BITS-1:0] read_frm;
endinterface endinterface

2
hw/rtl/interfaces/VX_writeback_if.v
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@@ -13,7 +13,7 @@ interface VX_writeback_if ();
wire [31:0] PC; wire [31:0] PC;
`IGNORE_WARNINGS_END `IGNORE_WARNINGS_END
wire [`NR_BITS-1:0] rd; wire [`NR_BITS-1:0] rd;
wire [`NUM_THREADS-1:0][31:0] data; wire [`NUM_THREADS-1:0][31:0] data;
wire ready; wire ready;

2
hw/rtl/interfaces/VX_wstall_if.v
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@@ -6,7 +6,7 @@
interface VX_wstall_if(); interface VX_wstall_if();
wire valid; wire valid;
wire [`NW_BITS-1:0] wid; wire [`NW_BITS-1:0] wid;
endinterface endinterface

12
hw/rtl/libs/VX_divide.v
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@@ -32,13 +32,13 @@ module VX_divide #(
); );
defparam defparam
divide.lpm_type = "LPM_DIVIDE", divide.lpm_type = "LPM_DIVIDE",
divide.lpm_widthn = WIDTHN, divide.lpm_widthn = WIDTHN,
divide.lpm_widthd = WIDTHD, divide.lpm_widthd = WIDTHD,
divide.lpm_nrepresentation = NSIGNED ? "SIGNED" : "UNSIGNED", divide.lpm_nrepresentation = NSIGNED ? "SIGNED" : "UNSIGNED",
divide.lpm_drepresentation = DSIGNED ? "SIGNED" : "UNSIGNED", divide.lpm_drepresentation = DSIGNED ? "SIGNED" : "UNSIGNED",
divide.lpm_hint = "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=FALSE", divide.lpm_hint = "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=FALSE",
divide.lpm_pipeline = LATENCY; divide.lpm_pipeline = LATENCY;
assign quotient = quotient_unqual [WIDTHQ-1:0]; assign quotient = quotient_unqual [WIDTHQ-1:0];
assign remainder = remainder_unqual [WIDTHR-1:0]; assign remainder = remainder_unqual [WIDTHR-1:0];

14
hw/rtl/libs/VX_dp_ram.v
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@@ -11,14 +11,14 @@ module VX_dp_ram #(
parameter SIZEW = $clog2(SIZE+1), parameter SIZEW = $clog2(SIZE+1),
parameter FASTRAM = 0 parameter FASTRAM = 0
) ( ) (
input wire clk, input wire clk,
input wire [ADDRW-1:0] waddr, input wire [ADDRW-1:0] waddr,
input wire [ADDRW-1:0] raddr, input wire [ADDRW-1:0] raddr,
input wire wren, input wire wren,
input wire [BYTEENW-1:0] byteen, input wire [BYTEENW-1:0] byteen,
input wire rden, input wire rden,
input wire [DATAW-1:0] din, input wire [DATAW-1:0] din,
output wire [DATAW-1:0] dout output wire [DATAW-1:0] dout
); );
if (FASTRAM) begin if (FASTRAM) begin

384
hw/rtl/libs/VX_scope.v
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@@ -1,223 +1,223 @@
`include "VX_platform.vh" `include "VX_platform.vh"
module VX_scope #( module VX_scope #(
parameter DATAW = 64, parameter DATAW = 64,
parameter BUSW = 64, parameter BUSW = 64,
parameter SIZE = 16, parameter SIZE = 16,
parameter UPDW = 1, parameter UPDW = 1,
parameter DELTAW = 16 parameter DELTAW = 16
) ( ) (
input wire clk, input wire clk,
input wire reset, input wire reset,
input wire start, input wire start,
input wire stop, input wire stop,
input wire changed, input wire changed,
input wire [DATAW-1:0] data_in, input wire [DATAW-1:0] data_in,
input wire [BUSW-1:0] bus_in, input wire [BUSW-1:0] bus_in,
output wire [BUSW-1:0] bus_out, output wire [BUSW-1:0] bus_out,
input wire bus_write, input wire bus_write,
input wire bus_read input wire bus_read
); );
localparam UPDW_ENABLE = (UPDW != 0); localparam UPDW_ENABLE = (UPDW != 0);
localparam MAX_DELTA = (2 ** DELTAW) - 1; localparam MAX_DELTA = (2 ** DELTAW) - 1;
localparam CMD_GET_VALID = 3'd0; localparam CMD_GET_VALID = 3'd0;
localparam CMD_GET_DATA = 3'd1; localparam CMD_GET_DATA = 3'd1;
localparam CMD_GET_WIDTH = 3'd2; localparam CMD_GET_WIDTH = 3'd2;
localparam CMD_GET_COUNT = 3'd3; localparam CMD_GET_COUNT = 3'd3;
localparam CMD_SET_DELAY = 3'd4; localparam CMD_SET_DELAY = 3'd4;
localparam CMD_SET_STOP = 3'd5; localparam CMD_SET_STOP = 3'd5;
localparam CMD_GET_OFFSET= 3'd6; localparam CMD_GET_OFFSET= 3'd6;
localparam CMD_RESERVED2 = 3'd7; localparam CMD_RESERVED2 = 3'd7;
localparam GET_VALID = 3'd0; localparam GET_VALID = 3'd0;
localparam GET_DATA = 3'd1; localparam GET_DATA = 3'd1;
localparam GET_WIDTH = 3'd2; localparam GET_WIDTH = 3'd2;
localparam GET_COUNT = 3'd3; localparam GET_COUNT = 3'd3;
localparam GET_OFFSET = 3'd6; localparam GET_OFFSET = 3'd6;
`NO_RW_RAM_CHECK reg [DATAW-1:0] data_store [SIZE-1:0]; `NO_RW_RAM_CHECK reg [DATAW-1:0] data_store [SIZE-1:0];
`NO_RW_RAM_CHECK reg [DELTAW-1:0] delta_store [SIZE-1:0]; `NO_RW_RAM_CHECK reg [DELTAW-1:0] delta_store [SIZE-1:0];
reg [UPDW-1:0] prev_trigger_id; reg [UPDW-1:0] prev_trigger_id;
reg [DELTAW-1:0] delta; reg [DELTAW-1:0] delta;
reg [BUSW-1:0] bus_out_r; reg [BUSW-1:0] bus_out_r;
reg [63:0] timestamp, start_time; reg [63:0] timestamp, start_time;
reg [`CLOG2(SIZE)-1:0] raddr, waddr, waddr_end; reg [`CLOG2(SIZE)-1:0] raddr, waddr, waddr_end;
reg [`LOG2UP(DATAW)-1:0] read_offset; reg [`LOG2UP(DATAW)-1:0] read_offset;
reg start_wait, recording, data_valid, read_delta, started, delta_flush; reg start_wait, recording, data_valid, read_delta, started, delta_flush;
reg [BUSW-3:0] delay_val, delay_cntr; reg [BUSW-3:0] delay_val, delay_cntr;
reg [2:0] get_cmd; reg [2:0] get_cmd;
wire [2:0] cmd_type; wire [2:0] cmd_type;
wire [BUSW-4:0] cmd_data; wire [BUSW-4:0] cmd_data;
assign {cmd_data, cmd_type} = bus_in; assign {cmd_data, cmd_type} = bus_in;
wire [UPDW-1:0] trigger_id = data_in[UPDW-1:0]; wire [UPDW-1:0] trigger_id = data_in[UPDW-1:0];
always @(posedge clk) begin always @(posedge clk) begin
if (reset) begin if (reset) begin
get_cmd <= $bits(get_cmd)'(CMD_GET_VALID); get_cmd <= $bits(get_cmd)'(CMD_GET_VALID);
raddr <= 0; raddr <= 0;
waddr <= 0; waddr <= 0;
waddr_end <= $bits(waddr)'(SIZE-1); waddr_end <= $bits(waddr)'(SIZE-1);
started <= 0; started <= 0;
start_wait <= 0; start_wait <= 0;
recording <= 0; recording <= 0;
delay_val <= 0; delay_val <= 0;
delay_cntr <= 0; delay_cntr <= 0;
delta <= 0; delta <= 0;
delta_flush <= 0; delta_flush <= 0;
prev_trigger_id <= 0; prev_trigger_id <= 0;
read_offset <= 0; read_offset <= 0;
read_delta <= 0; read_delta <= 0;
data_valid <= 0; data_valid <= 0;
timestamp <= 0; timestamp <= 0;
start_time <= 0; start_time <= 0;
end else begin end else begin
timestamp <= timestamp + 1; timestamp <= timestamp + 1;
if (bus_write) begin if (bus_write) begin
case (cmd_type) case (cmd_type)
CMD_GET_VALID, CMD_GET_VALID,
CMD_GET_DATA, CMD_GET_DATA,
CMD_GET_WIDTH, CMD_GET_WIDTH,
CMD_GET_OFFSET, CMD_GET_OFFSET,
CMD_GET_COUNT: get_cmd <= $bits(get_cmd)'(cmd_type); CMD_GET_COUNT: get_cmd <= $bits(get_cmd)'(cmd_type);
CMD_SET_DELAY: delay_val <= $bits(delay_val)'(cmd_data); CMD_SET_DELAY: delay_val <= $bits(delay_val)'(cmd_data);
CMD_SET_STOP: waddr_end <= $bits(waddr)'(cmd_data); CMD_SET_STOP: waddr_end <= $bits(waddr)'(cmd_data);
default:; default:;
endcase endcase
end end
if (start && !started) begin if (start && !started) begin
started <= 1; started <= 1;
delta_flush <= 1; delta_flush <= 1;
if (0 == delay_val) begin if (0 == delay_val) begin
start_wait <= 0; start_wait <= 0;
recording <= 1; recording <= 1;
delta <= 0; delta <= 0;
delay_cntr <= 0; delay_cntr <= 0;
start_time <= timestamp; start_time <= timestamp;
end else begin end else begin
start_wait <= 1; start_wait <= 1;
recording <= 0; recording <= 0;
delay_cntr <= delay_val; delay_cntr <= delay_val;
end end
end end
if (start_wait) begin if (start_wait) begin
delay_cntr <= delay_cntr - 1; delay_cntr <= delay_cntr - 1;
if (1 == delay_cntr) begin if (1 == delay_cntr) begin
start_wait <= 0; start_wait <= 0;
recording <= 1; recording <= 1;
delta <= 0; delta <= 0;
start_time <= timestamp; start_time <= timestamp;
end end
end end
if (recording) begin if (recording) begin
if (UPDW_ENABLE) begin if (UPDW_ENABLE) begin
if (delta_flush if (delta_flush
|| changed || changed
|| (trigger_id != prev_trigger_id)) begin || (trigger_id != prev_trigger_id)) begin
delta_store[waddr] <= delta; delta_store[waddr] <= delta;
data_store[waddr] <= data_in; data_store[waddr] <= data_in;
waddr <= waddr + $bits(waddr)'(1); waddr <= waddr + $bits(waddr)'(1);
delta <= 0; delta <= 0;
delta_flush <= 0; delta_flush <= 0;
end else begin end else begin
delta <= delta + DELTAW'(1); delta <= delta + DELTAW'(1);
delta_flush <= (delta == (MAX_DELTA-1)); delta_flush <= (delta == (MAX_DELTA-1));
end end
prev_trigger_id <= trigger_id; prev_trigger_id <= trigger_id;
end else begin end else begin
delta_store[waddr] <= 0; delta_store[waddr] <= 0;
data_store[waddr] <= data_in; data_store[waddr] <= data_in;
waddr <= waddr + 1; waddr <= waddr + 1;
end end
if (stop if (stop
|| (waddr >= waddr_end)) begin || (waddr >= waddr_end)) begin
waddr <= waddr; // keep last address waddr <= waddr; // keep last address
recording <= 0; recording <= 0;
data_valid <= 1; data_valid <= 1;
read_delta <= 1; read_delta <= 1;
end end
end end
if (bus_read if (bus_read
&& (get_cmd == GET_DATA) && (get_cmd == GET_DATA)
&& data_valid) begin && data_valid) begin
if (read_delta) begin if (read_delta) begin
read_delta <= 0; read_delta <= 0;
end else begin end else begin
if (DATAW > BUSW) begin if (DATAW > BUSW) begin
if (read_offset < $bits(read_offset)'(DATAW-BUSW)) begin if (read_offset < $bits(read_offset)'(DATAW-BUSW)) begin
read_offset <= read_offset + $bits(read_offset)'(BUSW); read_offset <= read_offset + $bits(read_offset)'(BUSW);
end else begin end else begin
raddr <= raddr + $bits(raddr)'(1); raddr <= raddr + $bits(raddr)'(1);
read_offset <= 0; read_offset <= 0;
read_delta <= 1; read_delta <= 1;
if (raddr == waddr) begin if (raddr == waddr) begin
data_valid <= 0; data_valid <= 0;
end end
end end
end else begin end else begin
raddr <= raddr + 1; raddr <= raddr + 1;
read_delta <= 1; read_delta <= 1;
if (raddr == waddr) begin if (raddr == waddr) begin
data_valid <= 0; data_valid <= 0;
end end
end end
end end
end end
end end
if (recording) begin if (recording) begin
if (UPDW_ENABLE) begin if (UPDW_ENABLE) begin
if (delta_flush if (delta_flush
|| changed || changed
|| (trigger_id != prev_trigger_id)) begin || (trigger_id != prev_trigger_id)) begin
delta_store[waddr] <= delta; delta_store[waddr] <= delta;
data_store[waddr] <= data_in; data_store[waddr] <= data_in;
end end
end else begin end else begin
delta_store[waddr] <= 0; delta_store[waddr] <= 0;
data_store[waddr] <= data_in; data_store[waddr] <= data_in;
end end
end end
end end
always @(*) begin always @(*) begin
case (get_cmd) case (get_cmd)
GET_VALID : bus_out_r = BUSW'(data_valid); GET_VALID : bus_out_r = BUSW'(data_valid);
GET_WIDTH : bus_out_r = BUSW'(DATAW); GET_WIDTH : bus_out_r = BUSW'(DATAW);
GET_COUNT : bus_out_r = BUSW'(waddr) + BUSW'(1); GET_COUNT : bus_out_r = BUSW'(waddr) + BUSW'(1);
GET_OFFSET: bus_out_r = BUSW'(start_time); GET_OFFSET: bus_out_r = BUSW'(start_time);
/* verilator lint_off WIDTH */ /* verilator lint_off WIDTH */
GET_DATA : bus_out_r = read_delta ? BUSW'(delta_store[raddr]) : BUSW'(data_store[raddr] >> read_offset); GET_DATA : bus_out_r = read_delta ? BUSW'(delta_store[raddr]) : BUSW'(data_store[raddr] >> read_offset);
/* verilator lint_on WIDTH */ /* verilator lint_on WIDTH */
default : bus_out_r = 0; default : bus_out_r = 0;
endcase endcase
end end
assign bus_out = bus_out_r; assign bus_out = bus_out_r;
`ifdef DBG_PRINT_SCOPE `ifdef DBG_PRINT_SCOPE
always @(posedge clk) begin always @(posedge clk) begin
if (bus_read) begin if (bus_read) begin
$display("%t: scope-read: cmd=%0d, addr=%0d, value=%0h", $time, get_cmd, raddr, bus_out); $display("%t: scope-read: cmd=%0d, addr=%0d, value=%0h", $time, get_cmd, raddr, bus_out);
end end
if (bus_write) begin if (bus_write) begin
$display("%t: scope-write: cmd=%0d, value=%0d", $time, cmd_type, cmd_data); $display("%t: scope-write: cmd=%0d, value=%0d", $time, cmd_type, cmd_data);
end end
end end
`endif `endif
endmodule endmodule

4
hw/rtl/libs/VX_skid_buffer.v
View File

@@ -12,8 +12,8 @@ module VX_skid_buffer #(
input wire ready_out, input wire ready_out,
output wire valid_out output wire valid_out
); );
reg [DATAW-1:0] data_out_r; reg [DATAW-1:0] data_out_r;
reg [DATAW-1:0] buffer; reg [DATAW-1:0] buffer;
reg valid_out_r; reg valid_out_r;
reg use_buffer; reg use_buffer;