diff --git a/hw/opae/ccip_std_afu.sv b/hw/opae/ccip_std_afu.sv index 1590e82f..4534d40c 100644 --- a/hw/opae/ccip_std_afu.sv +++ b/hw/opae/ccip_std_afu.sv @@ -113,7 +113,7 @@ module ccip_std_afu #( .avs_address (avs_address), .avs_waitrequest (avs_waitrequest), .avs_write (avs_write), - .avs_read (avs_read), + .avs_read (avs_read), .avs_byteenable (avs_byteenable), .avs_burstcount (avs_burstcount), .avs_readdatavalid (avs_readdatavalid), diff --git a/hw/opae/vortex_afu.sv b/hw/opae/vortex_afu.sv index c708fbcb..54dacc12 100644 --- a/hw/opae/vortex_afu.sv +++ b/hw/opae/vortex_afu.sv @@ -602,7 +602,7 @@ VX_avs_wrapper #( .avs_address (avs_address), .avs_waitrequest (avs_waitrequest), .avs_write (avs_write), - .avs_read (avs_read), + .avs_read (avs_read), .avs_byteenable (avs_byteenable), .avs_burstcount (avs_burstcount), .avs_readdatavalid (avs_readdatavalid), @@ -610,16 +610,16 @@ VX_avs_wrapper #( // DRAM request .dram_req_valid (dram_req_valid), - .dram_req_rw (dram_req_rw), + .dram_req_rw (dram_req_rw), .dram_req_byteen (dram_req_byteen), - .dram_req_addr (dram_req_addr), - .dram_req_data (dram_req_data), + .dram_req_addr (dram_req_addr), + .dram_req_data (dram_req_data), .dram_req_tag (dram_req_tag), .dram_req_ready (dram_req_ready), // DRAM response - .dram_rsp_valid (dram_rsp_valid), - .dram_rsp_data (dram_rsp_data), + .dram_rsp_valid (dram_rsp_valid), + .dram_rsp_data (dram_rsp_data), .dram_rsp_tag (dram_rsp_tag), .dram_rsp_ready (dram_rsp_ready) ); @@ -973,28 +973,28 @@ Vortex #() vortex ( // DRAM request .dram_req_valid (vx_dram_req_valid), - .dram_req_rw (vx_dram_req_rw), + .dram_req_rw (vx_dram_req_rw), .dram_req_byteen (vx_dram_req_byteen), - .dram_req_addr (vx_dram_req_addr), - .dram_req_data (vx_dram_req_data), + .dram_req_addr (vx_dram_req_addr), + .dram_req_data (vx_dram_req_data), .dram_req_tag (vx_dram_req_tag), .dram_req_ready (vx_dram_req_ready), // DRAM response - .dram_rsp_valid (vx_dram_rsp_valid), - .dram_rsp_data (vx_dram_rsp_data), + .dram_rsp_valid (vx_dram_rsp_valid), + .dram_rsp_data (vx_dram_rsp_data), .dram_rsp_tag (vx_dram_rsp_tag), .dram_rsp_ready (vx_dram_rsp_ready), // Snoop request - .snp_req_valid (vx_snp_req_valid), + .snp_req_valid (vx_snp_req_valid), .snp_req_addr (vx_snp_req_addr), .snp_req_invalidate(vx_snp_req_invalidate), .snp_req_tag (vx_snp_req_tag), .snp_req_ready (vx_snp_req_ready), // Snoop response - .snp_rsp_valid (vx_snp_rsp_valid), + .snp_rsp_valid (vx_snp_rsp_valid), .snp_rsp_tag (vx_snp_rsp_tag), .snp_rsp_ready (vx_snp_rsp_ready), @@ -1027,7 +1027,7 @@ Vortex #() vortex ( .csr_io_rsp_ready (vx_csr_io_rsp_ready), // status - .busy (vx_busy), + .busy (vx_busy), `UNUSED_PIN (ebreak) ); diff --git a/hw/rtl/VX_csr_arb.v b/hw/rtl/VX_csr_arb.v index 9801976a..dd51b639 100644 --- a/hw/rtl/VX_csr_arb.v +++ b/hw/rtl/VX_csr_arb.v @@ -19,12 +19,12 @@ module VX_csr_arb ( input wire select_io_rsp ); // requests - assign csr_req_if.valid = (~select_io_req) ? csr_core_req_if.valid : csr_io_req_if.valid; + assign csr_req_if.valid = (~select_io_req) ? csr_core_req_if.valid : csr_io_req_if.valid; assign csr_req_if.wid = (~select_io_req) ? csr_core_req_if.wid : 0; assign csr_req_if.tmask = (~select_io_req) ? csr_core_req_if.tmask : 0; assign csr_req_if.PC = (~select_io_req) ? csr_core_req_if.PC : 0; - assign csr_req_if.op_type = (~select_io_req) ? csr_core_req_if.op_type : (csr_io_req_if.rw ? `CSR_RW : `CSR_RS); - assign csr_req_if.csr_addr = (~select_io_req) ? csr_core_req_if.csr_addr : csr_io_req_if.addr; + assign csr_req_if.op_type = (~select_io_req) ? csr_core_req_if.op_type : (csr_io_req_if.rw ? `CSR_RW : `CSR_RS); + assign csr_req_if.csr_addr = (~select_io_req) ? csr_core_req_if.csr_addr : csr_io_req_if.addr; assign csr_req_if.csr_mask = (~select_io_req) ? csr_core_req_if.csr_mask : (csr_io_req_if.rw ? csr_io_req_if.data : 32'b0); assign csr_req_if.rd = (~select_io_req) ? csr_core_req_if.rd : 0; assign csr_req_if.wb = (~select_io_req) ? csr_core_req_if.wb : 0; diff --git a/hw/rtl/VX_csr_data.v b/hw/rtl/VX_csr_data.v index bd878237..b150f281 100644 --- a/hw/rtl/VX_csr_data.v +++ b/hw/rtl/VX_csr_data.v @@ -34,8 +34,8 @@ module VX_csr_data #( reg [63:0] csr_instret; reg [`FFG_BITS-1:0] csr_fflags [`NUM_WARPS-1:0]; - reg [`FRM_BITS-1:0] csr_frm [`NUM_WARPS-1:0]; - reg [`FRM_BITS+`FFG_BITS-1:0] csr_fcsr [`NUM_WARPS-1:0]; // fflags + frm + reg [`FRM_BITS-1:0] csr_frm [`NUM_WARPS-1:0]; + reg [`FRM_BITS+`FFG_BITS-1:0] csr_fcsr [`NUM_WARPS-1:0]; // fflags + frm reg [31:0] read_data_r; diff --git a/hw/rtl/VX_fpu_unit.v b/hw/rtl/VX_fpu_unit.v index 8540a9c5..c95ae8d4 100644 --- a/hw/rtl/VX_fpu_unit.v +++ b/hw/rtl/VX_fpu_unit.v @@ -3,14 +3,14 @@ module VX_fpu_unit #( parameter CORE_ID = 0 ) ( - // inputs - input wire clk, - input wire reset, + // inputs + input wire clk, + input wire reset, - // inputs - VX_fpu_req_if fpu_req_if, + // inputs + VX_fpu_req_if fpu_req_if, - // outputs + // outputs VX_fpu_to_csr_if fpu_to_csr_if, VX_commit_if fpu_commit_if, diff --git a/hw/rtl/VX_gpr_stage.v b/hw/rtl/VX_gpr_stage.v index 4a1bcd0f..6a39fcd4 100644 --- a/hw/rtl/VX_gpr_stage.v +++ b/hw/rtl/VX_gpr_stage.v @@ -36,9 +36,9 @@ module VX_gpr_stage #( .rs2_data (rs2_data) ); - always @(posedge clk) begin + always @(posedge clk) begin if (reset) begin - rsp_valid <= 0; + rsp_valid <= 0; end else begin rsp_valid <= gpr_req_if.valid; end @@ -47,40 +47,40 @@ module VX_gpr_stage #( rsp_pc <= gpr_req_if.PC; rs1_is_zero <= (0 == gpr_req_if.rs1); rs2_is_zero <= (0 == gpr_req_if.rs2); - end + end `ifdef EXT_F_ENABLE reg [`NUM_THREADS-1:0][31:0] rs3_data; - reg read_rs3, save_rs3; + reg read_rs3, save_rs3; - wire rs3_delay = gpr_req_if.valid && gpr_req_if.use_rs3 && !read_rs3; - wire read_fire = gpr_req_if.valid && gpr_rsp_if.ready; + wire rs3_delay = gpr_req_if.valid && gpr_req_if.use_rs3 && !read_rs3; + wire read_fire = gpr_req_if.valid && gpr_rsp_if.ready; - always @(posedge clk) begin - if (reset) begin - read_rs3 <= 0; - end else begin - if (rs3_delay) begin + always @(posedge clk) begin + if (reset) begin + read_rs3 <= 0; + end else begin + if (rs3_delay) begin read_rs3 <= 1; - end else if (read_fire) begin - read_rs3 <= 0; - end - assert(!read_rs3 || rsp_wid == gpr_req_if.wid); - end + end else if (read_fire) begin + read_rs3 <= 0; + end + assert(!read_rs3 || rsp_wid == gpr_req_if.wid); + end - if (rs3_delay) begin + if (rs3_delay) begin save_rs3 <= 1; end if (save_rs3) begin rs3_data <= rs1_data; save_rs3 <= 0; end - end + end - assign raddr1 = {gpr_req_if.wid, (rs3_delay ? gpr_req_if.rs3 : gpr_req_if.rs1)}; + assign raddr1 = {gpr_req_if.wid, (rs3_delay ? gpr_req_if.rs3 : gpr_req_if.rs1)}; assign gpr_req_if.ready = ~rs3_delay; - assign gpr_rsp_if.rs3_data = rs3_data; + assign gpr_rsp_if.rs3_data = rs3_data; `else diff --git a/hw/rtl/cache/VX_cache_miss_resrv.v b/hw/rtl/cache/VX_cache_miss_resrv.v index 023fcad6..14b00920 100644 --- a/hw/rtl/cache/VX_cache_miss_resrv.v +++ b/hw/rtl/cache/VX_cache_miss_resrv.v @@ -170,7 +170,7 @@ module VX_cache_miss_resrv #( .BUFFERED(0), .RWCHECK(1) ) metadata ( - .clk(clk), + .clk(clk), .waddr(tail_ptr), .raddr(schedule_ptr), .wren(msrq_push), diff --git a/hw/rtl/cache/VX_data_store.v b/hw/rtl/cache/VX_data_store.v index 1f3defd8..ac91dd69 100644 --- a/hw/rtl/cache/VX_data_store.v +++ b/hw/rtl/cache/VX_data_store.v @@ -40,7 +40,7 @@ module VX_data_store #( .BUFFERED(0), .RWCHECK(1) ) data ( - .clk(clk), + .clk(clk), .waddr(write_addr), .raddr(read_addr), .wren(write_enable), diff --git a/hw/rtl/cache/VX_tag_store.v b/hw/rtl/cache/VX_tag_store.v index e222e307..e5dc1d16 100644 --- a/hw/rtl/cache/VX_tag_store.v +++ b/hw/rtl/cache/VX_tag_store.v @@ -52,7 +52,7 @@ module VX_tag_store #( .BUFFERED(0), .RWCHECK(1) ) tags ( - .clk(clk), + .clk(clk), .waddr(write_addr), .raddr(read_addr), .wren(do_fill), diff --git a/hw/rtl/fp_cores/VX_fp_fpga.v b/hw/rtl/fp_cores/VX_fp_fpga.v index 37562811..44e70424 100644 --- a/hw/rtl/fp_cores/VX_fp_fpga.v +++ b/hw/rtl/fp_cores/VX_fp_fpga.v @@ -3,14 +3,14 @@ module VX_fp_fpga #( parameter TAGW = 1 ) ( - input wire clk, - input wire reset, + input wire clk, + input wire reset, input wire valid_in, output wire ready_in, input wire [TAGW-1:0] tag_in, - + input wire [`FPU_BITS-1:0] op_type, input wire [`MOD_BITS-1:0] frm, diff --git a/hw/rtl/fp_cores/VX_fp_noncomp.v b/hw/rtl/fp_cores/VX_fp_noncomp.v index 4959ace4..a08b3d48 100644 --- a/hw/rtl/fp_cores/VX_fp_noncomp.v +++ b/hw/rtl/fp_cores/VX_fp_noncomp.v @@ -4,14 +4,14 @@ module VX_fp_noncomp #( parameter TAGW = 1, parameter LANES = 1 ) ( - input wire clk, - input wire reset, + input wire clk, + input wire reset, output wire ready_in, input wire valid_in, input wire [TAGW-1:0] tag_in, - + input wire [`FPU_BITS-1:0] op_type, input wire [`FRM_BITS-1:0] frm, diff --git a/hw/rtl/fp_cores/VX_fp_type.v b/hw/rtl/fp_cores/VX_fp_type.v index f94e286e..850936a8 100644 --- a/hw/rtl/fp_cores/VX_fp_type.v +++ b/hw/rtl/fp_cores/VX_fp_type.v @@ -2,7 +2,7 @@ `include "VX_define.vh" module VX_fp_type ( - // inputs + // inputs input [7:0] exponent, input [22:0] mantissa, // outputs diff --git a/hw/rtl/fp_cores/VX_fpnew.v b/hw/rtl/fp_cores/VX_fpnew.v index d7dd399e..62014883 100644 --- a/hw/rtl/fp_cores/VX_fpnew.v +++ b/hw/rtl/fp_cores/VX_fpnew.v @@ -11,14 +11,14 @@ module VX_fpnew parameter FNONCOMP = 1, parameter FCONV = 1 ) ( - input wire clk, - input wire reset, + input wire clk, + input wire reset, input wire valid_in, output wire ready_in, input wire [TAGW-1:0] tag_in, - + input wire [`FPU_BITS-1:0] op_type, input wire [`MOD_BITS-1:0] frm, diff --git a/hw/rtl/interfaces/VX_fpu_to_csr_if.v b/hw/rtl/interfaces/VX_fpu_to_csr_if.v index ccb8856e..cd101820 100644 --- a/hw/rtl/interfaces/VX_fpu_to_csr_if.v +++ b/hw/rtl/interfaces/VX_fpu_to_csr_if.v @@ -5,12 +5,12 @@ interface VX_fpu_to_csr_if (); - wire write_enable; - wire [`NW_BITS-1:0] write_wid; - fflags_t write_fflags; + wire write_enable; + wire [`NW_BITS-1:0] write_wid; + fflags_t write_fflags; - wire [`NW_BITS-1:0] read_wid; - wire [`FRM_BITS-1:0] read_frm; + wire [`NW_BITS-1:0] read_wid; + wire [`FRM_BITS-1:0] read_frm; endinterface diff --git a/hw/rtl/interfaces/VX_writeback_if.v b/hw/rtl/interfaces/VX_writeback_if.v index 325b6bdc..dbc0efba 100644 --- a/hw/rtl/interfaces/VX_writeback_if.v +++ b/hw/rtl/interfaces/VX_writeback_if.v @@ -13,7 +13,7 @@ interface VX_writeback_if (); wire [31:0] PC; `IGNORE_WARNINGS_END wire [`NR_BITS-1:0] rd; - wire [`NUM_THREADS-1:0][31:0] data; + wire [`NUM_THREADS-1:0][31:0] data; wire ready; diff --git a/hw/rtl/interfaces/VX_wstall_if.v b/hw/rtl/interfaces/VX_wstall_if.v index 36260870..b50d0711 100644 --- a/hw/rtl/interfaces/VX_wstall_if.v +++ b/hw/rtl/interfaces/VX_wstall_if.v @@ -6,7 +6,7 @@ interface VX_wstall_if(); wire valid; - wire [`NW_BITS-1:0] wid; + wire [`NW_BITS-1:0] wid; endinterface diff --git a/hw/rtl/libs/VX_divide.v b/hw/rtl/libs/VX_divide.v index f960ba52..6d694204 100644 --- a/hw/rtl/libs/VX_divide.v +++ b/hw/rtl/libs/VX_divide.v @@ -32,13 +32,13 @@ module VX_divide #( ); defparam - divide.lpm_type = "LPM_DIVIDE", - divide.lpm_widthn = WIDTHN, - divide.lpm_widthd = WIDTHD, - divide.lpm_nrepresentation = NSIGNED ? "SIGNED" : "UNSIGNED", + divide.lpm_type = "LPM_DIVIDE", + divide.lpm_widthn = WIDTHN, + divide.lpm_widthd = WIDTHD, + divide.lpm_nrepresentation = NSIGNED ? "SIGNED" : "UNSIGNED", divide.lpm_drepresentation = DSIGNED ? "SIGNED" : "UNSIGNED", - divide.lpm_hint = "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=FALSE", - divide.lpm_pipeline = LATENCY; + divide.lpm_hint = "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=FALSE", + divide.lpm_pipeline = LATENCY; assign quotient = quotient_unqual [WIDTHQ-1:0]; assign remainder = remainder_unqual [WIDTHR-1:0]; diff --git a/hw/rtl/libs/VX_dp_ram.v b/hw/rtl/libs/VX_dp_ram.v index 07a188dc..4e75578c 100644 --- a/hw/rtl/libs/VX_dp_ram.v +++ b/hw/rtl/libs/VX_dp_ram.v @@ -11,14 +11,14 @@ module VX_dp_ram #( parameter SIZEW = $clog2(SIZE+1), parameter FASTRAM = 0 ) ( - input wire clk, - input wire [ADDRW-1:0] waddr, - input wire [ADDRW-1:0] raddr, - input wire wren, + input wire clk, + input wire [ADDRW-1:0] waddr, + input wire [ADDRW-1:0] raddr, + input wire wren, input wire [BYTEENW-1:0] byteen, - input wire rden, - input wire [DATAW-1:0] din, - output wire [DATAW-1:0] dout + input wire rden, + input wire [DATAW-1:0] din, + output wire [DATAW-1:0] dout ); if (FASTRAM) begin diff --git a/hw/rtl/libs/VX_generic_queue.v b/hw/rtl/libs/VX_generic_queue.v index 113c1bcf..c24e6488 100644 --- a/hw/rtl/libs/VX_generic_queue.v +++ b/hw/rtl/libs/VX_generic_queue.v @@ -112,7 +112,7 @@ module VX_generic_queue #( .RWCHECK(1), .FASTRAM(FASTRAM) ) dp_ram ( - .clk(clk), + .clk(clk), .waddr(wr_ptr_a), .raddr(rd_ptr_a), .wren(push), @@ -166,7 +166,7 @@ module VX_generic_queue #( .RWCHECK(0), .FASTRAM(FASTRAM) ) dp_ram ( - .clk(clk), + .clk(clk), .waddr(wr_ptr_r), .raddr(rd_ptr_n_r), .wren(push), diff --git a/hw/rtl/libs/VX_scope.v b/hw/rtl/libs/VX_scope.v index 159fb9a1..1b227e79 100644 --- a/hw/rtl/libs/VX_scope.v +++ b/hw/rtl/libs/VX_scope.v @@ -1,223 +1,223 @@ `include "VX_platform.vh" module VX_scope #( - parameter DATAW = 64, - parameter BUSW = 64, - parameter SIZE = 16, - parameter UPDW = 1, - parameter DELTAW = 16 + parameter DATAW = 64, + parameter BUSW = 64, + parameter SIZE = 16, + parameter UPDW = 1, + parameter DELTAW = 16 ) ( - input wire clk, - input wire reset, - input wire start, - input wire stop, - input wire changed, - input wire [DATAW-1:0] data_in, - input wire [BUSW-1:0] bus_in, - output wire [BUSW-1:0] bus_out, - input wire bus_write, - input wire bus_read + input wire clk, + input wire reset, + input wire start, + input wire stop, + input wire changed, + input wire [DATAW-1:0] data_in, + input wire [BUSW-1:0] bus_in, + output wire [BUSW-1:0] bus_out, + input wire bus_write, + input wire bus_read ); - localparam UPDW_ENABLE = (UPDW != 0); - localparam MAX_DELTA = (2 ** DELTAW) - 1; + localparam UPDW_ENABLE = (UPDW != 0); + localparam MAX_DELTA = (2 ** DELTAW) - 1; - localparam CMD_GET_VALID = 3'd0; - localparam CMD_GET_DATA = 3'd1; - localparam CMD_GET_WIDTH = 3'd2; - localparam CMD_GET_COUNT = 3'd3; - localparam CMD_SET_DELAY = 3'd4; - localparam CMD_SET_STOP = 3'd5; - localparam CMD_GET_OFFSET= 3'd6; - localparam CMD_RESERVED2 = 3'd7; + localparam CMD_GET_VALID = 3'd0; + localparam CMD_GET_DATA = 3'd1; + localparam CMD_GET_WIDTH = 3'd2; + localparam CMD_GET_COUNT = 3'd3; + localparam CMD_SET_DELAY = 3'd4; + localparam CMD_SET_STOP = 3'd5; + localparam CMD_GET_OFFSET= 3'd6; + localparam CMD_RESERVED2 = 3'd7; - localparam GET_VALID = 3'd0; - localparam GET_DATA = 3'd1; - localparam GET_WIDTH = 3'd2; - localparam GET_COUNT = 3'd3; - localparam GET_OFFSET = 3'd6; + localparam GET_VALID = 3'd0; + localparam GET_DATA = 3'd1; + localparam GET_WIDTH = 3'd2; + localparam GET_COUNT = 3'd3; + localparam GET_OFFSET = 3'd6; - `NO_RW_RAM_CHECK reg [DATAW-1:0] data_store [SIZE-1:0]; - `NO_RW_RAM_CHECK reg [DELTAW-1:0] delta_store [SIZE-1:0]; + `NO_RW_RAM_CHECK reg [DATAW-1:0] data_store [SIZE-1:0]; + `NO_RW_RAM_CHECK reg [DELTAW-1:0] delta_store [SIZE-1:0]; - reg [UPDW-1:0] prev_trigger_id; - reg [DELTAW-1:0] delta; - reg [BUSW-1:0] bus_out_r; - reg [63:0] timestamp, start_time; + reg [UPDW-1:0] prev_trigger_id; + reg [DELTAW-1:0] delta; + reg [BUSW-1:0] bus_out_r; + reg [63:0] timestamp, start_time; - reg [`CLOG2(SIZE)-1:0] raddr, waddr, waddr_end; + reg [`CLOG2(SIZE)-1:0] raddr, waddr, waddr_end; - reg [`LOG2UP(DATAW)-1:0] read_offset; + reg [`LOG2UP(DATAW)-1:0] read_offset; - reg start_wait, recording, data_valid, read_delta, started, delta_flush; + reg start_wait, recording, data_valid, read_delta, started, delta_flush; - reg [BUSW-3:0] delay_val, delay_cntr; + reg [BUSW-3:0] delay_val, delay_cntr; - reg [2:0] get_cmd; - wire [2:0] cmd_type; - wire [BUSW-4:0] cmd_data; - assign {cmd_data, cmd_type} = bus_in; + reg [2:0] get_cmd; + wire [2:0] cmd_type; + wire [BUSW-4:0] cmd_data; + assign {cmd_data, cmd_type} = bus_in; - wire [UPDW-1:0] trigger_id = data_in[UPDW-1:0]; + wire [UPDW-1:0] trigger_id = data_in[UPDW-1:0]; - always @(posedge clk) begin - if (reset) begin - get_cmd <= $bits(get_cmd)'(CMD_GET_VALID); - raddr <= 0; - waddr <= 0; - waddr_end <= $bits(waddr)'(SIZE-1); - started <= 0; - start_wait <= 0; - recording <= 0; - delay_val <= 0; - delay_cntr <= 0; - delta <= 0; - delta_flush <= 0; - prev_trigger_id <= 0; - read_offset <= 0; - read_delta <= 0; - data_valid <= 0; - timestamp <= 0; - start_time <= 0; - end else begin + always @(posedge clk) begin + if (reset) begin + get_cmd <= $bits(get_cmd)'(CMD_GET_VALID); + raddr <= 0; + waddr <= 0; + waddr_end <= $bits(waddr)'(SIZE-1); + started <= 0; + start_wait <= 0; + recording <= 0; + delay_val <= 0; + delay_cntr <= 0; + delta <= 0; + delta_flush <= 0; + prev_trigger_id <= 0; + read_offset <= 0; + read_delta <= 0; + data_valid <= 0; + timestamp <= 0; + start_time <= 0; + end else begin - timestamp <= timestamp + 1; + timestamp <= timestamp + 1; - if (bus_write) begin - case (cmd_type) - CMD_GET_VALID, - CMD_GET_DATA, - CMD_GET_WIDTH, - CMD_GET_OFFSET, - CMD_GET_COUNT: get_cmd <= $bits(get_cmd)'(cmd_type); - CMD_SET_DELAY: delay_val <= $bits(delay_val)'(cmd_data); - CMD_SET_STOP: waddr_end <= $bits(waddr)'(cmd_data); - default:; - endcase - end + if (bus_write) begin + case (cmd_type) + CMD_GET_VALID, + CMD_GET_DATA, + CMD_GET_WIDTH, + CMD_GET_OFFSET, + CMD_GET_COUNT: get_cmd <= $bits(get_cmd)'(cmd_type); + CMD_SET_DELAY: delay_val <= $bits(delay_val)'(cmd_data); + CMD_SET_STOP: waddr_end <= $bits(waddr)'(cmd_data); + default:; + endcase + end - if (start && !started) begin - started <= 1; - delta_flush <= 1; - if (0 == delay_val) begin - start_wait <= 0; - recording <= 1; - delta <= 0; - delay_cntr <= 0; - start_time <= timestamp; - end else begin - start_wait <= 1; - recording <= 0; - delay_cntr <= delay_val; - end - end + if (start && !started) begin + started <= 1; + delta_flush <= 1; + if (0 == delay_val) begin + start_wait <= 0; + recording <= 1; + delta <= 0; + delay_cntr <= 0; + start_time <= timestamp; + end else begin + start_wait <= 1; + recording <= 0; + delay_cntr <= delay_val; + end + end - if (start_wait) begin - delay_cntr <= delay_cntr - 1; - if (1 == delay_cntr) begin - start_wait <= 0; - recording <= 1; - delta <= 0; - start_time <= timestamp; - end - end + if (start_wait) begin + delay_cntr <= delay_cntr - 1; + if (1 == delay_cntr) begin + start_wait <= 0; + recording <= 1; + delta <= 0; + start_time <= timestamp; + end + end - if (recording) begin - if (UPDW_ENABLE) begin - if (delta_flush - || changed - || (trigger_id != prev_trigger_id)) begin - delta_store[waddr] <= delta; - data_store[waddr] <= data_in; - waddr <= waddr + $bits(waddr)'(1); - delta <= 0; - delta_flush <= 0; - end else begin - delta <= delta + DELTAW'(1); - delta_flush <= (delta == (MAX_DELTA-1)); - end - prev_trigger_id <= trigger_id; - end else begin - delta_store[waddr] <= 0; - data_store[waddr] <= data_in; - waddr <= waddr + 1; - end + if (recording) begin + if (UPDW_ENABLE) begin + if (delta_flush + || changed + || (trigger_id != prev_trigger_id)) begin + delta_store[waddr] <= delta; + data_store[waddr] <= data_in; + waddr <= waddr + $bits(waddr)'(1); + delta <= 0; + delta_flush <= 0; + end else begin + delta <= delta + DELTAW'(1); + delta_flush <= (delta == (MAX_DELTA-1)); + end + prev_trigger_id <= trigger_id; + end else begin + delta_store[waddr] <= 0; + data_store[waddr] <= data_in; + waddr <= waddr + 1; + end - if (stop - || (waddr >= waddr_end)) begin - waddr <= waddr; // keep last address - recording <= 0; - data_valid <= 1; - read_delta <= 1; - end - end + if (stop + || (waddr >= waddr_end)) begin + waddr <= waddr; // keep last address + recording <= 0; + data_valid <= 1; + read_delta <= 1; + end + end - if (bus_read - && (get_cmd == GET_DATA) - && data_valid) begin - if (read_delta) begin - read_delta <= 0; - end else begin - if (DATAW > BUSW) begin - if (read_offset < $bits(read_offset)'(DATAW-BUSW)) begin - read_offset <= read_offset + $bits(read_offset)'(BUSW); - end else begin - raddr <= raddr + $bits(raddr)'(1); - read_offset <= 0; - read_delta <= 1; - if (raddr == waddr) begin - data_valid <= 0; - end - end - end else begin - raddr <= raddr + 1; - read_delta <= 1; - if (raddr == waddr) begin - data_valid <= 0; - end - end - end - end - end + if (bus_read + && (get_cmd == GET_DATA) + && data_valid) begin + if (read_delta) begin + read_delta <= 0; + end else begin + if (DATAW > BUSW) begin + if (read_offset < $bits(read_offset)'(DATAW-BUSW)) begin + read_offset <= read_offset + $bits(read_offset)'(BUSW); + end else begin + raddr <= raddr + $bits(raddr)'(1); + read_offset <= 0; + read_delta <= 1; + if (raddr == waddr) begin + data_valid <= 0; + end + end + end else begin + raddr <= raddr + 1; + read_delta <= 1; + if (raddr == waddr) begin + data_valid <= 0; + end + end + end + end + end - if (recording) begin - if (UPDW_ENABLE) begin - if (delta_flush - || changed - || (trigger_id != prev_trigger_id)) begin - delta_store[waddr] <= delta; - data_store[waddr] <= data_in; - end - end else begin - delta_store[waddr] <= 0; - data_store[waddr] <= data_in; - end - end - end + if (recording) begin + if (UPDW_ENABLE) begin + if (delta_flush + || changed + || (trigger_id != prev_trigger_id)) begin + delta_store[waddr] <= delta; + data_store[waddr] <= data_in; + end + end else begin + delta_store[waddr] <= 0; + data_store[waddr] <= data_in; + end + end + end - always @(*) begin - case (get_cmd) - GET_VALID : bus_out_r = BUSW'(data_valid); - GET_WIDTH : bus_out_r = BUSW'(DATAW); - GET_COUNT : bus_out_r = BUSW'(waddr) + BUSW'(1); - GET_OFFSET: bus_out_r = BUSW'(start_time); - /* verilator lint_off WIDTH */ - GET_DATA : bus_out_r = read_delta ? BUSW'(delta_store[raddr]) : BUSW'(data_store[raddr] >> read_offset); - /* verilator lint_on WIDTH */ - default : bus_out_r = 0; - endcase - end + always @(*) begin + case (get_cmd) + GET_VALID : bus_out_r = BUSW'(data_valid); + GET_WIDTH : bus_out_r = BUSW'(DATAW); + GET_COUNT : bus_out_r = BUSW'(waddr) + BUSW'(1); + GET_OFFSET: bus_out_r = BUSW'(start_time); + /* verilator lint_off WIDTH */ + GET_DATA : bus_out_r = read_delta ? BUSW'(delta_store[raddr]) : BUSW'(data_store[raddr] >> read_offset); + /* verilator lint_on WIDTH */ + default : bus_out_r = 0; + endcase + end - assign bus_out = bus_out_r; + assign bus_out = bus_out_r; `ifdef DBG_PRINT_SCOPE - always @(posedge clk) begin - if (bus_read) begin - $display("%t: scope-read: cmd=%0d, addr=%0d, value=%0h", $time, get_cmd, raddr, bus_out); - end - if (bus_write) begin - $display("%t: scope-write: cmd=%0d, value=%0d", $time, cmd_type, cmd_data); - end - end + always @(posedge clk) begin + if (bus_read) begin + $display("%t: scope-read: cmd=%0d, addr=%0d, value=%0h", $time, get_cmd, raddr, bus_out); + end + if (bus_write) begin + $display("%t: scope-write: cmd=%0d, value=%0d", $time, cmd_type, cmd_data); + end + end `endif endmodule \ No newline at end of file diff --git a/hw/rtl/libs/VX_skid_buffer.v b/hw/rtl/libs/VX_skid_buffer.v index b42ae448..53319175 100644 --- a/hw/rtl/libs/VX_skid_buffer.v +++ b/hw/rtl/libs/VX_skid_buffer.v @@ -12,8 +12,8 @@ module VX_skid_buffer #( input wire ready_out, output wire valid_out ); - reg [DATAW-1:0] data_out_r; - reg [DATAW-1:0] buffer; + reg [DATAW-1:0] data_out_r; + reg [DATAW-1:0] buffer; reg valid_out_r; reg use_buffer;