code refactoring for Vivado, sv2v, and yosys compatibility

2021-09-27 08:55:10 -04:00
parent 9b04f3d9d6
commit 9f34b2944c
97 changed files with 1435 additions and 666 deletions
--- a/hw/rtl/interfaces/VX_gpr_req_if.v
+++ b/hw/rtl/interfaces/VX_gpr_req_if.v
@@ -8,7 +8,21 @@ interface VX_gpr_req_if ();
    wire [`NW_BITS-1:0] wid;
    wire [`NR_BITS-1:0] rs1;
    wire [`NR_BITS-1:0] rs2;  
-    wire [`NR_BITS-1:0] rs3; 
+    wire [`NR_BITS-1:0] rs3;
+
+    modport master (
+        output wid,    
+        output rs1,
+        output rs2,
+        output rs3
+    );
+
+    modport slave (
+        input wid,    
+        input rs1,
+        input rs2,
+        input rs3
+    );

 endinterface