29 lines
461 B
Verilog
29 lines
461 B
Verilog
`ifndef VX_GPR_REQ_IF
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`define VX_GPR_REQ_IF
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`include "VX_define.vh"
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interface VX_gpr_req_if ();
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wire [`NW_BITS-1:0] wid;
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wire [`NR_BITS-1:0] rs1;
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wire [`NR_BITS-1:0] rs2;
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wire [`NR_BITS-1:0] rs3;
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modport master (
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output wid,
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output rs1,
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output rs2,
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output rs3
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);
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modport slave (
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input wid,
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input rs1,
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input rs2,
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input rs3
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);
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endinterface
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`endif |