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minor update

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This commit is contained in:
Blaise Tine
2020-06-03 06:40:25 -04:00
parent 626a4f6fc1
commit 9eb0389717
5 changed files with 7 additions and 4 deletions
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4
driver/rtlsim/Makefile
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@@ -1,7 +1,7 @@
#CFLAGS += -std=c++11 -O2 -DNDEBUG -Wall -Wextra -Wfatal-errors #CFLAGS += -std=c++11 -O2 -DNDEBUG -Wall -Wextra -Wfatal-errors
CFLAGS += -std=c++11 -g -O0 -Wall -Wextra -Wfatal-errors CFLAGS += -std=c++11 -g -O0 -Wall -Wextra -Wfatal-errors
CFLAGS += -I../../include -I../../../hw/simulate -I../../../runtime CFLAGS += -I../../include -I../../../hw/simulate -I../../../hw
# control RTL debug print states # control RTL debug print states
DBG_PRINT_FLAGS = -DDBG_PRINT_CORE_ICACHE \ DBG_PRINT_FLAGS = -DDBG_PRINT_CORE_ICACHE \
@@ -19,7 +19,7 @@ DBG_PRINT_FLAGS = -DDBG_PRINT_CORE_ICACHE \
MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2 MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2
#DEBUG = 1 #DEBUG = 1
AFU=1 #AFU=1
CFLAGS += -fPIC CFLAGS += -fPIC

3
driver/rtlsim/vortex.cpp
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@@ -7,6 +7,7 @@
#include <chrono> #include <chrono>
#include <vortex.h> #include <vortex.h>
#include <ram.h>
#include <simulator.h> #include <simulator.h>
/////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////
@@ -59,6 +60,7 @@ class vx_device {
public: public:
vx_device() { vx_device() {
mem_allocation_ = vx_dev_caps(VX_CAPS_ALLOC_BASE_ADDR); mem_allocation_ = vx_dev_caps(VX_CAPS_ALLOC_BASE_ADDR);
simulator_.attach_ram(&ram_);
} }
~vx_device() { ~vx_device() {
@@ -144,6 +146,7 @@ public:
private: private:
size_t mem_allocation_; size_t mem_allocation_;
RAM ram_;
Simulator simulator_; Simulator simulator_;
std::future<void> future_; std::future<void> future_;
}; };

BIN
driver/tests/demo/kernel.elf
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2
hw/opae/vortex_afu.sv
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@@ -436,7 +436,7 @@ begin
end end
if (cci_dram_wr_req_fire) begin if (cci_dram_wr_req_fire) begin
cci_dram_wr_req_addr <= cci_dram_wr_req_addr + ((t_cci_rdq_tag'(cci_dram_wr_req_ctr) == (DRAM_ADDR_WIDTH)'(CCI_RD_WINDOW_SIZE-1)) ? (DRAM_ADDR_WIDTH)'(CCI_RD_WINDOW_SIZE) : 0); cci_dram_wr_req_addr <= cci_dram_wr_req_addr + ((t_cci_rdq_tag'(cci_dram_wr_req_ctr) == t_cci_rdq_tag'(CCI_RD_WINDOW_SIZE-1)) ? (DRAM_ADDR_WIDTH)'(CCI_RD_WINDOW_SIZE) : 0);
cci_dram_wr_req_ctr <= cci_dram_wr_req_ctr + 1; cci_dram_wr_req_ctr <= cci_dram_wr_req_ctr + 1;
`ifdef DBG_PRINT_OPAE `ifdef DBG_PRINT_OPAE
$display("%t: AVS Wr Req: addr=%0h, data=%0h, rem=%0d", $time, `DRAM_TO_BYTE_ADDR(avs_address), avs_writedata, (cci_dram_wr_req_ctr + 1)); $display("%t: AVS Wr Req: addr=%0h, data=%0h, rem=%0d", $time, `DRAM_TO_BYTE_ADDR(avs_address), avs_writedata, (cci_dram_wr_req_ctr + 1));

2
hw/rtl/libs/VX_generic_queue.v
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@@ -121,7 +121,7 @@ module VX_generic_queue #(
if (!reading) begin if (!reading) begin
empty_r <= 0; empty_r <= 0;
if (size_r == SIZE-1) begin if (size_r == ($bits(size_r)'(SIZE-1))) begin
full_r <= 1; full_r <= 1;
end end
size_r <= size_r + 1; size_r <= size_r + 1;