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pipereg refactoring

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This commit is contained in:
Blaise Tine
2020-07-10 19:31:40 -04:00
parent bdfacf709c
commit 9cf8bf6149
4 changed files with 28 additions and 106 deletions
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30
hw/rtl/VX_d_e_reg.v
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@@ -1,30 +0,0 @@
`include "VX_define.vh"
module VX_d_e_reg (
input wire clk,
input wire reset,
input wire branch_stall,
input wire freeze,
VX_backend_req_if frE_to_bckE_req_if,
VX_backend_req_if bckE_req_if
);
wire stall = freeze;
wire flush = (branch_stall != 0);
VX_generic_register #(
.N(233 + `NW_BITS-1 + 1 + `NUM_THREADS)
) d_e_reg (
.clk (clk),
.reset (reset),
.stall (stall),
.flush (flush),
.in ({frE_to_bckE_req_if.csr_addr, frE_to_bckE_req_if.is_jal, frE_to_bckE_req_if.is_etype, frE_to_bckE_req_if.is_csr, frE_to_bckE_req_if.csr_immed, frE_to_bckE_req_if.csr_mask, frE_to_bckE_req_if.rd, frE_to_bckE_req_if.rs1, frE_to_bckE_req_if.rs2, frE_to_bckE_req_if.alu_op, frE_to_bckE_req_if.wb, frE_to_bckE_req_if.rs2_src, frE_to_bckE_req_if.itype_immed, frE_to_bckE_req_if.mem_read, frE_to_bckE_req_if.mem_write, frE_to_bckE_req_if.branch_type, frE_to_bckE_req_if.upper_immed, frE_to_bckE_req_if.curr_PC, frE_to_bckE_req_if.jal, frE_to_bckE_req_if.jal_offset, frE_to_bckE_req_if.next_PC, frE_to_bckE_req_if.valid, frE_to_bckE_req_if.warp_num, frE_to_bckE_req_if.is_wspawn, frE_to_bckE_req_if.is_tmc, frE_to_bckE_req_if.is_split, frE_to_bckE_req_if.is_barrier}),
.out ({bckE_req_if.csr_addr , bckE_req_if.is_jal , bckE_req_if.is_etype ,bckE_req_if.is_csr , bckE_req_if.csr_immed , bckE_req_if.csr_mask , bckE_req_if.rd , bckE_req_if.rs1 , bckE_req_if.rs2 , bckE_req_if.alu_op , bckE_req_if.wb , bckE_req_if.rs2_src , bckE_req_if.itype_immed , bckE_req_if.mem_read , bckE_req_if.mem_write , bckE_req_if.branch_type , bckE_req_if.upper_immed , bckE_req_if.curr_PC , bckE_req_if.jal , bckE_req_if.jal_offset , bckE_req_if.next_PC , bckE_req_if.valid , bckE_req_if.warp_num , bckE_req_if.is_wspawn , bckE_req_if.is_tmc , bckE_req_if.is_split , bckE_req_if.is_barrier })
);
endmodule

27
hw/rtl/VX_f_d_reg.v
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@@ -1,27 +0,0 @@
`include "VX_define.vh"
module VX_f_d_reg (
input wire clk,
input wire reset,
input wire freeze,
VX_inst_meta_if fe_inst_meta_fd,
VX_inst_meta_if fd_inst_meta_de
);
wire flush = 1'b0;
wire stall = freeze == 1'b1;
VX_generic_register #(
.N(64+`NW_BITS-1+1+`NUM_THREADS)
) f_d_reg (
.clk (clk),
.reset (reset),
.stall (stall),
.flush (flush),
.in ({fe_inst_meta_fd.instruction, fe_inst_meta_fd.curr_PC, fe_inst_meta_fd.warp_num, fe_inst_meta_fd.valid}),
.out ({fd_inst_meta_de.instruction, fd_inst_meta_de.curr_PC, fd_inst_meta_de.warp_num, fd_inst_meta_de.valid})
);
endmodule

48
hw/rtl/VX_front_end.v
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@@ -54,12 +54,15 @@ module VX_front_end #(
.fe_inst_meta_fi (fe_inst_meta_fi) .fe_inst_meta_fi (fe_inst_meta_fi)
); );
VX_f_d_reg f_i_reg ( VX_generic_register #(
.clk (clk), .N(64+`NW_BITS-1+1+`NUM_THREADS)
.reset (reset), ) f_d_reg (
.freeze (icache_stage_delay), .clk (clk),
.fe_inst_meta_fd (fe_inst_meta_fi), .reset (reset),
.fd_inst_meta_de (fe_inst_meta_fi2) .stall (icache_stage_delay),
.flush (1'b0),
.in ({fe_inst_meta_fi.instruction, fe_inst_meta_fi.curr_PC, fe_inst_meta_fi.warp_num, fe_inst_meta_fi.valid}),
.out ({fe_inst_meta_fi2.instruction, fe_inst_meta_fi2.curr_PC, fe_inst_meta_fi2.warp_num, fe_inst_meta_fi2.valid})
); );
VX_icache_stage #( VX_icache_stage #(
@@ -79,12 +82,15 @@ module VX_front_end #(
.icache_req_if (icache_req_if) .icache_req_if (icache_req_if)
); );
VX_i_d_reg i_d_reg ( VX_generic_register #(
.clk (clk), .N(64 + `NW_BITS-1 + 1 + `NUM_THREADS)
.reset (reset), ) i_d_reg (
.freeze (total_freeze), .clk (clk),
.fe_inst_meta_fd (fe_inst_meta_id), .reset (reset),
.fd_inst_meta_de (fd_inst_meta_de) .stall (total_freeze),
.flush (1'b0),
.in ({fe_inst_meta_id.instruction, fe_inst_meta_id.curr_PC, fe_inst_meta_id.warp_num, fe_inst_meta_id.valid}),
.out ({fd_inst_meta_de.instruction, fd_inst_meta_de.curr_PC, fd_inst_meta_de.warp_num, fd_inst_meta_de.valid})
); );
VX_decode decode ( VX_decode decode (
@@ -94,15 +100,15 @@ module VX_front_end #(
.join_if (join_if) .join_if (join_if)
); );
wire no_br_stall = 0; VX_generic_register #(
.N(233 + `NW_BITS-1 + 1 + `NUM_THREADS)
VX_d_e_reg d_e_reg ( ) d_e_reg (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
.branch_stall (no_br_stall), .stall (total_freeze),
.freeze (total_freeze), .flush (1'b0),
.frE_to_bckE_req_if (frE_to_bckE_req_if), .in ({frE_to_bckE_req_if.csr_addr, frE_to_bckE_req_if.is_jal, frE_to_bckE_req_if.is_etype, frE_to_bckE_req_if.is_csr, frE_to_bckE_req_if.csr_immed, frE_to_bckE_req_if.csr_mask, frE_to_bckE_req_if.rd, frE_to_bckE_req_if.rs1, frE_to_bckE_req_if.rs2, frE_to_bckE_req_if.alu_op, frE_to_bckE_req_if.wb, frE_to_bckE_req_if.rs2_src, frE_to_bckE_req_if.itype_immed, frE_to_bckE_req_if.mem_read, frE_to_bckE_req_if.mem_write, frE_to_bckE_req_if.branch_type, frE_to_bckE_req_if.upper_immed, frE_to_bckE_req_if.curr_PC, frE_to_bckE_req_if.jal, frE_to_bckE_req_if.jal_offset, frE_to_bckE_req_if.next_PC, frE_to_bckE_req_if.valid, frE_to_bckE_req_if.warp_num, frE_to_bckE_req_if.is_wspawn, frE_to_bckE_req_if.is_tmc, frE_to_bckE_req_if.is_split, frE_to_bckE_req_if.is_barrier}),
.bckE_req_if (bckE_req_if) .out ({bckE_req_if.csr_addr , bckE_req_if.is_jal , bckE_req_if.is_etype ,bckE_req_if.is_csr , bckE_req_if.csr_immed , bckE_req_if.csr_mask , bckE_req_if.rd , bckE_req_if.rs1 , bckE_req_if.rs2 , bckE_req_if.alu_op , bckE_req_if.wb , bckE_req_if.rs2_src , bckE_req_if.itype_immed , bckE_req_if.mem_read , bckE_req_if.mem_write , bckE_req_if.branch_type , bckE_req_if.upper_immed , bckE_req_if.curr_PC , bckE_req_if.jal , bckE_req_if.jal_offset , bckE_req_if.next_PC , bckE_req_if.valid , bckE_req_if.warp_num , bckE_req_if.is_wspawn , bckE_req_if.is_tmc , bckE_req_if.is_split , bckE_req_if.is_barrier })
); );
endmodule endmodule

27
hw/rtl/VX_i_d_reg.v
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@@ -1,27 +0,0 @@
`include "VX_define.vh"
module VX_i_d_reg (
input wire clk,
input wire reset,
input wire freeze,
VX_inst_meta_if fe_inst_meta_fd,
VX_inst_meta_if fd_inst_meta_de
);
wire flush = 1'b0;
wire stall = freeze == 1'b1;
VX_generic_register #(
.N(64 + `NW_BITS-1 + 1 + `NUM_THREADS)
) i_d_reg (
.clk (clk),
.reset (reset),
.stall (stall),
.flush (flush),
.in ({fe_inst_meta_fd.instruction, fe_inst_meta_fd.curr_PC, fe_inst_meta_fd.warp_num, fe_inst_meta_fd.valid}),
.out ({fd_inst_meta_de.instruction, fd_inst_meta_de.curr_PC, fd_inst_meta_de.warp_num, fd_inst_meta_de.valid})
);
endmodule