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RTL code refactoring

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This commit is contained in:
Blaise Tine
2020-04-19 03:38:00 -04:00
parent 460aabf6b1
commit 9b476f1e17
97 changed files with 3127 additions and 18563 deletions
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171
hw/simulate/simulator.cpp
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@@ -51,18 +51,17 @@ void Simulator::ibus_driver() {
}
}
if (vortex_->I_dram_req && !I_dram_stalled_) {
if (!I_dram_stalled_) {
// std::cout << "Icache Dram Request received!\n";
if (vortex_->I_dram_req_read) {
// std::cout << "Icache Dram Request is read!\n";
// Need to add an element
dram_req_t dram_req;
dram_req.cycles_left = DRAM_LATENCY;
dram_req.data_length = vortex_->I_dram_req_size / 4;
dram_req.base_addr = vortex_->I_dram_req_addr;
dram_req.data = (unsigned *)malloc(dram_req.data_length * sizeof(unsigned));
dram_req.data = (unsigned *)malloc(GLOBAL_BLOCK_SIZE_BYTES);
for (int i = 0; i < dram_req.data_length; i++) {
for (int i = 0; i < (GLOBAL_BLOCK_SIZE_BYTES / 4); i++) {
unsigned curr_addr = dram_req.base_addr + (i * 4);
unsigned data_rd;
ram_->getWord(curr_addr, &data_rd);
@@ -74,9 +73,8 @@ void Simulator::ibus_driver() {
if (vortex_->I_dram_req_write) {
unsigned base_addr = vortex_->I_dram_req_addr;
unsigned data_length = vortex_->I_dram_req_size / 4;
for (int i = 0; i < data_length; i++) {
for (int i = 0; i < (GLOBAL_BLOCK_SIZE_BYTES / 4); i++) {
unsigned curr_addr = base_addr + (i * 4);
unsigned data_wr = vortex_->I_dram_req_data[i];
ram_->writeWord(curr_addr, &data_wr);
@@ -84,22 +82,22 @@ void Simulator::ibus_driver() {
}
}
if (vortex_->I_dram_fill_accept && dequeue_valid) {
if (vortex_->I_dram_rsp_ready && dequeue_valid) {
// std::cout << "Icache Dram Response Sending...!\n";
vortex_->I_dram_fill_rsp = 1;
vortex_->I_dram_fill_rsp_addr = I_dram_req_vec_[dequeue_index].base_addr;
vortex_->I_dram_rsp_valid = 1;
vortex_->I_dram_rsp_addr = I_dram_req_vec_[dequeue_index].base_addr;
// std::cout << "Fill Rsp -> Addr: " << std::hex << (I_dram_req_vec_[dequeue_index].base_addr) << std::dec << "\n";
for (int i = 0; i < I_dram_req_vec_[dequeue_index].data_length; i++) {
vortex_->I_dram_fill_rsp_data[i] = I_dram_req_vec_[dequeue_index].data[i];
for (int i = 0; i < (GLOBAL_BLOCK_SIZE_BYTES / 4); i++) {
vortex_->I_dram_rsp_data[i] = I_dram_req_vec_[dequeue_index].data[i];
}
free(I_dram_req_vec_[dequeue_index].data);
I_dram_req_vec_.erase(I_dram_req_vec_.begin() + dequeue_index);
} else {
vortex_->I_dram_fill_rsp = 0;
vortex_->I_dram_fill_rsp_addr = 0;
vortex_->I_dram_rsp_valid = 0;
vortex_->I_dram_rsp_addr = 0;
}
#ifdef ENABLE_DRAM_STALLS
@@ -112,7 +110,7 @@ void Simulator::ibus_driver() {
}
#endif
vortex_->dram_req_delay = I_dram_stalled_;
vortex_->dram_req_full = I_dram_stalled_;
}
#endif
@@ -144,63 +142,15 @@ void Simulator::dbus_driver() {
#ifdef USE_MULTICORE
if (vortex_->out_dram_req && !dram_stalled_) {
if (vortex_->out_dram_req_read) {
// Need to add an element
dram_req_t dram_req;
dram_req.cycles_left = DRAM_LATENCY;
dram_req.data_length = vortex_->out_dram_req_size / 4;
dram_req.base_addr = vortex_->out_dram_req_addr;
dram_req.data = (unsigned *)malloc(dram_req.data_length * sizeof(unsigned));
for (int i = 0; i < dram_req.data_length; i++) {
unsigned curr_addr = dram_req.base_addr + (i * 4);
unsigned data_rd;
ram_->getWord(curr_addr, &data_rd);
dram_req.data[i] = data_rd;
}
dram_req_vec_.push_back(dram_req);
}
if (vortex_->out_dram_req_write) {
unsigned base_addr = vortex_->out_dram_req_addr;
unsigned data_length = vortex_->out_dram_req_size / 4;
for (int i = 0; i < data_length; i++) {
unsigned curr_addr = base_addr + (i * 4);
unsigned data_wr = vortex_->out_dram_req_data[i];
ram_->writeWord(curr_addr, &data_wr);
}
}
}
if (vortex_->out_dram_fill_accept && dequeue_valid) {
vortex_->out_dram_fill_rsp = 1;
vortex_->out_dram_fill_rsp_addr = dram_req_vec_[dequeue_index].base_addr;
for (int i = 0; i < dram_req_vec_[dequeue_index].data_length; i++) {
vortex_->out_dram_fill_rsp_data[i] = dram_req_vec_[dequeue_index].data[i];
}
free(dram_req_vec_[dequeue_index].data);
dram_req_vec_.erase(dram_req_vec_.begin() + dequeue_index);
} else {
vortex_->out_dram_fill_rsp = 0;
vortex_->out_dram_fill_rsp_addr = 0;
}
#else
if (vortex_->dram_req && !dram_stalled_) {
if (!dram_stalled_) {
if (vortex_->dram_req_read) {
// Need to add an element
dram_req_t dram_req;
dram_req.cycles_left = DRAM_LATENCY;
dram_req.data_length = vortex_->dram_req_size / 4;
dram_req.base_addr = vortex_->dram_req_addr;
dram_req.data = (unsigned *)malloc(dram_req.data_length * sizeof(unsigned));
dram_req.data = (unsigned *)malloc(GLOBAL_BLOCK_SIZE_BYTES);
for (int i = 0; i < dram_req.data_length; i++) {
for (int i = 0; i < (GLOBAL_BLOCK_SIZE_BYTES / 4); i++) {
unsigned curr_addr = dram_req.base_addr + (i * 4);
unsigned data_rd;
ram_->getWord(curr_addr, &data_rd);
@@ -211,9 +161,8 @@ void Simulator::dbus_driver() {
if (vortex_->dram_req_write) {
unsigned base_addr = vortex_->dram_req_addr;
unsigned data_length = vortex_->dram_req_size / 4;
for (int i = 0; i < data_length; i++) {
for (int i = 0; i < (GLOBAL_BLOCK_SIZE_BYTES / 4); i++) {
unsigned curr_addr = base_addr + (i * 4);
unsigned data_wr = vortex_->dram_req_data[i];
ram_->writeWord(curr_addr, &data_wr);
@@ -221,34 +170,79 @@ void Simulator::dbus_driver() {
}
}
if (vortex_->dram_fill_accept && dequeue_valid) {
vortex_->dram_fill_rsp = 1;
vortex_->dram_fill_rsp_addr = dram_req_vec_[dequeue_index].base_addr;
if (vortex_->dram_rsp_ready && dequeue_valid) {
vortex_->dram_rsp_valid = 1;
vortex_->dram_rsp_addr = dram_req_vec_[dequeue_index].base_addr;
for (int i = 0; i < dram_req_vec_[dequeue_index].data_length; i++) {
vortex_->dram_fill_rsp_data[i] = dram_req_vec_[dequeue_index].data[i];
for (int i = 0; i < (GLOBAL_BLOCK_SIZE_BYTES / 4); i++) {
vortex_->dram_rsp_data[i] = dram_req_vec_[dequeue_index].data[i];
}
free(dram_req_vec_[dequeue_index].data);
dram_req_vec_.erase(dram_req_vec_.begin() + dequeue_index);
} else {
vortex_->dram_fill_rsp = 0;
vortex_->dram_fill_rsp_addr = 0;
vortex_->dram_rsp_valid = 0;
vortex_->dram_rsp_addr = 0;
}
#else
if (!dram_stalled_) {
if (vortex_->dram_req_read) {
// Need to add an element
dram_req_t dram_req;
dram_req.cycles_left = DRAM_LATENCY;
dram_req.base_addr = vortex_->dram_req_addr;
dram_req.data = (unsigned *)malloc(GLOBAL_BLOCK_SIZE_BYTES);
for (int i = 0; i < (GLOBAL_BLOCK_SIZE_BYTES / 4); i++) {
unsigned curr_addr = dram_req.base_addr + (i * 4);
unsigned data_rd;
ram_->getWord(curr_addr, &data_rd);
dram_req.data[i] = data_rd;
}
dram_req_vec_.push_back(dram_req);
}
if (vortex_->dram_req_write) {
unsigned base_addr = vortex_->dram_req_addr;
for (int i = 0; i < (GLOBAL_BLOCK_SIZE_BYTES / 4); i++) {
unsigned curr_addr = base_addr + (i * 4);
unsigned data_wr = vortex_->dram_req_data[i];
ram_->writeWord(curr_addr, &data_wr);
}
}
}
if (vortex_->dram_rsp_ready && dequeue_valid) {
vortex_->dram_rsp_valid = 1;
vortex_->dram_rsp_addr = dram_req_vec_[dequeue_index].base_addr;
for (int i = 0; i < (GLOBAL_BLOCK_SIZE_BYTES / 4); i++) {
vortex_->dram_rsp_data[i] = dram_req_vec_[dequeue_index].data[i];
}
free(dram_req_vec_[dequeue_index].data);
dram_req_vec_.erase(dram_req_vec_.begin() + dequeue_index);
} else {
vortex_->dram_rsp_valid = 0;
vortex_->dram_rsp_addr = 0;
}
#endif
#ifdef USE_MULTICORE
vortex_->out_dram_req_delay = dram_stalled_;
vortex_->dram_req_full = dram_stalled_;
#else
vortex_->dram_req_delay = dram_stalled_;
vortex_->dram_req_full = dram_stalled_;
#endif
}
void Simulator::io_handler() {
#ifdef USE_MULTICORE
bool io_valid = false;
for (int c = 0; c < vortex_->number_cores; c++) {
for (int c = 0; c < NUM_CORES; c++) {
if (vortex_->io_valid[c]) {
uint32_t data_write = (uint32_t)vortex_->io_data[c];
char c = (char)data_write;
@@ -318,33 +312,33 @@ void Simulator::send_snoops(uint32_t mem_addr, uint32_t size) {
#ifdef USE_MULTICORE
// submit snoop requests for the needed blocks
vortex_->llc_snp_req_addr = aligned_addr_start;
vortex_->llc_snp_req = false;
vortex_->llc_snp_req_valid = false;
for (;;) {
this->step();
if (vortex_->llc_snp_req) {
vortex_->llc_snp_req = false;
if (vortex_->llc_snp_req_valid) {
vortex_->llc_snp_req_valid = false;
if (vortex_->llc_snp_req_addr >= aligned_addr_end)
break;
vortex_->llc_snp_req_addr += GLOBAL_BLOCK_SIZE_BYTES;
}
if (!vortex_->llc_snp_req_delay) {
vortex_->llc_snp_req = true;
if (!vortex_->llc_snp_req_full) {
vortex_->llc_snp_req_valid = true;
}
}
#else
// submit snoop requests for the needed blocks
vortex_->snp_req_addr = aligned_addr_start;
vortex_->snp_req = false;
vortex_->snp_req_valid = false;
for (;;) {
this->step();
if (vortex_->snp_req) {
vortex_->snp_req = false;
if (vortex_->snp_req_valid) {
vortex_->snp_req_valid = false;
if (vortex_->snp_req_addr >= aligned_addr_end)
break;
vortex_->snp_req_addr += GLOBAL_BLOCK_SIZE_BYTES;
}
if (!vortex_->snp_req_delay) {
vortex_->snp_req = true;
if (!vortex_->snp_req_full) {
vortex_->snp_req_valid = true;
}
}
#endif
@@ -362,7 +356,6 @@ void Simulator::flush_caches(uint32_t mem_addr, uint32_t size) {
// this->send_snoops(mem_addr, size);
// this->wait(PIPELINE_FLUSH_LATENCY);
// #endif
}
bool Simulator::run() {
@@ -381,7 +374,7 @@ bool Simulator::run() {
int status = 0;
#else
// check riscv-tests PASSED/FAILED status
int status = (int)vortex_->Vortex->vx_back_end->VX_wb->last_data_wb & 0xf;
int status = (int)vortex_->Vortex->vx_back_end->vx_wb->last_data_wb & 0xf;
#endif
return (status == 1);