From 9b476f1e17d9cb4b760deb7269933e78d076573e Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Sun, 19 Apr 2020 03:38:00 -0400 Subject: [PATCH] RTL code refactoring --- driver/rtlsim/Makefile | 2 + hw/Makefile | 2 + .../cln28hpm/rf2_128x128_wm1/command.log | 3759 ----------------- .../cln28hpm/rf2_256x128_wm1/command.log | 3759 ----------------- .../cln28hpm/rf2_256x19_wm0/command.log | 3759 ----------------- .../cln28hpm/rf2_32x128_wm1/command.log | 3759 ----------------- hw/modelsim/vortex_tb.v | 6 +- hw/opae/sources.txt | 4 +- hw/opae/vortex_afu.sv | 58 +- hw/opae/wave.do | 69 - hw/rtl/VX_alu.v | 356 +- hw/rtl/VX_back_end.v | 131 +- hw/rtl/VX_csr_data.v | 65 +- hw/rtl/VX_csr_handler.v | 109 +- hw/rtl/VX_csr_pipe.v | 75 +- hw/rtl/VX_csr_wrapper.v | 21 +- hw/rtl/VX_decode.v | 561 ++- hw/rtl/VX_define.vh | 29 +- hw/rtl/VX_dmem_controller.v | 355 +- hw/rtl/VX_execute_unit.v | 108 +- hw/rtl/VX_fetch.v | 144 +- hw/rtl/VX_front_end.v | 46 +- hw/rtl/VX_generic_queue.v | 26 +- hw/rtl/VX_generic_queue_ll.v | 52 +- hw/rtl/VX_generic_register.v | 33 +- hw/rtl/VX_gpgpu_inst.v | 78 +- hw/rtl/VX_gpr.v | 224 +- hw/rtl/VX_gpr_stage.v | 241 +- hw/rtl/VX_gpr_wrapper.v | 29 +- hw/rtl/VX_icache_stage.v | 79 +- hw/rtl/VX_inst_multiplex.v | 112 +- hw/rtl/VX_lsu.v | 94 +- hw/rtl/VX_scheduler.v | 74 +- hw/rtl/VX_warp.v | 4 +- hw/rtl/VX_warp_scheduler.v | 10 +- hw/rtl/VX_writeback.v | 58 +- hw/rtl/Vortex.v | 320 +- hw/rtl/Vortex_Cluster.v | 234 +- hw/rtl/Vortex_Socket.v | 262 +- hw/rtl/byte_enabled_simple_dual_port_ram.v | 41 +- hw/rtl/cache/VX_cache_data.v | 383 +- hw/rtl/compat/VX_divide.v | 37 +- hw/rtl/compat/VX_mult.v | 38 +- hw/rtl/generic_cache/VX_bank.v | 178 +- hw/rtl/generic_cache/VX_cache.v | 355 +- hw/rtl/generic_cache/VX_cache_config.vh | 30 +- .../VX_cache_core_req_bank_sel.v | 2 - hw/rtl/generic_cache/VX_cache_dfq_queue.v | 40 +- hw/rtl/generic_cache/VX_cache_dram_req_arb.v | 121 +- hw/rtl/generic_cache/VX_cache_miss_resrv.v | 162 +- hw/rtl/generic_cache/VX_cache_req_queue.v | 52 +- hw/rtl/generic_cache/VX_cache_wb_sel_merge.v | 123 +- .../VX_dcache_llv_resp_bank_sel.v | 22 +- hw/rtl/generic_cache/VX_fill_invalidator.v | 22 +- hw/rtl/generic_cache/VX_prefetcher.v | 33 +- hw/rtl/generic_cache/VX_snp_fwd_arb.v | 24 +- hw/rtl/generic_cache/VX_tag_data_access.v | 127 +- hw/rtl/generic_cache/VX_tag_data_structure.v | 83 +- hw/rtl/interfaces/VX_branch_response_inter.v | 9 +- hw/rtl/interfaces/VX_csr_req_inter.v | 18 +- hw/rtl/interfaces/VX_csr_wb_inter.v | 10 +- hw/rtl/interfaces/VX_dcache_request_inter.v | 10 +- hw/rtl/interfaces/VX_dcache_response_inter.v | 4 +- hw/rtl/interfaces/VX_dram_req_rsp_inter.v | 17 +- hw/rtl/interfaces/VX_exec_unit_req_inter.v | 52 +- hw/rtl/interfaces/VX_frE_to_bckE_req_inter.v | 58 +- hw/rtl/interfaces/VX_gpr_clone_inter.v | 6 +- hw/rtl/interfaces/VX_gpr_data_inter.v | 4 +- hw/rtl/interfaces/VX_gpr_read_inter.v | 6 +- hw/rtl/interfaces/VX_gpr_wspawn_inter.v | 3 +- .../interfaces/VX_gpu_dcache_dram_req_inter.v | 25 +- .../interfaces/VX_gpu_dcache_dram_res_inter.v | 18 - .../interfaces/VX_gpu_dcache_dram_rsp_inter.v | 16 + hw/rtl/interfaces/VX_gpu_dcache_req_inter.v | 10 +- ..._res_inter.v => VX_gpu_dcache_rsp_inter.v} | 13 +- .../interfaces/VX_gpu_dcache_snp_req_inter.v | 2 +- hw/rtl/interfaces/VX_gpu_inst_req_inter.v | 8 +- hw/rtl/interfaces/VX_gpu_snp_req_rsp.v | 7 +- hw/rtl/interfaces/VX_icache_request_inter.v | 10 +- hw/rtl/interfaces/VX_icache_response_inter.v | 4 +- hw/rtl/interfaces/VX_inst_exec_wb_inter.v | 12 +- hw/rtl/interfaces/VX_inst_mem_wb_inter.v | 12 +- hw/rtl/interfaces/VX_inst_meta_inter.v | 8 +- hw/rtl/interfaces/VX_jal_response_inter.v | 4 +- hw/rtl/interfaces/VX_join_inter.v | 4 +- hw/rtl/interfaces/VX_lsu_req_inter.v | 20 +- hw/rtl/interfaces/VX_mem_req_inter.v | 28 +- hw/rtl/interfaces/VX_mw_wb_inter.v | 14 +- hw/rtl/interfaces/VX_warp_ctl_inter.v | 34 +- hw/rtl/interfaces/VX_wb_inter.v | 12 +- hw/rtl/interfaces/VX_wstall_inter.v | 4 +- hw/rtl/pipe_regs/VX_d_e_reg.v | 40 +- hw/rtl/shared_memory/VX_priority_encoder_sm.v | 2 +- hw/rtl/shared_memory/VX_shared_memory_block.v | 32 +- hw/simulate/simulator.cpp | 171 +- hw/simulate/simulator.h | 1 - hw/simulate/testbench.cpp | 2 +- 97 files changed, 3127 insertions(+), 18563 deletions(-) delete mode 100644 hw/models/memory/cln28hpm/rf2_128x128_wm1/command.log delete mode 100644 hw/models/memory/cln28hpm/rf2_256x128_wm1/command.log delete mode 100644 hw/models/memory/cln28hpm/rf2_256x19_wm0/command.log delete mode 100644 hw/models/memory/cln28hpm/rf2_32x128_wm1/command.log delete mode 100644 hw/opae/wave.do delete mode 100644 hw/rtl/interfaces/VX_gpu_dcache_dram_res_inter.v create mode 100644 hw/rtl/interfaces/VX_gpu_dcache_dram_rsp_inter.v rename hw/rtl/interfaces/{VX_gpu_dcache_res_inter.v => VX_gpu_dcache_rsp_inter.v} (70%) diff --git a/driver/rtlsim/Makefile b/driver/rtlsim/Makefile index 6e092f0c..3c6fea76 100644 --- a/driver/rtlsim/Makefile +++ b/driver/rtlsim/Makefile @@ -23,6 +23,8 @@ SRCS = vortex.cpp ../common/vx_utils.cpp ../../hw/simulate/simulator.cpp RTL_INCLUDE = -I../../hw/rtl -I../../hw/rtl/interfaces -I../../hw/rtl/cache -I../../hw/rtl/generic_cache -I../../hw/rtl/shared_memory -I../../hw/rtl/pipe_regs -I../../hw/rtl/compat +VL_FLAGS += --assert -Wall -Wpedantic + # Enable Verilator multithreaded simulation #THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))') #VL_FLAGS += --threads $(THREADS) diff --git a/hw/Makefile b/hw/Makefile index 8692902f..9e3d9577 100644 --- a/hw/Makefile +++ b/hw/Makefile @@ -10,6 +10,8 @@ EXE += --exe ./simulate/testbench.cpp ./simulate/simulator.cpp VF += -compiler gcc --language 1800-2009 +VF += --assert -Wall -Wpedantic + # LIB=-LDFLAGS '-L/usr/local/systemc/' LIB += diff --git a/hw/models/memory/cln28hpm/rf2_128x128_wm1/command.log b/hw/models/memory/cln28hpm/rf2_128x128_wm1/command.log deleted file mode 100644 index bdc75f4a..00000000 --- a/hw/models/memory/cln28hpm/rf2_128x128_wm1/command.log +++ /dev/null @@ -1,3759 +0,0 @@ -#@ # -#@ # Running lc_shell Version J-2014.09-SP3 for amd64 -- Jan 19, 2015 -#@ # Date: Mon Oct 28 14:39:43 2019 -#@ # Run by: lzhu308@gtcad-srv1 -#@ - -source /tools/synopsys/synthesis/j201409sp3/admin/setup/.synopsys_dc.setup -#@ # -- Starting source /tools/synopsys/synthesis/j201409sp3/admin/setup/.synopsys_dc.setup - -#@ # -#@ # ".synopsys_dc.setup" Initialization File for -#@ # -#@ # Dc_Shell and Design_Analyzer -#@ # -#@ # The variables in this file define the behavior of many parts -#@ # of the Synopsys Synthesis Tools. Upon installation, they should -#@ # be reviewed and modified to fit your site's needs. Each engineer -#@ # can have a .synopsys file in his/her home directory or current -#@ # directory to override variable settings in this file. -#@ # -#@ # Each logical grouping of variables is commented as to their -#@ # nature and effect on the Synthesis Commands. Examples of -#@ # variable groups are the Compile Variable Group, which affects -#@ # the designs produced by the COMPILE command, and the Schematic -#@ # Variable Group, which affects the output of the create_schematic -#@ # command. -#@ # -#@ # You can type "man _variables" in dc_shell or -#@ # design_analyzer to get help about a group of variables. -#@ # For instance, to get help about the "system" variable group, -#@ # type "help system_variables". You can also type -#@ # "man ", to get help on the that variable's -#@ # group. -#@ # -#@ -#@ # System variables -#@ set sh_command_abbrev_mode "Anywhere" -#@ set sh_continue_on_error "true" -#@ update_app_var -default true sh_continue_on_error -#@ set sh_enable_page_mode "true" -#@ update_app_var -default true sh_enable_page_mode -#@ set sh_source_uses_search_path "true" -#@ update_app_var -default true sh_source_uses_search_path -#@ if {$synopsys_program_name == "dc_shell" || $synopsys_program_name == "de_shell" || $synopsys_program_name == "dc_sms_shell" } { -#@ set sh_new_variable_message "false" -#@ update_app_var -default false sh_new_variable_message -#@ } else { -#@ set sh_new_variable_message "true" -#@ update_app_var -default true sh_new_variable_message -#@ } -#@ -#@ if {$synopsys_program_name == "dc_shell"} { -#@ set html_log_enable "false" -#@ set html_log_filename "default.html" -#@ } -#@ -#@ if {$synopsys_program_name == "de_shell"} { -#@ set de_log_html_filename "default.html" -#@ } -#@ -#@ if { [string compare $dc_shell_mode "tcl"] == 0 } { -#@ set sh_enable_line_editing "true" -#@ set sh_line_editing_mode "emacs" -#@ } -#@ -#@ if {$synopsys_program_name == "icc_shell"} { -#@ if {"$sh_output_log_file" == ""} { -#@ set sh_output_log_file "icc_output.txt" -#@ } -#@ -#@ ## the variable sh_redirect_progress_messages only makes it possible -#@ ## for some commands to redirect progress messages to the log file,thereby -#@ ## bypassing the console and reducing the volume of messages on the console. -#@ set sh_redirect_progress_messages true -#@ } -#@ -#@ -#@ # Suppress new variable messages for the following variables -#@ array set auto_index {} -#@ set auto_oldpath "" -#@ -#@ # Enable customer support banner on fatal -#@ if { $sh_arch == "linux" || $sh_arch == "amd64" || $sh_arch == "suse32" || $sh_arch == "suse64" || $sh_arch == "sparcOS5" || $sh_arch == "sparc64" || $sh_arch == "x86sol32" || $sh_arch == "x86sol64" || $sh_arch == "rs6000" || $sh_arch == "aix64" } { -#@ setenv SYNOPSYS_TRACE "" -#@ } -#@ -#@ # -#@ # Load the procedures which make up part of the user interface. -#@ # -#@ if { [string compare $dc_shell_mode "tcl"] == 0 } { -#@ source $synopsys_root/auxx/syn/.dc_common_procs.tcl -#@ if {$synopsys_program_name != "dc_sms_shell"} { -#@ source $synopsys_root/auxx/syn/.dc_procs.tcl -#@ } -#@ alias list_commands help -#@ } -#@ # -- Starting source /tools/synopsys/synthesis/j201409sp3/auxx/syn/.dc_common_procs.tcl - -#@ ############################################################################## -#@ # -#@ # -#@ # FILE: auxx/syn/.dc_common_procs.tcl -#@ # -#@ # ABSTRACT: These procedures are part of the PrimeTime and DC -#@ # user interface. -#@ # They are loaded by .synopsys_pt.setup and .synopsys_dc.setup. -#@ # -#@ ############################################################################## -#@ # -#@ # -#@ -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: group_variable -#@ # -#@ # ABSTRACT: Add a variable to the specified variable group. -#@ # This command is typically used by the system -#@ # administrator only. -#@ # -#@ # Below the proc is the command which creates the command -#@ # help information and semantic data for the argument. -#@ # -#@ # RETURNS: 1 if it is successful. -#@ # error code if the variable does not exist. -#@ # error code of the variable is already in the group. -#@ # -#@ # SYNTAX: group_variable group_name variable_name -#@ # -#@ ############################################################################## -#@ # -#@ -#@ -#@ proc group_variable { args } { -#@ global _Variable_Groups -#@ -#@ parse_proc_arguments -args $args resarr -#@ set group $resarr(group) -#@ set var $resarr(variable_name) -#@ -#@ if { ![info exists _Variable_Groups($group)] } { -#@ set _Variable_Groups($group) "" -#@ } -#@ -#@ # Verify that var exists as a global variable -#@ -#@ set cmd "uplevel #0 \{info exists $var\}" -#@ if { ![eval $cmd] } { -#@ return -code error "Variable '$var' is not defined." -#@ } -#@ -#@ # Only add it if it's not already there -#@ -#@ if { [lsearch $_Variable_Groups($group) $var] == -1 } { -#@ lappend _Variable_Groups($group) $var -#@ } -#@ -#@ return 1 -#@ } -#@ -#@ define_proc_attributes group_variable -info "Add a variable to a variable group" -command_group "Builtins" -permanent -dont_abbrev -define_args { -#@ {group "Variable group name" group} -#@ {variable_name "Variable name" variable_name}} -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: print_variable_group -#@ # -#@ # ABSTRACT: Shows variables and their values defined in the given group. -#@ -#@ # -#@ # Below the proc is the command which creates the command -#@ # help information and semantic data for the argument. -#@ # -#@ # RETURNS: 1 if it is successful. -#@ # error code of the variable group does not exist. -#@ # -#@ # SYNTAX: print_variable_group group_name -#@ # -#@ ############################################################################## -#@ # -#@ -#@ proc print_variable_group { args } { -#@ global _Variable_Groups -#@ -#@ parse_proc_arguments -args $args resarr -#@ set group $resarr(group) -#@ -#@ if { [string compare $group "all"] == 0 } { -#@ set cmd "uplevel #0 \{printvar\}" -#@ return [eval $cmd] -#@ } -#@ -#@ if { ![info exists _Variable_Groups($group)] } { -#@ return -code error "Variable group '$group' does not exist." -#@ } -#@ -#@ # Print out each global variable in the list. To be totally bulletproof, -#@ # test that each variable in the group is still defined. If not, remove -#@ # it from the list. -#@ -#@ foreach var [lsort $_Variable_Groups($group)] { -#@ set cmd "uplevel #0 \{info exists $var\}" -#@ if { ![eval $cmd] } { -#@ # Remove it -#@ set n [lsearch $_Variable_Groups($group) $var] -#@ set $_Variable_Groups($group) [lreplace $_Variable_Groups($group) $n $n] -#@ } else { -#@ # Print it. -#@ set cmd "uplevel #0 \{set $var\}" -#@ set val [eval $cmd] -#@ echo [format "%-25s = \"%s\"" $var $val] -#@ } -#@ } -#@ -#@ return 1 -#@ } -#@ -#@ define_proc_attributes print_variable_group -info "Print the contents of a variable group" -command_group "Builtins" -permanent -define_args {{group "Variable group name" group}} -#@ -#@ -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: _Variable_Groups_Get_Groups -#@ # -#@ # ABSTRACT: Return a list of all variable groups. This command is hidden -#@ # and is used by Design Vision. -#@ # -#@ # RETURNS: Tcl list of all variable groups including group all -#@ # -#@ # SYNTAX: _Variable_Groups_Get_Groups -#@ ############################################################################## -#@ # -#@ -#@ proc _Variable_Groups_Get_Groups { } { -#@ global _Variable_Groups -#@ -#@ set groups [array names _Variable_Groups] -#@ append groups " all" -#@ return $groups -#@ } -#@ define_proc_attributes _Variable_Groups_Get_Groups -hidden -#@ -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: _Variable_Groups_Get_Variables_Of_Group -#@ # -#@ # ABSTRACT: Return a list of all variables of a variable group. -#@ # It also works for pseudo group all. -#@ # -#@ # RETURNS: Tcl list of all variables of a variable group including -#@ # pseudo group all -#@ # -#@ # SYNTAX: _Variable_Groups_Get_Groups -#@ ############################################################################## -#@ # -#@ -#@ proc _Variable_Groups_Get_Variables_Of_Group { group } { -#@ global _Variable_Groups -#@ -#@ if { [string compare $group "all"] == 0 } { -#@ set itr [array startsearch _Variable_Groups] -#@ for { } { [array anymore _Variable_Groups $itr]} { } { -#@ set index [array nextelement _Variable_Groups $itr] -#@ append vars $_Variable_Groups($index) -#@ } -#@ array donesearch _Variable_Groups $itr -#@ return $vars -#@ } -#@ -#@ if { ![info exists _Variable_Groups($group)] } { -#@ return -code error "Variable group '$group' does not exist." -#@ } -#@ -#@ # Test if all variables in the list of variables are still defined. -#@ # Remove not existing variables. -#@ foreach var [lsort $_Variable_Groups($group)] { -#@ set cmd "uplevel #0 \{info exists $var\}" -#@ if { ![eval $cmd] } { -#@ # Remove it -#@ set n [lsearch $_Variable_Groups($group) $var] -#@ set $_Variable_Groups($group) [lreplace $_Variable_Groups($group) $n $n] -#@ } -#@ } -#@ return $_Variable_Groups($group) -#@ } -#@ define_proc_attributes _Variable_Groups_Get_Variables_Of_Group -hidden -#@ -#@ # -- End source /tools/synopsys/synthesis/j201409sp3/auxx/syn/.dc_common_procs.tcl - -#@ # -- Starting source /tools/synopsys/synthesis/j201409sp3/auxx/syn/.dc_procs.tcl - -#@ ############################################################################## -#@ # -#@ # -#@ # FILE: auxx/syn/.dc_procs.tcl -#@ # -#@ # ABSTRACT: These procedures are part of the Design Compiler Tcl -#@ # user interface. -#@ # They are loaded by .synopsys_dc.setup. -#@ # -#@ ############################################################################## -#@ # -#@ # -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: read_verilog -#@ # -#@ # ABSTRACT: Emulate PT's read_verilog command in DC: -#@ # -#@ # Usage: read_verilog # Read one or more verilog files -#@ # *[-hdl_compiler] (Use HDL Compiler (ignored)) -#@ # file_names (Files to read) -#@ # -#@ # Modified: Bharat 11/17/99. Use uplevel to ensure that the command -#@ # sees user/hidden variables from the top level. Star 92970. -#@ # -#@ # Modified: Evan Rosser, 12/5/01. Support -netlist and -rtl flags. -#@ # -#@ ############################################################################## -#@ # -#@ -#@ if { $synopsys_program_name != "icc_shell" } { -#@ proc read_verilog { args } { -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {read_file -format verilog %s %s [list %s]} [array names ra -rtl] [array names ra -netlist] $ra(file_names)] -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes read_verilog -info " Read one or more verilog files" -permanent -define_args { -#@ {file_names "Files to read" file_names list required} -#@ {-netlist "Use structural Verilog netlist reader" "" boolean optional} -#@ {-rtl "Use RTL Verilog compiler (Presto or HDLC)" "" boolean optional} -#@ {-hdl_compiler "Use HDL Compiler (ignored)" "" boolean {hidden optional}} -#@ } -#@ } -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: read_sverilog -#@ # -#@ # ABSTRACT: Emulate PT's read_sverilog command in DC: -#@ # -#@ # Usage: read_sverilog # Read one or more systemverilog files -#@ # *[-hdl_compiler] (Use HDL Compiler (ignored)) -#@ # file_names (Files to read) -#@ # -#@ # Modified: Yong Xiao, 01/31/2003: Copied from read_verilog to support -#@ # systemverilog input. -#@ # -#@ ############################################################################## -#@ # -#@ -#@ proc read_sverilog { args } { -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {read_file -format sverilog %s %s [list %s]} [array names ra -rtl] [array names ra -netlist] $ra(file_names)] -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes read_sverilog -info " Read one or more systemverilog files" -permanent -define_args { -#@ {file_names "Files to read" file_names list required} -#@ {-netlist "Use structural Verilog netlist reader" "" boolean optional} -#@ {-rtl "Use RTL Systemverilog compiler (Presto or HDLC)" "" boolean optional} -#@ {-hdl_compiler "Use HDL Compiler (ignored)" "" boolean {hidden optional}} -#@ } -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: read_vhdl -#@ # -#@ # ABSTRACT: Emulate PT's read_vhdl command in DC: -#@ # -#@ # Usage: read_vhdl # Read one or more vhdl files -#@ # file_names (Files to read) -#@ # -#@ # -#@ ############################################################################## -#@ # -#@ -#@ proc read_vhdl { args } { -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {read_file -format vhdl %s [list %s]} [array names ra -netlist] $ra(file_names)] -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes read_vhdl -info " Read one or more vhdl files" -permanent -define_args { -#@ {file_names "Files to read" file_names list required} -#@ {-netlist "Use structural VHDL netlist reader" "" boolean optional} -#@ } -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: read_db -#@ # -#@ # ABSTRACT: Emulate PT's read_db command in DC: -#@ # -#@ # Usage: -#@ # read_db # Read one or more db files -#@ # *[-netlist_only] (Do not read any attributes from db (ignored)) -#@ # *[-library] (File is a library DB (ignored)) -#@ # file_names (Files to read) -#@ # -#@ # -#@ ############################################################################## -#@ # -#@ -#@ proc read_db { args } { -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {read_file -format db [list %s]} $ra(file_names)] -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes read_db -info " Read one or more db files" -permanent -define_args { -#@ {file_names "Files to read" file_names list required} -#@ {-netlist_only "Do not read any attributes from db (ignored)" "" boolean {hidden optional}} -#@ {-library "File is a library DB (ignored)" "" boolean {hidden optional}} -#@ } -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: read_edif -#@ # -#@ # ABSTRACT: Emulate PT's read_edif command in DC: -#@ # -#@ # Usage: -#@ # read_edif # Read one or more edif files -#@ # *[-complete_language] (Use ptxr to read the file (ignored)) -#@ # file_names (Files to read) -#@ # -#@ # -#@ ############################################################################## -#@ # -#@ proc read_edif { args } { -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {read_file -format edif [list %s]} $ra(file_names)] -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes read_edif -info " Read one or more edif files" -permanent -define_args { -#@ {file_names "Files to read" file_names list required} -#@ {-complete_language "Use ptxr to read the file (ignored)" "" boolean {hidden optional}} -#@ } -#@ -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: read_ddc -#@ # -#@ # ABSTRACT: Shorthand for "read_file -format ddc": -#@ # -#@ # Usage: -#@ # read_ddc # Read one or more ddc files -#@ # *[-scenarios] only read constraints for specified scenarios -#@ # *[-active_scenarios] only activate the specified scenarios -#@ # file_names (Files to read) -#@ # -#@ # -#@ ############################################################################## -#@ # -#@ -#@ proc read_ddc { args } { -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd "read_file -format ddc" -#@ if { [ info exists ra(-scenarios) ] } { -#@ set cmd "$cmd -scenarios { $ra(-scenarios) }" -#@ } -#@ if { [ info exists ra(-active_scenarios) ] } { -#@ set cmd "$cmd -active_scenarios { $ra(-active_scenarios) }" -#@ } -#@ set cmd "$cmd { $ra(file_names) }" -#@ return [uplevel \#0 $cmd] -#@ } -#@ -#@ define_proc_attributes read_ddc -info "Read one or more ddc files" -permanent -define_args { -#@ {file_names "Files to read" file_names list required} -#@ {-scenarios "list of scenarios to be read from ddc file" -#@ scenario_list list optional} -#@ {-active_scenarios "list of scenarios to be made active" -#@ active_scenario_list list optional}} -#@ -#@ -#@ -#@ ############################################################################## -#@ # -#@ # PROCEDURE: source_tcl_file -#@ # -#@ # ABSTRACT: generic procedure to source another tcl file -#@ # -#@ # Arguments: -#@ # filename tcl filename -#@ # dir directory to check for file -#@ # msg verbose message -#@ # verbose verbose mode -#@ # -#@ # Usage: -#@ # -#@ ############################################################################## -#@ # -#@ proc source_tcl_file { filename dir msg {verbose 1} } { -#@ set __qual_pref_file [file join $dir $filename] -#@ if {[file exists $__qual_pref_file]} { -#@ if { $verbose } { -#@ echo $msg $__qual_pref_file -#@ } -#@ # use catch to recover from errors in the pref file -#@ echo_trace "Sourcing " $__qual_pref_file -#@ # to speed up sourcing use read and eval -#@ set f [open $__qual_pref_file] -#@ if {[catch {namespace eval :: [read -nonewline $f]} __msg]} { -#@ echo Error: Error during sourcing of $__qual_pref_file -#@ if {$__msg != ""} { echo $__msg } -#@ # actually, it looks like $__msg is always null after -#@ # source fails -#@ } -#@ close $f -#@ } else { -#@ echo_trace "Info: File '" $__qual_pref_file "' does not exist!" -#@ } -#@ } -#@ define_proc_attributes source_tcl_file -hidden -#@ -#@ -#@ -#@ ############################################################################## -#@ # -#@ # PROCEDURE: echo_trace -#@ # -#@ # ABSTRACT: echo only in trace modus -#@ # -#@ ############################################################################## -#@ # -#@ proc echo_trace { args } { -#@ if { [info exists ::env(TCL_TRACE)] } { -#@ echo TRACE\> [join $args "" ] -#@ } -#@ } -#@ define_proc_attributes echo_trace -hidden -#@ -#@ ############################################################################# -#@ # -#@ # Following procedures added for PC write_script -#@ # -#@ # -#@ # -#@ ############################################################################ -#@ -#@ proc set_cell_restriction { args } { -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {set_attribute %s -type integer restrictions %s } $ra(cell) $ra(value)] -#@ return [uplevel #0 $cmd] -#@ -#@ } -#@ define_proc_attributes set_cell_restriction -hidden -define_args { {cell "cell_name" cell string required} {value "value" value string required} } -#@ -#@ -#@ proc set_cell_soft_keepout {args} { -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {set_keepout_margin -type soft -outer {%d %d %d %d} [list %s] } $ra(llx) $ra(lly) $ra(urx) $ra(ury) $ra(objects)] -#@ return [uplevel #0 $cmd] -#@ -#@ -#@ } -#@ -#@ define_proc_attributes set_cell_soft_keepout -hidden -define_args { {llx "llx" llx float required} {lly "lly" lly float required} {urx "urx" urx float required} {ury "ury" ury float required} {objects "objects" objects list required} } -#@ -#@ proc set_cell_hard_keepout {args} { -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {set_keepout_margin -type soft -outer {%d %d %d %d} [list %s] } $ra(llx) $ra(lly) $ra(urx) $ra(ury) $ra(objects)] -#@ return [uplevel #0 $cmd] -#@ -#@ -#@ } -#@ -#@ define_proc_attributes set_cell_hard_keepout -hidden -define_args { {llx "llx" llx float required} {lly "lly" lly float required} {urx "urx" urx float required} {ury "ury" ury float required} {objects "objects" objects list required} } -#@ -#@ set mw_use_pdb_lib_format false -#@ -#@ ############################################################################## -#@ # -#@ # PROCEDURE: write_milkyway -#@ # -#@ # ABSTRACT: wrapper around save_mw_cel to support original write_milkyway -#@ # interface -#@ # if { [info commands open_mw_cel] == "open_mw_cel" } {} -#@ # -#@ ############################################################################## -#@ -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ -#@ proc write_milkyway args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {save_mw_cel -as %s %s %s %s %s} $ra(-output) [array names ra -overwrite] [array names ra -create] [array names ra -all] [array names ra -dps]] -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes write_milkyway -hidden -info " Saves the design as milkyway CEL" -define_args {{-output fileName "Name" string {optional}} {-overwrite "Overwrite the current version" "" boolean {optional}} {-create "Create from scratch" "" boolean {hidden optional}} {-all "Save all modified cells" "" boolean {hidden optional}} {-dps "Save internal DPS design" "" boolean {hidden optional}}} -#@ -#@ ############################################################################## -#@ # -#@ # PROCEDURE: read_milkyway -#@ # -#@ # ABSTRACT: wrapper around open_mw_cel to support original read_milkyway -#@ # interface -#@ # MODIFIED: To support DPS in Galileo we need to pass the filtering -#@ # parameters to the DPS command. (Pankaj Goswami, Mar09 2005) -#@ # -#@ ############################################################################## -#@ -#@ proc read_milkyway args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {open_mw_cel %s} $ra() ] -#@ -#@ if {[info exists ra(-library)]} { -#@ set cmd [concat [concat $cmd " -library " ] " $ra(-library) "] -#@ } -#@ -#@ if {[info exists ra(-read_only)]} { -#@ lappend cmd {-readonly} -#@ } -#@ -#@ # DPS specific stuff -#@ set dps_cmd "vh_set_current_partition " -#@ set read_mw_with_dps_filter false -#@ -#@ if {[info exists ra(-vh_module_only)]} { -#@ append dps_cmd "-vh_module_only " -#@ set read_mw_with_dps_filter true -#@ } -#@ -#@ if {[info exists ra(-vh_include)]} { -#@ append dps_cmd [concat " -vh_include " " \{ $ra(-vh_include) \}"] -#@ append dps_cmd " " -#@ set read_mw_with_dps_filter true -#@ } -#@ -#@ if {[info exists ra(-vh_exclude)]} { -#@ append dps_cmd [concat " -vh_exclude" " \{ $ra(-vh_exclude) \}"] -#@ set read_mw_with_dps_filter true -#@ } -#@ -#@ if { $read_mw_with_dps_filter == true } { -#@ # Call the DPS command to store the DPS filtering params. -#@ uplevel #0 $dps_cmd -#@ } else { -#@ # If there is no DPS filtering params, then we need to reset the -#@ # params which might have been stored from the provious command. -#@ append dps_cmd " -vh_reset_partition" -#@ uplevel #0 $dps_cmd -#@ } -#@ # End of DPS stuff -#@ -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes read_milkyway -hidden -info " Read milkyway CEL from disk" -define_args {{-library "library name" "lib_name" string {optional}} {-read_only "open design in read only mode" "" boolean {optional}} {-version "version number of the CEL" "number" string {optional}} {-vh_module_only "open design for DPS module only partition" "" boolean {hidden optional}} {-vh_include "list of designs to be included in the DPS partition" "include_designs" list {hidden optional}} {-vh_exclude "list of designs to be excluded in the DPS partition" "exclude_designs" list {hidden optional}} {"" fileName "CEL name" string {required}}} -#@ -#@ } -#@ -#@ ############################################################################## -#@ # -#@ # PROCEDURE: set_mw_technology_file -#@ # -#@ # ABSTRACT: wrapper around update_mw_lib -#@ # -#@ # HISTORY : 2009/6/21, yunz, support ALF reader in ICC -#@ # -#@ ############################################################################## -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] || -#@ ([string match -nocase {*d[ce]_shell*} $synopsys_program_name] && [shell_is_mwlib_enabled]) } { -#@ -#@ proc set_mw_technology_file args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd "" -#@ set lib_name "" -#@ set pdb_file "tech.pdb" -#@ set log_file "log_file" -#@ set alf_file "" -#@ -#@ if {[info exists ra(-technology)] && [info exists ra(-plib)]} { -#@ echo "Error: the $ra(-technology) and $ra(-plib) options are mutually exclusive." -#@ return [uplevel #0 $cmd] -#@ } elseif {[info exists ra(-technology)] && [info exists ra(-alf)]} { -#@ echo "Error: the $ra(-technology) and $ra(-alf) options are mutually exclusive." -#@ return [uplevel #0 $cmd] -#@ } elseif {[info exists ra(-plib)] && [info exists ra(-alf)]} { -#@ echo "Error: the $ra(-plib) and $ra(-alf) options are mutually exclusive." -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ if {[info exists ra(-technology)]} { -#@ -#@ set cmd [format {update_mw_lib -technology %s %s} $ra(-technology) $ra() ] -#@ } -#@ -#@ if {[info exists ra(-plib)]} { -#@ -#@ set cmd [format {update_mw_lib %s} $ra() ] -#@ -#@ if {[string match -nocase {*.pdb} $ra(-plib) ] } { -#@ set cmd [concat [concat $cmd " -plib " ] " $ra(-plib) "] -#@ } -#@ if {[string match -nocase {*.plib} $ra(-plib) ] } { -#@ set subcmd [format {set lc_enable_legacy_library_compiler true;read_lib %s} $ra(-plib)] -#@ redirect -file log_file {uplevel #0 $subcmd} -#@ set f1 [open $log_file] -#@ while {[gets $f1 line] >= 0} { -#@ set msg1 [lindex $line 3] -#@ set msg2 [lindex $line 4] -#@ if {[string match {read} $msg1] && -#@ [string match {successfully} $msg2] } { -#@ set msg [lindex $line 2] -#@ set len [string length $msg] -#@ set lib_name [string range $msg 1 [expr $len-2] ] -#@ break -#@ } -#@ if {[string match {old} $msg1] && -#@ [string match {technology} $msg2] } { -#@ set msg [lindex $line 6] -#@ set len [string length $msg] -#@ set path [string range $msg 1 [expr $len-2] ] -#@ set name1 [lindex [split $path {/}] end] -#@ regexp {(.+?).pdb} $name1 match lib_name -#@ break -#@ } -#@ } -#@ if {$lib_name != ""} { -#@ set subcmd [format {write_lib %s -output %s} $lib_name $pdb_file] -#@ uplevel #0 $subcmd -#@ -#@ echo "Command is : " -#@ echo $cmd -#@ -#@ set cmd [concat [concat $cmd " -plib " ] " $pdb_file "] -#@ -#@ echo "Command is : " -#@ echo $cmd -#@ -#@ } else { -#@ echo "Error: Can not compile $ra(-plib) to pdb successfully" -#@ return 0; -#@ } -#@ } -#@ } -#@ if {[info exists ra(-alf)]} { -#@ -#@ set cmd [format {update_mw_lib %s} $ra() ] -#@ -#@ set cmd [concat [concat $cmd " -alf " ] " $ra(-alf) "] -#@ } -#@ -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes set_mw_technology_file -hide_body -info " Set technology file for the library " -define_args {{-technology "Technology file name" "tech_file" string {optional}} {-plib "Plib file name" "file_name" string {optional}} {-alf "alf file name" "file_name" string {optional}} {"" "Library name" "libName" string {required}}} -#@ -#@ ############################################################################## -#@ # -#@ # PROCEDURE: rebuild_mw_lib -#@ # -#@ # ABSTRACT: wrapper around update_mw_lib -#@ # -#@ ############################################################################## -#@ -#@ proc rebuild_mw_lib args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {update_mw_lib -rebuild %s} $ra() ] -#@ -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes rebuild_mw_lib -hide_body -info " Rebuild the library " -define_args {{"" "Library name" "libName" string {required}}} -#@ -#@ ############################################################################## -#@ # -#@ # PROCEDURE: set_mw_lib_reference -#@ # -#@ # ABSTRACT: Procedure to set ref lib list or ref ctrl file -#@ # -#@ ############################################################################## -#@ -#@ proc set_mw_lib_reference args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd "" -#@ -#@ if {[info exists ra(-mw_reference_library)]} { -#@ set cmd [format {set_reference_control_file -reference_libraries {%s} %s} $ra(-mw_reference_library) $ra() ] -#@ } -#@ -#@ if {[info exists ra(-reference_control_file)]} { -#@ set cmd [format {set_reference_control_file -file %s %s} $ra(-reference_control_file) $ra() ] -#@ } -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes set_mw_lib_reference -hide_body -info " Set reference for the library " -define_args {{-mw_reference_library "List of reference libraries" "lib_list" list {optional}} {-reference_control_file "Reference control file" "file_name" string {optional}} {"" "Library name" "libName" string {required}}} -#@ -#@ # -#@ ############################################################################## -#@ # -#@ # PROCEDURE: create_mw_lib -#@ # -#@ # ABSTRACT: wrapper around MWUI create_mw_lib -#@ # -#@ ############################################################################## -#@ -#@ proc create_mw_lib args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd "" -#@ set lib_name "" -#@ set pdb_file "tech.pdb" -#@ set log_file "log_file" -#@ -#@ if {[info exists ra(-ignore_case)]} { -#@ set cmd [format {org_create_mw_lib %s} $ra() ] -#@ } else { -#@ set cmd [format {org_create_mw_lib -case_sensitive %s} $ra() ] -#@ } -#@ -#@ if {[info exists ra(-technology)]} { -#@ set cmd [concat [concat $cmd " -technology " ] " $ra(-technology) "] -#@ } -#@ -#@ if {[info exists ra(-ignore_tf_error)]} { -#@ set cmd [concat $cmd " -ignore_tf_error " ] -#@ } -#@ -#@ if {[info exists ra(-hier_separator)]} { -#@ set cmd [concat [concat $cmd " -hier_seperator " ] " $ra(-hier_separator) "] -#@ } -#@ -#@ if {[info exists ra(-bus_naming_style)]} { -#@ set cmd [concat [concat $cmd " -bus_naming_style " ] " {$ra(-bus_naming_style)} "] -#@ } -#@ -#@ -#@ if {[info exists ra(-reference_control_file)]} { -#@ set cmd [concat [concat $cmd " -reference_control_file " ] " $ra(-reference_control_file) "] -#@ } -#@ -#@ if {[info exists ra(-mw_reference_library)]} { -#@ set cmd [concat [concat [concat $cmd " -mw_reference_library {" ] " $ra(-mw_reference_library) "] "}"] -#@ } -#@ -#@ if {[info exists ra(-plib)]} { -#@ if {[string match -nocase {*.pdb} $ra(-plib) ] } { -#@ set cmd [concat [concat $cmd " -plib " ] " $ra(-plib) "] -#@ } -#@ if {[string match -nocase {*.plib} $ra(-plib) ] } { -#@ set subcmd [format {set lc_enable_legacy_library_compiler true; read_lib %s} $ra(-plib)] -#@ redirect -file log_file {uplevel #0 $subcmd} -#@ set f1 [open $log_file] -#@ while {[gets $f1 line] >= 0} { -#@ set msg1 [lindex $line 3] -#@ set msg2 [lindex $line 4] -#@ if {[string match {read} $msg1] && -#@ [string match {successfully} $msg2] } { -#@ set msg [lindex $line 2] -#@ set len [string length $msg] -#@ set lib_name [string range $msg 1 [expr $len-2] ] -#@ break -#@ } -#@ if {[string match {old} $msg1] && -#@ [string match {technology} $msg2] } { -#@ set msg [lindex $line 6] -#@ set len [string length $msg] -#@ set path [string range $msg 1 [expr $len-2] ] -#@ set name1 [lindex [split $path {/}] end] -#@ regexp {(.+?).pdb} $name1 match lib_name -#@ break -#@ } -#@ } -#@ if {$lib_name != ""} { -#@ set subcmd [format {write_lib %s -output %s} $lib_name $pdb_file] -#@ uplevel #0 $subcmd -#@ set cmd [concat [concat $cmd " -plib " ] " $pdb_file "] -#@ } else { -#@ echo "Error: Can not compile $ra(-plib) to pdb successfully" -#@ return 0; -#@ } -#@ } -#@ } -#@ -#@ if { ![uplevel #0 $cmd] } { -#@ return 0 -#@ } -#@ -#@ set cmd "" -#@ -#@ if {[info exists ra(-open)]} { -#@ uplevel #0 $cmd -#@ set cmd [format {open_mw_lib %s} $ra() ] -#@ } -#@ -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes create_mw_lib -hide_body -info " Create a milkyway library " -define_args {{-technology "Technology file name" "file_name" string {optional}} {-ignore_tf_error "Ignore the error in technology file" "" boolean {hidden optional}} {-plib "Plib file name" "file_name" string {optional}} {-hier_separator "Hierarchical separator, default is backslash / " "separator" string {hidden optional}} {-bus_naming_style "Bus naming style" "bus_naming_style" string {optional}} {-ignore_case "Make case insensitive" "" boolean {hidden optional}} {-case_sensitive "Make case sensitive" "" boolean {hidden optional}} {-mw_reference_library "List of reference libraries" "lib_list" list {optional}} {-reference_control_file "Reference control file" "file_name" string {optional}} {-open "Open the library after creation" "" boolean {optional}} {"" "Library name to create" "libName" string {required}}} -#@ -#@ # -#@ ############################################################################## -#@ # -#@ # PROCEDURE: report_mw_lib -#@ # -#@ # ABSTRACT: wrapper around MWUI report_mw_lib -#@ # -#@ ############################################################################## -#@ -#@ proc report_mw_lib args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd "" -#@ -#@ if {[info exists ra(-mw_reference_library)]} { -#@ if {[info exists ra()]} { -#@ set cmd [format {org_report_mw_lib -mw_reference_library %s} $ra() ] -#@ } else { -#@ set cmd [format {org_report_mw_lib -mw_reference_library} ] -#@ } -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ if {[info exists ra(-unit_range)]} { -#@ if {[info exists ra()]} { -#@ set cmd [format {org_report_mw_lib -unit_range %s} $ra() ] -#@ } else { -#@ echo "Error : Library name must be specified when using this option" -#@ return 0; -#@ } -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ } -#@ -#@ define_proc_attributes report_mw_lib -hide_body -info " Report information about the library " -define_args {{-unit_range "Report unit range of library" "" boolean {optional}} {-mw_reference_library "Report list of reference libraries" "" boolean {optional}} {"" "Library to be reported" "libName" string {optional}}} -#@ -#@ ############################################################################## -#@ # -#@ # PROCEDURE: close_mw_lib -#@ # -#@ # ABSTRACT: Wrapper around close_mw_lib to handle -save option properly -#@ # - save_mw_cel to save current cel with dc_netlist -#@ # - close_mw_cel to close current cel -#@ # - save_open_cels to save other open cels before closing library -#@ # -#@ ############################################################################## -#@ -#@ proc close_mw_lib args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ if {$args == ""} { -#@ set cmd [format {icc_is_dc_up} ] -#@ if {[uplevel #0 $cmd]} { -#@ set cmd [format {remove_design -quiet -designs} ] -#@ if {[uplevel #0 $cmd]} { -#@ set cmd [format {org_close_mw_lib } ] -#@ return [uplevel #0 $cmd] -#@ } else { -#@ return 0 -#@ } -#@ } else { -#@ set cmd [format {org_close_mw_lib } ] -#@ return [uplevel #0 $cmd] -#@ } -#@ } -#@ -#@ if {[info exists ra(-save)]} { -#@ -#@ set cmd [format {save_mw_cel} ] -#@ if {![uplevel #0 $cmd]} { -#@ return -#@ } -#@ -#@ set cmd [format {close_mw_cel} ] -#@ if {![uplevel #0 $cmd]} { -#@ return -#@ } -#@ -#@ set cmd [format {save_open_cels} ] -#@ if {![uplevel #0 $cmd]} { -#@ return -#@ } -#@ } -#@ -#@ set cmd [format {org_close_mw_lib} ] -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ define_proc_attributes close_mw_lib -hide_body -info " Closes the milkyway library " -define_args {{-save "Save open cels" "" boolean {optional}} {"" "libraries to be closed" "lib list" list {hidden optional}}} -#@ } else { -#@ define_proc_attributes close_mw_lib -hide_body -info " Closes the milkyway library " -define_args {{-no_save "Don't save open cels" "" boolean {hidden optional}} {"" "libraries to be closed" "lib list" list {hidden optional}}} -#@ } -#@ ############################################################################## -#@ # -#@ # PROCEDURE: write_mw_lib_files -#@ # -#@ # ABSTRACT: Write technology or reference control file -#@ # History: Yun Zhang 2012/12/11, public option -stream_layer_map_file -#@ # History: Yun Zhang 2012/9/5. support new hidden option -vt_cell_placement_properties -#@ # History: Yun Zhang 2011/12/5. add new hidden option -stream_layer_map_file -#@ # -#@ ############################################################################## -#@ proc write_mw_lib_files args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd "" -#@ -#@ if {[info exists ra(-reference_control_file)]} { -#@ #Option -reference_contrl_file, -plib and -technology are exclusive. -#@ # If both of them are set at the same time, error reported. -#@ # 9000273455, by xqsun, 2009/2/4 -#@ if {[info exists ra(-technology)]} { -#@ echo "Error: Cannot specify '-reference_control_file' with '-technology'.(CMD-001)" -#@ return 0 -#@ } elseif {[info exists ra(-plib)]} { -#@ echo "Error: Cannot specify '-reference_control_file' with '-plib'.(CMD-001)" -#@ return 0 -#@ } elseif {[info exists ra(-vt_cell_placement_properties)]} { -#@ echo "Error: Cannot specify '-reference_control_file' with '-vt_cell_placement_properties'.(CMD-001)" -#@ return 0 -#@ } elseif {[info exists ra(-stream_layer_map_file)]} { -#@ echo "Error: Cannot specify '-reference_control_file' with '-stream_layer_map_file'.(CMD-001)" -#@ return 0 -#@ } else { -#@ set cmd [format {report_mw_lib_ref_ctrl_file -output %s %s} $ra(-output) $ra() ] -#@ return [uplevel #0 $cmd] -#@ } -#@ } -#@ -#@ if {[info exists ra(-technology)]} { -#@ if {[info exists ra(-plib)]} { -#@ echo "Error: Cannot specify '-technology' with '-plib'.(CMD-001)" -#@ return 0 -#@ } elseif {[info exists ra(-vt_cell_placement_properties)]} { -#@ echo "Error: Cannot specify '-technology' with '-vt_cell_placement_properties'.(CMD-001)" -#@ return 0 -#@ } elseif {[info exists ra(-stream_layer_map_file)]} { -#@ echo "Error: Cannot specify '-technology' with '-stream_layer_map_file'.(CMD-001)" -#@ return 0 -#@ } else { -#@ set cmd [format {org_report_mw_lib -output %s %s} $ra(-output) $ra() ] -#@ return [uplevel #0 $cmd] -#@ } -#@ } -#@ -#@ if {[info exists ra(-plib)]} { -#@ if {[info exists ra(-stream_layer_map_file)]} { -#@ echo "Error: Cannot specify '-plib' with '-stream_layer_map_file'.(CMD-001)" -#@ return 0 -#@ } elseif {[info exists ra(-vt_cell_placement_properties)]} { -#@ echo "Error: Cannot specify '-plib' with '-vt_cell_placement_properties'.(CMD-001)" -#@ return 0 -#@ } else { -#@ set cmd [format {write_plib -lib_name %s %s} $ra() $ra(-output) ] -#@ return [uplevel #0 $cmd] -#@ } -#@ } -#@ -#@ if {[info exists ra(-vt_cell_placement_properties)]} { -#@ if {[info exists ra(-stream_layer_map_file)]} { -#@ echo "Error: Cannot specify '-vt_cell_placement_properties' with '-stream_layer_map_file'.(CMD-001)" -#@ return 0 -#@ } else { -#@ set cmd [format {org_report_mw_lib -vt_cell_placement_properties -output %s %s} $ra(-output) $ra() ] -#@ return [uplevel #0 $cmd] -#@ } -#@ } -#@ -#@ if {[info exists ra(-stream_layer_map_file)]} { -#@ set cmd [format {org_report_mw_lib -stream_layer_map_file %s -output %s %s} $ra(-stream_layer_map_file) $ra(-output) $ra() ] -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ } -#@ -#@ define_proc_attributes write_mw_lib_files -hide_body -info " Write technology or reference control file " -define_args {{-technology "Dump technology file" "" boolean {optional}} {-plib "Dump plib file" "" boolean {optional}} {-vt_cell_placement_properties "Dump multi-VT cells' implant layer information of library" "" boolean {optional hidden}} {-reference_control_file "Dump reference control file" "" boolean {optional}} {-stream_layer_map_file "Dump layer map file during stream in/out" "" string {optional}} {-output "Output file" "file_name" string {required}} {"" "Library to be reported" "libName" string {required}}} -#@ } -#@ ############################################################################## -#@ # -#@ # PROCEDURE: close_mw_cel -#@ # -#@ # ABSTRACT: Wrapper around close_mw_cel to add -save option -#@ # remove_timing_design is the command to shutdown dc netlist -#@ # -#@ ############################################################################## -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ -#@ proc close_mw_cel args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ global mw_is_all_views -#@ set cmd [format {icc_is_dc_up} ] -#@ set dc_is_up [uplevel #0 $cmd] -#@ -#@ set cmd_close [format {org_close_mw_cel} ] -#@ -#@ if {[info exists ra(-all_views)]} { -#@ set cmd_close [format {%s -all_views} $cmd_close] -#@ set mw_is_all_views 1 -#@ } -#@ if {[info exists ra(-all_versions)]} { -#@ set cmd_close [format {%s -all_versions} $cmd_close] -#@ } -#@ if {[info exists ra(-save)]} { -#@ set cmd_close [format {%s -save} $cmd_close] -#@ } -#@ if {[info exists ra(-verbose)]} { -#@ set cmd_close [format {%s -verbose} $cmd_close] -#@ } -#@ if {[info exists ra(-hierarchy)]} { -#@ set cmd_close [format {%s -hierarchy} $cmd_close] -#@ } -#@ -#@ ui_util_clean_saved_lib_attr $args -#@ -#@ set cmd "" -#@ set lcels "" -#@ set is_current_closed 1 -#@ -#@ if {[info exists ra()]} { -#@ set lcels $ra() -#@ } -#@ set len [string length $lcels] -#@ if {$len > 0} { -#@ set is_current_closed [is_current_mw_cel $lcels] -#@ set cmd_close [format {%s {%s}} $cmd_close $lcels] -#@ } -#@ if {[uplevel #0 $cmd_close]} { -#@ set mw_is_all_views 0 -#@ if {$dc_is_up == 1} { -#@ if {$is_current_closed == 1} { -#@ set cmd [format {remove_design -quiet -designs} ] -#@ return [uplevel #0 $cmd] -#@ } -#@ return 1 -#@ } else { -#@ return 1 -#@ } -#@ } else { -#@ set mw_is_all_views 0 -#@ return 0 -#@ } -#@ } -#@ -#@ define_proc_attributes close_mw_cel -hide_body -info " Closes the design " -define_args {{-save "Save the design" "" boolean {optional}} {-discard "Discard any changes" "" boolean {optional hidden}} {-verbose "Print out debugging messages" "" boolean {optional hidden}} {-hierarchy "Close top design and its child designs" "" boolean {optional}} {-all_views "Close all views of the design" "" boolean {optional}} {-all_versions "Close all versions of the design" "" boolean {optional}} {"" "designs to be closed" "design list" list {optional}}} -#@ -#@ ############################################################################## -#@ # -#@ # PROCEDURE: save_all_mw_cel -#@ # -#@ # ABSTRACT: Wrapper around save_mw_cel to save all the open cels. Needed for Black box flow. -#@ # -#@ ############################################################################## -#@ -#@ proc save_all_mw_cels { } { -#@ set top_cel [get_attribute [current_mw_cel] name] -#@ -#@ set cels [fp_get_open_cells] -#@ -#@ foreach cel $cels { -#@ if {$cel != $top_cel} { -#@ current_mw_cel $cel -#@ -#@ save_mw_cel -#@ } -#@ } -#@ -#@ current_mw_cel $top_cel -#@ -#@ save_mw_cel -#@ } -#@ -#@ icc_hide_cmd save_all_mw_cels -#@ -#@ ############################################################################## -#@ # PROCEDURE: execute_command_and_create_cel_from_scratch -#@ # ABSTRACT: This procedure executes the given command and creates the CEL -#@ # from scratch after executing this command. -#@ ############################################################################## -#@ proc execute_command_and_create_cel_from_scratch {org_cmd_name args} { -#@ global mw_create_cel_force -#@ global mw_enable_auto_cel -#@ global mw_force_auto_cel -#@ -#@ set lib [current_mw_lib] -#@ -#@ # If no MW lib, design is not from MW. Execute the original command -#@ # and return. -#@ if {$lib == ""} { -#@ return [eval $org_cmd_name $args] -#@ } -#@ -#@ # Get values of few variables. -#@ set incr_mode $mw_create_cel_force -#@ set mw_create_cel_force TRUE -#@ -#@ # Get auto cel mode, disable it temporarily if enabled. -#@ set auto_cel_mode $mw_enable_auto_cel -#@ set mw_enable_auto_cel FALSE -#@ -#@ # Check if the already existing CEL is auto-CEL. -#@ set auto_cel 0 -#@ if {[is_cel_auto_cel]} { -#@ set auto_cel 1 -#@ } elseif {![get_top_cel_mwid]} { -#@ set auto_cel 1 -#@ } -#@ -#@ -#@ # Run the original command, if not successful restore the incr_mode -#@ # variable and return. No CEL is created. -#@ if {![eval $org_cmd_name $args]} { -#@ set mw_create_cel_force $incr_mode -#@ set mw_enable_auto_cel $auto_cel_mode -#@ return 0 -#@ } -#@ -#@ # Restore auto_cel mode -#@ set mw_enable_auto_cel $auto_cel_mode -#@ -#@ # Now create auto or real CEL depending on what the original CEL was. -#@ if {$auto_cel == "1"} { -#@ # Force creation of auto-CEL, since commands other than read_def/pdef -#@ # do not decouple CEL from DC. -#@ -#@ set mw_force_auto_cel TRUE -#@ set cmd [format {save_mw_cel -auto}] -#@ } else { -#@ if [get_top_cel_mwid] { -#@ set cmd [format {save_mw_cel -create}] -#@ echo "Information: Command not supported by incr. update or write-thru." -#@ echo " Creating new CEL from scratch, old CEL will be closed." -#@ } -#@ } -#@ -#@ # Create the Auto CEL or normal CEL from scratch. -#@ if {![uplevel #0 $cmd]} { -#@ set mw_create_cel_force $incr_mode -#@ set mw_force_auto_cel FALSE -#@ return 0 -#@ } -#@ -#@ set mw_create_cel_force $incr_mode -#@ set mw_force_auto_cel FALSE -#@ return 1 -#@ } -#@ -#@ define_proc_attributes execute_command_and_create_cel_from_scratch -hidden -hide_body -#@ -#@ ############################################################################## -#@ # PROCEDURE: read_def -#@ # ABSTRACT: Wrapper around read_def to handle incremental update properly -#@ # if MW based read_def is used, bypass the wrapper -#@ # enable_milkyway_def_reader_writer must be TRUE and use_pdb_lib_format must -#@ # be false for MW read_Def to be run, use wrapper if either condition fails -#@ ############################################################################## -#@ rename -force dc_read_def org_read_def -#@ icc_hide_cmd org_read_def -#@ proc dc_read_def args { -#@ parse_proc_arguments -args $args ra -#@ -#@ return [eval execute_command_and_create_cel_from_scratch "org_read_def" $args] -#@ } -#@ -#@ define_proc_attributes dc_read_def -hide_body -info " Read a def file " -define_args {{-design "name of design for which clusters are to be read" "" string {optional}} {-quiet "do not print out any warnings" "" boolean {optional}} {-verbose "print out more warnings" "" boolean {optional}} {-allow_physical_cells "allow physical cells" "" boolean {optional}} {-allow_physical_ports "allow physical ports" "" boolean {optional}} {-allow_physical_nets "allow physical nets" "" boolean {optional}} {-skip_signal_nets "skip signal nets" "" boolean {optional}} {-incremental "incremental" "" boolean {optional}} {-enforce_scaling "enforce_scaling" "" boolean {optional}} {-move_bounds "move bounds" "" boolean {optional}} {"" "input def file names" "input_def_file_name" string {required}}} -#@ -#@ -#@ ############################################################################## -#@ # PROCEDURE: group -#@ # ABSTRACT: Wrapper around group to handle incremental update properly -#@ ############################################################################## -#@ rename -force group org_group -#@ icc_hide_cmd org_group -#@ proc group args { -#@ parse_proc_arguments -args $args ra -#@ return [eval execute_command_and_create_cel_from_scratch "org_group" $args] -#@ } -#@ -#@ define_proc_attributes group -hide_body -info " create new hierarchy" -define_args {{-except "cells not to be included in the group" "exclude_list" list {optional}} -#@ {-design_name "name of design created for new hierarchy" "design_name" string {optional}} -#@ {-cell_name "name of cell created for new hierarchy" "cell_name" string {optional}} -#@ {-logic "group any combinational elements" "" boolean {optional}} -#@ {-pla "group any PLA elements" "" boolean {optional}} -#@ {-fsm "group all elements part of a finite state machine" "" boolean {optional}} -#@ {-hdl_block "name of hdl_block to group" "" string {optional}} -#@ {-hdl_bussed "group all bussed gates under this block" "" boolean {optional}} -#@ {-hdl_all_blocks "group all hdl blocks under this block" "" boolean {optional}} -#@ {-soft "set the group_name attribute" "" boolean {optional}} -#@ {"" "cells to be included in the group" "cell_list" list {optional}}} -#@ -#@ ############################################################################## -#@ # PROCEDURE: copy_design -#@ # ABSTRACT: Wrapper around copy_design to handle incremental update properly -#@ ############################################################################## -#@ rename -force copy_design org_copy_design -#@ icc_hide_cmd org_copy_design -#@ proc copy_design args { -#@ parse_proc_arguments -args $args ra -#@ return [eval execute_command_and_create_cel_from_scratch "org_copy_design" $args] -#@ } -#@ -#@ define_proc_attributes copy_design -hide_body -info " copy_design" -define_args {{"" "List of designs to be copied" "design_list" list {required}} -#@ {"" "Name of new design or target file" "target_name" string {required}}} -#@ -#@ ############################################################################## -#@ # PROCEDURE: create_design -#@ # ABSTRACT: Wrapper around create_design to handle incremental update properly -#@ ############################################################################## -#@ rename -force create_design org_create_design -#@ icc_hide_cmd org_create_design -#@ proc create_design args { -#@ parse_proc_arguments -args $args ra -#@ return [eval execute_command_and_create_cel_from_scratch "org_create_design" $args] -#@ } -#@ -#@ define_proc_attributes create_design -hide_body -info " Creates a design in dc_shell memory" -define_args {{"" "name of the design to create" "" string {required}} -#@ {"" "name of file for design; optional" "" string {optional}}} -#@ -#@ ############################################################################## -#@ # PROCEDURE: reset_design -#@ # ABSTRACT: Wrapper around reset_design to handle incremental update properly -#@ ############################################################################## -#@ #rename -force reset_design org_reset_design -#@ #icc_hide_cmd org_reset_design -#@ #proc reset_design args { -#@ # parse_proc_arguments -args $args ra -#@ # return [eval execute_command_and_create_cel_from_scratch "org_reset_design" $args] -#@ #} -#@ -#@ ############################################################################## -#@ # PROCEDURE: rename_design -#@ # ABSTRACT: Wrapper around rename_design to handle incremental update properly -#@ ############################################################################## -#@ rename -force rename_design org_rename_design -#@ icc_hide_cmd org_rename_design -#@ proc rename_design args { -#@ parse_proc_arguments -args $args ra -#@ return [eval execute_command_and_create_cel_from_scratch "org_rename_design" $args] -#@ } -#@ -#@ define_proc_attributes rename_design -hide_body -info " rename_design" -define_args {{"" "List of designs to be renamed" "design_list" list {required}} -#@ {"" "Name of new design or target file" "target_name" string {required}}} -#@ -#@ } -#@ -#@ ############################################################################## -#@ # If we are in icc_shell (i.e. Galileo) then -#@ # load the procedures to switch between DC and Milkyway collections. -#@ # Set the default to MW collection unless otherwise specified. -#@ ############################################################################## -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ # load the procedures that switch between DC and MW collections -#@ source $synopsys_root/auxx/syn/collection_procs.tcl -#@ -#@ set CS mw -#@ -#@ # see if the user wants DC -#@ if {! [catch {getenv USE_DC_COLLECTIONS_ONLY}] && -#@ [getenv USE_DC_COLLECTIONS_ONLY] } { -#@ set CS dc -#@ } -#@ -#@ # set the collection source now -#@ redirect /dev/null { -#@ if {[catch {set_collection_mode -handle $CS}]} { -#@ catch {set_collection_option -handle $CS} -#@ } -#@ } -#@ -#@ unset CS -#@ } -#@ -#@ ############################################################################## -#@ # procedure for route command -#@ # echo the command to a temp tcl file for seperate process to pick up -#@ ############################################################################## -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ rename -force route org_route -#@ icc_hide_cmd org_route -#@ proc route args { -#@ set route_cmd_file_name ".route_cmd.tcl" -#@ set route_cmd_temp_file_name ".route_cmd.tcl.temp" -#@ set fp [open $route_cmd_file_name "w"] -#@ set route_cmd [concat "sep_proc_route " $args " -child"] -#@ puts $fp $route_cmd -#@ close $fp -#@ -#@ uplevel #0 rename -force route route_temp_proc -#@ uplevel #0 rename -force org_route route -#@ set status [ uplevel #0 route $args ] -#@ uplevel #0 rename -force route org_route -#@ uplevel #0 rename -force route_temp_proc route -#@ -#@ if { [info exist status ] == 1 } { -#@ return $status -#@ } -#@ return -#@ } -#@ } -#@ -#@ ############################################################################## -#@ # Tcl Command: set_ignore_cell -#@ # Description: Load the command only in IC Compiler (icc_shell) -#@ ############################################################################## -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ source $synopsys_root/auxx/syn/psyn/ideal_cell.tcl.e -#@ } -#@ -#@ ############################################################################## -#@ # Tcl Command: check_physical_design -#@ # Description: Load the command only in IC Compiler (icc_shell) -#@ ############################################################################## -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ # Load the compiled Tcl byte-code: -#@ # 9000784997: Do not log to command.log when sourcing .tbc files -#@ set prev_sh_source_logging [get_app_var sh_source_logging] -#@ set_app_var sh_source_logging 0 -#@ source $synopsys_root/auxx/syn/psyn/check_physical_design_core.tbc -#@ source $synopsys_root/auxx/syn/psyn/check_physical_design_utils.tbc -#@ source $synopsys_root/auxx/syn/psyn/check_physical_design_flows.tbc -#@ source $synopsys_root/auxx/syn/psyn/check_physical_design_reports.tbc -#@ source $synopsys_root/auxx/syn/psyn/check_physical_design_ui.tbc -#@ source $synopsys_root/auxx/syn/psyn/create_qor_snapshot.tbc -#@ source $synopsys_root/auxx/syn/psyn/report_qor_snapshot.tbc -#@ source $synopsys_root/auxx/syn/psyn/msgParser.tbc -#@ source $synopsys_root/auxx/syn/psyn/displacement_gui.tbc -#@ source $synopsys_root/auxx/syn/psyn/categorize_timing_gui.tbc -#@ set_app_var sh_source_logging $prev_sh_source_logging -#@ -#@ source $synopsys_root/auxx/syn/psyn/mcmm_utils.tcl.e -#@ source $synopsys_root/auxx/syn/psyn/propagate_all_clocks.tcl.e -#@ } -#@ -#@ if { [string match -nocase {*dc_shell*} $synopsys_program_name] && [shell_is_in_topographical_mode] } { -#@ # 9000784997: Do not log to command.log when sourcing .tbc files -#@ set prev_sh_source_logging [get_app_var sh_source_logging] -#@ set_app_var sh_source_logging 0 -#@ source $synopsys_root/auxx/syn/psyn/create_qor_snapshot.tbc -#@ source $synopsys_root/auxx/syn/psyn/report_qor_snapshot.tbc -#@ set_app_var sh_source_logging $prev_sh_source_logging -#@ -#@ source $synopsys_root/auxx/syn/psyn/mcmm_utils.tcl.e -#@ } -#@ -#@ if { $synopsys_program_name == "de_shell" } { -#@ # 9000784997: Do not log to command.log when sourcing .tbc files -#@ set prev_sh_source_logging [get_app_var sh_source_logging] -#@ set_app_var sh_source_logging 0 -#@ source $synopsys_root/auxx/syn/psyn/create_qor_snapshot.tbc -#@ source $synopsys_root/auxx/syn/psyn/report_qor_snapshot.tbc -#@ set_app_var sh_source_logging $prev_sh_source_logging -#@ -#@ source $synopsys_root/auxx/syn/psyn/mcmm_utils.tcl.e -#@ } -#@ -#@ ############################################################################## -#@ # ICC setup and hiding commands/procs etc -#@ ############################################################################## -#@ -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ #set save_mw_cel_lib_setup TRUE -#@ #set auto_restore_mw_cel_lib_setup FALSE -#@ -#@ alias create_wiring_keepout create_wiring_keepouts -#@ alias get_wiring_keepout get_wiring_keepouts -#@ alias get_placement_keepout get_placement_keepouts -#@ alias create_placement_keepout create_placement_keepouts -#@ -#@ icc_hide_cmd execute_command_and_create_cel_from_scratch -#@ icc_hide_cmd dc_read_def -#@ icc_hide_cmd read_edif -#@ icc_hide_cmd read_sverilog -#@ icc_hide_cmd read_vhdl -#@ icc_hide_cmd set_collection_mode -#@ icc_hide_cmd return_dc_collection -#@ icc_hide_cmd return_mw_collection -#@ set mw_use_pdb_lib_format true -#@ } -#@ -#@ -#@ ############################################################################## -#@ # Tcl Command: get_dont_touch_nets -#@ # Description: wrapper of "get_nets -filter dont_touch_reason==mv" -#@ ############################################################################## -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ -#@ proc get_dont_touch_nets args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {get_nets}] -#@ -#@ if {[info exists ra()]} { -#@ set cmd [format {%s {%s}} $cmd $ra()] -#@ } -#@ if {[info exists ra(-type)]} { -#@ set cmd [format {%s -filter dont_touch_reasons=~*%s*} $cmd $ra(-type)] -#@ } -#@ if {[info exists ra(-hierarchical)]} { -#@ set cmd [format {%s -hierarchical} $cmd] -#@ } -#@ if {[info exists ra(-quiet)]} { -#@ set cmd [format {%s -quiet} $cmd] -#@ } -#@ if {[info exists ra(-regexp)]} { -#@ set cmd [format {%s -regexp} $cmd] -#@ } -#@ if {[info exists ra(-nocase)]} { -#@ set cmd [format {%s -nocase} $cmd] -#@ } -#@ if {[info exists ra(-exact)]} { -#@ set cmd [format {%s -exact} $cmd] -#@ } -#@ -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes get_dont_touch_nets -info " Get dont_touch nets " -permanent -define_args { {"" "Match net names against patterns" "patterns" list {optional}} {-type "Match net dont_touch reasons" "reasons" list {required}} {-hierarchical "Search level-by-level in current instance" "" boolean {optional}} {-quiet "Suppress all messages" "" boolean {optional hidden}} {-regexp "Patterns are full regular expressions" "" boolean {optional hidden}} {-nocase "With -regexp, matches are case-insensitive" "" boolean {optional hidden}} {-exact "Wildcards are considered as plain characters" "" boolean {optional hidden}} } -#@ -#@ alias get_dont_touch_net get_dont_touch_nets -#@ } -#@ -#@ -#@ ############################################################################## -#@ # return the first {index value} pair in Tcl array ary. -#@ ############################################################################## -#@ proc _snps_array_peek { level ary } { -#@ upvar #$level $ary loc_ary -#@ set ret [list] -#@ set token [array startsearch loc_ary] -#@ while {[array anymore loc_ary $token]} { -#@ set k [array nextelement loc_ary $token] -#@ set v $loc_ary($k) -#@ set ret [list $k $v] -#@ break -#@ } -#@ array donesearch loc_ary $token -#@ return $ret; -#@ } -#@ define_proc_attributes _snps_array_peek -hidden -#@ # -- End source /tools/synopsys/synthesis/j201409sp3/auxx/syn/.dc_procs.tcl - -#@ -#@ # Temporary fix for the LMC_HOME variable- set it to an empty string -#@ -#@ if { [catch {getenv LMC_HOME } __err ] != 0 } { -#@ setenv LMC_HOME "" -#@ } -#@ -#@ -#@ # -#@ # -#@ # Site-Specific Variables -#@ # -#@ # These are the variables that are most commonly changed at a -#@ # specific site, either upon installation of the Synopsys software, -#@ # or by specific engineers in their local .synopsys files. -#@ # -#@ # -#@ -#@ # from the System Variable Group -#@ set link_library { * your_library.db } -#@ -#@ set search_path [list . ${synopsys_root}/libraries/syn ${synopsys_root}/minpower/syn ${synopsys_root}/dw/syn_ver ${synopsys_root}/dw/sim_ver] -#@ set target_library your_library.db -#@ set synthetic_library "" -#@ set command_log_file "./command.log" -#@ set designer "" -#@ set company "" -#@ set find_converts_name_lists "false" -#@ -#@ set symbol_library your_library.sdb -#@ -#@ # Turn on Formality SVF recording -#@ if { $synopsys_program_name == "dc_shell" || $synopsys_program_name == "de_shell" || $synopsys_program_name == "design_vision" } { -#@ set_svf -default default.svf -#@ } -#@ -#@ # from the Schematic Variable Group -#@ -#@ # from the Plot Variable Group -#@ # [froi] 07/06/2012: Remove old Design Analyzer plot_command variable -#@ #if { $sh_arch == "hp700" } { -#@ # set plot_command "lp -d" -#@ #} else { -#@ # set plot_command "lpr -Plw" -#@ #} -#@ -#@ set view_command_log_file "./view_command.log" -#@ -#@ # from the View Variable group -#@ if { $sh_arch == "hp700" } { -#@ set text_print_command "lp -d" -#@ } else { -#@ set text_print_command "lpr -Plw" -#@ } -#@ # -#@ # System Variable Group: -#@ # -#@ # These variables are system-wide variables. -#@ # -#@ set arch_init_path ${synopsys_root}/${sh_arch}/motif/syn/uid -#@ set auto_link_disable "false" -#@ set auto_link_options "-all" -#@ set uniquify_naming_style "%s_%d" -#@ set verbose_messages "true" -#@ set echo_include_commands "true" -#@ set svf_file_records_change_names_changes "true" -#@ set change_names_update_inst_tree "true" -#@ set change_names_dont_change_bus_members false -#@ set default_name_rules "" -#@ #set tdrc_enable_clock_table_creation "true" -#@ -#@ # -#@ # Compile Variable Group: -#@ # -#@ # These variables affect the designs created by the COMPILE command. -#@ # -#@ set compile_assume_fully_decoded_three_state_busses "false" -#@ set compile_no_new_cells_at_top_level "false" -#@ set compile_dont_touch_annotated_cell_during_inplace_opt "false" -#@ set compile_update_annotated_delays_during_inplace_opt "true" -#@ set compile_instance_name_prefix "U" -#@ set compile_instance_name_suffix "" -#@ set compile_negative_logic_methodology "false" -#@ set compile_disable_hierarchical_inverter_opt "false" -#@ set compile_use_low_timing_effort "false" -#@ set compile_fix_cell_degradation "false" -#@ set compile_preserve_subdesign_interfaces "false" -#@ set compile_enable_constant_propagation_with_no_boundary_opt "true" -#@ set port_complement_naming_style "%s_BAR" -#@ set compile_implementation_selection "true" -#@ set compile_delete_unloaded_sequential_cells "true" -#@ set reoptimize_design_changed_list_file_name "" -#@ set compile_checkpoint_phases "false" -#@ set compile_cpu_limit 0.0 -#@ set compile_log_format " %elap_time %area %wns %tns %drc %endpoint"; -#@ set compile_top_all_paths "false" -#@ set compile_top_acs_partition "false" -#@ set default_port_connection_class "universal" -#@ set compile_hold_reduce_cell_count "false" -#@ set compile_retime_license_behavior "wait" -#@ set dont_touch_nets_with_size_only_cells "false" -#@ if { $synopsys_program_name == "dc_shell" && [shell_is_in_topographical_mode] } { -#@ set dct_prioritize_area_correlation "false" -#@ set compile_error_on_missing_physical_cells "false" -#@ } -#@ -#@ set ldd_return_val 0 -#@ if { [string compare $dc_shell_mode "default"] == 0 } { -#@ set ldd_script ${synopsys_root}/auxx/syn/scripts/list_duplicate_designs.dcsh -#@ alias list_duplicate_designs "include -quiet ldd_script; dc_shell_status = ldd_return_val " -#@ -#@ } -#@ if { [string compare $dc_shell_mode "tcl"] == 0 } { -#@ if {$synopsys_program_name != "dc_sms_shell"} { -#@ source ${synopsys_root}/auxx/syn/scripts/list_duplicate_designs.tcl -#@ # 9000784997: Do not log to command.log when sourcing .tbc files -#@ set prev_sh_source_logging [get_app_var sh_source_logging] -#@ set_app_var sh_source_logging 0 -#@ source ${synopsys_root}/auxx/syn/scripts/analyze_datapath.tbc -#@ set_app_var sh_source_logging $prev_sh_source_logging -#@ } -#@ } -#@ # -- Starting source /tools/synopsys/synthesis/j201409sp3/auxx/syn/scripts/list_duplicate_designs.tcl - -#@ ####################################################################### -#@ # -#@ # list_duplicate_designs.tcl 21 Sept. 2006 -#@ # -#@ # List designs in dc_shell memory that have the same design name -#@ # -#@ # COPYRIGHT (C) 2006, SYNOPSYS INC., ALL RIGHTS RESERVED. -#@ # -#@ ####################################################################### -#@ -#@ proc list_duplicate_designs { args } { -#@ parse_proc_arguments -args $args ra -#@ -#@ # Get the list of duplicate designs -#@ set the_pid [pid] -#@ set rand_1 [expr int(rand() * 100000)] -#@ set temp_file_1 [format "/tmp/ldd_design_%s_%s" $the_pid $rand_1] -#@ -#@ redirect $temp_file_1 { foreach_in_collection ldd_design [find design "*"] { -#@ echo [get_object_name $ldd_design] -#@ } } -#@ -#@ set rand_2 [expr int(rand() * 100000)] -#@ set temp_file_2 [format "/tmp/ldd_design_%s_%s" $the_pid $rand_2] -#@ -#@ sh sort $temp_file_1 | uniq -d | tee $temp_file_2 -#@ file delete $temp_file_1 -#@ -#@ # Report duplicates -#@ if { ! [file size $temp_file_2] } { -#@ echo [concat {No duplicate designs found.}] -#@ set ldd_return_val 0 -#@ } else { -#@ set rand_3 [expr int(rand() * 100000)] -#@ set temp_file_3 [format "/tmp/ldd_design_%s_%s" $the_pid $rand_3] -#@ echo {Warning: Multiple designs in memory with the same design name.} -#@ echo {} -#@ echo { Design File Path} -#@ echo { ------ ---- ----} -#@ list_designs -table > $temp_file_3 -#@ echo [sh fgrep -f $temp_file_2 $temp_file_3 | sort | grep -v 'Design.*File.*Path'] -#@ file delete $temp_file_3 -#@ set ldd_return_val 1 -#@ } -#@ -#@ # Clean up -#@ file delete $temp_file_2 -#@ -#@ set list_duplicate_designs1 $ldd_return_val -#@ } -#@ -#@ define_proc_attributes list_duplicate_designs -info " List designs of same names" -permanent -define_args { -#@ } -#@ # -- End source /tools/synopsys/synthesis/j201409sp3/auxx/syn/scripts/list_duplicate_designs.tcl - -#@ -#@ -#@ set compile_log_format " %elap_time %area %wns %tns %drc %endpoint"; -#@ -#@ set compile_top_all_paths "false" -#@ alias compile_inplace_changed_list_file_name reoptimize_design_changed_list_file_name -#@ -#@ # -#@ # These variables affects compile, report_timing and report_constraints -#@ # commands. -#@ # -#@ set enable_recovery_removal_arcs "false" -#@ set timing_report_attributes {dont_touch dont_use map_only size_only ideal_net infeasible_paths} -#@ -#@ # -#@ # Multibit Variable Group: -#@ # -#@ # These variables affect the multibit mapping functionality -#@ # -#@ -#@ set bus_multiple_separator_style "," -#@ -#@ # -#@ # ILM Variable Group: -#@ # -#@ # These variables affect Interface Logic Model functionality -#@ # -#@ -#@ set ilm_ignore_percentage 25 -#@ -#@ # -#@ # Estimator Variable Group: -#@ # -#@ # These variables affect the designs created by the ESTIMATE command. -#@ # -#@ set estimate_resource_preference "fast" -#@ alias est_resource_preference estimate_resource_preference -#@ set lbo_lfo_enable_at_pin_count 3 -#@ set lbo_cells_in_regions "false" -#@ -#@ # Synthetic Library Group: -#@ # -#@ # These variable affect synthetic library processing. -#@ # -#@ set cache_dir_chmod_octal "777" -#@ set cache_file_chmod_octal "666" -#@ set cache_read "~" -#@ set cache_read_info "false" -#@ set cache_write "~" -#@ set cache_write_info "false" -#@ set synlib_dont_get_license {} -#@ set synlib_library_list {DW01 DW02 DW03 DW04 DW05 DW06 DW07} -#@ set synlib_wait_for_design_license {} -#@ set synlib_dwhomeip {} -#@ -#@ # -#@ # Insert_DFT Variable Group: -#@ # -#@ #set test_default_client_order [list] -#@ set insert_dft_clean_up "true" -#@ set insert_test_design_naming_style "%s_test_%d" -#@ # /*insert_test_scan_chain_only_one_clock = "false" -#@ # Replace by command line option (star 17215) -- Denis Martin 28-Jan-93*/ -#@ set test_clock_port_naming_style "test_c%s" -#@ set test_scan_clock_a_port_naming_style "test_sca%s" -#@ set test_scan_clock_b_port_naming_style "test_scb%s" -#@ set test_scan_clock_port_naming_style "test_sc%s" -#@ set test_scan_enable_inverted_port_naming_style "test_sei%s" -#@ set test_scan_enable_port_naming_style "test_se%s" -#@ set test_scan_in_port_naming_style "test_si%s%s" -#@ set test_scan_out_port_naming_style "test_so%s%s" -#@ set test_non_scan_clock_port_naming_style "test_nsc_%s" -#@ set test_default_min_fault_coverage 95 -#@ set test_dedicated_subdesign_scan_outs "false" -#@ set test_disable_find_best_scan_out "false" -#@ set test_dont_fix_constraint_violations "false" -#@ set test_isolate_hier_scan_out 0 -#@ set test_mode_port_naming_style "test_mode%s" -#@ set test_mode_port_inverted_naming_style "test_mode_i%s" -#@ set compile_dont_use_dedicated_scanout 1 -#@ set test_mux_constant_si "false" -#@ -#@ # -#@ # Analyze_Scan Variable Group: -#@ # -#@ # These variables affect the designs created by the PREVIEW_SCAN command. -#@ # -#@ set test_preview_scan_shows_cell_types "false" -#@ set test_scan_link_so_lockup_key "l" -#@ set test_scan_link_wire_key "w" -#@ set test_scan_segment_key "s" -#@ set test_scan_true_key "t" -#@ -#@ # -#@ # bsd Variable Group: -#@ -#@ # These variables affect the report generated by the check_bsd command -#@ # and the BSDLout generated by the write_bsdl command. -#@ # -#@ set test_user_test_data_register_naming_style "UTDR%d" -#@ -#@ set test_user_defined_instruction_naming_style "USER%d" -#@ -#@ set test_bsdl_default_suffix_name "bsdl" -#@ -#@ set test_bsdl_max_line_length 80 -#@ -#@ set test_cc_ir_masked_bits 0 -#@ -#@ set test_cc_ir_value_of_masked_bits 0 -#@ -#@ set test_bsd_allow_tolerable_violations "false" -#@ set test_bsd_optimize_control_cell "false" -#@ set test_bsd_control_cell_drive_limit 0 -#@ set test_bsd_manufacturer_id 0 -#@ set test_bsd_part_number 0 -#@ set test_bsd_version_number 0 -#@ set bsd_max_in_switching_limit 60000 -#@ set bsd_max_out_switching_limit 60000 -#@ -#@ # -#@ # TestManager Variable Group: -#@ # -#@ # These variables affect the TestManager methodology. -#@ # -#@ set multi_pass_test_generation "false" -#@ -#@ # -#@ # TestSim Variable Group: -#@ # -#@ # These variables affect the TestSim behavior. -#@ # -#@ # set testsim_print_stats_file "true" -#@ -#@ # Test DRC Variable Group: -#@ # -#@ # These variables affect the check_test command. -#@ # -#@ set test_capture_clock_skew "small_skew" -#@ set test_allow_clock_reconvergence "true" -#@ set test_check_port_changes_in_capture "true" -#@ set test_infer_slave_clock_pulse_after_capture "infer" -#@ -#@ # -#@ # Test Variable Group: -#@ # -#@ # These variables affect the rtldrc, check_test, write_test_protocol -#@ # and write_test command. -#@ # -#@ set test_default_delay 0.0 -#@ set test_default_bidir_delay 0.0 -#@ set test_default_strobe 40.0 -#@ set test_default_strobe_width 0.0 -#@ set test_default_period 100.0 -#@ set test_stil_max_line_length 72 -#@ -#@ #added for B-2008.09-place_opt-004 to disable this option in ICC -#@ -#@ if { $synopsys_program_name != "icc_shell"} { -#@ set test_write_four_cycle_stil_protocol "false" -#@ set test_protocol_add_cycle "true" -#@ set test_stil_multiclock_capture_procedures "false" -#@ set write_test_new_translation_engine "false" -#@ set test_default_scan_style "multiplexed_flip_flop" -#@ set test_jump_over_bufs_invs "true" -#@ set test_point_keep_hierarchy "false" -#@ set test_mux_constant_so "false" -#@ set test_use_test_models "false" -#@ set test_stil_netlist_format "db" -#@ group_variable test "test_protocol_add_cycle" -#@ group_variable test "test_write_four_cycle_stil_protocol" -#@ group_variable test "test_stil_multiclock_capture_procedures" -#@ group_variable test "test_default_scan_style" -#@ group_variable preview_scan "test_jump_over_bufs_invs" -#@ group_variable insert_dft "test_point_keep_hierarchy" -#@ group_variable insert_dft "test_mux_constant_so" -#@ group_variable test "test_stil_netlist_format" -#@ } -#@ set test_rtldrc_latch_check_style "default" -#@ set test_enable_capture_checks "true" -#@ set ctldb_use_old_prot_flow "false" -#@ set test_bsd_default_delay 0.0 -#@ set test_bsd_default_bidir_delay 0.0 -#@ set test_bsd_default_strobe 95.0 -#@ set test_bsd_default_strobe_width 0.0 -#@ -#@ # -#@ # Test Variable Group: -#@ # -#@ # These variables affects the set_scan_state command. -#@ # -#@ -#@ set compile_seqmap_identify_shift_registers_with_synchronous_logic_ascii false -#@ -#@ # -#@ # Write_Test Variable Group: -#@ # -#@ # These variables affect output of the WRITE_TEST command. -#@ # -#@ set write_test_input_dont_care_value "X" -#@ set write_test_vector_file_naming_style "%s_%d.%s" -#@ set write_test_scan_check_file_naming_style "%s_schk.%s" -#@ set write_test_pattern_set_naming_style "TC_Syn_%d" -#@ set write_test_max_cycles 0 -#@ set write_test_max_scan_patterns 0 -#@ # /*retain "tssi_ascii" (equivalent to "tds") for backward compatability */ -#@ set write_test_formats {synopsys tssi_ascii tds verilog vhdl wgl} -#@ set write_test_include_scan_cell_info "true" -#@ set write_test_round_timing_values "true" -#@ -#@ -#@ # -#@ # Schematic and EDIF and Hdl Variable Groups: -#@ # -#@ # These variables affect the schematics created by the -#@ # create_schematic command, define the behavior of the -#@ # DC system EDIF interface, and are for controlling hdl -#@ # reading. -#@ # -#@ set bus_dimension_separator_style {][} -#@ set bus_naming_style {%s[%d]} -#@ -#@ -#@ # -#@ # Schematic and EDIF Variable Groups: -#@ # -#@ # These variables affect the schematics created by the -#@ # create_schematic command and define the behavior of -#@ # the DC system EDIF interface. -#@ # -#@ set bus_range_separator_style ":" -#@ -#@ -#@ # -#@ # EDIF and Io Variable Groups: -#@ # -#@ # These variables define the behavior of the DC system EDIF interface and -#@ # define the behavior of the DC system interfaces, i.e. LSI, Mentor, TDL, SGE,# etc. -#@ -#@ set bus_inference_descending_sort "true" -#@ set bus_inference_style "" -#@ set write_name_nets_same_as_ports "false" -#@ # -#@ # Schematic Variable Group: -#@ # -#@ # These variables affect the schematics created by the -#@ # create_schematic command. -#@ # -#@ set font_library "1_25.font" -#@ set generic_symbol_library "generic.sdb" -#@ -#@ # -#@ # Io Variable Group: -#@ # -#@ # These variables define the behavior of the DC system -#@ # interfaces, i.e. LSI, Mentor, TDL, SGE, etc. -#@ # -#@ #set db2sge_output_directory "" -#@ #set db2sge_scale "2" -#@ #set db2sge_overwrite "true" -#@ #set db2sge_display_symbol_names "false" -#@ -#@ -#@ #set db2sge_display_pin_names "false" -#@ #set db2sge_display_instance_names "false" -#@ #set db2sge_use_bustaps "false" -#@ #set db2sge_use_compound_names "true" -#@ #set db2sge_bit_type "std_logic" -#@ #set db2sge_bit_vector_type "std_logic_vector" -#@ #set db2sge_one_name "'1'" -#@ #set db2sge_zero_name "'0'" -#@ #set db2sge_unknown_name "'X'" -#@ #set db2sge_target_xp "false" -#@ #set db2sge_tcf_package_file "synopsys_tcf.vhd" -#@ #set db2sge_use_lib_section "" -#@ #set db2sge_script "" -#@ #set db2sge_command "" -#@ -#@ # set equationout_and_sign "*" -#@ # set equationout_or_sign "+" -#@ # set equationout_postfix_negation "true" -#@ -#@ # # [wjchen] 2006/08/14: The following variables are obsoleted for DC simpilification. -#@ #set lsiin_net_name_prefix "NET_" -#@ #set lsiout_inverter_cell "" -#@ #set lsiout_upcase "true" -#@ -#@ #set mentor_bidirect_value "INOUT" -#@ #set mentor_do_path "" -#@ #set mentor_input_output_property_name "PINTYPE" -#@ #set mentor_input_value "IN" -#@ #set mentor_logic_one_value "1SF" -#@ #set mentor_logic_zero_one_property_name "INIT" -#@ #set mentor_logic_zero_value "0SF" -#@ #set mentor_output_value "OUT" -#@ #set mentor_primitive_property_name "PRIMITIVE" -#@ #set mentor_primitive_property_value "MODULE" -#@ #set mentor_reference_property_name "COMP" -#@ #set mentor_search_path "" -#@ #set mentor_write_symbols "true" -#@ -#@ ## [wjchen] 0606_simp -#@ #set pla_read_create_flip_flop "false" -#@ #set tdlout_upcase "true" -#@ -#@ # # [wjchen] 2006/08/14: The following4 variables are obsoleted for DC simpilification. -#@ # set xnfout_constraints_per_endpoint "50" -#@ # set xnfout_default_time_constraints true -#@ # set xnfout_clock_attribute_style "CLK_ONLY" -#@ # set xnfout_library_version "" -#@ -#@ # # [wjchen] 2006/08/11: The following 8 variables are obsoleted for DC simpilification. -#@ # set xnfin_family "4000" -#@ # set xnfin_ignore_pins "GTS GSR GR" -#@ # set xnfin_dff_reset_pin_name "RD" -#@ # set xnfin_dff_set_pin_name "SD" -#@ # set xnfin_dff_clock_enable_pin_name "CE" -#@ # set xnfin_dff_data_pin_name "D" -#@ # set xnfin_dff_clock_pin_name "C" -#@ # set xnfin_dff_q_pin_name "Q" -#@ # -#@ -#@ # -#@ # EDIF Variable Group: -#@ # -#@ # These variables define the behavior of the DC system -#@ # EDIF interface. -#@ # -#@ -#@ ##[wjchen] 2006/08/24 -#@ -#@ # set bus_extraction_style {%s[%d:%d]} -#@ -#@ ##[wjchen] 2006/08/24 -#@ #set edifin_autoconnect_offpageconnectors "false" -#@ #set edifin_autoconnect_ports "false" -#@ #set edifin_dc_script_flag "" -#@ #set edifin_delete_empty_cells "true" -#@ #set edifin_delete_ripper_cells "true" -#@ #set edifin_ground_net_name "" -#@ #set edifin_ground_net_property_name "" -#@ #set edifin_ground_net_property_value "" -#@ #set edifin_ground_port_name "" -#@ #set edifin_instance_property_name "" -#@ #set edifin_portinstance_disabled_property_name "" -#@ #set edifin_portinstance_disabled_property_value "" -#@ #set edifin_portinstance_property_name "" -#@ #set edifin_power_net_name "" -#@ #set edifin_power_net_property_name "" -#@ #set edifin_power_net_property_value "" -#@ #set edifin_power_port_name "" -#@ #set edifin_use_identifier_in_rename "false" -#@ #set edifin_view_identifier_property_name "" -#@ #set edifin_lib_logic_1_symbol "" -#@ #set edifin_lib_logic_0_symbol "" -#@ #set edifin_lib_in_port_symbol "" -#@ #set edifin_lib_out_port_symbol "" -#@ #set edifin_lib_inout_port_symbol "" -#@ #set edifin_lib_in_osc_symbol "" -#@ #set edifin_lib_out_osc_symbol "" -#@ #set edifin_lib_inout_osc_symbol "" -#@ #set edifin_lib_mentor_netcon_symbol "" -#@ #set edifin_lib_ripper_bits_property "" -#@ #set edifin_lib_ripper_bus_end "" -#@ #set edifin_lib_ripper_cell_name "" -#@ #set edifin_lib_ripper_view_name "" -#@ #set edifin_lib_route_grid 1024 -#@ #set edifin_lib_templates {} -#@ #set edifout_dc_script_flag "" -#@ #set edifout_design_name "Synopsys_edif" -#@ #set edifout_designs_library_name "DESIGNS" -#@ #set edifout_display_instance_names "false" -#@ #set edifout_display_net_names "false" -#@ #set edifout_external "true" -#@ #set edifout_external_graphic_view_name "Graphic_representation" -#@ #set edifout_external_netlist_view_name "Netlist_representation" -#@ #set edifout_external_schematic_view_name "Schematic_representation" -#@ #set edifout_ground_name "logic_0" -#@ #set edifout_ground_net_name "" -#@ #set edifout_ground_net_property_name "" -#@ #set edifout_ground_net_property_value "" -#@ #set edifout_ground_pin_name "logic_0_pin" -#@ #set edifout_ground_port_name "GND" -#@ #set edifout_instance_property_name "" -#@ #set edifout_instantiate_ports "false" -#@ #set edifout_library_graphic_view_name "Graphic_representation" -#@ #set edifout_library_netlist_view_name "Netlist_representation" -#@ #set edifout_library_schematic_view_name "Schematic_representation" -#@ #set edifout_merge_libraries "false" -#@ #set edifout_multidimension_arrays "false" -#@ #set edifout_name_oscs_different_from_ports "false" -#@ #set edifout_name_rippers_same_as_wires "false" -#@ #set edifout_netlist_only "false" -#@ #set edifout_no_array "false" -#@ #set edifout_numerical_array_members "false" -#@ #set edifout_pin_direction_in_value "" -#@ #set edifout_pin_direction_inout_value "" -#@ #set edifout_pin_direction_out_value "" -#@ #set edifout_pin_direction_property_name "" -#@ #set edifout_pin_name_property_name "" -#@ #set edifout_portinstance_disabled_property_name "" -#@ #set edifout_portinstance_disabled_property_value "" -#@ #set edifout_portinstance_property_name "" -#@ #set edifout_power_and_ground_representation "cell" -#@ #set edifout_power_name "logic_1" -#@ #set edifout_power_net_name "" -#@ #set edifout_power_net_property_name "" -#@ #set edifout_power_net_property_value "" -#@ #set edifout_power_pin_name "logic_1_pin" -#@ #set edifout_power_port_name "VDD" -#@ #set edifout_skip_port_implementations "false" -#@ #set edifout_target_system "" -#@ #set edifout_top_level_symbol "true" -#@ #set edifout_translate_origin "" -#@ #set edifout_unused_property_value "" -#@ #set edifout_write_attributes "false" -#@ #set edifout_write_constraints "false" -#@ #set edifout_write_properties_list {} -#@ #set read_name_mapping_nowarn_libraries {} -#@ #set write_name_mapping_nowarn_libraries {} -#@ -#@ # -#@ # Hdl and Vhdlio Variable Groups: -#@ # -#@ # These variables are for controlling hdl reading, writing, -#@ # and optimizing. -#@ # -#@ set hdlin_enable_upf_compatible_naming "FALSE" -#@ set hdlin_auto_save_templates "FALSE" -#@ set hdlin_generate_naming_style "%s_%d" -#@ set hdlin_enable_relative_placement "rb" -#@ set hdlin_mux_rp_limit "128x4" -#@ set hdlin_generate_separator_style "_" -#@ set hdlin_ignore_textio_constructs "TRUE" -#@ set hdlin_infer_function_local_latches "FALSE" -#@ set hdlin_keep_signal_name "all_driving" -#@ set hdlin_module_arch_name_splitting "FALSE" -#@ set hdlin_preserve_sequential "none" -#@ set hdlin_presto_net_name_prefix "N" -#@ set hdlin_presto_cell_name_prefix "C" -#@ set hdlin_strict_verilog_reader "FALSE" -#@ set hdlin_prohibit_nontri_multiple_drivers "TRUE" -#@ if { $synopsys_program_name == "de_shell" } { -#@ set hdlin_elab_errors_deep "TRUE" -#@ } else { -#@ set hdlin_elab_errors_deep "FALSE" -#@ } -#@ set hdlin_mux_size_min 2 -#@ set hdlin_subprogram_default_values "FALSE" -#@ set hdlin_field_naming_style "" -#@ set hdlin_upcase_names "FALSE" -#@ set hdlin_sv_union_member_naming "FALSE" -#@ set hdlin_vhdl_std 2008 -#@ set hdlin_vhdl93_concat "TRUE" -#@ set hdlin_vhdl_syntax_extensions "FALSE" -#@ set hdlin_analyze_verbose_mode 0 -#@ set hdlin_report_sequential_pruning "FALSE" -#@ set hdlin_vrlg_std 2005 -#@ set hdlin_sverilog_std 2012 -#@ set hdlin_while_loop_iterations 4096 -#@ set hdlin_reporting_level "basic" -#@ set hdlin_autoread_verilog_extensions ".v" -#@ set hdlin_autoread_sverilog_extensions ".sv .sverilog" -#@ set hdlin_autoread_vhdl_extensions ".vhd .vhdl" -#@ set hdlin_autoread_exclude_extensions "" -#@ -#@ set bus_minus_style "-%d" -#@ set hdlin_latch_always_async_set_reset FALSE -#@ set hdlin_ff_always_sync_set_reset FALSE -#@ set hdlin_ff_always_async_set_reset TRUE -#@ set hdlin_check_input_netlist FALSE -#@ set hdlin_check_no_latch FALSE -#@ set hdlin_mux_for_array_read_sparseness_limit 90 -#@ set hdlin_infer_mux "default" -#@ set hdlin_mux_oversize_ratio 100 -#@ set hdlin_mux_size_limit 32 -#@ set hdlin_mux_size_only 1 -#@ set hdlin_infer_multibit "default_none" -#@ set hdlin_enable_rtldrc_info "false" -#@ set hdlin_interface_port_ABI 3 -#@ set hdlin_shorten_long_module_name "false" -#@ set hdlin_module_name_limit 256 -#@ set hdlin_enable_assertions "FALSE" -#@ set hdlin_enable_configurations "FALSE" -#@ set hdlin_sv_blackbox_modules "" -#@ set hdlin_sv_tokens "FALSE" -#@ set hdlin_sv_packages "enable" -#@ set hdlin_verification_priority "FALSE" -#@ set hdlin_enable_elaborate_ref_linking "FALSE" -#@ set hdlin_enable_hier_naming "FALSE" -#@ set hdlin_vhdl_mixed_language_instantiation "FALSE" -#@ set hdl_preferred_license "" -#@ set hdl_keep_licenses "true" -#@ set hlo_resource_allocation "constraint_driven" -#@ set sdfout_top_instance_name "" -#@ set sdfout_time_scale 1.0 -#@ set sdfout_min_rise_net_delay 0. -#@ set sdfout_min_fall_net_delay 0. -#@ set sdfout_min_rise_cell_delay 0. -#@ set sdfout_min_fall_cell_delay 0. -#@ set sdfout_write_to_output "false" -#@ set sdfout_allow_non_positive_constraints "false" -#@ set sdfin_top_instance_name "" -#@ set sdfin_min_rise_net_delay 0. -#@ set sdfin_min_fall_net_delay 0. -#@ set sdfin_min_rise_cell_delay 0. -#@ set sdfin_min_fall_cell_delay 0. -#@ set sdfin_rise_net_delay_type "maximum" -#@ set sdfin_fall_net_delay_type "maximum" -#@ set sdfin_rise_cell_delay_type "maximum" -#@ set sdfin_fall_cell_delay_type "maximum" -#@ set site_info_file ${synopsys_root}/admin/license/site_info -#@ if { [string compare $dc_shell_mode "tcl"] == 0 } { -#@ alias site_info sh cat $site_info_file -#@ } else { -#@ alias site_info "sh cat site_info_file" -#@ } -#@ set template_naming_style "%s_%p" -#@ set template_parameter_style "%s%d" -#@ set template_separator_style "_" -#@ set verilogout_equation "false" -#@ set verilogout_ignore_case "false" -#@ set verilogout_no_tri "false" -#@ set verilogout_inout_is_in "false" -#@ set verilogout_single_bit "false" -#@ set verilogout_higher_designs_first "FALSE" -#@ # set verilogout_levelize "FALSE" -#@ set verilogout_include_files {} -#@ set verilogout_unconnected_prefix "SYNOPSYS_UNCONNECTED_" -#@ set verilogout_show_unconnected_pins "FALSE" -#@ set verilogout_no_negative_index "FALSE" -#@ #set enable_2003.03_verilog_reader TRUE -#@ # to have a net instead of 1'b0 and 1'b1 in inouts: -#@ set verilogout_indirect_inout_connection "FALSE" -#@ -#@ # set vhdlout_architecture_name "SYN_%a_%u" -#@ set vhdlout_bit_type "std_logic" -#@ # set vhdlout_bit_type_resolved "TRUE" -#@ set vhdlout_bit_vector_type "std_logic_vector" -#@ # set vhdlout_conversion_functions {} -#@ # set vhdlout_dont_write_types "FALSE" -#@ set vhdlout_equations "FALSE" -#@ set vhdlout_one_name "'1'" -#@ set vhdlout_package_naming_style "CONV_PACK_%d" -#@ set vhdlout_preserve_hierarchical_types "VECTOR" -#@ set vhdlout_separate_scan_in "FALSE" -#@ set vhdlout_single_bit "USER" -#@ set vhdlout_target_simulator "" -#@ set vhdlout_three_state_name "'Z'" -#@ set vhdlout_three_state_res_func "" -#@ # set vhdlout_time_scale 1.0 -#@ set vhdlout_top_configuration_arch_name "A" -#@ set vhdlout_top_configuration_entity_name "E" -#@ set vhdlout_top_configuration_name "CFG_TB_E" -#@ set vhdlout_unknown_name "'X'" -#@ set vhdlout_upcase "FALSE" -#@ set vhdlout_use_packages {IEEE.std_logic_1164} -#@ set vhdlout_wired_and_res_func "" -#@ set vhdlout_wired_or_res_func "" -#@ set vhdlout_write_architecture "TRUE" -#@ set vhdlout_write_components "TRUE" -#@ set vhdlout_write_entity "TRUE" -#@ set vhdlout_write_top_configuration "FALSE" -#@ # set vhdlout_synthesis_off "TRUE" -#@ set vhdlout_zero_name "'0'" -#@ #set vhdlout_levelize "FALSE" -#@ set vhdlout_dont_create_dummy_nets "FALSE" -#@ set vhdlout_follow_vector_direction "TRUE" -#@ -#@ -#@ # vhdl netlist reader variables -#@ set enable_vhdl_netlist_reader "FALSE" -#@ -#@ # variables pertaining to VHDL library generation -#@ set vhdllib_timing_mesg "true" -#@ set vhdllib_timing_xgen "false" -#@ set vhdllib_timing_checks "true" -#@ set vhdllib_negative_constraint "false" -#@ set vhdllib_glitch_handle "true" -#@ set vhdllib_pulse_handle "use_vhdllib_glitch_handle" -#@ # /*vhdllib_architecture = {FTBM, UDSM, FTSM, FTGS, VITAL}; */ -#@ set vhdllib_architecture {VITAL} -#@ set vhdllib_tb_compare 0 -#@ set vhdllib_tb_x_eq_dontcare FALSE -#@ set vhdllib_logic_system "ieee-1164" -#@ set vhdllib_logical_name "" -#@ -#@ # variables pertaining to technology library processing -#@ set read_db_lib_warnings FALSE -#@ set read_translate_msff TRUE -#@ set libgen_max_differences -1 -#@ -#@ # -#@ # Gui Variable Group -#@ # used for design_vision and psyn_gui -#@ # -#@ set gui_auto_start 0 -#@ set gui_start_option_no_windows 0 -#@ group_variable gui_variables "gui_auto_start" -#@ group_variable gui_variables "gui_start_option_no_windows" -#@ -#@ # -#@ # If you like emacs, uncomment the next line -#@ # set text_editor_command "emacs -fn 8x13 %s &" ; -#@ -#@ # You can delete pairs from this list, but you can't add new ones -#@ # unless you also update the UIL files. So, customers can not add -#@ # dialogs to this list, only Synopsys can do that. -#@ # -#@ set view_independent_dialogs { "test_report" " Test Reports " "report_print" " Report " "report_options" " Report Options " "report_win" " Report Output " "manual_page" " Manual Page " } -#@ -#@ # if color Silicon Graphics workstation -#@ if { [info exists x11_vendor_string] && [info exists x11_is_color]} { -#@ if { $x11_vendor_string == "Silicon" && $x11_is_color == "true" } { -#@ set x11_set_cursor_foreground "magenta" -#@ set view_use_small_cursor "true" -#@ set view_set_selecting_color "white" -#@ } -#@ } -#@ -#@ # if running on an Apollo machine -#@ set found_x11_vendor_string_apollo 0 -#@ set found_arch_apollo 0 -#@ if { [info exists x11_vendor_string]} { -#@ if { $x11_vendor_string == "Apollo "} { -#@ set found_x11_vendor_string_apollo 1 -#@ } -#@ } -#@ if { [info exists arch]} { -#@ if { $arch == "apollo"} { -#@ set found_arch_apollo 1 -#@ } -#@ } -#@ if { $found_x11_vendor_string_apollo == 1 || $found_arch_apollo == 1} { -#@ set enable_page_mode "false" -#@ } else { -#@ set enable_page_mode "true" -#@ } -#@ -#@ # don't work around this bug on the Apollo -#@ if { $found_x11_vendor_string_apollo == 1} { -#@ set view_extend_thick_lines "false" -#@ } else { -#@ set view_extend_thick_lines "true" -#@ } -#@ -#@ # -#@ # Suffix Variable Group: -#@ # -#@ # Suffixes recognized by the Design Analyzer menu in file choices -#@ # -#@ if { $synopsys_program_name == "design_vision" || $synopsys_program_name == "psyn_gui" } { -#@ # For star 93040 do NOT include NET in list, 108991 : pdb suffix added -#@ set view_read_file_suffix {db gdb sdb pdb edif eqn fnc lsi mif pla st tdl v vhd vhdl xnf} -#@ } else { -#@ set view_read_file_suffix {db gdb sdb edif eqn fnc lsi mif NET pla st tdl v vhd vhdl xnf} -#@ } -#@ -#@ set view_analyze_file_suffix {v vhd vhdl} -#@ set view_write_file_suffix {gdb db sdb do edif eqn fnc lsi NET neted pla st tdl v vhd vhdl xnf} -#@ set view_execute_script_suffix {.script .scr .dcs .dcv .dc .con} -#@ set view_arch_types {sparcOS5 hpux10 rs6000 sgimips} -#@ -#@ # -#@ # links_to_layout Variable Group: -#@ # -#@ # These variables affect the read_timing, write_timing -#@ # set_annotated_delay, compile, create_wire_load and reoptimize_design -#@ # commands. -#@ # -#@ if {$synopsys_program_name != "dc_sms_shell"} { -#@ set auto_wire_load_selection "true" -#@ set compile_create_wire_load_table "false" -#@ } -#@ set rtl_load_resistance_factor 0.0 -#@ -#@ # power Variable Group: -#@ # -#@ # These variables affect the behavior of power optimization and analysis. -#@ # -#@ -#@ set power_keep_license_after_power_commands "false" -#@ set power_rtl_saif_file "power_rtl.saif" -#@ set power_sdpd_saif_file "power_sdpd.saif" -#@ set power_preserve_rtl_hier_names "false" -#@ set power_do_not_size_icg_cells "true" -#@ set power_hdlc_do_not_split_cg_cells "false" -#@ set power_cg_flatten "false" -#@ set power_opto_extra_high_dynamic_power_effort "false" -#@ set power_default_static_probability 0.5 -#@ set power_default_toggle_rate 0.1 -#@ set power_default_toggle_rate_type "fastest_clock" -#@ set power_model_preference "nlpm" -#@ set power_sa_propagation_effort "low" -#@ set power_sa_propagation_verbose "false" -#@ set power_fix_sdpd_annotation "true" -#@ set power_fix_sdpd_annotation_verbose "false" -#@ set power_sdpd_message_tolerance 0.00001 -#@ set do_operand_isolation "false" -#@ set power_cg_module_naming_style "" -#@ set power_cg_cell_naming_style "" -#@ set power_cg_gated_clock_net_naming_style "" -#@ set power_rclock_use_asynch_inputs "false" -#@ set power_rclock_inputs_use_clocks_fanout "true" -#@ set power_rclock_unrelated_use_fastest "true" -#@ set power_lib2saif_rise_fall_pd "false" -#@ set power_min_internal_power_threshold "" -#@ -#@ -#@ # SystemC related variables -#@ set systemcout_levelize "true" -#@ set systemcout_debug_mode "false" -#@ -#@ # ACS Variables -#@ if { [info exists acs_work_dir] } { -#@ set acs_area_report_suffix "area" -#@ set acs_autopart_max_area "0.0" -#@ set acs_autopart_max_percent "0.0" -#@ set acs_budgeted_cstr_suffix "con" -#@ set acs_compile_script_suffix "autoscr" -#@ set acs_constraint_file_suffix "con" -#@ set acs_cstr_report_suffix "cstr" -#@ set acs_db_suffix "db" -#@ set acs_dc_exec "" -#@ set acs_default_pass_name "pass" -#@ set acs_exclude_extensions {} -#@ set acs_exclude_list [list $synopsys_root] -#@ set acs_global_user_compile_strategy_script "default" -#@ set acs_hdl_verilog_define_list {} -#@ set acs_hdl_source {} -#@ set acs_lic_wait 0 -#@ set acs_log_file_suffix "log" -#@ set acs_make_args "set acs_make_args" -#@ set acs_make_exec "gmake" -#@ set acs_makefile_name "Makefile" -#@ set acs_num_parallel_jobs 1 -#@ set acs_override_report_suffix "report" -#@ set acs_override_script_suffix "scr" -#@ set acs_qor_report_suffix "qor" -#@ set acs_timing_report_suffix "tim" -#@ set acs_use_autopartition "false" -#@ set acs_use_default_delays "false" -#@ set acs_user_budgeting_script "budget.scr" -#@ set acs_user_compile_strategy_script_suffix "compile" -#@ set acs_verilog_extensions {.v} -#@ set acs_vhdl_extensions {.vhd} -#@ set acs_work_dir [pwd] -#@ set check_error_list [list CMD-004 CMD-006 CMD-007 CMD-008 CMD-009 CMD-010 CMD-011 CMD-012 CMD-014 CMD-015 CMD-016 CMD-019 CMD-026 CMD-031 CMD-037 DB-1 DCSH-11 DES-001 ACS-193 FILE-1 FILE-2 FILE-3 FILE-4 LINK-7 LINT-7 LINT-20 LNK-023 OPT-100 OPT-101 OPT-102 OPT-114 OPT-124 OPT-127 OPT-128 OPT-155 OPT-157 OPT-181 OPT-462 UI-11 UI-14 UI-15 UI-16 UI-17 UI-19 UI-20 UI-21 UI-22 UI-23 UI-40 UI-41 UID-4 UID-6 UID-7 UID-8 UID-9 UID-13 UID-14 UID-15 UID-19 UID-20 UID-25 UID-27 UID-28 UID-29 UID-30 UID-32 UID-58 UID-87 UID-103 UID-109 UID-270 UID-272 UID-403 UID-440 UID-444 UIO-2 UIO-3 UIO-4 UIO-25 UIO-65 UIO-66 UIO-75 UIO-94 UIO-95 EQN-6 EQN-11 EQN-15 EQN-16 EQN-18 EQN-20 ] -#@ set ilm_preserve_core_constraints "false" -#@ } -#@ -#@ # -#@ # -#@ # DesignTime Variable Group -#@ # -#@ # The variables which affect the DesignTime timing engine -#@ # -#@ -#@ set case_analysis_log_file "" -#@ set case_analysis_sequential_propagate "false" -#@ set create_clock_no_input_delay "false" -#@ set disable_auto_time_borrow "false" -#@ set disable_case_analysis "false" -#@ set disable_conditional_mode_analysis "false" -#@ set disable_library_transition_degradation "false" -#@ set dont_bind_unused_pins_to_logic_constant "false" -#@ set enable_slew_degradation "true" -#@ set high_fanout_net_pin_capacitance 1.000000 -#@ set high_fanout_net_threshold 1000 -#@ set lib_thresholds_per_lib "true" -#@ set rc_adjust_rd_when_less_than_rnet "true" -#@ set rc_ceff_delay_min_diff_ps 0.250000 -#@ set rc_degrade_min_slew_when_rd_less_than_rnet "false" -#@ set rc_driver_model_max_error_pct 0.160000 -#@ set rc_filter_rd_less_than_rnet "true" -#@ set rc_input_threshold_pct_fall 50.000000 -#@ set rc_input_threshold_pct_rise 50.000000 -#@ set rc_output_threshold_pct_fall 50.000000 -#@ set rc_output_threshold_pct_rise 50.000000 -#@ set rc_rd_less_than_rnet_threshold 0.450000 -#@ set rc_slew_derate_from_library 1.000000 -#@ set rc_slew_lower_threshold_pct_fall 20.000000 -#@ set rc_slew_lower_threshold_pct_rise 20.000000 -#@ set rc_slew_upper_threshold_pct_fall 80.000000 -#@ set rc_slew_upper_threshold_pct_rise 80.000000 -#@ set timing_disable_cond_default_arcs "false" -#@ #timing_enable_multiple_clocks_per_reg is on by default -#@ #set timing_enable_multiple_clocks_per_reg "false" -#@ set timing_report_attributes {dont_touch dont_use map_only size_only ideal_net infeasible_paths} -#@ set timing_self_loops_no_skew "false" -#@ set when_analysis_permitted "true" -#@ set when_analysis_without_case_analysis "false" -#@ -#@ -#@ # -#@ # Variable Group Definitions: -#@ # -#@ # The group_variable() command groups variables for display -#@ # in the "File/Defaults" dialog and defines groups of variables -#@ # for the list() command. -#@ # -#@ -#@ set enable_instances_in_report_net "true" -#@ # Set report options env variables -#@ set view_report_interactive "true" -#@ set view_report_output2file "false" -#@ set view_report_append "true" -#@ -#@ if { $synopsys_program_name != "ptxr" } { -#@ -#@ group_variable report_variables "enable_instances_in_report_net" -#@ group_variable report_variables "view_report_interactive" -#@ group_variable report_variables "view_report_output2file" -#@ group_variable report_variables "view_report_append" -#@ -#@ # "links_to_layout" variables are used by multiple commands -#@ # auto_wire_load_selection is also in the "compile" variable group. -#@ group_variable links_to_layout "auto_wire_load_selection" -#@ -#@ # variables starting with "compile" are also in the compile variable group -#@ group_variable links_to_layout "compile_dont_touch_annotated_cell_during_inplace_opt" -#@ -#@ group_variable links_to_layout "compile_update_annotated_delays_during_inplace_opt" -#@ group_variable links_to_layout "compile_create_wire_load_table" -#@ -#@ group_variable links_to_layout "reoptimize_design_changed_list_file_name" -#@ group_variable links_to_layout "sdfout_allow_non_positive_constraints" -#@ -#@ } ;# $synopsys_program_name != "ptxr" -#@ -#@ # -#@ # to find the XErrorDB and XKeySymDB for X11 file -#@ set motif_files ${synopsys_root}/admin/setup -#@ # set filename for logging input file -#@ set filename_log_file "filenames.log" -#@ # whether to delete the filename log after the normal exits -#@ set exit_delete_filename_log_file "true" -#@ -#@ # executable to fire off RTLA/BCV -#@ set xterm_executable "xterm" -#@ -#@ if { $synopsys_program_name != "ptxr" } { -#@ -#@ # "system" variables are used by multiple commands -#@ group_variable system auto_link_disable -#@ group_variable system auto_link_options -#@ group_variable system command_log_file -#@ group_variable system company -#@ group_variable system compatibility_version -#@ -#@ if { [string compare $dc_shell_mode "default"] == 0 } { -#@ group_variable system "current_design" -#@ group_variable system "current_instance" -#@ group_variable system "dc_shell_status" -#@ } else { -#@ set current_design "" -#@ set current_instance "" -#@ group_variable system "current_design" -#@ group_variable system "current_instance" -#@ } -#@ -#@ group_variable system "designer" -#@ group_variable system "echo_include_commands" -#@ group_variable system "enable_page_mode" -#@ group_variable system "change_names_update_inst_tree" -#@ group_variable system "change_names_dont_change_bus_members" -#@ group_variable system "default_name_rules" -#@ group_variable system "verbose_messages" -#@ group_variable system "link_library" -#@ group_variable system "link_force_case" -#@ group_variable system "search_path" -#@ group_variable system "synthetic_library" -#@ group_variable system "target_library" -#@ group_variable system "uniquify_naming_style" -#@ group_variable system "suppress_errors" -#@ group_variable system "find_converts_name_lists" -#@ group_variable system "filename_log_file" -#@ group_variable system "exit_delete_filename_log_file" -#@ group_variable system "syntax_check_status" -#@ group_variable system "context_check_status" -#@ -#@ #/* "compile" variables are used by the compile command */ -#@ group_variable compile "compile_assume_fully_decoded_three_state_busses" -#@ group_variable compile "compile_no_new_cells_at_top_level" -#@ group_variable compile "compile_dont_touch_annotated_cell_during_inplace_opt" -#@ group_variable compile "reoptimize_design_changed_list_file_name" -#@ group_variable compile "compile_create_wire_load_table" -#@ group_variable compile "compile_update_annotated_delays_during_inplace_opt" -#@ group_variable compile "compile_instance_name_prefix" -#@ group_variable compile "compile_instance_name_suffix" -#@ group_variable compile "compile_negative_logic_methodology" -#@ group_variable compile "compile_disable_hierarchical_inverter_opt" -#@ -#@ group_variable compile "port_complement_naming_style" -#@ group_variable compile "auto_wire_load_selection" -#@ group_variable compile "rtl_load_resistance_factor" -#@ group_variable compile "compile_implementation_selection" -#@ group_variable compile "compile_use_low_timing_effort" -#@ group_variable compile "compile_fix_cell_degradation" -#@ group_variable compile "compile_preserve_subdesign_interfaces" -#@ group_variable compile "compile_enable_constant_propagation_with_no_boundary_opt" -#@ group_variable compile "compile_delete_unloaded_sequential_cells" -#@ group_variable compile "enable_recovery_removal_arcs" -#@ group_variable compile "compile_checkpoint_phases" -#@ group_variable compile "compile_cpu_limit" -#@ group_variable compile "compile_top_all_paths" -#@ group_variable compile "compile_top_all_paths" -#@ group_variable compile "compile_top_acs_partition" -#@ group_variable compile "default_port_connection_class" -#@ group_variable compile "compile_retime_license_behavior" -#@ group_variable compile "dont_touch_nets_with_size_only_cells" -#@ group_variable compile "compile_seqmap_no_scan_cell" -#@ -#@ if { $synopsys_program_name == "dc_shell" && [shell_is_in_topographical_mode] } { -#@ group_variable compile "dct_prioritize_area_correlation" -#@ group_variable compile "compile_error_on_missing_physical_cells" -#@ } -#@ -#@ # "multibit" variables are used by the the multibit mapping functionality -#@ -#@ group_variable multibit "bus_multiple_separator_style" -#@ -#@ # "ilm" variables are used by Interface Logic Model functionality -#@ -#@ group_variable ilm "ilm_ignore_percentage" -#@ -#@ # "estimate" variables are used by the estimate command -#@ # The estimate command also recognizes the "compile" variables. -#@ group_variable estimate "estimate_resource_preference" -#@ -#@ # "synthetic_library" variables -#@ group_variable synlib "cache_dir_chmod_octal" -#@ group_variable synlib "cache_file_chmod_octal" -#@ group_variable synlib "cache_read" -#@ group_variable synlib "cache_read_info" -#@ group_variable synlib "cache_write" -#@ group_variable synlib "cache_write_info" -#@ group_variable synlib "synlib_dont_get_license" -#@ group_variable synlib "synlib_wait_for_design_license" -#@ group_variable synlib "synthetic_library" -#@ -#@ # "insert_dft" variables are used by the insert_dft and preview_dft commands -#@ #group_variable insert_dft "test_default_client_order" -#@ group_variable insert_dft "insert_dft_clean_up" -#@ group_variable insert_dft "insert_test_design_naming_style" -#@ group_variable insert_dft "test_clock_port_naming_style" -#@ group_variable insert_dft "test_default_min_fault_coverage" -#@ group_variable insert_dft "test_scan_clock_a_port_naming_style" -#@ group_variable insert_dft "test_scan_clock_b_port_naming_style" -#@ group_variable insert_dft "test_scan_clock_port_naming_style" -#@ group_variable insert_dft "test_scan_enable_inverted_port_naming_style" -#@ group_variable insert_dft "test_scan_enable_port_naming_style" -#@ group_variable insert_dft "test_scan_in_port_naming_style" -#@ group_variable insert_dft "test_scan_out_port_naming_style" -#@ group_variable insert_dft "test_non_scan_clock_port_naming_style" -#@ group_variable insert_dft "test_dedicated_subdesign_scan_outs" -#@ group_variable insert_dft "test_disable_find_best_scan_out" -#@ group_variable insert_dft "test_dont_fix_constraint_violations" -#@ group_variable insert_dft "test_isolate_hier_scan_out" -#@ group_variable insert_dft "test_mode_port_naming_style" -#@ group_variable insert_dft "test_mode_port_inverted_naming_style" -#@ group_variable insert_dft "compile_dont_use_dedicated_scanout" -#@ group_variable insert_dft "test_mux_constant_si" -#@ -#@ # "preview_scan" variables are used by the preview_scan command -#@ group_variable preview_scan "test_preview_scan_shows_cell_types" -#@ group_variable preview_scan "test_scan_link_so_lockup_key" -#@ group_variable preview_scan "test_scan_link_wire_key" -#@ group_variable preview_scan "test_scan_segment_key" -#@ group_variable preview_scan "test_scan_true_key" -#@ -#@ # "bsd" variables are used by the check_bsd and write_bsdl commands -#@ group_variable bsd "test_user_test_data_register_naming_style" -#@ group_variable bsd "test_user_defined_instruction_naming_style" -#@ group_variable bsd "test_bsdl_default_suffix_name" -#@ group_variable bsd "test_bsdl_max_line_length" -#@ group_variable bsd "test_cc_ir_masked_bits" -#@ group_variable bsd "test_cc_ir_value_of_masked_bits" -#@ -#@ group_variable bsd "test_bsd_allow_tolerable_violations" -#@ group_variable bsd "test_bsd_optimize_control_cell" -#@ group_variable bsd "test_bsd_control_cell_drive_limit" -#@ group_variable bsd "test_bsd_manufacturer_id" -#@ group_variable bsd "test_bsd_part_number" -#@ group_variable bsd "test_bsd_version_number" -#@ group_variable bsd "bsd_max_in_switching_limit" -#@ group_variable bsd "bsd_max_out_switching_limit" -#@ -#@ # testmanager variables -#@ group_variable testmanager "multi_pass_test_generation" -#@ -#@ # "testsim" variables -#@ # group_variable testsim "testsim_print_stats_file" -#@ -#@ # "test" variables -#@ group_variable test "test_default_bidir_delay" -#@ group_variable test "test_default_delay" -#@ group_variable test "test_default_period" -#@ group_variable test "test_default_strobe" -#@ group_variable test "test_default_strobe_width" -#@ group_variable test "test_capture_clock_skew" -#@ group_variable test "test_allow_clock_reconvergence" -#@ group_variable test "test_check_port_changes_in_capture" -#@ group_variable test "test_stil_max_line_length" -#@ group_variable test "test_infer_slave_clock_pulse_after_capture" -#@ group_variable test "test_rtldrc_latch_check_style" -#@ group_variable test "test_enable_capture_checks" -#@ -#@ # "write_test" variables are used by the write_test command -#@ group_variable write_test "write_test_formats" -#@ group_variable write_test "write_test_include_scan_cell_info" -#@ group_variable write_test "write_test_input_dont_care_value" -#@ group_variable write_test "write_test_max_cycles" -#@ group_variable write_test "write_test_max_scan_patterns" -#@ group_variable write_test "write_test_pattern_set_naming_style" -#@ group_variable write_test "write_test_scan_check_file_naming_style" -#@ group_variable write_test "write_test_vector_file_naming_style" -#@ group_variable write_test "write_test_round_timing_values" -#@ -#@ group_variable view "test_design_analyzer_uses_insert_scan" -#@ -#@ # "io" variables are used by the read, read_lib, db2sge and write commands -#@ group_variable io "bus_inference_descending_sort" -#@ group_variable io "bus_inference_style" -#@ #group_variable io "db2sge_output_directory" -#@ #group_variable io "db2sge_scale" -#@ #group_variable io "db2sge_overwrite" -#@ #group_variable io "db2sge_display_symbol_names" -#@ #group_variable io "db2sge_display_pin_names" -#@ #group_variable io "db2sge_display_instance_names" -#@ #group_variable io "db2sge_use_bustaps" -#@ #group_variable io "db2sge_use_compound_names" -#@ #group_variable io "db2sge_bit_type" -#@ #group_variable io "db2sge_bit_vector_type" -#@ #group_variable io "db2sge_one_name" -#@ #group_variable io "db2sge_zero_name" -#@ #group_variable io "db2sge_unknown_name" -#@ #group_variable io "db2sge_target_xp" -#@ #group_variable io "db2sge_tcf_package_file" -#@ #group_variable io "db2sge_use_lib_section" -#@ #group_variable io "db2sge_script" -#@ #group_variable io "db2sge_command" -#@ -#@ # group_variable io "equationout_and_sign" -#@ # group_variable io "equationout_or_sign" -#@ # group_variable io "equationout_postfix_negation" -#@ -#@ # group_variable io "lsiin_net_name_prefix" -#@ # group_variable io "lsiout_inverter_cell" -#@ # group_variable io "lsiout_upcase" -#@ -#@ #group_variable io "mentor_bidirect_value" -#@ #group_variable io "mentor_do_path" -#@ #group_variable io "mentor_input_output_property_name" -#@ #group_variable io "mentor_input_value" -#@ #group_variable io "mentor_logic_one_value" -#@ #group_variable io "mentor_logic_zero_one_property_name" -#@ #group_variable io "mentor_logic_zero_value" -#@ #group_variable io "mentor_output_value" -#@ #group_variable io "mentor_primitive_property_name" -#@ #group_variable io "mentor_primitive_property_value" -#@ #group_variable io "mentor_reference_property_name" -#@ #group_variable io "mentor_search_path" -#@ #group_variable io "mentor_write_symbols" -#@ # group_variable io "pla_read_create_flip_flop" -#@ # group_variable io "tdlout_upcase" -#@ group_variable io "write_name_nets_same_as_ports" -#@ -#@ # # [wjchen] 2006/08/14: The following 4 variables are obsoleted for DC simpilification. -#@ -#@ # group_variable io "xnfout_constraints_per_endpoint" -#@ # group_variable io "xnfout_default_time_constraints" -#@ # group_variable io "xnfout_clock_attribute_style" -#@ # group_variable io "xnfout_library_version" -#@ -#@ # # [wjchen] 2006/08/11: The following 8 variables are obsoleted for DC simpilification. -#@ # group_variable io "xnfin_family" -#@ # group_variable io "xnfin_ignore_pins" -#@ # group_variable io "xnfin_dff_reset_pin_name" -#@ # group_variable io "xnfin_dff_set_pin_name" -#@ # group_variable io "xnfin_dff_clock_enable_pin_name" -#@ # group_variable io "xnfin_dff_data_pin_name" -#@ # group_variable io "xnfin_dff_clock_pin_name" ; -#@ # group_variable io "xnfin_dff_q_pin_name"; -#@ -#@ group_variable io "sdfin_min_rise_net_delay" ; -#@ group_variable io "sdfin_min_fall_net_delay" ; -#@ group_variable io "sdfin_min_rise_cell_delay" ; -#@ group_variable io "sdfin_min_fall_cell_delay" ; -#@ group_variable io "sdfin_rise_net_delay_type" ; -#@ group_variable io "sdfin_fall_net_delay_type" ; -#@ group_variable io "sdfin_rise_cell_delay_type" ; -#@ group_variable io "sdfin_fall_cell_delay_type" ; -#@ group_variable io "sdfin_top_instance_name" ; -#@ group_variable io "sdfout_time_scale" ; -#@ group_variable io "sdfout_write_to_output" ; -#@ group_variable io "sdfout_top_instance_name" ; -#@ group_variable io "sdfout_min_rise_net_delay" ; -#@ group_variable io "sdfout_min_fall_net_delay" ; -#@ group_variable io "sdfout_min_rise_cell_delay" ; -#@ group_variable io "sdfout_min_fall_cell_delay" ; -#@ group_variable io "read_db_lib_warnings" ; -#@ group_variable io "read_translate_msff" ; -#@ group_variable io "libgen_max_differences" ; -#@ -#@ # #[wjchen] 2006/08/22: The following variables are hidden for XG mode for DC simpilification. -#@ # group_variable io "read_name_mapping_nowarn_libraries" ; -#@ # group_variable io "write_name_mapping_nowarn_libraries" ; -#@ -#@ -#@ # "edif" variables are used by the EDIF format read, read_lib, write, -#@ # and write_lib commands -#@ # group_variable edif "bus_dimension_separator_style" ; -#@ # group_variable edif "bus_extraction_style" ; -#@ group_variable edif "bus_inference_descending_sort" ; -#@ group_variable edif "bus_inference_style" ; -#@ group_variable edif "bus_naming_style" ; -#@ group_variable edif "bus_range_separator_style" ; -#@ # group_variable edif "edifin_autoconnect_offpageconnectors" ; -#@ # group_variable edif "edifin_autoconnect_ports" ; -#@ # group_variable edif "edifin_delete_empty_cells" ; -#@ # group_variable edif "edifin_delete_ripper_cells" ; -#@ # group_variable edif "edifin_ground_net_name" ; -#@ # group_variable edif "edifin_ground_net_property_name" ; -#@ # group_variable edif "edifin_ground_net_property_value" ; -#@ # group_variable edif "edifin_ground_port_name" ; -#@ # group_variable edif "edifin_instance_property_name" ; -#@ # group_variable edif "edifin_portinstance_disabled_property_name" ; -#@ # group_variable edif "edifin_portinstance_disabled_property_value" ; -#@ # group_variable edif "edifin_portinstance_property_name" ; -#@ # group_variable edif "edifin_power_net_name" ; -#@ # group_variable edif "edifin_power_net_property_name" ; -#@ # group_variable edif "edifin_power_net_property_value" ; -#@ # group_variable edif "edifin_power_port_name" ; -#@ # group_variable edif "edifin_use_identifier_in_rename" ; -#@ # group_variable edif "edifin_view_identifier_property_name" ; -#@ # group_variable edif "edifin_dc_script_flag" ; -#@ # group_variable edif "edifin_lib_logic_1_symbol" ; -#@ # group_variable edif "edifin_lib_logic_0_symbol" ; -#@ # group_variable edif "edifin_lib_in_port_symbol" ; -#@ # group_variable edif "edifin_lib_out_port_symbol" ; -#@ # group_variable edif "edifin_lib_inout_port_symbol" ; -#@ # group_variable edif "edifin_lib_in_osc_symbol" ; -#@ # group_variable edif "edifin_lib_out_osc_symbol" ; -#@ # group_variable edif "edifin_lib_inout_osc_symbol" ; -#@ # group_variable edif "edifin_lib_mentor_netcon_symbol" ; -#@ # group_variable edif "edifin_lib_ripper_bits_property" ; -#@ # group_variable edif "edifin_lib_ripper_bus_end" ; -#@ # group_variable edif "edifin_lib_ripper_cell_name" ; -#@ # group_variable edif "edifin_lib_ripper_view_name" ; -#@ # group_variable edif "edifin_lib_route_grid" ; -#@ # group_variable edif "edifin_lib_templates" ; -#@ # group_variable edif "edifout_dc_script_flag" ; -#@ # group_variable edif "edifout_design_name" ; -#@ # group_variable edif "edifout_designs_library_name" ; -#@ # group_variable edif "edifout_display_instance_names" ; -#@ # group_variable edif "edifout_display_net_names" ; -#@ # group_variable edif "edifout_external" ; -#@ # group_variable edif "edifout_external_graphic_view_name" ; -#@ # group_variable edif "edifout_external_netlist_view_name" ; -#@ # group_variable edif "edifout_external_schematic_view_name" ; -#@ # group_variable edif "edifout_ground_name" ; -#@ # group_variable edif "edifout_ground_net_name" ; -#@ # group_variable edif "edifout_ground_net_property_name" ; -#@ # group_variable edif "edifout_ground_net_property_value" ; -#@ # group_variable edif "edifout_ground_pin_name" ; -#@ # group_variable edif "edifout_ground_port_name" ; -#@ # group_variable edif "edifout_instance_property_name" ; -#@ # group_variable edif "edifout_instantiate_ports" ; -#@ # group_variable edif "edifout_library_graphic_view_name" ; -#@ # group_variable edif "edifout_library_netlist_view_name" ; -#@ # group_variable edif "edifout_library_schematic_view_name" ; -#@ # group_variable edif "edifout_merge_libraries" ; -#@ # group_variable edif "edifout_multidimension_arrays" ; -#@ # group_variable edif "edifout_name_oscs_different_from_ports" ; -#@ # group_variable edif "edifout_name_rippers_same_as_wires" ; -#@ # group_variable edif "edifout_netlist_only" ; -#@ # group_variable edif "edifout_no_array" ; -#@ # group_variable edif "edifout_numerical_array_members" ; -#@ # group_variable edif "edifout_pin_direction_property_name" ; -#@ # group_variable edif "edifout_pin_direction_in_value" ; -#@ # group_variable edif "edifout_pin_direction_inout_value" ; -#@ # group_variable edif "edifout_pin_direction_out_value" ; -#@ # group_variable edif "edifout_pin_name_property_name" ; -#@ # group_variable edif "edifout_portinstance_disabled_property_name" ; -#@ # group_variable edif "edifout_portinstance_disabled_property_value" ; -#@ # group_variable edif "edifout_portinstance_property_name" -#@ # group_variable edif "edifout_power_and_ground_representation" -#@ # group_variable edif "edifout_power_name" -#@ # group_variable edif "edifout_power_net_name" -#@ # group_variable edif "edifout_power_net_property_name" -#@ # group_variable edif "edifout_power_net_property_value" -#@ # group_variable edif "edifout_power_pin_name" -#@ # group_variable edif "edifout_power_port_name" -#@ # group_variable edif "edifout_skip_port_implementations" -#@ # group_variable edif "edifout_target_system" -#@ # group_variable edif "edifout_top_level_symbol" -#@ # group_variable edif "edifout_translate_origin" -#@ # group_variable edif "edifout_unused_property_value" -#@ # group_variable edif "edifout_write_attributes" -#@ # group_variable edif "edifout_write_constraints" -#@ # group_variable edif "edifout_write_properties_list" -#@ # group_variable edif "write_name_nets_same_as_ports" -#@ -#@ # "hdl" variables are variables pertaining to hdl reading and optimizing -#@ group_variable hdl "bus_dimension_separator_style" -#@ group_variable hdl "bus_minus_style" -#@ group_variable hdl "bus_naming_style" -#@ group_variable hdl "hdlin_ignore_textio_constructs" -#@ group_variable hdl "hdlin_latch_always_async_set_reset" -#@ group_variable hdl "hdlin_ff_always_sync_set_reset" -#@ group_variable hdl "hdlin_ff_always_async_set_reset" -#@ group_variable hdl "hdlin_check_input_netlist" -#@ group_variable hdl "hdlin_check_no_latch" -#@ group_variable hdl "hdlin_reporting_level" -#@ group_variable hdl "hdlin_infer_mux" -#@ group_variable hdl "hdlin_mux_oversize_ratio" -#@ group_variable hdl "hdlin_mux_size_limit" -#@ group_variable hdl "hdlin_infer_multibit" -#@ group_variable hdl "hdl_preferred_license" -#@ group_variable hdl "hdl_keep_licenses" -#@ group_variable hdl "hlo_resource_allocation" -#@ group_variable hdl "template_naming_style" -#@ group_variable hdl "template_parameter_style" -#@ group_variable hdl "template_separator_style" -#@ group_variable hdl "verilogout_equation" -#@ group_variable hdl "verilogout_ignore_case" -#@ group_variable hdl "verilogout_no_tri" -#@ group_variable hdl "verilogout_inout_is_in" -#@ group_variable hdl "verilogout_single_bit" -#@ group_variable hdl "verilogout_higher_designs_first" -#@ # group_variable hdl "verilogout_levelize" -#@ group_variable hdl "verilogout_include_files" -#@ group_variable hdl "verilogout_unconnected_prefix" -#@ group_variable hdl "verilogout_show_unconnected_pins" -#@ group_variable hdl "verilogout_no_negative_index" -#@ group_variable hdl "hdlin_enable_rtldrc_info" -#@ group_variable hdl "hdlin_sv_blackbox_modules" -#@ group_variable hdl "hdlin_infer_function_local_latches" -#@ group_variable hdl "hdlin_module_arch_name_splitting" -#@ group_variable hdl "hdlin_mux_size_min" -#@ group_variable hdl "hdlin_prohibit_nontri_multiple_drivers" -#@ group_variable hdl "hdlin_subprogram_default_values" -#@ group_variable hdl "hdlin_upcase_names" -#@ group_variable hdl "hdlin_vhdl_std" -#@ group_variable hdl "hdlin_vhdl93_concat" -#@ group_variable hdl "hdlin_vhdl_syntax_extensions" -#@ group_variable hdl "hdlin_vrlg_std" -#@ group_variable hdl "hdlin_while_loop_iterations" -#@ group_variable hdl "hdlin_auto_save_templates" -#@ group_variable hdl "hdlin_elab_errors_deep" -#@ group_variable hdl "hdlin_enable_assertions" -#@ group_variable hdl "hdlin_enable_configurations" -#@ group_variable hdl "hdlin_field_naming_style" -#@ group_variable hdl "hdlin_generate_naming_style" -#@ group_variable hdl "hdlin_generate_separator_style" -#@ group_variable hdl "hdlin_enable_relative_placement" -#@ group_variable hdl "hdlin_mux_rp_limit" -#@ group_variable hdl "hdlin_keep_signal_name" -#@ group_variable hdl "hdlin_module_name_limit" -#@ group_variable hdl "hdlin_mux_size_only" -#@ group_variable hdl "hdlin_preserve_sequential" -#@ group_variable hdl "hdlin_presto_cell_name_prefix" -#@ group_variable hdl "hdlin_presto_net_name_prefix" -#@ group_variable hdl "hdlin_strict_verilog_reader" -#@ group_variable hdl "hdlin_shorten_long_module_name" -#@ group_variable hdl "hdlin_sv_packages" -#@ group_variable hdl "hdlin_sv_tokens" -#@ group_variable hdl "hdlin_enable_elaborate_ref_linking" -#@ group_variable hdl "hdlin_enable_hier_naming" -#@ group_variable hdl "hdlin_autoread_verilog_extensions" -#@ group_variable hdl "hdlin_autoread_sverilog_extensions" -#@ group_variable hdl "hdlin_autoread_vhdl_extensions" -#@ group_variable hdl "hdlin_autoread_exclude_extensions" -#@ group_variable hdl "hdlin_enable_upf_compatible_naming" -#@ group_variable hdl "hdlin_report_sequential_pruning" -#@ group_variable hdl "hdlin_analyze_verbose_mode" -#@ -#@ # "vhdlio" variables are variables pertaining to VHDL generation -#@ group_variable vhdlio "vhdllib_timing_mesg" -#@ group_variable vhdlio "vhdllib_timing_xgen" -#@ group_variable vhdlio "vhdllib_timing_checks" -#@ group_variable vhdlio "vhdllib_negative_constraint" -#@ group_variable vhdlio "vhdllib_pulse_handle" -#@ group_variable vhdlio "vhdllib_glitch_handle" -#@ group_variable vhdlio "vhdllib_architecture" -#@ group_variable vhdlio "vhdllib_tb_compare" -#@ group_variable vhdlio "vhdllib_tb_x_eq_dontcare" -#@ group_variable vhdlio "vhdllib_logic_system" -#@ group_variable vhdlio "vhdllib_logical_name" -#@ -#@ # group_variable vhdlio "vhdlout_architecture_name" -#@ group_variable vhdlio "vhdlout_bit_type" -#@ # group_variable vhdlio "vhdlout_bit_type_resolved" -#@ group_variable vhdlio "vhdlout_bit_vector_type" -#@ # group_variable vhdlio "vhdlout_conversion_functions" -#@ # group_variable vhdlio "vhdlout_dont_write_types" -#@ group_variable vhdlio "vhdlout_equations" -#@ group_variable vhdlio "vhdlout_one_name" -#@ group_variable vhdlio "vhdlout_package_naming_style" -#@ group_variable vhdlio "vhdlout_preserve_hierarchical_types" -#@ group_variable vhdlio "vhdlout_separate_scan_in" -#@ group_variable vhdlio "vhdlout_single_bit" -#@ group_variable vhdlio "vhdlout_target_simulator" -#@ group_variable vhdlio "vhdlout_top_configuration_arch_name" -#@ group_variable vhdlio "vhdlout_top_configuration_entity_name" -#@ group_variable vhdlio "vhdlout_top_configuration_name" -#@ group_variable vhdlio "vhdlout_three_state_name" -#@ group_variable vhdlio "vhdlout_three_state_res_func" -#@ # group_variable vhdlio "vhdlout_time_scale" -#@ group_variable vhdlio "vhdlout_unknown_name" -#@ group_variable vhdlio "vhdlout_use_packages" -#@ group_variable vhdlio "vhdlout_wired_and_res_func" -#@ group_variable vhdlio "vhdlout_wired_or_res_func" -#@ group_variable vhdlio "vhdlout_write_architecture" -#@ group_variable vhdlio "vhdlout_write_entity" -#@ group_variable vhdlio "vhdlout_write_top_configuration" -#@ # group_variable vhdlio "vhdlout_synthesis_off" -#@ group_variable vhdlio "vhdlout_write_components" -#@ group_variable vhdlio "vhdlout_zero_name" -#@ # group_variable vhdlio "vhdlout_levelize" -#@ group_variable vhdlio "vhdlout_dont_create_dummy_nets" -#@ group_variable vhdlio "vhdlout_follow_vector_direction" -#@ -#@ # "suffix" variables are used to find the suffixes of different file types -#@ group_variable suffix "view_execute_script_suffix" -#@ group_variable suffix "view_read_file_suffix" -#@ group_variable suffix "view_analyze_file_suffix" -#@ group_variable suffix "view_write_file_suffix" -#@ -#@ # Meenakshi: Added new group scc (for SystemC compiler) -#@ group_variable scc {systemcout_levelize} -#@ group_variable scc {systemcout_debug_mode} -#@ -#@ # "power" variables are for power-analysis. -#@ group_variable power {power_keep_license_after_power_commands} -#@ group_variable power {power_preserve_rtl_hier_names} -#@ group_variable power {power_do_not_size_icg_cells} -#@ group_variable power {power_hdlc_do_not_split_cg_cells} -#@ group_variable power {power_rtl_saif_file} -#@ group_variable power {power_sdpd_saif_file} -#@ group_variable power {power_cg_flatten} -#@ group_variable power {power_opto_extra_high_dynamic_power_effort} -#@ group_variable power {power_default_static_probability} -#@ group_variable power {power_default_toggle_rate} -#@ group_variable power {power_default_toggle_rate_type} -#@ group_variable power {power_model_preference} -#@ group_variable power {power_sa_propagation_effort} -#@ group_variable power {power_sa_propagation_verbose} -#@ group_variable power {power_fix_sdpd_annotation} -#@ group_variable power {power_fix_sdpd_annotation_verbose} -#@ group_variable power {power_sdpd_message_tolerance} -#@ group_variable power {power_rclock_use_asynch_inputs} -#@ group_variable power {power_rclock_inputs_use_clocks_fanout} -#@ group_variable power {power_rclock_unrelated_use_fastest} -#@ group_variable power {power_lib2saif_rise_fall_pd} -#@ group_variable power {power_min_internal_power_threshold} -#@ group_variable power {power_cg_module_naming_style} -#@ group_variable power {power_cg_cell_naming_style} -#@ group_variable power {power_cg_gated_clock_net_naming_style} -#@ group_variable power {do_operand_isolation} -#@ -#@ # dpcm variables are used by DPCM lib and controllong DC when using DPCM -#@ -#@ if { [info exists dpcm_debuglevel] } { -#@ group_variable dpcm "dpcm_debuglevel" -#@ group_variable dpcm "dpcm_rulespath" -#@ group_variable dpcm "dpcm_rulepath" -#@ group_variable dpcm "dpcm_tablepath" -#@ group_variable dpcm "dpcm_libraries" -#@ group_variable dpcm "dpcm_version" -#@ group_variable dpcm "dpcm_level" -#@ group_variable dpcm "dpcm_temperaturescope" -#@ group_variable dpcm "dpcm_voltagescope" -#@ group_variable dpcm "dpcm_functionscope" -#@ group_variable dpcm "dpcm_wireloadscope" -#@ group_variable dpcm "dpcm_slewlimit" -#@ group_variable dpcm "dpcm_arc_sense_mapping" -#@ -#@ } -#@ -#@ set dpcm_slewlimit "TRUE" -#@ -#@ # executable to fire off RTLA/BCV -#@ group_variable hdl {xterm_executable} -#@ -#@ # Variable group for Chip Compiler -#@ if {[info exists acs_work_dir]} { -#@ group_variable acs acs_area_report_suffix -#@ group_variable acs acs_autopart_max_area -#@ group_variable acs acs_autopart_max_percent -#@ group_variable acs acs_budgeted_cstr_suffix -#@ group_variable acs acs_compile_script_suffix -#@ group_variable acs acs_constraint_file_suffix -#@ group_variable acs acs_cstr_report_suffix -#@ group_variable acs acs_db_suffix -#@ group_variable acs acs_dc_exec -#@ group_variable acs acs_default_pass_name -#@ group_variable acs acs_exclude_extensions -#@ group_variable acs acs_exclude_list -#@ group_variable acs acs_global_user_compile_strategy_script -#@ group_variable acs acs_hdl_verilog_define_list -#@ group_variable acs acs_hdl_source -#@ group_variable acs acs_lic_wait -#@ group_variable acs acs_log_file_suffix -#@ group_variable acs acs_make_args -#@ group_variable acs acs_make_exec -#@ group_variable acs acs_makefile_name -#@ group_variable acs acs_num_parallel_jobs -#@ group_variable acs acs_override_report_suffix -#@ group_variable acs acs_override_script_suffix -#@ group_variable acs acs_qor_report_suffix -#@ group_variable acs acs_timing_report_suffix -#@ group_variable acs acs_use_autopartition -#@ group_variable acs acs_use_default_delays -#@ group_variable acs acs_user_budgeting_script -#@ group_variable acs acs_user_compile_strategy_script_suffix -#@ group_variable acs acs_verilog_extensions -#@ group_variable acs acs_vhdl_extensions -#@ group_variable acs acs_work_dir -#@ group_variable acs check_error_list -#@ group_variable acs ilm_preserve_core_constraints -#@ -#@ } -#@ -#@ # -#@ # DesignTime Variable Group timing -#@ # -#@ -#@ group_variable timing case_analysis_log_file -#@ group_variable timing case_analysis_sequential_propagate -#@ group_variable timing case_analysis_with_logic_constants -#@ group_variable timing create_clock_no_input_delay -#@ group_variable timing disable_auto_time_borrow -#@ group_variable timing disable_case_analysis -#@ group_variable timing disable_conditional_mode_analysis -#@ group_variable timing disable_library_transition_degradation -#@ group_variable timing dont_bind_unused_pins_to_logic_constant -#@ group_variable timing enable_slew_degradation -#@ group_variable timing high_fanout_net_pin_capacitance -#@ group_variable timing high_fanout_net_threshold -#@ group_variable timing lib_thresholds_per_lib -#@ group_variable timing rc_adjust_rd_when_less_than_rnet -#@ group_variable timing rc_ceff_delay_min_diff_ps -#@ group_variable timing rc_degrade_min_slew_when_rd_less_than_rnet -#@ group_variable timing rc_driver_model_max_error_pct -#@ group_variable timing rc_filter_rd_less_than_rnet -#@ group_variable timing rc_input_threshold_pct_fall -#@ group_variable timing rc_input_threshold_pct_rise -#@ group_variable timing rc_output_threshold_pct_fall -#@ group_variable timing rc_output_threshold_pct_rise -#@ group_variable timing rc_rd_less_than_rnet_threshold -#@ group_variable timing rc_slew_derate_from_library -#@ group_variable timing rc_slew_lower_threshold_pct_fall -#@ group_variable timing rc_slew_lower_threshold_pct_rise -#@ group_variable timing rc_slew_upper_threshold_pct_fall -#@ group_variable timing rc_slew_upper_threshold_pct_rise -#@ group_variable timing timing_disable_cond_default_arcs -#@ # group_variable timing timing_enable_multiple_clocks_per_reg -#@ group_variable timing timing_report_attributes -#@ group_variable timing timing_self_loops_no_skew -#@ group_variable timing when_analysis_permitted -#@ group_variable timing when_analysis_without_case_analysis -#@ -#@ } ;# $synopsys_program_name != "ptxr" -#@ -#@ if { $synopsys_program_name == "icc_shell"} { -#@ # -#@ # IC Compile Variable Group: -#@ # -#@ # These variables affect the designs created by the route_opt command. -#@ # -#@ group_variable routeopt routeopt_checkpoint -#@ group_variable routeopt routeopt_disable_cpulimit -#@ } -#@ -#@ if { $synopsys_program_name == "icc_shell"} { -#@ # -#@ # IC Compiler Variable Group: MCMM -#@ # -#@ # These variables affect Multi-Corner/Multi-Mode. Currently, MCMM is -#@ # only supported in ICC--hence the "icc_shell" qualification, above -#@ # -#@ group_variable MCMM mcmm_enable_high_capacity_flow -#@ } -#@ -#@ # Aliases for backwards compatibility or other reasons -#@ group_variable compile {compile_log_format} -#@ alias view_cursor_number x11_set_cursor_number -#@ alias set_internal_load set_load -#@ alias set_internal_arrival set_arrival -#@ alias set_connect_delay "set_annotated_delay -net" -#@ alias create_test_vectors create_test_patterns -#@ alias compile_test insert_test -#@ alias check_clocks check_timing -#@ alias lint check_design -#@ # gen removed; alias gen create_schematic -#@ alias free remove_design -#@ alias group_bus create_bus -#@ alias ungroup_bus remove_bus -#@ alias groupvar group_variable -#@ alias report_constraints report_constraint -#@ alias report_attributes report_attribute -#@ alias fsm_reduce reduce_fsm -#@ alias fsm_minimize minimize_fsm -#@ alias disable_timing set_disable_timing -#@ alias dont_touch set_dont_touch -#@ alias dont_touch_network set_dont_touch_network -#@ alias dont_use set_dont_use -#@ alias fix_hold set_fix_hold -#@ alias prefer set_prefer -#@ alias remove_package "echo remove_package command is obsolete: packages are stored on disk not in-memory:" -#@ alias analyze_scan preview_scan -#@ alias get_clock get_clocks -#@ alias dc_shell_is_in_incr_mode shell_is_in_xg_mode -#@ alias set_vh_module_options set_dps_module_options -#@ alias set_vh_physopt_options set_dps_options -#@ alias update_vh_design update_dps_design -#@ alias vh_start dps_start -#@ alias vh_end dps_end -#@ alias all_vh_modules all_dps_modules -#@ alias all_designs_of_vh all_designs_of_dps -#@ alias vh_use_auto_partitioning dps_auto_partitioning -#@ alias vh_write_changes dps_write_changes -#@ alias vh_read_changes dps_read_changes -#@ alias vh_write_module_clock dps_write_module_clock -#@ alias get_lib get_libs -#@ -#@ # Enable unsupported psyn commands -#@ if { $synopsys_program_name == "psyn_shell" || $synopsys_program_name == "icc_shell"} { -#@ proc enable_unsupported_commands { { arg "default" } } { -#@ global cgpi_use_new_wire_factors -#@ global cgpi_use_relative_wire_factors -#@ global cgpi_use_new_path_factors -#@ global pwlm_use_new_wire_factors -#@ global pwlm_use_relative_wire_factors -#@ global pwlm_use_new_path_factors -#@ global psyn_unsupported_commands_dir -#@ global synopsys_root -#@ if {![info exists psyn_unsupported_commands_dir]} { -#@ set psyn_unsupported_commands_dir $synopsys_root/auxx/syn/psyn/unsupported_commands -#@ } -#@ set psyn_unsupported_commands_option1 $arg -#@ if {[file readable $psyn_unsupported_commands_dir/setup.tcl]} { -#@ source $psyn_unsupported_commands_dir/setup.tcl -#@ } else { -#@ source -encrypted $psyn_unsupported_commands_dir/setup.tcl.e -#@ } -#@ } -#@ } -#@ # For Intel -#@ if { $synopsys_program_name == "icc_shell"} { -#@ set psyn_unsupported_commands_dir $synopsys_root/auxx/syn/psyn/unsupported_commands -#@ source -encrypted $psyn_unsupported_commands_dir/max_dist.tcl.e -#@ } -#@ -#@ -#@ if { $synopsys_program_name == "icc_shell"} { -#@ # to enable CLE readline-ish terminal by default for ICC -#@ set sh_enable_line_editing true -#@ -#@ # Astro forms create an enormous number of new variables which are -#@ # very annoying for users to see, so the default of this variable -#@ # for ICC is false -#@ set sh_new_variable_message false -#@ } -#@ -#@ if { $synopsys_program_name == "icc_shell" || (($synopsys_program_name == "dc_shell") && ([shell_is_in_topographical_mode])) } { -#@ source $synopsys_root/auxx/syn/psyn/verify_ilm.tcl -#@ } -#@ -#@ # Enable vh psyn commands -#@ if { $synopsys_program_name == "psyn_shell" } { -#@ proc enable_vh_flow { } { -#@ global VH_SCRIPT_FILE -#@ global synopsys_root -#@ global suppress_errors -#@ set suppress_errors "$suppress_errors CMD-041 UID-95 SEL-003 SEL-005" -#@ if {![info exists VH_SCRIPT_FILE]} { -#@ set VH_SCRIPT_FILE $synopsys_root/auxx/syn/psyn/vh_pc.tcl.e -#@ } -#@ if {[file readable $VH_SCRIPT_FILE]} { -#@ if {[string match *.tcl $VH_SCRIPT_FILE]} { -#@ source $VH_SCRIPT_FILE -#@ } else { -#@ source -encrypted $VH_SCRIPT_FILE -#@ } -#@ } else { -#@ puts "Error: VH script file $VH_SCRIPT_FILE not found." -#@ } -#@ } -#@ } -#@ -#@ -#@ #Turn on enable_netl_view to true by default. -#@ set enable_netl_view "TRUE" -#@ -#@ -#@ #Turn on physopt_bypass_multiple_plib_check by default -#@ if { $synopsys_program_name == "psyn_shell" } { -#@ set physopt_bypass_multiple_plib_check TRUE -#@ } -#@ -#@ # The ls command is gone, now it is just an alias for dc_shell eqn mode -#@ -#@ if { [string compare $dc_shell_mode "default"] == 0 } { -#@ if { ( $sh_arch == {mips}) && ( ( $synopsys_program_name == {design_analyzer}) || ( $isatty == 0)) } { -#@ alias ls "sh ls -a " -#@ } else { -#@ if { ( $sh_arch == {mips}) || ( $sh_arch == {necmips}) } { -#@ alias ls "sh ls -aC " -#@ } else { -#@ alias ls "sh ls -aC " -#@ } -#@ } -#@ } -#@ -#@ # Aliases for RouteCompiler -#@ alias run_rodeo_router route66 -#@ -#@ # Removing route_global from the code. Earlier it was hidden. --Mukesh -#@ #proc route_global {} { -#@ # global route_global_keep_tmp_data -#@ # global rt66_dont_lock_dir -#@ # -#@ # set rt66_dont_lock_dir TRUE -#@ # -#@ # for { set i 0} {1==1} {incr i} { -#@ # set wdir [file join [pwd] ".route_global.$i"] -#@ # if {[file exist $wdir] == 0} { -#@ # break; -#@ # } -#@ # } -#@ # -#@ # set_routing_options -cut_out_covered_port CORE_ONLY -#@ # set_routing_options -internal_routing FALSE -#@ # set_routing_options -stick_routing FALSE -#@ # -#@ # ###puts "wdir = $wdir" -#@ # -#@ # set success [route66 -global -dontstop -dir $wdir] -#@ # -#@ # #clean tmp data if required: -#@ # if { $success == 1 } { -#@ # if [catch {string toupper $route_global_keep_tmp_data} result] { -#@ # #variable is not defined -#@ # ###puts "result_1 = $result => removing dir ..." -#@ # catch { file delete -force $wdir } -#@ # } else { -#@ # #variable is set to FALSE -#@ # if { [string compare $result "TRUE"] != 0} { -#@ # ###puts "result_2 = $result => removing dir ..." -#@ # catch { file delete -force $wdir } -#@ # } -#@ # } -#@ # } -#@ # -#@ # set rt66_dont_lock_dir FALSE -#@ # return 1 -#@ #} -#@ #define_proc_attributes route_global -hidden -#@ -#@ #/* Aliases added for report command */ -#@ alias report_clock_constraint "report_timing -path end -to all_registers(-data_pins)" -#@ alias report_clock_fanout "report_transitive_fanout -clock_tree" -#@ alias report_clocks report_clock -#@ alias report_synthetic report_cell -#@ -#@ # Alias added for Ultra backward compatibility mode -#@ alias set_ultra_mode set_ultra_optimization -#@ -#@ # alias for write_sge and menu item in DA for db2sge -#@ -#@ #if { [string compare $dc_shell_mode "tcl"] == 0 } { -#@ # set db2sge_script ${synopsys_root}/admin/setup/.dc_write_sge.tcl -#@ #} else { -#@ # set db2sge_script ${synopsys_root}/admin/setup/.dc_write_sge -#@ #} -#@ -#@ #set db2sge_command ${synopsys_root}/${sh_arch}/syn/bin/db2sge -#@ set view_script_submenu_items "\"DA to SGE Transfer\" write_sge" -#@ -#@ -#@ if { $synopsys_program_name != "lc_shell"} { -#@ # read schematic annotation setup file -#@ #source ${synopsys_root}/admin/setup/.dc_annotate -#@ -#@ # setup the default layer settings -#@ #source ${synopsys_root}/admin/setup/.dc_layers -#@ -#@ if {$synopsys_program_name != "dc_sms_shell"} { -#@ source ${synopsys_root}/admin/setup/.dc_name_rules -#@ } -#@ } else { -#@ #for read_lib -html -#@ source ${synopsys_root}/auxx/syn/lc/read_lib_html_msg_list.tcl -#@ } -#@ # -- Starting source /tools/synopsys/synthesis/j201409sp3/auxx/syn/lc/read_lib_html_msg_list.tcl - -#@ ############################################################################## -#@ # message ID and descriptions for read_lib -html -#@ ############################################################################## -#@ set read_lib_ccs_noise_msg { -#@ LBDB-660 -#@ LBDB-706 -#@ LBDB-708 -#@ LBDB-709 -#@ LBDB-710 -#@ LBDB-711 -#@ LBDB-712 -#@ LBDB-713 -#@ LBDB-714 -#@ LBDB-715 -#@ LBDB-716 -#@ LBDB-717 -#@ LBDB-718 -#@ LBDB-733 -#@ LBDB-734 -#@ LBDB-784 -#@ LBDB-824 -#@ LBDB-825 -#@ LBDB-858 -#@ LBDB-898 -#@ LBDB-899 -#@ LBDB-908 -#@ LBDB-920 -#@ LBDB-935 -#@ LBDB-936 -#@ LBDB-937 -#@ LBDB-938 -#@ LBDB-939 -#@ } -#@ # -- End source /tools/synopsys/synthesis/j201409sp3/auxx/syn/lc/read_lib_html_msg_list.tcl - -#@ -#@ if { $synopsys_program_name == "psyn_gui"} { -#@ # read RouteCompiler GUI file for timing critical pathes. -#@ source ${synopsys_root}/auxx/syn/route_gui/write_route_timing_path.tcl -#@ } -#@ -#@ # Set physopt_dw_opto to false -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ set physopt_dw_opto FALSE -#@ } -#@ -#@ #/* Read budgeting setup script */ -#@ -#@ if { [string compare $dc_shell_mode "default"] == 0 } { -#@ -#@ # Need a encrypted file in Tcl format for budget.setup.et -#@ if { $sh_arch != "msvc50" && $sh_arch != "alpha_nt" } { -#@ # source -e synopsys_root + "/admin/setup/budget.setup.et" -#@ } -#@ } -#@ -#@ if { $synopsys_program_name == "icc_shell"} { -#@ source $synopsys_root/auxx/syn/.icc_procs.tcl -#@ source -encrypted $synopsys_root/auxx/syn/cts/fast_atomic_cts.tcl.e -#@ } -#@ -#@ if { $synopsys_program_name == "icc_shell"} { -#@ alias report_scenario report_scenarios -#@ } -#@ -#@ # floorplanning preferences globals -#@ global fp_snap_type -#@ -#@ set fp_snap_type(port) wiretrack -#@ set fp_snap_type(cell) litho -#@ set fp_snap_type(pin) wiretrack -#@ set fp_snap_type(movebound) litho -#@ set fp_snap_type(port_shape) wiretrack -#@ set fp_snap_type(wiring_keepout) wiretrack -#@ set fp_snap_type(placement_keepout) litho -#@ set fp_snap_type(net_shape) wiretrack -#@ set fp_snap_type(route_shape) wiretrack -#@ set fp_snap_type(none) litho -#@ -#@ # STAR 9000615813. PWR-18 is no longer internally suppressed. -#@ # Instead call tcl suppress_message so that it can be unsuppressed by users in -#@ # command line if needed -#@ suppress_message PWR-18 -#@ -#@ # alias for write_sge is always the last line of the setup file -#@ #if { [string compare $dc_shell_mode "tcl"] == 0 } { -#@ # alias write_sge "source db2sge_script" -#@ #} else { -#@ # alias write_sge "include db2sge_script" -#@ #} -#@ -#@ if { $dc_shell_mode == "tcl" } { -#@ # Configure Execute script dialog to display .tcl files -#@ set view_execute_script_suffix "$view_execute_script_suffix .tcl" -#@ } -#@ -#@ # -#@ # Shirley Lu 5/15/2007 -#@ # -#@ # Invoke NCX validation/correlation/fomatter from lc_shell: -#@ # -#@ # UNIX shell: -#@ # setenv SYNOPSYS_NCX_ROOT /mydisk/ncx_2007.06 -#@ # -#@ -#@ if {[info exists env(SYNOPSYS_NCX_ROOT)]} { -#@ -#@ set ncx_path $env(SYNOPSYS_NCX_ROOT)/ncx/${sh_arch}/bin -#@ -#@ # -#@ # check_ccs_lib -#@ # use libchecker under $ncx_path defined above -#@ # Disable this command since 2010.12-SP3 (should be done in 2010.12 release) -#@ #proc check_ccs_lib {args} { -#@ # global ncx_path -#@ # set cmdStr [linsert $args 0 ${ncx_path}/libchecker -lc_shell] -#@ # set cmd [open "| $cmdStr 2>@ stdout"] -#@ # catch { -#@ # while {[gets $cmd info] >= 0} { -#@ # echo $info -#@ # } -#@ # } -#@ # if {[catch {close $cmd} msg]} { -#@ # } -#@ #} -#@ -#@ # -#@ # format_lib -#@ # use ncx under $ncx_path defined above -#@ # Disable format_lib command in 2014.09 release -- xwwang, 7/25/2014 -#@ #proc format_lib {args} { -#@ # global ncx_path -#@ # echo "Warning: format_lib command is scheduled to become obsolete in a future production release." -#@ # set cmdStr [linsert $args 0 ${ncx_path}/ncx -lc_shell] -#@ # set cmd [open "| $cmdStr 2>@ stdout"] -#@ # catch { -#@ # while {[gets $cmd info] >= 0} { -#@ # echo $info -#@ # } -#@ # } -#@ # if {[catch {close $cmd} msg]} { -#@ # } -#@ #} -#@ -#@ } -#@ -#@ proc get_nglc_search_path { } { -#@ set exec_path "invalid" -#@ if {[info exists ::env(SYNOPSYS_LC_ROOT)] && [file exists $::env(SYNOPSYS_LC_ROOT)/$::sh_arch/lc/bin/lc_shell_exec]} { -#@ set exec_path $::env(SYNOPSYS_LC_ROOT)/$::sh_arch/lc/bin/lc_shell_exec -#@ } -#@ -#@ return $exec_path -#@ } -#@ -#@ proc get_libra_synopsys_root { } { -#@ return [file dirname [file dirname [file dirname [file dirname $::nglc_search_path] ] ] ] -#@ } -#@ -#@ proc valias {v_orig v_alias} { -#@ uplevel 1 "upvar 0 $v_orig $v_alias" -#@ } -#@ -#@ set nglc_result_path "/tmp" -#@ set nglc_replay_tcl_file "nglc_shell_command.tcl" -#@ set nglc_search_path [get_nglc_search_path] -#@ set lc_run_from_legacy_library_compiler "true" -#@ set nglc_is_none_tech_file "false" -#@ set nglc_keep_nglc_temp_files "false" -#@ set nglc_intermediate_db_files "" -#@ set nglc_log_path "" -#@ set lc_enable_legacy_library_compiler "false" -#@ -#@ valias lc_enable_legacy_library_compiler lc_enable_common_shell_lc -#@ -#@ proc nglc_read_lib { args } { -#@ common_shell_read_lib $args -#@ } -#@ -#@ -#@ proc common_shell_read_lib {args } { -#@ set_folder_var -#@ set tcl_file "$::nglc_result_path/$::nglc_log_path/$::nglc_replay_tcl_file" -#@ set chan [open $tcl_file a] -#@ export_tcl_var $chan -#@ gen_nglc_read_lib_procedure $chan $args -#@ close $chan -#@ run_libra_with_echo $tcl_file -#@ common_shell_read_dbs -#@ set_none_tech_file -#@ } -#@ -#@ # create the unique folder under tmp -#@ proc set_folder_var { } { -#@ set fileName [pid] -#@ set ::nglc_log_path [append fileName "_" [clock microseconds]] -#@ file delete -force $::nglc_result_path/$::nglc_log_path -#@ file mkdir $::nglc_result_path/$::nglc_log_path -#@ } -#@ -#@ # export all the vars -#@ proc export_tcl_var { fileName } { -#@ foreach var [info vars ::* ] { -#@ if [array exists $var] { -#@ continue; -#@ } -#@ puts $fileName "set $var \[list [set $var]\]" -#@ } -#@ } -#@ -#@ # excuted by libra shell to read the dbs generated by common_shell -#@ proc common_shell_read_dbs { } { -#@ set dbNames "" -#@ foreach var [glob -nocomplain -directory $::nglc_result_path/$::nglc_log_path *.db] { -#@ append dbNames " " $var -#@ } -#@ set ::nglc_intermediate_db_files $dbNames -#@ } -#@ -#@ # display the log file genrated by common_shell in Libra and then remove the unique folder -#@ proc common_shell_clean_up { } { -#@ if { $::nglc_keep_nglc_temp_files == "false" } { -#@ file delete -force $::nglc_result_path/$::nglc_log_path -#@ } -#@ } -#@ -#@ proc gen_nglc_read_lib_procedure { fileName args} { -#@ puts $fileName "##@@@## gen_common_shell_read_lib" -#@ puts $fileName "eval [lindex [lindex $args 0] 0]" -#@ puts $fileName "##@@@##" -#@ puts $fileName "set lc_write_view_db_file false" -#@ puts $fileName "set librs \[get_libs\]" -#@ puts $fileName "for {set i 0} {\$i < \[ sizeof \$librs \]} {incr i 1} {" -#@ puts $fileName " set lib \[index_collection \$librs \$i]" -#@ puts $fileName " redirect -var a \"query_object \$lib\" " -#@ puts $fileName " if \[regexp {{(\")?(gtech)(\")?}} \$a\] { " -#@ puts $fileName " } elseif \[regexp {{(\")?(standard.sldb)(\")?}} \$a] { " -#@ puts $fileName " } else {" -#@ puts $fileName " regexp {{(\")?(\[^\"\]*)(\")?}} \$a b c d e " -#@ puts $fileName " write_lib \$d -o \$nglc_result_path/\$nglc_log_path/\$d.db" -#@ puts $fileName " }" -#@ puts $fileName "}" -#@ puts $fileName "exit" -#@ } -#@ -#@ proc set_none_tech_file { } { -#@ if { [file exists $::nglc_result_path/$::nglc_log_path/is_non_tech_file] } { -#@ set ::nglc_is_none_tech_file true; -#@ } else { -#@ set ::nglc_is_none_tech_file false; -#@ } -#@ } -#@ -#@ proc run_libra_with_echo {tcl_file} { -#@ set chan [open "|$::nglc_search_path -r [get_libra_synopsys_root] -f $tcl_file" r] -#@ # things to do: In debug mode, we want copy the whole output (beginning to end) -#@ # to a file -#@ if {$::nglc_keep_nglc_temp_files} { -#@ set log [open $::nglc_result_path/$::nglc_log_path/libra.log w] -#@ } -#@ set echo 0 -#@ set firstLine true -#@ while {[gets $chan line] >= 0} { -#@ if {$::nglc_keep_nglc_temp_files} { puts $log $line } -#@ if {[string equal -length 7 $line "##@@@##"]} { -#@ set echo [expr ! $echo] -#@ continue; -#@ } -#@ if {$echo} { -#@ if { $firstLine } { -#@ set firstLine false -#@ continue; -#@ } else { -#@ puts $line -#@ } -#@ } -#@ } -#@ close $chan -#@ if {$::nglc_keep_nglc_temp_files} { -#@ close $log -#@ } -#@ } -#@ -#@ # -- End source /tools/synopsys/synthesis/j201409sp3/admin/setup/.synopsys_dc.setup - -source -echo -verbose /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/rf2_128x128_wm1/../convert_lib_to_db.tcl -#@ # -- Starting source /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/rf2_128x128_wm1/../convert_lib_to_db.tcl - -#@ set SOURCE_FILES [glob *.lib] -#@ foreach FILE ${SOURCE_FILES} { -#@ read_lib $FILE -#@ redirect -variable CURR_LIB {get_lib} -#@ -#@ set CURR_LIB [string range $CURR_LIB 2 end-3] -#@ set CURR_LIB [lindex $CURR_LIB 0] -#@ set FILENAME [string range $FILE 0 end-4] -#@ write_lib $CURR_LIB -output ${FILENAME}.db -#@ remove_lib $CURR_LIB -#@ } -#@ -#@ exit diff --git a/hw/models/memory/cln28hpm/rf2_256x128_wm1/command.log b/hw/models/memory/cln28hpm/rf2_256x128_wm1/command.log deleted file mode 100644 index a1faba32..00000000 --- a/hw/models/memory/cln28hpm/rf2_256x128_wm1/command.log +++ /dev/null @@ -1,3759 +0,0 @@ -#@ # -#@ # Running lc_shell Version J-2014.09-SP3 for amd64 -- Jan 19, 2015 -#@ # Date: Mon Oct 28 14:39:58 2019 -#@ # Run by: lzhu308@gtcad-srv1 -#@ - -source /tools/synopsys/synthesis/j201409sp3/admin/setup/.synopsys_dc.setup -#@ # -- Starting source /tools/synopsys/synthesis/j201409sp3/admin/setup/.synopsys_dc.setup - -#@ # -#@ # ".synopsys_dc.setup" Initialization File for -#@ # -#@ # Dc_Shell and Design_Analyzer -#@ # -#@ # The variables in this file define the behavior of many parts -#@ # of the Synopsys Synthesis Tools. Upon installation, they should -#@ # be reviewed and modified to fit your site's needs. Each engineer -#@ # can have a .synopsys file in his/her home directory or current -#@ # directory to override variable settings in this file. -#@ # -#@ # Each logical grouping of variables is commented as to their -#@ # nature and effect on the Synthesis Commands. Examples of -#@ # variable groups are the Compile Variable Group, which affects -#@ # the designs produced by the COMPILE command, and the Schematic -#@ # Variable Group, which affects the output of the create_schematic -#@ # command. -#@ # -#@ # You can type "man _variables" in dc_shell or -#@ # design_analyzer to get help about a group of variables. -#@ # For instance, to get help about the "system" variable group, -#@ # type "help system_variables". You can also type -#@ # "man ", to get help on the that variable's -#@ # group. -#@ # -#@ -#@ # System variables -#@ set sh_command_abbrev_mode "Anywhere" -#@ set sh_continue_on_error "true" -#@ update_app_var -default true sh_continue_on_error -#@ set sh_enable_page_mode "true" -#@ update_app_var -default true sh_enable_page_mode -#@ set sh_source_uses_search_path "true" -#@ update_app_var -default true sh_source_uses_search_path -#@ if {$synopsys_program_name == "dc_shell" || $synopsys_program_name == "de_shell" || $synopsys_program_name == "dc_sms_shell" } { -#@ set sh_new_variable_message "false" -#@ update_app_var -default false sh_new_variable_message -#@ } else { -#@ set sh_new_variable_message "true" -#@ update_app_var -default true sh_new_variable_message -#@ } -#@ -#@ if {$synopsys_program_name == "dc_shell"} { -#@ set html_log_enable "false" -#@ set html_log_filename "default.html" -#@ } -#@ -#@ if {$synopsys_program_name == "de_shell"} { -#@ set de_log_html_filename "default.html" -#@ } -#@ -#@ if { [string compare $dc_shell_mode "tcl"] == 0 } { -#@ set sh_enable_line_editing "true" -#@ set sh_line_editing_mode "emacs" -#@ } -#@ -#@ if {$synopsys_program_name == "icc_shell"} { -#@ if {"$sh_output_log_file" == ""} { -#@ set sh_output_log_file "icc_output.txt" -#@ } -#@ -#@ ## the variable sh_redirect_progress_messages only makes it possible -#@ ## for some commands to redirect progress messages to the log file,thereby -#@ ## bypassing the console and reducing the volume of messages on the console. -#@ set sh_redirect_progress_messages true -#@ } -#@ -#@ -#@ # Suppress new variable messages for the following variables -#@ array set auto_index {} -#@ set auto_oldpath "" -#@ -#@ # Enable customer support banner on fatal -#@ if { $sh_arch == "linux" || $sh_arch == "amd64" || $sh_arch == "suse32" || $sh_arch == "suse64" || $sh_arch == "sparcOS5" || $sh_arch == "sparc64" || $sh_arch == "x86sol32" || $sh_arch == "x86sol64" || $sh_arch == "rs6000" || $sh_arch == "aix64" } { -#@ setenv SYNOPSYS_TRACE "" -#@ } -#@ -#@ # -#@ # Load the procedures which make up part of the user interface. -#@ # -#@ if { [string compare $dc_shell_mode "tcl"] == 0 } { -#@ source $synopsys_root/auxx/syn/.dc_common_procs.tcl -#@ if {$synopsys_program_name != "dc_sms_shell"} { -#@ source $synopsys_root/auxx/syn/.dc_procs.tcl -#@ } -#@ alias list_commands help -#@ } -#@ # -- Starting source /tools/synopsys/synthesis/j201409sp3/auxx/syn/.dc_common_procs.tcl - -#@ ############################################################################## -#@ # -#@ # -#@ # FILE: auxx/syn/.dc_common_procs.tcl -#@ # -#@ # ABSTRACT: These procedures are part of the PrimeTime and DC -#@ # user interface. -#@ # They are loaded by .synopsys_pt.setup and .synopsys_dc.setup. -#@ # -#@ ############################################################################## -#@ # -#@ # -#@ -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: group_variable -#@ # -#@ # ABSTRACT: Add a variable to the specified variable group. -#@ # This command is typically used by the system -#@ # administrator only. -#@ # -#@ # Below the proc is the command which creates the command -#@ # help information and semantic data for the argument. -#@ # -#@ # RETURNS: 1 if it is successful. -#@ # error code if the variable does not exist. -#@ # error code of the variable is already in the group. -#@ # -#@ # SYNTAX: group_variable group_name variable_name -#@ # -#@ ############################################################################## -#@ # -#@ -#@ -#@ proc group_variable { args } { -#@ global _Variable_Groups -#@ -#@ parse_proc_arguments -args $args resarr -#@ set group $resarr(group) -#@ set var $resarr(variable_name) -#@ -#@ if { ![info exists _Variable_Groups($group)] } { -#@ set _Variable_Groups($group) "" -#@ } -#@ -#@ # Verify that var exists as a global variable -#@ -#@ set cmd "uplevel #0 \{info exists $var\}" -#@ if { ![eval $cmd] } { -#@ return -code error "Variable '$var' is not defined." -#@ } -#@ -#@ # Only add it if it's not already there -#@ -#@ if { [lsearch $_Variable_Groups($group) $var] == -1 } { -#@ lappend _Variable_Groups($group) $var -#@ } -#@ -#@ return 1 -#@ } -#@ -#@ define_proc_attributes group_variable -info "Add a variable to a variable group" -command_group "Builtins" -permanent -dont_abbrev -define_args { -#@ {group "Variable group name" group} -#@ {variable_name "Variable name" variable_name}} -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: print_variable_group -#@ # -#@ # ABSTRACT: Shows variables and their values defined in the given group. -#@ -#@ # -#@ # Below the proc is the command which creates the command -#@ # help information and semantic data for the argument. -#@ # -#@ # RETURNS: 1 if it is successful. -#@ # error code of the variable group does not exist. -#@ # -#@ # SYNTAX: print_variable_group group_name -#@ # -#@ ############################################################################## -#@ # -#@ -#@ proc print_variable_group { args } { -#@ global _Variable_Groups -#@ -#@ parse_proc_arguments -args $args resarr -#@ set group $resarr(group) -#@ -#@ if { [string compare $group "all"] == 0 } { -#@ set cmd "uplevel #0 \{printvar\}" -#@ return [eval $cmd] -#@ } -#@ -#@ if { ![info exists _Variable_Groups($group)] } { -#@ return -code error "Variable group '$group' does not exist." -#@ } -#@ -#@ # Print out each global variable in the list. To be totally bulletproof, -#@ # test that each variable in the group is still defined. If not, remove -#@ # it from the list. -#@ -#@ foreach var [lsort $_Variable_Groups($group)] { -#@ set cmd "uplevel #0 \{info exists $var\}" -#@ if { ![eval $cmd] } { -#@ # Remove it -#@ set n [lsearch $_Variable_Groups($group) $var] -#@ set $_Variable_Groups($group) [lreplace $_Variable_Groups($group) $n $n] -#@ } else { -#@ # Print it. -#@ set cmd "uplevel #0 \{set $var\}" -#@ set val [eval $cmd] -#@ echo [format "%-25s = \"%s\"" $var $val] -#@ } -#@ } -#@ -#@ return 1 -#@ } -#@ -#@ define_proc_attributes print_variable_group -info "Print the contents of a variable group" -command_group "Builtins" -permanent -define_args {{group "Variable group name" group}} -#@ -#@ -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: _Variable_Groups_Get_Groups -#@ # -#@ # ABSTRACT: Return a list of all variable groups. This command is hidden -#@ # and is used by Design Vision. -#@ # -#@ # RETURNS: Tcl list of all variable groups including group all -#@ # -#@ # SYNTAX: _Variable_Groups_Get_Groups -#@ ############################################################################## -#@ # -#@ -#@ proc _Variable_Groups_Get_Groups { } { -#@ global _Variable_Groups -#@ -#@ set groups [array names _Variable_Groups] -#@ append groups " all" -#@ return $groups -#@ } -#@ define_proc_attributes _Variable_Groups_Get_Groups -hidden -#@ -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: _Variable_Groups_Get_Variables_Of_Group -#@ # -#@ # ABSTRACT: Return a list of all variables of a variable group. -#@ # It also works for pseudo group all. -#@ # -#@ # RETURNS: Tcl list of all variables of a variable group including -#@ # pseudo group all -#@ # -#@ # SYNTAX: _Variable_Groups_Get_Groups -#@ ############################################################################## -#@ # -#@ -#@ proc _Variable_Groups_Get_Variables_Of_Group { group } { -#@ global _Variable_Groups -#@ -#@ if { [string compare $group "all"] == 0 } { -#@ set itr [array startsearch _Variable_Groups] -#@ for { } { [array anymore _Variable_Groups $itr]} { } { -#@ set index [array nextelement _Variable_Groups $itr] -#@ append vars $_Variable_Groups($index) -#@ } -#@ array donesearch _Variable_Groups $itr -#@ return $vars -#@ } -#@ -#@ if { ![info exists _Variable_Groups($group)] } { -#@ return -code error "Variable group '$group' does not exist." -#@ } -#@ -#@ # Test if all variables in the list of variables are still defined. -#@ # Remove not existing variables. -#@ foreach var [lsort $_Variable_Groups($group)] { -#@ set cmd "uplevel #0 \{info exists $var\}" -#@ if { ![eval $cmd] } { -#@ # Remove it -#@ set n [lsearch $_Variable_Groups($group) $var] -#@ set $_Variable_Groups($group) [lreplace $_Variable_Groups($group) $n $n] -#@ } -#@ } -#@ return $_Variable_Groups($group) -#@ } -#@ define_proc_attributes _Variable_Groups_Get_Variables_Of_Group -hidden -#@ -#@ # -- End source /tools/synopsys/synthesis/j201409sp3/auxx/syn/.dc_common_procs.tcl - -#@ # -- Starting source /tools/synopsys/synthesis/j201409sp3/auxx/syn/.dc_procs.tcl - -#@ ############################################################################## -#@ # -#@ # -#@ # FILE: auxx/syn/.dc_procs.tcl -#@ # -#@ # ABSTRACT: These procedures are part of the Design Compiler Tcl -#@ # user interface. -#@ # They are loaded by .synopsys_dc.setup. -#@ # -#@ ############################################################################## -#@ # -#@ # -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: read_verilog -#@ # -#@ # ABSTRACT: Emulate PT's read_verilog command in DC: -#@ # -#@ # Usage: read_verilog # Read one or more verilog files -#@ # *[-hdl_compiler] (Use HDL Compiler (ignored)) -#@ # file_names (Files to read) -#@ # -#@ # Modified: Bharat 11/17/99. Use uplevel to ensure that the command -#@ # sees user/hidden variables from the top level. Star 92970. -#@ # -#@ # Modified: Evan Rosser, 12/5/01. Support -netlist and -rtl flags. -#@ # -#@ ############################################################################## -#@ # -#@ -#@ if { $synopsys_program_name != "icc_shell" } { -#@ proc read_verilog { args } { -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {read_file -format verilog %s %s [list %s]} [array names ra -rtl] [array names ra -netlist] $ra(file_names)] -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes read_verilog -info " Read one or more verilog files" -permanent -define_args { -#@ {file_names "Files to read" file_names list required} -#@ {-netlist "Use structural Verilog netlist reader" "" boolean optional} -#@ {-rtl "Use RTL Verilog compiler (Presto or HDLC)" "" boolean optional} -#@ {-hdl_compiler "Use HDL Compiler (ignored)" "" boolean {hidden optional}} -#@ } -#@ } -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: read_sverilog -#@ # -#@ # ABSTRACT: Emulate PT's read_sverilog command in DC: -#@ # -#@ # Usage: read_sverilog # Read one or more systemverilog files -#@ # *[-hdl_compiler] (Use HDL Compiler (ignored)) -#@ # file_names (Files to read) -#@ # -#@ # Modified: Yong Xiao, 01/31/2003: Copied from read_verilog to support -#@ # systemverilog input. -#@ # -#@ ############################################################################## -#@ # -#@ -#@ proc read_sverilog { args } { -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {read_file -format sverilog %s %s [list %s]} [array names ra -rtl] [array names ra -netlist] $ra(file_names)] -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes read_sverilog -info " Read one or more systemverilog files" -permanent -define_args { -#@ {file_names "Files to read" file_names list required} -#@ {-netlist "Use structural Verilog netlist reader" "" boolean optional} -#@ {-rtl "Use RTL Systemverilog compiler (Presto or HDLC)" "" boolean optional} -#@ {-hdl_compiler "Use HDL Compiler (ignored)" "" boolean {hidden optional}} -#@ } -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: read_vhdl -#@ # -#@ # ABSTRACT: Emulate PT's read_vhdl command in DC: -#@ # -#@ # Usage: read_vhdl # Read one or more vhdl files -#@ # file_names (Files to read) -#@ # -#@ # -#@ ############################################################################## -#@ # -#@ -#@ proc read_vhdl { args } { -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {read_file -format vhdl %s [list %s]} [array names ra -netlist] $ra(file_names)] -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes read_vhdl -info " Read one or more vhdl files" -permanent -define_args { -#@ {file_names "Files to read" file_names list required} -#@ {-netlist "Use structural VHDL netlist reader" "" boolean optional} -#@ } -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: read_db -#@ # -#@ # ABSTRACT: Emulate PT's read_db command in DC: -#@ # -#@ # Usage: -#@ # read_db # Read one or more db files -#@ # *[-netlist_only] (Do not read any attributes from db (ignored)) -#@ # *[-library] (File is a library DB (ignored)) -#@ # file_names (Files to read) -#@ # -#@ # -#@ ############################################################################## -#@ # -#@ -#@ proc read_db { args } { -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {read_file -format db [list %s]} $ra(file_names)] -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes read_db -info " Read one or more db files" -permanent -define_args { -#@ {file_names "Files to read" file_names list required} -#@ {-netlist_only "Do not read any attributes from db (ignored)" "" boolean {hidden optional}} -#@ {-library "File is a library DB (ignored)" "" boolean {hidden optional}} -#@ } -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: read_edif -#@ # -#@ # ABSTRACT: Emulate PT's read_edif command in DC: -#@ # -#@ # Usage: -#@ # read_edif # Read one or more edif files -#@ # *[-complete_language] (Use ptxr to read the file (ignored)) -#@ # file_names (Files to read) -#@ # -#@ # -#@ ############################################################################## -#@ # -#@ proc read_edif { args } { -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {read_file -format edif [list %s]} $ra(file_names)] -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes read_edif -info " Read one or more edif files" -permanent -define_args { -#@ {file_names "Files to read" file_names list required} -#@ {-complete_language "Use ptxr to read the file (ignored)" "" boolean {hidden optional}} -#@ } -#@ -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: read_ddc -#@ # -#@ # ABSTRACT: Shorthand for "read_file -format ddc": -#@ # -#@ # Usage: -#@ # read_ddc # Read one or more ddc files -#@ # *[-scenarios] only read constraints for specified scenarios -#@ # *[-active_scenarios] only activate the specified scenarios -#@ # file_names (Files to read) -#@ # -#@ # -#@ ############################################################################## -#@ # -#@ -#@ proc read_ddc { args } { -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd "read_file -format ddc" -#@ if { [ info exists ra(-scenarios) ] } { -#@ set cmd "$cmd -scenarios { $ra(-scenarios) }" -#@ } -#@ if { [ info exists ra(-active_scenarios) ] } { -#@ set cmd "$cmd -active_scenarios { $ra(-active_scenarios) }" -#@ } -#@ set cmd "$cmd { $ra(file_names) }" -#@ return [uplevel \#0 $cmd] -#@ } -#@ -#@ define_proc_attributes read_ddc -info "Read one or more ddc files" -permanent -define_args { -#@ {file_names "Files to read" file_names list required} -#@ {-scenarios "list of scenarios to be read from ddc file" -#@ scenario_list list optional} -#@ {-active_scenarios "list of scenarios to be made active" -#@ active_scenario_list list optional}} -#@ -#@ -#@ -#@ ############################################################################## -#@ # -#@ # PROCEDURE: source_tcl_file -#@ # -#@ # ABSTRACT: generic procedure to source another tcl file -#@ # -#@ # Arguments: -#@ # filename tcl filename -#@ # dir directory to check for file -#@ # msg verbose message -#@ # verbose verbose mode -#@ # -#@ # Usage: -#@ # -#@ ############################################################################## -#@ # -#@ proc source_tcl_file { filename dir msg {verbose 1} } { -#@ set __qual_pref_file [file join $dir $filename] -#@ if {[file exists $__qual_pref_file]} { -#@ if { $verbose } { -#@ echo $msg $__qual_pref_file -#@ } -#@ # use catch to recover from errors in the pref file -#@ echo_trace "Sourcing " $__qual_pref_file -#@ # to speed up sourcing use read and eval -#@ set f [open $__qual_pref_file] -#@ if {[catch {namespace eval :: [read -nonewline $f]} __msg]} { -#@ echo Error: Error during sourcing of $__qual_pref_file -#@ if {$__msg != ""} { echo $__msg } -#@ # actually, it looks like $__msg is always null after -#@ # source fails -#@ } -#@ close $f -#@ } else { -#@ echo_trace "Info: File '" $__qual_pref_file "' does not exist!" -#@ } -#@ } -#@ define_proc_attributes source_tcl_file -hidden -#@ -#@ -#@ -#@ ############################################################################## -#@ # -#@ # PROCEDURE: echo_trace -#@ # -#@ # ABSTRACT: echo only in trace modus -#@ # -#@ ############################################################################## -#@ # -#@ proc echo_trace { args } { -#@ if { [info exists ::env(TCL_TRACE)] } { -#@ echo TRACE\> [join $args "" ] -#@ } -#@ } -#@ define_proc_attributes echo_trace -hidden -#@ -#@ ############################################################################# -#@ # -#@ # Following procedures added for PC write_script -#@ # -#@ # -#@ # -#@ ############################################################################ -#@ -#@ proc set_cell_restriction { args } { -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {set_attribute %s -type integer restrictions %s } $ra(cell) $ra(value)] -#@ return [uplevel #0 $cmd] -#@ -#@ } -#@ define_proc_attributes set_cell_restriction -hidden -define_args { {cell "cell_name" cell string required} {value "value" value string required} } -#@ -#@ -#@ proc set_cell_soft_keepout {args} { -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {set_keepout_margin -type soft -outer {%d %d %d %d} [list %s] } $ra(llx) $ra(lly) $ra(urx) $ra(ury) $ra(objects)] -#@ return [uplevel #0 $cmd] -#@ -#@ -#@ } -#@ -#@ define_proc_attributes set_cell_soft_keepout -hidden -define_args { {llx "llx" llx float required} {lly "lly" lly float required} {urx "urx" urx float required} {ury "ury" ury float required} {objects "objects" objects list required} } -#@ -#@ proc set_cell_hard_keepout {args} { -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {set_keepout_margin -type soft -outer {%d %d %d %d} [list %s] } $ra(llx) $ra(lly) $ra(urx) $ra(ury) $ra(objects)] -#@ return [uplevel #0 $cmd] -#@ -#@ -#@ } -#@ -#@ define_proc_attributes set_cell_hard_keepout -hidden -define_args { {llx "llx" llx float required} {lly "lly" lly float required} {urx "urx" urx float required} {ury "ury" ury float required} {objects "objects" objects list required} } -#@ -#@ set mw_use_pdb_lib_format false -#@ -#@ ############################################################################## -#@ # -#@ # PROCEDURE: write_milkyway -#@ # -#@ # ABSTRACT: wrapper around save_mw_cel to support original write_milkyway -#@ # interface -#@ # if { [info commands open_mw_cel] == "open_mw_cel" } {} -#@ # -#@ ############################################################################## -#@ -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ -#@ proc write_milkyway args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {save_mw_cel -as %s %s %s %s %s} $ra(-output) [array names ra -overwrite] [array names ra -create] [array names ra -all] [array names ra -dps]] -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes write_milkyway -hidden -info " Saves the design as milkyway CEL" -define_args {{-output fileName "Name" string {optional}} {-overwrite "Overwrite the current version" "" boolean {optional}} {-create "Create from scratch" "" boolean {hidden optional}} {-all "Save all modified cells" "" boolean {hidden optional}} {-dps "Save internal DPS design" "" boolean {hidden optional}}} -#@ -#@ ############################################################################## -#@ # -#@ # PROCEDURE: read_milkyway -#@ # -#@ # ABSTRACT: wrapper around open_mw_cel to support original read_milkyway -#@ # interface -#@ # MODIFIED: To support DPS in Galileo we need to pass the filtering -#@ # parameters to the DPS command. (Pankaj Goswami, Mar09 2005) -#@ # -#@ ############################################################################## -#@ -#@ proc read_milkyway args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {open_mw_cel %s} $ra() ] -#@ -#@ if {[info exists ra(-library)]} { -#@ set cmd [concat [concat $cmd " -library " ] " $ra(-library) "] -#@ } -#@ -#@ if {[info exists ra(-read_only)]} { -#@ lappend cmd {-readonly} -#@ } -#@ -#@ # DPS specific stuff -#@ set dps_cmd "vh_set_current_partition " -#@ set read_mw_with_dps_filter false -#@ -#@ if {[info exists ra(-vh_module_only)]} { -#@ append dps_cmd "-vh_module_only " -#@ set read_mw_with_dps_filter true -#@ } -#@ -#@ if {[info exists ra(-vh_include)]} { -#@ append dps_cmd [concat " -vh_include " " \{ $ra(-vh_include) \}"] -#@ append dps_cmd " " -#@ set read_mw_with_dps_filter true -#@ } -#@ -#@ if {[info exists ra(-vh_exclude)]} { -#@ append dps_cmd [concat " -vh_exclude" " \{ $ra(-vh_exclude) \}"] -#@ set read_mw_with_dps_filter true -#@ } -#@ -#@ if { $read_mw_with_dps_filter == true } { -#@ # Call the DPS command to store the DPS filtering params. -#@ uplevel #0 $dps_cmd -#@ } else { -#@ # If there is no DPS filtering params, then we need to reset the -#@ # params which might have been stored from the provious command. -#@ append dps_cmd " -vh_reset_partition" -#@ uplevel #0 $dps_cmd -#@ } -#@ # End of DPS stuff -#@ -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes read_milkyway -hidden -info " Read milkyway CEL from disk" -define_args {{-library "library name" "lib_name" string {optional}} {-read_only "open design in read only mode" "" boolean {optional}} {-version "version number of the CEL" "number" string {optional}} {-vh_module_only "open design for DPS module only partition" "" boolean {hidden optional}} {-vh_include "list of designs to be included in the DPS partition" "include_designs" list {hidden optional}} {-vh_exclude "list of designs to be excluded in the DPS partition" "exclude_designs" list {hidden optional}} {"" fileName "CEL name" string {required}}} -#@ -#@ } -#@ -#@ ############################################################################## -#@ # -#@ # PROCEDURE: set_mw_technology_file -#@ # -#@ # ABSTRACT: wrapper around update_mw_lib -#@ # -#@ # HISTORY : 2009/6/21, yunz, support ALF reader in ICC -#@ # -#@ ############################################################################## -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] || -#@ ([string match -nocase {*d[ce]_shell*} $synopsys_program_name] && [shell_is_mwlib_enabled]) } { -#@ -#@ proc set_mw_technology_file args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd "" -#@ set lib_name "" -#@ set pdb_file "tech.pdb" -#@ set log_file "log_file" -#@ set alf_file "" -#@ -#@ if {[info exists ra(-technology)] && [info exists ra(-plib)]} { -#@ echo "Error: the $ra(-technology) and $ra(-plib) options are mutually exclusive." -#@ return [uplevel #0 $cmd] -#@ } elseif {[info exists ra(-technology)] && [info exists ra(-alf)]} { -#@ echo "Error: the $ra(-technology) and $ra(-alf) options are mutually exclusive." -#@ return [uplevel #0 $cmd] -#@ } elseif {[info exists ra(-plib)] && [info exists ra(-alf)]} { -#@ echo "Error: the $ra(-plib) and $ra(-alf) options are mutually exclusive." -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ if {[info exists ra(-technology)]} { -#@ -#@ set cmd [format {update_mw_lib -technology %s %s} $ra(-technology) $ra() ] -#@ } -#@ -#@ if {[info exists ra(-plib)]} { -#@ -#@ set cmd [format {update_mw_lib %s} $ra() ] -#@ -#@ if {[string match -nocase {*.pdb} $ra(-plib) ] } { -#@ set cmd [concat [concat $cmd " -plib " ] " $ra(-plib) "] -#@ } -#@ if {[string match -nocase {*.plib} $ra(-plib) ] } { -#@ set subcmd [format {set lc_enable_legacy_library_compiler true;read_lib %s} $ra(-plib)] -#@ redirect -file log_file {uplevel #0 $subcmd} -#@ set f1 [open $log_file] -#@ while {[gets $f1 line] >= 0} { -#@ set msg1 [lindex $line 3] -#@ set msg2 [lindex $line 4] -#@ if {[string match {read} $msg1] && -#@ [string match {successfully} $msg2] } { -#@ set msg [lindex $line 2] -#@ set len [string length $msg] -#@ set lib_name [string range $msg 1 [expr $len-2] ] -#@ break -#@ } -#@ if {[string match {old} $msg1] && -#@ [string match {technology} $msg2] } { -#@ set msg [lindex $line 6] -#@ set len [string length $msg] -#@ set path [string range $msg 1 [expr $len-2] ] -#@ set name1 [lindex [split $path {/}] end] -#@ regexp {(.+?).pdb} $name1 match lib_name -#@ break -#@ } -#@ } -#@ if {$lib_name != ""} { -#@ set subcmd [format {write_lib %s -output %s} $lib_name $pdb_file] -#@ uplevel #0 $subcmd -#@ -#@ echo "Command is : " -#@ echo $cmd -#@ -#@ set cmd [concat [concat $cmd " -plib " ] " $pdb_file "] -#@ -#@ echo "Command is : " -#@ echo $cmd -#@ -#@ } else { -#@ echo "Error: Can not compile $ra(-plib) to pdb successfully" -#@ return 0; -#@ } -#@ } -#@ } -#@ if {[info exists ra(-alf)]} { -#@ -#@ set cmd [format {update_mw_lib %s} $ra() ] -#@ -#@ set cmd [concat [concat $cmd " -alf " ] " $ra(-alf) "] -#@ } -#@ -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes set_mw_technology_file -hide_body -info " Set technology file for the library " -define_args {{-technology "Technology file name" "tech_file" string {optional}} {-plib "Plib file name" "file_name" string {optional}} {-alf "alf file name" "file_name" string {optional}} {"" "Library name" "libName" string {required}}} -#@ -#@ ############################################################################## -#@ # -#@ # PROCEDURE: rebuild_mw_lib -#@ # -#@ # ABSTRACT: wrapper around update_mw_lib -#@ # -#@ ############################################################################## -#@ -#@ proc rebuild_mw_lib args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {update_mw_lib -rebuild %s} $ra() ] -#@ -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes rebuild_mw_lib -hide_body -info " Rebuild the library " -define_args {{"" "Library name" "libName" string {required}}} -#@ -#@ ############################################################################## -#@ # -#@ # PROCEDURE: set_mw_lib_reference -#@ # -#@ # ABSTRACT: Procedure to set ref lib list or ref ctrl file -#@ # -#@ ############################################################################## -#@ -#@ proc set_mw_lib_reference args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd "" -#@ -#@ if {[info exists ra(-mw_reference_library)]} { -#@ set cmd [format {set_reference_control_file -reference_libraries {%s} %s} $ra(-mw_reference_library) $ra() ] -#@ } -#@ -#@ if {[info exists ra(-reference_control_file)]} { -#@ set cmd [format {set_reference_control_file -file %s %s} $ra(-reference_control_file) $ra() ] -#@ } -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes set_mw_lib_reference -hide_body -info " Set reference for the library " -define_args {{-mw_reference_library "List of reference libraries" "lib_list" list {optional}} {-reference_control_file "Reference control file" "file_name" string {optional}} {"" "Library name" "libName" string {required}}} -#@ -#@ # -#@ ############################################################################## -#@ # -#@ # PROCEDURE: create_mw_lib -#@ # -#@ # ABSTRACT: wrapper around MWUI create_mw_lib -#@ # -#@ ############################################################################## -#@ -#@ proc create_mw_lib args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd "" -#@ set lib_name "" -#@ set pdb_file "tech.pdb" -#@ set log_file "log_file" -#@ -#@ if {[info exists ra(-ignore_case)]} { -#@ set cmd [format {org_create_mw_lib %s} $ra() ] -#@ } else { -#@ set cmd [format {org_create_mw_lib -case_sensitive %s} $ra() ] -#@ } -#@ -#@ if {[info exists ra(-technology)]} { -#@ set cmd [concat [concat $cmd " -technology " ] " $ra(-technology) "] -#@ } -#@ -#@ if {[info exists ra(-ignore_tf_error)]} { -#@ set cmd [concat $cmd " -ignore_tf_error " ] -#@ } -#@ -#@ if {[info exists ra(-hier_separator)]} { -#@ set cmd [concat [concat $cmd " -hier_seperator " ] " $ra(-hier_separator) "] -#@ } -#@ -#@ if {[info exists ra(-bus_naming_style)]} { -#@ set cmd [concat [concat $cmd " -bus_naming_style " ] " {$ra(-bus_naming_style)} "] -#@ } -#@ -#@ -#@ if {[info exists ra(-reference_control_file)]} { -#@ set cmd [concat [concat $cmd " -reference_control_file " ] " $ra(-reference_control_file) "] -#@ } -#@ -#@ if {[info exists ra(-mw_reference_library)]} { -#@ set cmd [concat [concat [concat $cmd " -mw_reference_library {" ] " $ra(-mw_reference_library) "] "}"] -#@ } -#@ -#@ if {[info exists ra(-plib)]} { -#@ if {[string match -nocase {*.pdb} $ra(-plib) ] } { -#@ set cmd [concat [concat $cmd " -plib " ] " $ra(-plib) "] -#@ } -#@ if {[string match -nocase {*.plib} $ra(-plib) ] } { -#@ set subcmd [format {set lc_enable_legacy_library_compiler true; read_lib %s} $ra(-plib)] -#@ redirect -file log_file {uplevel #0 $subcmd} -#@ set f1 [open $log_file] -#@ while {[gets $f1 line] >= 0} { -#@ set msg1 [lindex $line 3] -#@ set msg2 [lindex $line 4] -#@ if {[string match {read} $msg1] && -#@ [string match {successfully} $msg2] } { -#@ set msg [lindex $line 2] -#@ set len [string length $msg] -#@ set lib_name [string range $msg 1 [expr $len-2] ] -#@ break -#@ } -#@ if {[string match {old} $msg1] && -#@ [string match {technology} $msg2] } { -#@ set msg [lindex $line 6] -#@ set len [string length $msg] -#@ set path [string range $msg 1 [expr $len-2] ] -#@ set name1 [lindex [split $path {/}] end] -#@ regexp {(.+?).pdb} $name1 match lib_name -#@ break -#@ } -#@ } -#@ if {$lib_name != ""} { -#@ set subcmd [format {write_lib %s -output %s} $lib_name $pdb_file] -#@ uplevel #0 $subcmd -#@ set cmd [concat [concat $cmd " -plib " ] " $pdb_file "] -#@ } else { -#@ echo "Error: Can not compile $ra(-plib) to pdb successfully" -#@ return 0; -#@ } -#@ } -#@ } -#@ -#@ if { ![uplevel #0 $cmd] } { -#@ return 0 -#@ } -#@ -#@ set cmd "" -#@ -#@ if {[info exists ra(-open)]} { -#@ uplevel #0 $cmd -#@ set cmd [format {open_mw_lib %s} $ra() ] -#@ } -#@ -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes create_mw_lib -hide_body -info " Create a milkyway library " -define_args {{-technology "Technology file name" "file_name" string {optional}} {-ignore_tf_error "Ignore the error in technology file" "" boolean {hidden optional}} {-plib "Plib file name" "file_name" string {optional}} {-hier_separator "Hierarchical separator, default is backslash / " "separator" string {hidden optional}} {-bus_naming_style "Bus naming style" "bus_naming_style" string {optional}} {-ignore_case "Make case insensitive" "" boolean {hidden optional}} {-case_sensitive "Make case sensitive" "" boolean {hidden optional}} {-mw_reference_library "List of reference libraries" "lib_list" list {optional}} {-reference_control_file "Reference control file" "file_name" string {optional}} {-open "Open the library after creation" "" boolean {optional}} {"" "Library name to create" "libName" string {required}}} -#@ -#@ # -#@ ############################################################################## -#@ # -#@ # PROCEDURE: report_mw_lib -#@ # -#@ # ABSTRACT: wrapper around MWUI report_mw_lib -#@ # -#@ ############################################################################## -#@ -#@ proc report_mw_lib args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd "" -#@ -#@ if {[info exists ra(-mw_reference_library)]} { -#@ if {[info exists ra()]} { -#@ set cmd [format {org_report_mw_lib -mw_reference_library %s} $ra() ] -#@ } else { -#@ set cmd [format {org_report_mw_lib -mw_reference_library} ] -#@ } -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ if {[info exists ra(-unit_range)]} { -#@ if {[info exists ra()]} { -#@ set cmd [format {org_report_mw_lib -unit_range %s} $ra() ] -#@ } else { -#@ echo "Error : Library name must be specified when using this option" -#@ return 0; -#@ } -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ } -#@ -#@ define_proc_attributes report_mw_lib -hide_body -info " Report information about the library " -define_args {{-unit_range "Report unit range of library" "" boolean {optional}} {-mw_reference_library "Report list of reference libraries" "" boolean {optional}} {"" "Library to be reported" "libName" string {optional}}} -#@ -#@ ############################################################################## -#@ # -#@ # PROCEDURE: close_mw_lib -#@ # -#@ # ABSTRACT: Wrapper around close_mw_lib to handle -save option properly -#@ # - save_mw_cel to save current cel with dc_netlist -#@ # - close_mw_cel to close current cel -#@ # - save_open_cels to save other open cels before closing library -#@ # -#@ ############################################################################## -#@ -#@ proc close_mw_lib args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ if {$args == ""} { -#@ set cmd [format {icc_is_dc_up} ] -#@ if {[uplevel #0 $cmd]} { -#@ set cmd [format {remove_design -quiet -designs} ] -#@ if {[uplevel #0 $cmd]} { -#@ set cmd [format {org_close_mw_lib } ] -#@ return [uplevel #0 $cmd] -#@ } else { -#@ return 0 -#@ } -#@ } else { -#@ set cmd [format {org_close_mw_lib } ] -#@ return [uplevel #0 $cmd] -#@ } -#@ } -#@ -#@ if {[info exists ra(-save)]} { -#@ -#@ set cmd [format {save_mw_cel} ] -#@ if {![uplevel #0 $cmd]} { -#@ return -#@ } -#@ -#@ set cmd [format {close_mw_cel} ] -#@ if {![uplevel #0 $cmd]} { -#@ return -#@ } -#@ -#@ set cmd [format {save_open_cels} ] -#@ if {![uplevel #0 $cmd]} { -#@ return -#@ } -#@ } -#@ -#@ set cmd [format {org_close_mw_lib} ] -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ define_proc_attributes close_mw_lib -hide_body -info " Closes the milkyway library " -define_args {{-save "Save open cels" "" boolean {optional}} {"" "libraries to be closed" "lib list" list {hidden optional}}} -#@ } else { -#@ define_proc_attributes close_mw_lib -hide_body -info " Closes the milkyway library " -define_args {{-no_save "Don't save open cels" "" boolean {hidden optional}} {"" "libraries to be closed" "lib list" list {hidden optional}}} -#@ } -#@ ############################################################################## -#@ # -#@ # PROCEDURE: write_mw_lib_files -#@ # -#@ # ABSTRACT: Write technology or reference control file -#@ # History: Yun Zhang 2012/12/11, public option -stream_layer_map_file -#@ # History: Yun Zhang 2012/9/5. support new hidden option -vt_cell_placement_properties -#@ # History: Yun Zhang 2011/12/5. add new hidden option -stream_layer_map_file -#@ # -#@ ############################################################################## -#@ proc write_mw_lib_files args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd "" -#@ -#@ if {[info exists ra(-reference_control_file)]} { -#@ #Option -reference_contrl_file, -plib and -technology are exclusive. -#@ # If both of them are set at the same time, error reported. -#@ # 9000273455, by xqsun, 2009/2/4 -#@ if {[info exists ra(-technology)]} { -#@ echo "Error: Cannot specify '-reference_control_file' with '-technology'.(CMD-001)" -#@ return 0 -#@ } elseif {[info exists ra(-plib)]} { -#@ echo "Error: Cannot specify '-reference_control_file' with '-plib'.(CMD-001)" -#@ return 0 -#@ } elseif {[info exists ra(-vt_cell_placement_properties)]} { -#@ echo "Error: Cannot specify '-reference_control_file' with '-vt_cell_placement_properties'.(CMD-001)" -#@ return 0 -#@ } elseif {[info exists ra(-stream_layer_map_file)]} { -#@ echo "Error: Cannot specify '-reference_control_file' with '-stream_layer_map_file'.(CMD-001)" -#@ return 0 -#@ } else { -#@ set cmd [format {report_mw_lib_ref_ctrl_file -output %s %s} $ra(-output) $ra() ] -#@ return [uplevel #0 $cmd] -#@ } -#@ } -#@ -#@ if {[info exists ra(-technology)]} { -#@ if {[info exists ra(-plib)]} { -#@ echo "Error: Cannot specify '-technology' with '-plib'.(CMD-001)" -#@ return 0 -#@ } elseif {[info exists ra(-vt_cell_placement_properties)]} { -#@ echo "Error: Cannot specify '-technology' with '-vt_cell_placement_properties'.(CMD-001)" -#@ return 0 -#@ } elseif {[info exists ra(-stream_layer_map_file)]} { -#@ echo "Error: Cannot specify '-technology' with '-stream_layer_map_file'.(CMD-001)" -#@ return 0 -#@ } else { -#@ set cmd [format {org_report_mw_lib -output %s %s} $ra(-output) $ra() ] -#@ return [uplevel #0 $cmd] -#@ } -#@ } -#@ -#@ if {[info exists ra(-plib)]} { -#@ if {[info exists ra(-stream_layer_map_file)]} { -#@ echo "Error: Cannot specify '-plib' with '-stream_layer_map_file'.(CMD-001)" -#@ return 0 -#@ } elseif {[info exists ra(-vt_cell_placement_properties)]} { -#@ echo "Error: Cannot specify '-plib' with '-vt_cell_placement_properties'.(CMD-001)" -#@ return 0 -#@ } else { -#@ set cmd [format {write_plib -lib_name %s %s} $ra() $ra(-output) ] -#@ return [uplevel #0 $cmd] -#@ } -#@ } -#@ -#@ if {[info exists ra(-vt_cell_placement_properties)]} { -#@ if {[info exists ra(-stream_layer_map_file)]} { -#@ echo "Error: Cannot specify '-vt_cell_placement_properties' with '-stream_layer_map_file'.(CMD-001)" -#@ return 0 -#@ } else { -#@ set cmd [format {org_report_mw_lib -vt_cell_placement_properties -output %s %s} $ra(-output) $ra() ] -#@ return [uplevel #0 $cmd] -#@ } -#@ } -#@ -#@ if {[info exists ra(-stream_layer_map_file)]} { -#@ set cmd [format {org_report_mw_lib -stream_layer_map_file %s -output %s %s} $ra(-stream_layer_map_file) $ra(-output) $ra() ] -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ } -#@ -#@ define_proc_attributes write_mw_lib_files -hide_body -info " Write technology or reference control file " -define_args {{-technology "Dump technology file" "" boolean {optional}} {-plib "Dump plib file" "" boolean {optional}} {-vt_cell_placement_properties "Dump multi-VT cells' implant layer information of library" "" boolean {optional hidden}} {-reference_control_file "Dump reference control file" "" boolean {optional}} {-stream_layer_map_file "Dump layer map file during stream in/out" "" string {optional}} {-output "Output file" "file_name" string {required}} {"" "Library to be reported" "libName" string {required}}} -#@ } -#@ ############################################################################## -#@ # -#@ # PROCEDURE: close_mw_cel -#@ # -#@ # ABSTRACT: Wrapper around close_mw_cel to add -save option -#@ # remove_timing_design is the command to shutdown dc netlist -#@ # -#@ ############################################################################## -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ -#@ proc close_mw_cel args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ global mw_is_all_views -#@ set cmd [format {icc_is_dc_up} ] -#@ set dc_is_up [uplevel #0 $cmd] -#@ -#@ set cmd_close [format {org_close_mw_cel} ] -#@ -#@ if {[info exists ra(-all_views)]} { -#@ set cmd_close [format {%s -all_views} $cmd_close] -#@ set mw_is_all_views 1 -#@ } -#@ if {[info exists ra(-all_versions)]} { -#@ set cmd_close [format {%s -all_versions} $cmd_close] -#@ } -#@ if {[info exists ra(-save)]} { -#@ set cmd_close [format {%s -save} $cmd_close] -#@ } -#@ if {[info exists ra(-verbose)]} { -#@ set cmd_close [format {%s -verbose} $cmd_close] -#@ } -#@ if {[info exists ra(-hierarchy)]} { -#@ set cmd_close [format {%s -hierarchy} $cmd_close] -#@ } -#@ -#@ ui_util_clean_saved_lib_attr $args -#@ -#@ set cmd "" -#@ set lcels "" -#@ set is_current_closed 1 -#@ -#@ if {[info exists ra()]} { -#@ set lcels $ra() -#@ } -#@ set len [string length $lcels] -#@ if {$len > 0} { -#@ set is_current_closed [is_current_mw_cel $lcels] -#@ set cmd_close [format {%s {%s}} $cmd_close $lcels] -#@ } -#@ if {[uplevel #0 $cmd_close]} { -#@ set mw_is_all_views 0 -#@ if {$dc_is_up == 1} { -#@ if {$is_current_closed == 1} { -#@ set cmd [format {remove_design -quiet -designs} ] -#@ return [uplevel #0 $cmd] -#@ } -#@ return 1 -#@ } else { -#@ return 1 -#@ } -#@ } else { -#@ set mw_is_all_views 0 -#@ return 0 -#@ } -#@ } -#@ -#@ define_proc_attributes close_mw_cel -hide_body -info " Closes the design " -define_args {{-save "Save the design" "" boolean {optional}} {-discard "Discard any changes" "" boolean {optional hidden}} {-verbose "Print out debugging messages" "" boolean {optional hidden}} {-hierarchy "Close top design and its child designs" "" boolean {optional}} {-all_views "Close all views of the design" "" boolean {optional}} {-all_versions "Close all versions of the design" "" boolean {optional}} {"" "designs to be closed" "design list" list {optional}}} -#@ -#@ ############################################################################## -#@ # -#@ # PROCEDURE: save_all_mw_cel -#@ # -#@ # ABSTRACT: Wrapper around save_mw_cel to save all the open cels. Needed for Black box flow. -#@ # -#@ ############################################################################## -#@ -#@ proc save_all_mw_cels { } { -#@ set top_cel [get_attribute [current_mw_cel] name] -#@ -#@ set cels [fp_get_open_cells] -#@ -#@ foreach cel $cels { -#@ if {$cel != $top_cel} { -#@ current_mw_cel $cel -#@ -#@ save_mw_cel -#@ } -#@ } -#@ -#@ current_mw_cel $top_cel -#@ -#@ save_mw_cel -#@ } -#@ -#@ icc_hide_cmd save_all_mw_cels -#@ -#@ ############################################################################## -#@ # PROCEDURE: execute_command_and_create_cel_from_scratch -#@ # ABSTRACT: This procedure executes the given command and creates the CEL -#@ # from scratch after executing this command. -#@ ############################################################################## -#@ proc execute_command_and_create_cel_from_scratch {org_cmd_name args} { -#@ global mw_create_cel_force -#@ global mw_enable_auto_cel -#@ global mw_force_auto_cel -#@ -#@ set lib [current_mw_lib] -#@ -#@ # If no MW lib, design is not from MW. Execute the original command -#@ # and return. -#@ if {$lib == ""} { -#@ return [eval $org_cmd_name $args] -#@ } -#@ -#@ # Get values of few variables. -#@ set incr_mode $mw_create_cel_force -#@ set mw_create_cel_force TRUE -#@ -#@ # Get auto cel mode, disable it temporarily if enabled. -#@ set auto_cel_mode $mw_enable_auto_cel -#@ set mw_enable_auto_cel FALSE -#@ -#@ # Check if the already existing CEL is auto-CEL. -#@ set auto_cel 0 -#@ if {[is_cel_auto_cel]} { -#@ set auto_cel 1 -#@ } elseif {![get_top_cel_mwid]} { -#@ set auto_cel 1 -#@ } -#@ -#@ -#@ # Run the original command, if not successful restore the incr_mode -#@ # variable and return. No CEL is created. -#@ if {![eval $org_cmd_name $args]} { -#@ set mw_create_cel_force $incr_mode -#@ set mw_enable_auto_cel $auto_cel_mode -#@ return 0 -#@ } -#@ -#@ # Restore auto_cel mode -#@ set mw_enable_auto_cel $auto_cel_mode -#@ -#@ # Now create auto or real CEL depending on what the original CEL was. -#@ if {$auto_cel == "1"} { -#@ # Force creation of auto-CEL, since commands other than read_def/pdef -#@ # do not decouple CEL from DC. -#@ -#@ set mw_force_auto_cel TRUE -#@ set cmd [format {save_mw_cel -auto}] -#@ } else { -#@ if [get_top_cel_mwid] { -#@ set cmd [format {save_mw_cel -create}] -#@ echo "Information: Command not supported by incr. update or write-thru." -#@ echo " Creating new CEL from scratch, old CEL will be closed." -#@ } -#@ } -#@ -#@ # Create the Auto CEL or normal CEL from scratch. -#@ if {![uplevel #0 $cmd]} { -#@ set mw_create_cel_force $incr_mode -#@ set mw_force_auto_cel FALSE -#@ return 0 -#@ } -#@ -#@ set mw_create_cel_force $incr_mode -#@ set mw_force_auto_cel FALSE -#@ return 1 -#@ } -#@ -#@ define_proc_attributes execute_command_and_create_cel_from_scratch -hidden -hide_body -#@ -#@ ############################################################################## -#@ # PROCEDURE: read_def -#@ # ABSTRACT: Wrapper around read_def to handle incremental update properly -#@ # if MW based read_def is used, bypass the wrapper -#@ # enable_milkyway_def_reader_writer must be TRUE and use_pdb_lib_format must -#@ # be false for MW read_Def to be run, use wrapper if either condition fails -#@ ############################################################################## -#@ rename -force dc_read_def org_read_def -#@ icc_hide_cmd org_read_def -#@ proc dc_read_def args { -#@ parse_proc_arguments -args $args ra -#@ -#@ return [eval execute_command_and_create_cel_from_scratch "org_read_def" $args] -#@ } -#@ -#@ define_proc_attributes dc_read_def -hide_body -info " Read a def file " -define_args {{-design "name of design for which clusters are to be read" "" string {optional}} {-quiet "do not print out any warnings" "" boolean {optional}} {-verbose "print out more warnings" "" boolean {optional}} {-allow_physical_cells "allow physical cells" "" boolean {optional}} {-allow_physical_ports "allow physical ports" "" boolean {optional}} {-allow_physical_nets "allow physical nets" "" boolean {optional}} {-skip_signal_nets "skip signal nets" "" boolean {optional}} {-incremental "incremental" "" boolean {optional}} {-enforce_scaling "enforce_scaling" "" boolean {optional}} {-move_bounds "move bounds" "" boolean {optional}} {"" "input def file names" "input_def_file_name" string {required}}} -#@ -#@ -#@ ############################################################################## -#@ # PROCEDURE: group -#@ # ABSTRACT: Wrapper around group to handle incremental update properly -#@ ############################################################################## -#@ rename -force group org_group -#@ icc_hide_cmd org_group -#@ proc group args { -#@ parse_proc_arguments -args $args ra -#@ return [eval execute_command_and_create_cel_from_scratch "org_group" $args] -#@ } -#@ -#@ define_proc_attributes group -hide_body -info " create new hierarchy" -define_args {{-except "cells not to be included in the group" "exclude_list" list {optional}} -#@ {-design_name "name of design created for new hierarchy" "design_name" string {optional}} -#@ {-cell_name "name of cell created for new hierarchy" "cell_name" string {optional}} -#@ {-logic "group any combinational elements" "" boolean {optional}} -#@ {-pla "group any PLA elements" "" boolean {optional}} -#@ {-fsm "group all elements part of a finite state machine" "" boolean {optional}} -#@ {-hdl_block "name of hdl_block to group" "" string {optional}} -#@ {-hdl_bussed "group all bussed gates under this block" "" boolean {optional}} -#@ {-hdl_all_blocks "group all hdl blocks under this block" "" boolean {optional}} -#@ {-soft "set the group_name attribute" "" boolean {optional}} -#@ {"" "cells to be included in the group" "cell_list" list {optional}}} -#@ -#@ ############################################################################## -#@ # PROCEDURE: copy_design -#@ # ABSTRACT: Wrapper around copy_design to handle incremental update properly -#@ ############################################################################## -#@ rename -force copy_design org_copy_design -#@ icc_hide_cmd org_copy_design -#@ proc copy_design args { -#@ parse_proc_arguments -args $args ra -#@ return [eval execute_command_and_create_cel_from_scratch "org_copy_design" $args] -#@ } -#@ -#@ define_proc_attributes copy_design -hide_body -info " copy_design" -define_args {{"" "List of designs to be copied" "design_list" list {required}} -#@ {"" "Name of new design or target file" "target_name" string {required}}} -#@ -#@ ############################################################################## -#@ # PROCEDURE: create_design -#@ # ABSTRACT: Wrapper around create_design to handle incremental update properly -#@ ############################################################################## -#@ rename -force create_design org_create_design -#@ icc_hide_cmd org_create_design -#@ proc create_design args { -#@ parse_proc_arguments -args $args ra -#@ return [eval execute_command_and_create_cel_from_scratch "org_create_design" $args] -#@ } -#@ -#@ define_proc_attributes create_design -hide_body -info " Creates a design in dc_shell memory" -define_args {{"" "name of the design to create" "" string {required}} -#@ {"" "name of file for design; optional" "" string {optional}}} -#@ -#@ ############################################################################## -#@ # PROCEDURE: reset_design -#@ # ABSTRACT: Wrapper around reset_design to handle incremental update properly -#@ ############################################################################## -#@ #rename -force reset_design org_reset_design -#@ #icc_hide_cmd org_reset_design -#@ #proc reset_design args { -#@ # parse_proc_arguments -args $args ra -#@ # return [eval execute_command_and_create_cel_from_scratch "org_reset_design" $args] -#@ #} -#@ -#@ ############################################################################## -#@ # PROCEDURE: rename_design -#@ # ABSTRACT: Wrapper around rename_design to handle incremental update properly -#@ ############################################################################## -#@ rename -force rename_design org_rename_design -#@ icc_hide_cmd org_rename_design -#@ proc rename_design args { -#@ parse_proc_arguments -args $args ra -#@ return [eval execute_command_and_create_cel_from_scratch "org_rename_design" $args] -#@ } -#@ -#@ define_proc_attributes rename_design -hide_body -info " rename_design" -define_args {{"" "List of designs to be renamed" "design_list" list {required}} -#@ {"" "Name of new design or target file" "target_name" string {required}}} -#@ -#@ } -#@ -#@ ############################################################################## -#@ # If we are in icc_shell (i.e. Galileo) then -#@ # load the procedures to switch between DC and Milkyway collections. -#@ # Set the default to MW collection unless otherwise specified. -#@ ############################################################################## -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ # load the procedures that switch between DC and MW collections -#@ source $synopsys_root/auxx/syn/collection_procs.tcl -#@ -#@ set CS mw -#@ -#@ # see if the user wants DC -#@ if {! [catch {getenv USE_DC_COLLECTIONS_ONLY}] && -#@ [getenv USE_DC_COLLECTIONS_ONLY] } { -#@ set CS dc -#@ } -#@ -#@ # set the collection source now -#@ redirect /dev/null { -#@ if {[catch {set_collection_mode -handle $CS}]} { -#@ catch {set_collection_option -handle $CS} -#@ } -#@ } -#@ -#@ unset CS -#@ } -#@ -#@ ############################################################################## -#@ # procedure for route command -#@ # echo the command to a temp tcl file for seperate process to pick up -#@ ############################################################################## -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ rename -force route org_route -#@ icc_hide_cmd org_route -#@ proc route args { -#@ set route_cmd_file_name ".route_cmd.tcl" -#@ set route_cmd_temp_file_name ".route_cmd.tcl.temp" -#@ set fp [open $route_cmd_file_name "w"] -#@ set route_cmd [concat "sep_proc_route " $args " -child"] -#@ puts $fp $route_cmd -#@ close $fp -#@ -#@ uplevel #0 rename -force route route_temp_proc -#@ uplevel #0 rename -force org_route route -#@ set status [ uplevel #0 route $args ] -#@ uplevel #0 rename -force route org_route -#@ uplevel #0 rename -force route_temp_proc route -#@ -#@ if { [info exist status ] == 1 } { -#@ return $status -#@ } -#@ return -#@ } -#@ } -#@ -#@ ############################################################################## -#@ # Tcl Command: set_ignore_cell -#@ # Description: Load the command only in IC Compiler (icc_shell) -#@ ############################################################################## -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ source $synopsys_root/auxx/syn/psyn/ideal_cell.tcl.e -#@ } -#@ -#@ ############################################################################## -#@ # Tcl Command: check_physical_design -#@ # Description: Load the command only in IC Compiler (icc_shell) -#@ ############################################################################## -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ # Load the compiled Tcl byte-code: -#@ # 9000784997: Do not log to command.log when sourcing .tbc files -#@ set prev_sh_source_logging [get_app_var sh_source_logging] -#@ set_app_var sh_source_logging 0 -#@ source $synopsys_root/auxx/syn/psyn/check_physical_design_core.tbc -#@ source $synopsys_root/auxx/syn/psyn/check_physical_design_utils.tbc -#@ source $synopsys_root/auxx/syn/psyn/check_physical_design_flows.tbc -#@ source $synopsys_root/auxx/syn/psyn/check_physical_design_reports.tbc -#@ source $synopsys_root/auxx/syn/psyn/check_physical_design_ui.tbc -#@ source $synopsys_root/auxx/syn/psyn/create_qor_snapshot.tbc -#@ source $synopsys_root/auxx/syn/psyn/report_qor_snapshot.tbc -#@ source $synopsys_root/auxx/syn/psyn/msgParser.tbc -#@ source $synopsys_root/auxx/syn/psyn/displacement_gui.tbc -#@ source $synopsys_root/auxx/syn/psyn/categorize_timing_gui.tbc -#@ set_app_var sh_source_logging $prev_sh_source_logging -#@ -#@ source $synopsys_root/auxx/syn/psyn/mcmm_utils.tcl.e -#@ source $synopsys_root/auxx/syn/psyn/propagate_all_clocks.tcl.e -#@ } -#@ -#@ if { [string match -nocase {*dc_shell*} $synopsys_program_name] && [shell_is_in_topographical_mode] } { -#@ # 9000784997: Do not log to command.log when sourcing .tbc files -#@ set prev_sh_source_logging [get_app_var sh_source_logging] -#@ set_app_var sh_source_logging 0 -#@ source $synopsys_root/auxx/syn/psyn/create_qor_snapshot.tbc -#@ source $synopsys_root/auxx/syn/psyn/report_qor_snapshot.tbc -#@ set_app_var sh_source_logging $prev_sh_source_logging -#@ -#@ source $synopsys_root/auxx/syn/psyn/mcmm_utils.tcl.e -#@ } -#@ -#@ if { $synopsys_program_name == "de_shell" } { -#@ # 9000784997: Do not log to command.log when sourcing .tbc files -#@ set prev_sh_source_logging [get_app_var sh_source_logging] -#@ set_app_var sh_source_logging 0 -#@ source $synopsys_root/auxx/syn/psyn/create_qor_snapshot.tbc -#@ source $synopsys_root/auxx/syn/psyn/report_qor_snapshot.tbc -#@ set_app_var sh_source_logging $prev_sh_source_logging -#@ -#@ source $synopsys_root/auxx/syn/psyn/mcmm_utils.tcl.e -#@ } -#@ -#@ ############################################################################## -#@ # ICC setup and hiding commands/procs etc -#@ ############################################################################## -#@ -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ #set save_mw_cel_lib_setup TRUE -#@ #set auto_restore_mw_cel_lib_setup FALSE -#@ -#@ alias create_wiring_keepout create_wiring_keepouts -#@ alias get_wiring_keepout get_wiring_keepouts -#@ alias get_placement_keepout get_placement_keepouts -#@ alias create_placement_keepout create_placement_keepouts -#@ -#@ icc_hide_cmd execute_command_and_create_cel_from_scratch -#@ icc_hide_cmd dc_read_def -#@ icc_hide_cmd read_edif -#@ icc_hide_cmd read_sverilog -#@ icc_hide_cmd read_vhdl -#@ icc_hide_cmd set_collection_mode -#@ icc_hide_cmd return_dc_collection -#@ icc_hide_cmd return_mw_collection -#@ set mw_use_pdb_lib_format true -#@ } -#@ -#@ -#@ ############################################################################## -#@ # Tcl Command: get_dont_touch_nets -#@ # Description: wrapper of "get_nets -filter dont_touch_reason==mv" -#@ ############################################################################## -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ -#@ proc get_dont_touch_nets args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {get_nets}] -#@ -#@ if {[info exists ra()]} { -#@ set cmd [format {%s {%s}} $cmd $ra()] -#@ } -#@ if {[info exists ra(-type)]} { -#@ set cmd [format {%s -filter dont_touch_reasons=~*%s*} $cmd $ra(-type)] -#@ } -#@ if {[info exists ra(-hierarchical)]} { -#@ set cmd [format {%s -hierarchical} $cmd] -#@ } -#@ if {[info exists ra(-quiet)]} { -#@ set cmd [format {%s -quiet} $cmd] -#@ } -#@ if {[info exists ra(-regexp)]} { -#@ set cmd [format {%s -regexp} $cmd] -#@ } -#@ if {[info exists ra(-nocase)]} { -#@ set cmd [format {%s -nocase} $cmd] -#@ } -#@ if {[info exists ra(-exact)]} { -#@ set cmd [format {%s -exact} $cmd] -#@ } -#@ -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes get_dont_touch_nets -info " Get dont_touch nets " -permanent -define_args { {"" "Match net names against patterns" "patterns" list {optional}} {-type "Match net dont_touch reasons" "reasons" list {required}} {-hierarchical "Search level-by-level in current instance" "" boolean {optional}} {-quiet "Suppress all messages" "" boolean {optional hidden}} {-regexp "Patterns are full regular expressions" "" boolean {optional hidden}} {-nocase "With -regexp, matches are case-insensitive" "" boolean {optional hidden}} {-exact "Wildcards are considered as plain characters" "" boolean {optional hidden}} } -#@ -#@ alias get_dont_touch_net get_dont_touch_nets -#@ } -#@ -#@ -#@ ############################################################################## -#@ # return the first {index value} pair in Tcl array ary. -#@ ############################################################################## -#@ proc _snps_array_peek { level ary } { -#@ upvar #$level $ary loc_ary -#@ set ret [list] -#@ set token [array startsearch loc_ary] -#@ while {[array anymore loc_ary $token]} { -#@ set k [array nextelement loc_ary $token] -#@ set v $loc_ary($k) -#@ set ret [list $k $v] -#@ break -#@ } -#@ array donesearch loc_ary $token -#@ return $ret; -#@ } -#@ define_proc_attributes _snps_array_peek -hidden -#@ # -- End source /tools/synopsys/synthesis/j201409sp3/auxx/syn/.dc_procs.tcl - -#@ -#@ # Temporary fix for the LMC_HOME variable- set it to an empty string -#@ -#@ if { [catch {getenv LMC_HOME } __err ] != 0 } { -#@ setenv LMC_HOME "" -#@ } -#@ -#@ -#@ # -#@ # -#@ # Site-Specific Variables -#@ # -#@ # These are the variables that are most commonly changed at a -#@ # specific site, either upon installation of the Synopsys software, -#@ # or by specific engineers in their local .synopsys files. -#@ # -#@ # -#@ -#@ # from the System Variable Group -#@ set link_library { * your_library.db } -#@ -#@ set search_path [list . ${synopsys_root}/libraries/syn ${synopsys_root}/minpower/syn ${synopsys_root}/dw/syn_ver ${synopsys_root}/dw/sim_ver] -#@ set target_library your_library.db -#@ set synthetic_library "" -#@ set command_log_file "./command.log" -#@ set designer "" -#@ set company "" -#@ set find_converts_name_lists "false" -#@ -#@ set symbol_library your_library.sdb -#@ -#@ # Turn on Formality SVF recording -#@ if { $synopsys_program_name == "dc_shell" || $synopsys_program_name == "de_shell" || $synopsys_program_name == "design_vision" } { -#@ set_svf -default default.svf -#@ } -#@ -#@ # from the Schematic Variable Group -#@ -#@ # from the Plot Variable Group -#@ # [froi] 07/06/2012: Remove old Design Analyzer plot_command variable -#@ #if { $sh_arch == "hp700" } { -#@ # set plot_command "lp -d" -#@ #} else { -#@ # set plot_command "lpr -Plw" -#@ #} -#@ -#@ set view_command_log_file "./view_command.log" -#@ -#@ # from the View Variable group -#@ if { $sh_arch == "hp700" } { -#@ set text_print_command "lp -d" -#@ } else { -#@ set text_print_command "lpr -Plw" -#@ } -#@ # -#@ # System Variable Group: -#@ # -#@ # These variables are system-wide variables. -#@ # -#@ set arch_init_path ${synopsys_root}/${sh_arch}/motif/syn/uid -#@ set auto_link_disable "false" -#@ set auto_link_options "-all" -#@ set uniquify_naming_style "%s_%d" -#@ set verbose_messages "true" -#@ set echo_include_commands "true" -#@ set svf_file_records_change_names_changes "true" -#@ set change_names_update_inst_tree "true" -#@ set change_names_dont_change_bus_members false -#@ set default_name_rules "" -#@ #set tdrc_enable_clock_table_creation "true" -#@ -#@ # -#@ # Compile Variable Group: -#@ # -#@ # These variables affect the designs created by the COMPILE command. -#@ # -#@ set compile_assume_fully_decoded_three_state_busses "false" -#@ set compile_no_new_cells_at_top_level "false" -#@ set compile_dont_touch_annotated_cell_during_inplace_opt "false" -#@ set compile_update_annotated_delays_during_inplace_opt "true" -#@ set compile_instance_name_prefix "U" -#@ set compile_instance_name_suffix "" -#@ set compile_negative_logic_methodology "false" -#@ set compile_disable_hierarchical_inverter_opt "false" -#@ set compile_use_low_timing_effort "false" -#@ set compile_fix_cell_degradation "false" -#@ set compile_preserve_subdesign_interfaces "false" -#@ set compile_enable_constant_propagation_with_no_boundary_opt "true" -#@ set port_complement_naming_style "%s_BAR" -#@ set compile_implementation_selection "true" -#@ set compile_delete_unloaded_sequential_cells "true" -#@ set reoptimize_design_changed_list_file_name "" -#@ set compile_checkpoint_phases "false" -#@ set compile_cpu_limit 0.0 -#@ set compile_log_format " %elap_time %area %wns %tns %drc %endpoint"; -#@ set compile_top_all_paths "false" -#@ set compile_top_acs_partition "false" -#@ set default_port_connection_class "universal" -#@ set compile_hold_reduce_cell_count "false" -#@ set compile_retime_license_behavior "wait" -#@ set dont_touch_nets_with_size_only_cells "false" -#@ if { $synopsys_program_name == "dc_shell" && [shell_is_in_topographical_mode] } { -#@ set dct_prioritize_area_correlation "false" -#@ set compile_error_on_missing_physical_cells "false" -#@ } -#@ -#@ set ldd_return_val 0 -#@ if { [string compare $dc_shell_mode "default"] == 0 } { -#@ set ldd_script ${synopsys_root}/auxx/syn/scripts/list_duplicate_designs.dcsh -#@ alias list_duplicate_designs "include -quiet ldd_script; dc_shell_status = ldd_return_val " -#@ -#@ } -#@ if { [string compare $dc_shell_mode "tcl"] == 0 } { -#@ if {$synopsys_program_name != "dc_sms_shell"} { -#@ source ${synopsys_root}/auxx/syn/scripts/list_duplicate_designs.tcl -#@ # 9000784997: Do not log to command.log when sourcing .tbc files -#@ set prev_sh_source_logging [get_app_var sh_source_logging] -#@ set_app_var sh_source_logging 0 -#@ source ${synopsys_root}/auxx/syn/scripts/analyze_datapath.tbc -#@ set_app_var sh_source_logging $prev_sh_source_logging -#@ } -#@ } -#@ # -- Starting source /tools/synopsys/synthesis/j201409sp3/auxx/syn/scripts/list_duplicate_designs.tcl - -#@ ####################################################################### -#@ # -#@ # list_duplicate_designs.tcl 21 Sept. 2006 -#@ # -#@ # List designs in dc_shell memory that have the same design name -#@ # -#@ # COPYRIGHT (C) 2006, SYNOPSYS INC., ALL RIGHTS RESERVED. -#@ # -#@ ####################################################################### -#@ -#@ proc list_duplicate_designs { args } { -#@ parse_proc_arguments -args $args ra -#@ -#@ # Get the list of duplicate designs -#@ set the_pid [pid] -#@ set rand_1 [expr int(rand() * 100000)] -#@ set temp_file_1 [format "/tmp/ldd_design_%s_%s" $the_pid $rand_1] -#@ -#@ redirect $temp_file_1 { foreach_in_collection ldd_design [find design "*"] { -#@ echo [get_object_name $ldd_design] -#@ } } -#@ -#@ set rand_2 [expr int(rand() * 100000)] -#@ set temp_file_2 [format "/tmp/ldd_design_%s_%s" $the_pid $rand_2] -#@ -#@ sh sort $temp_file_1 | uniq -d | tee $temp_file_2 -#@ file delete $temp_file_1 -#@ -#@ # Report duplicates -#@ if { ! [file size $temp_file_2] } { -#@ echo [concat {No duplicate designs found.}] -#@ set ldd_return_val 0 -#@ } else { -#@ set rand_3 [expr int(rand() * 100000)] -#@ set temp_file_3 [format "/tmp/ldd_design_%s_%s" $the_pid $rand_3] -#@ echo {Warning: Multiple designs in memory with the same design name.} -#@ echo {} -#@ echo { Design File Path} -#@ echo { ------ ---- ----} -#@ list_designs -table > $temp_file_3 -#@ echo [sh fgrep -f $temp_file_2 $temp_file_3 | sort | grep -v 'Design.*File.*Path'] -#@ file delete $temp_file_3 -#@ set ldd_return_val 1 -#@ } -#@ -#@ # Clean up -#@ file delete $temp_file_2 -#@ -#@ set list_duplicate_designs1 $ldd_return_val -#@ } -#@ -#@ define_proc_attributes list_duplicate_designs -info " List designs of same names" -permanent -define_args { -#@ } -#@ # -- End source /tools/synopsys/synthesis/j201409sp3/auxx/syn/scripts/list_duplicate_designs.tcl - -#@ -#@ -#@ set compile_log_format " %elap_time %area %wns %tns %drc %endpoint"; -#@ -#@ set compile_top_all_paths "false" -#@ alias compile_inplace_changed_list_file_name reoptimize_design_changed_list_file_name -#@ -#@ # -#@ # These variables affects compile, report_timing and report_constraints -#@ # commands. -#@ # -#@ set enable_recovery_removal_arcs "false" -#@ set timing_report_attributes {dont_touch dont_use map_only size_only ideal_net infeasible_paths} -#@ -#@ # -#@ # Multibit Variable Group: -#@ # -#@ # These variables affect the multibit mapping functionality -#@ # -#@ -#@ set bus_multiple_separator_style "," -#@ -#@ # -#@ # ILM Variable Group: -#@ # -#@ # These variables affect Interface Logic Model functionality -#@ # -#@ -#@ set ilm_ignore_percentage 25 -#@ -#@ # -#@ # Estimator Variable Group: -#@ # -#@ # These variables affect the designs created by the ESTIMATE command. -#@ # -#@ set estimate_resource_preference "fast" -#@ alias est_resource_preference estimate_resource_preference -#@ set lbo_lfo_enable_at_pin_count 3 -#@ set lbo_cells_in_regions "false" -#@ -#@ # Synthetic Library Group: -#@ # -#@ # These variable affect synthetic library processing. -#@ # -#@ set cache_dir_chmod_octal "777" -#@ set cache_file_chmod_octal "666" -#@ set cache_read "~" -#@ set cache_read_info "false" -#@ set cache_write "~" -#@ set cache_write_info "false" -#@ set synlib_dont_get_license {} -#@ set synlib_library_list {DW01 DW02 DW03 DW04 DW05 DW06 DW07} -#@ set synlib_wait_for_design_license {} -#@ set synlib_dwhomeip {} -#@ -#@ # -#@ # Insert_DFT Variable Group: -#@ # -#@ #set test_default_client_order [list] -#@ set insert_dft_clean_up "true" -#@ set insert_test_design_naming_style "%s_test_%d" -#@ # /*insert_test_scan_chain_only_one_clock = "false" -#@ # Replace by command line option (star 17215) -- Denis Martin 28-Jan-93*/ -#@ set test_clock_port_naming_style "test_c%s" -#@ set test_scan_clock_a_port_naming_style "test_sca%s" -#@ set test_scan_clock_b_port_naming_style "test_scb%s" -#@ set test_scan_clock_port_naming_style "test_sc%s" -#@ set test_scan_enable_inverted_port_naming_style "test_sei%s" -#@ set test_scan_enable_port_naming_style "test_se%s" -#@ set test_scan_in_port_naming_style "test_si%s%s" -#@ set test_scan_out_port_naming_style "test_so%s%s" -#@ set test_non_scan_clock_port_naming_style "test_nsc_%s" -#@ set test_default_min_fault_coverage 95 -#@ set test_dedicated_subdesign_scan_outs "false" -#@ set test_disable_find_best_scan_out "false" -#@ set test_dont_fix_constraint_violations "false" -#@ set test_isolate_hier_scan_out 0 -#@ set test_mode_port_naming_style "test_mode%s" -#@ set test_mode_port_inverted_naming_style "test_mode_i%s" -#@ set compile_dont_use_dedicated_scanout 1 -#@ set test_mux_constant_si "false" -#@ -#@ # -#@ # Analyze_Scan Variable Group: -#@ # -#@ # These variables affect the designs created by the PREVIEW_SCAN command. -#@ # -#@ set test_preview_scan_shows_cell_types "false" -#@ set test_scan_link_so_lockup_key "l" -#@ set test_scan_link_wire_key "w" -#@ set test_scan_segment_key "s" -#@ set test_scan_true_key "t" -#@ -#@ # -#@ # bsd Variable Group: -#@ -#@ # These variables affect the report generated by the check_bsd command -#@ # and the BSDLout generated by the write_bsdl command. -#@ # -#@ set test_user_test_data_register_naming_style "UTDR%d" -#@ -#@ set test_user_defined_instruction_naming_style "USER%d" -#@ -#@ set test_bsdl_default_suffix_name "bsdl" -#@ -#@ set test_bsdl_max_line_length 80 -#@ -#@ set test_cc_ir_masked_bits 0 -#@ -#@ set test_cc_ir_value_of_masked_bits 0 -#@ -#@ set test_bsd_allow_tolerable_violations "false" -#@ set test_bsd_optimize_control_cell "false" -#@ set test_bsd_control_cell_drive_limit 0 -#@ set test_bsd_manufacturer_id 0 -#@ set test_bsd_part_number 0 -#@ set test_bsd_version_number 0 -#@ set bsd_max_in_switching_limit 60000 -#@ set bsd_max_out_switching_limit 60000 -#@ -#@ # -#@ # TestManager Variable Group: -#@ # -#@ # These variables affect the TestManager methodology. -#@ # -#@ set multi_pass_test_generation "false" -#@ -#@ # -#@ # TestSim Variable Group: -#@ # -#@ # These variables affect the TestSim behavior. -#@ # -#@ # set testsim_print_stats_file "true" -#@ -#@ # Test DRC Variable Group: -#@ # -#@ # These variables affect the check_test command. -#@ # -#@ set test_capture_clock_skew "small_skew" -#@ set test_allow_clock_reconvergence "true" -#@ set test_check_port_changes_in_capture "true" -#@ set test_infer_slave_clock_pulse_after_capture "infer" -#@ -#@ # -#@ # Test Variable Group: -#@ # -#@ # These variables affect the rtldrc, check_test, write_test_protocol -#@ # and write_test command. -#@ # -#@ set test_default_delay 0.0 -#@ set test_default_bidir_delay 0.0 -#@ set test_default_strobe 40.0 -#@ set test_default_strobe_width 0.0 -#@ set test_default_period 100.0 -#@ set test_stil_max_line_length 72 -#@ -#@ #added for B-2008.09-place_opt-004 to disable this option in ICC -#@ -#@ if { $synopsys_program_name != "icc_shell"} { -#@ set test_write_four_cycle_stil_protocol "false" -#@ set test_protocol_add_cycle "true" -#@ set test_stil_multiclock_capture_procedures "false" -#@ set write_test_new_translation_engine "false" -#@ set test_default_scan_style "multiplexed_flip_flop" -#@ set test_jump_over_bufs_invs "true" -#@ set test_point_keep_hierarchy "false" -#@ set test_mux_constant_so "false" -#@ set test_use_test_models "false" -#@ set test_stil_netlist_format "db" -#@ group_variable test "test_protocol_add_cycle" -#@ group_variable test "test_write_four_cycle_stil_protocol" -#@ group_variable test "test_stil_multiclock_capture_procedures" -#@ group_variable test "test_default_scan_style" -#@ group_variable preview_scan "test_jump_over_bufs_invs" -#@ group_variable insert_dft "test_point_keep_hierarchy" -#@ group_variable insert_dft "test_mux_constant_so" -#@ group_variable test "test_stil_netlist_format" -#@ } -#@ set test_rtldrc_latch_check_style "default" -#@ set test_enable_capture_checks "true" -#@ set ctldb_use_old_prot_flow "false" -#@ set test_bsd_default_delay 0.0 -#@ set test_bsd_default_bidir_delay 0.0 -#@ set test_bsd_default_strobe 95.0 -#@ set test_bsd_default_strobe_width 0.0 -#@ -#@ # -#@ # Test Variable Group: -#@ # -#@ # These variables affects the set_scan_state command. -#@ # -#@ -#@ set compile_seqmap_identify_shift_registers_with_synchronous_logic_ascii false -#@ -#@ # -#@ # Write_Test Variable Group: -#@ # -#@ # These variables affect output of the WRITE_TEST command. -#@ # -#@ set write_test_input_dont_care_value "X" -#@ set write_test_vector_file_naming_style "%s_%d.%s" -#@ set write_test_scan_check_file_naming_style "%s_schk.%s" -#@ set write_test_pattern_set_naming_style "TC_Syn_%d" -#@ set write_test_max_cycles 0 -#@ set write_test_max_scan_patterns 0 -#@ # /*retain "tssi_ascii" (equivalent to "tds") for backward compatability */ -#@ set write_test_formats {synopsys tssi_ascii tds verilog vhdl wgl} -#@ set write_test_include_scan_cell_info "true" -#@ set write_test_round_timing_values "true" -#@ -#@ -#@ # -#@ # Schematic and EDIF and Hdl Variable Groups: -#@ # -#@ # These variables affect the schematics created by the -#@ # create_schematic command, define the behavior of the -#@ # DC system EDIF interface, and are for controlling hdl -#@ # reading. -#@ # -#@ set bus_dimension_separator_style {][} -#@ set bus_naming_style {%s[%d]} -#@ -#@ -#@ # -#@ # Schematic and EDIF Variable Groups: -#@ # -#@ # These variables affect the schematics created by the -#@ # create_schematic command and define the behavior of -#@ # the DC system EDIF interface. -#@ # -#@ set bus_range_separator_style ":" -#@ -#@ -#@ # -#@ # EDIF and Io Variable Groups: -#@ # -#@ # These variables define the behavior of the DC system EDIF interface and -#@ # define the behavior of the DC system interfaces, i.e. LSI, Mentor, TDL, SGE,# etc. -#@ -#@ set bus_inference_descending_sort "true" -#@ set bus_inference_style "" -#@ set write_name_nets_same_as_ports "false" -#@ # -#@ # Schematic Variable Group: -#@ # -#@ # These variables affect the schematics created by the -#@ # create_schematic command. -#@ # -#@ set font_library "1_25.font" -#@ set generic_symbol_library "generic.sdb" -#@ -#@ # -#@ # Io Variable Group: -#@ # -#@ # These variables define the behavior of the DC system -#@ # interfaces, i.e. LSI, Mentor, TDL, SGE, etc. -#@ # -#@ #set db2sge_output_directory "" -#@ #set db2sge_scale "2" -#@ #set db2sge_overwrite "true" -#@ #set db2sge_display_symbol_names "false" -#@ -#@ -#@ #set db2sge_display_pin_names "false" -#@ #set db2sge_display_instance_names "false" -#@ #set db2sge_use_bustaps "false" -#@ #set db2sge_use_compound_names "true" -#@ #set db2sge_bit_type "std_logic" -#@ #set db2sge_bit_vector_type "std_logic_vector" -#@ #set db2sge_one_name "'1'" -#@ #set db2sge_zero_name "'0'" -#@ #set db2sge_unknown_name "'X'" -#@ #set db2sge_target_xp "false" -#@ #set db2sge_tcf_package_file "synopsys_tcf.vhd" -#@ #set db2sge_use_lib_section "" -#@ #set db2sge_script "" -#@ #set db2sge_command "" -#@ -#@ # set equationout_and_sign "*" -#@ # set equationout_or_sign "+" -#@ # set equationout_postfix_negation "true" -#@ -#@ # # [wjchen] 2006/08/14: The following variables are obsoleted for DC simpilification. -#@ #set lsiin_net_name_prefix "NET_" -#@ #set lsiout_inverter_cell "" -#@ #set lsiout_upcase "true" -#@ -#@ #set mentor_bidirect_value "INOUT" -#@ #set mentor_do_path "" -#@ #set mentor_input_output_property_name "PINTYPE" -#@ #set mentor_input_value "IN" -#@ #set mentor_logic_one_value "1SF" -#@ #set mentor_logic_zero_one_property_name "INIT" -#@ #set mentor_logic_zero_value "0SF" -#@ #set mentor_output_value "OUT" -#@ #set mentor_primitive_property_name "PRIMITIVE" -#@ #set mentor_primitive_property_value "MODULE" -#@ #set mentor_reference_property_name "COMP" -#@ #set mentor_search_path "" -#@ #set mentor_write_symbols "true" -#@ -#@ ## [wjchen] 0606_simp -#@ #set pla_read_create_flip_flop "false" -#@ #set tdlout_upcase "true" -#@ -#@ # # [wjchen] 2006/08/14: The following4 variables are obsoleted for DC simpilification. -#@ # set xnfout_constraints_per_endpoint "50" -#@ # set xnfout_default_time_constraints true -#@ # set xnfout_clock_attribute_style "CLK_ONLY" -#@ # set xnfout_library_version "" -#@ -#@ # # [wjchen] 2006/08/11: The following 8 variables are obsoleted for DC simpilification. -#@ # set xnfin_family "4000" -#@ # set xnfin_ignore_pins "GTS GSR GR" -#@ # set xnfin_dff_reset_pin_name "RD" -#@ # set xnfin_dff_set_pin_name "SD" -#@ # set xnfin_dff_clock_enable_pin_name "CE" -#@ # set xnfin_dff_data_pin_name "D" -#@ # set xnfin_dff_clock_pin_name "C" -#@ # set xnfin_dff_q_pin_name "Q" -#@ # -#@ -#@ # -#@ # EDIF Variable Group: -#@ # -#@ # These variables define the behavior of the DC system -#@ # EDIF interface. -#@ # -#@ -#@ ##[wjchen] 2006/08/24 -#@ -#@ # set bus_extraction_style {%s[%d:%d]} -#@ -#@ ##[wjchen] 2006/08/24 -#@ #set edifin_autoconnect_offpageconnectors "false" -#@ #set edifin_autoconnect_ports "false" -#@ #set edifin_dc_script_flag "" -#@ #set edifin_delete_empty_cells "true" -#@ #set edifin_delete_ripper_cells "true" -#@ #set edifin_ground_net_name "" -#@ #set edifin_ground_net_property_name "" -#@ #set edifin_ground_net_property_value "" -#@ #set edifin_ground_port_name "" -#@ #set edifin_instance_property_name "" -#@ #set edifin_portinstance_disabled_property_name "" -#@ #set edifin_portinstance_disabled_property_value "" -#@ #set edifin_portinstance_property_name "" -#@ #set edifin_power_net_name "" -#@ #set edifin_power_net_property_name "" -#@ #set edifin_power_net_property_value "" -#@ #set edifin_power_port_name "" -#@ #set edifin_use_identifier_in_rename "false" -#@ #set edifin_view_identifier_property_name "" -#@ #set edifin_lib_logic_1_symbol "" -#@ #set edifin_lib_logic_0_symbol "" -#@ #set edifin_lib_in_port_symbol "" -#@ #set edifin_lib_out_port_symbol "" -#@ #set edifin_lib_inout_port_symbol "" -#@ #set edifin_lib_in_osc_symbol "" -#@ #set edifin_lib_out_osc_symbol "" -#@ #set edifin_lib_inout_osc_symbol "" -#@ #set edifin_lib_mentor_netcon_symbol "" -#@ #set edifin_lib_ripper_bits_property "" -#@ #set edifin_lib_ripper_bus_end "" -#@ #set edifin_lib_ripper_cell_name "" -#@ #set edifin_lib_ripper_view_name "" -#@ #set edifin_lib_route_grid 1024 -#@ #set edifin_lib_templates {} -#@ #set edifout_dc_script_flag "" -#@ #set edifout_design_name "Synopsys_edif" -#@ #set edifout_designs_library_name "DESIGNS" -#@ #set edifout_display_instance_names "false" -#@ #set edifout_display_net_names "false" -#@ #set edifout_external "true" -#@ #set edifout_external_graphic_view_name "Graphic_representation" -#@ #set edifout_external_netlist_view_name "Netlist_representation" -#@ #set edifout_external_schematic_view_name "Schematic_representation" -#@ #set edifout_ground_name "logic_0" -#@ #set edifout_ground_net_name "" -#@ #set edifout_ground_net_property_name "" -#@ #set edifout_ground_net_property_value "" -#@ #set edifout_ground_pin_name "logic_0_pin" -#@ #set edifout_ground_port_name "GND" -#@ #set edifout_instance_property_name "" -#@ #set edifout_instantiate_ports "false" -#@ #set edifout_library_graphic_view_name "Graphic_representation" -#@ #set edifout_library_netlist_view_name "Netlist_representation" -#@ #set edifout_library_schematic_view_name "Schematic_representation" -#@ #set edifout_merge_libraries "false" -#@ #set edifout_multidimension_arrays "false" -#@ #set edifout_name_oscs_different_from_ports "false" -#@ #set edifout_name_rippers_same_as_wires "false" -#@ #set edifout_netlist_only "false" -#@ #set edifout_no_array "false" -#@ #set edifout_numerical_array_members "false" -#@ #set edifout_pin_direction_in_value "" -#@ #set edifout_pin_direction_inout_value "" -#@ #set edifout_pin_direction_out_value "" -#@ #set edifout_pin_direction_property_name "" -#@ #set edifout_pin_name_property_name "" -#@ #set edifout_portinstance_disabled_property_name "" -#@ #set edifout_portinstance_disabled_property_value "" -#@ #set edifout_portinstance_property_name "" -#@ #set edifout_power_and_ground_representation "cell" -#@ #set edifout_power_name "logic_1" -#@ #set edifout_power_net_name "" -#@ #set edifout_power_net_property_name "" -#@ #set edifout_power_net_property_value "" -#@ #set edifout_power_pin_name "logic_1_pin" -#@ #set edifout_power_port_name "VDD" -#@ #set edifout_skip_port_implementations "false" -#@ #set edifout_target_system "" -#@ #set edifout_top_level_symbol "true" -#@ #set edifout_translate_origin "" -#@ #set edifout_unused_property_value "" -#@ #set edifout_write_attributes "false" -#@ #set edifout_write_constraints "false" -#@ #set edifout_write_properties_list {} -#@ #set read_name_mapping_nowarn_libraries {} -#@ #set write_name_mapping_nowarn_libraries {} -#@ -#@ # -#@ # Hdl and Vhdlio Variable Groups: -#@ # -#@ # These variables are for controlling hdl reading, writing, -#@ # and optimizing. -#@ # -#@ set hdlin_enable_upf_compatible_naming "FALSE" -#@ set hdlin_auto_save_templates "FALSE" -#@ set hdlin_generate_naming_style "%s_%d" -#@ set hdlin_enable_relative_placement "rb" -#@ set hdlin_mux_rp_limit "128x4" -#@ set hdlin_generate_separator_style "_" -#@ set hdlin_ignore_textio_constructs "TRUE" -#@ set hdlin_infer_function_local_latches "FALSE" -#@ set hdlin_keep_signal_name "all_driving" -#@ set hdlin_module_arch_name_splitting "FALSE" -#@ set hdlin_preserve_sequential "none" -#@ set hdlin_presto_net_name_prefix "N" -#@ set hdlin_presto_cell_name_prefix "C" -#@ set hdlin_strict_verilog_reader "FALSE" -#@ set hdlin_prohibit_nontri_multiple_drivers "TRUE" -#@ if { $synopsys_program_name == "de_shell" } { -#@ set hdlin_elab_errors_deep "TRUE" -#@ } else { -#@ set hdlin_elab_errors_deep "FALSE" -#@ } -#@ set hdlin_mux_size_min 2 -#@ set hdlin_subprogram_default_values "FALSE" -#@ set hdlin_field_naming_style "" -#@ set hdlin_upcase_names "FALSE" -#@ set hdlin_sv_union_member_naming "FALSE" -#@ set hdlin_vhdl_std 2008 -#@ set hdlin_vhdl93_concat "TRUE" -#@ set hdlin_vhdl_syntax_extensions "FALSE" -#@ set hdlin_analyze_verbose_mode 0 -#@ set hdlin_report_sequential_pruning "FALSE" -#@ set hdlin_vrlg_std 2005 -#@ set hdlin_sverilog_std 2012 -#@ set hdlin_while_loop_iterations 4096 -#@ set hdlin_reporting_level "basic" -#@ set hdlin_autoread_verilog_extensions ".v" -#@ set hdlin_autoread_sverilog_extensions ".sv .sverilog" -#@ set hdlin_autoread_vhdl_extensions ".vhd .vhdl" -#@ set hdlin_autoread_exclude_extensions "" -#@ -#@ set bus_minus_style "-%d" -#@ set hdlin_latch_always_async_set_reset FALSE -#@ set hdlin_ff_always_sync_set_reset FALSE -#@ set hdlin_ff_always_async_set_reset TRUE -#@ set hdlin_check_input_netlist FALSE -#@ set hdlin_check_no_latch FALSE -#@ set hdlin_mux_for_array_read_sparseness_limit 90 -#@ set hdlin_infer_mux "default" -#@ set hdlin_mux_oversize_ratio 100 -#@ set hdlin_mux_size_limit 32 -#@ set hdlin_mux_size_only 1 -#@ set hdlin_infer_multibit "default_none" -#@ set hdlin_enable_rtldrc_info "false" -#@ set hdlin_interface_port_ABI 3 -#@ set hdlin_shorten_long_module_name "false" -#@ set hdlin_module_name_limit 256 -#@ set hdlin_enable_assertions "FALSE" -#@ set hdlin_enable_configurations "FALSE" -#@ set hdlin_sv_blackbox_modules "" -#@ set hdlin_sv_tokens "FALSE" -#@ set hdlin_sv_packages "enable" -#@ set hdlin_verification_priority "FALSE" -#@ set hdlin_enable_elaborate_ref_linking "FALSE" -#@ set hdlin_enable_hier_naming "FALSE" -#@ set hdlin_vhdl_mixed_language_instantiation "FALSE" -#@ set hdl_preferred_license "" -#@ set hdl_keep_licenses "true" -#@ set hlo_resource_allocation "constraint_driven" -#@ set sdfout_top_instance_name "" -#@ set sdfout_time_scale 1.0 -#@ set sdfout_min_rise_net_delay 0. -#@ set sdfout_min_fall_net_delay 0. -#@ set sdfout_min_rise_cell_delay 0. -#@ set sdfout_min_fall_cell_delay 0. -#@ set sdfout_write_to_output "false" -#@ set sdfout_allow_non_positive_constraints "false" -#@ set sdfin_top_instance_name "" -#@ set sdfin_min_rise_net_delay 0. -#@ set sdfin_min_fall_net_delay 0. -#@ set sdfin_min_rise_cell_delay 0. -#@ set sdfin_min_fall_cell_delay 0. -#@ set sdfin_rise_net_delay_type "maximum" -#@ set sdfin_fall_net_delay_type "maximum" -#@ set sdfin_rise_cell_delay_type "maximum" -#@ set sdfin_fall_cell_delay_type "maximum" -#@ set site_info_file ${synopsys_root}/admin/license/site_info -#@ if { [string compare $dc_shell_mode "tcl"] == 0 } { -#@ alias site_info sh cat $site_info_file -#@ } else { -#@ alias site_info "sh cat site_info_file" -#@ } -#@ set template_naming_style "%s_%p" -#@ set template_parameter_style "%s%d" -#@ set template_separator_style "_" -#@ set verilogout_equation "false" -#@ set verilogout_ignore_case "false" -#@ set verilogout_no_tri "false" -#@ set verilogout_inout_is_in "false" -#@ set verilogout_single_bit "false" -#@ set verilogout_higher_designs_first "FALSE" -#@ # set verilogout_levelize "FALSE" -#@ set verilogout_include_files {} -#@ set verilogout_unconnected_prefix "SYNOPSYS_UNCONNECTED_" -#@ set verilogout_show_unconnected_pins "FALSE" -#@ set verilogout_no_negative_index "FALSE" -#@ #set enable_2003.03_verilog_reader TRUE -#@ # to have a net instead of 1'b0 and 1'b1 in inouts: -#@ set verilogout_indirect_inout_connection "FALSE" -#@ -#@ # set vhdlout_architecture_name "SYN_%a_%u" -#@ set vhdlout_bit_type "std_logic" -#@ # set vhdlout_bit_type_resolved "TRUE" -#@ set vhdlout_bit_vector_type "std_logic_vector" -#@ # set vhdlout_conversion_functions {} -#@ # set vhdlout_dont_write_types "FALSE" -#@ set vhdlout_equations "FALSE" -#@ set vhdlout_one_name "'1'" -#@ set vhdlout_package_naming_style "CONV_PACK_%d" -#@ set vhdlout_preserve_hierarchical_types "VECTOR" -#@ set vhdlout_separate_scan_in "FALSE" -#@ set vhdlout_single_bit "USER" -#@ set vhdlout_target_simulator "" -#@ set vhdlout_three_state_name "'Z'" -#@ set vhdlout_three_state_res_func "" -#@ # set vhdlout_time_scale 1.0 -#@ set vhdlout_top_configuration_arch_name "A" -#@ set vhdlout_top_configuration_entity_name "E" -#@ set vhdlout_top_configuration_name "CFG_TB_E" -#@ set vhdlout_unknown_name "'X'" -#@ set vhdlout_upcase "FALSE" -#@ set vhdlout_use_packages {IEEE.std_logic_1164} -#@ set vhdlout_wired_and_res_func "" -#@ set vhdlout_wired_or_res_func "" -#@ set vhdlout_write_architecture "TRUE" -#@ set vhdlout_write_components "TRUE" -#@ set vhdlout_write_entity "TRUE" -#@ set vhdlout_write_top_configuration "FALSE" -#@ # set vhdlout_synthesis_off "TRUE" -#@ set vhdlout_zero_name "'0'" -#@ #set vhdlout_levelize "FALSE" -#@ set vhdlout_dont_create_dummy_nets "FALSE" -#@ set vhdlout_follow_vector_direction "TRUE" -#@ -#@ -#@ # vhdl netlist reader variables -#@ set enable_vhdl_netlist_reader "FALSE" -#@ -#@ # variables pertaining to VHDL library generation -#@ set vhdllib_timing_mesg "true" -#@ set vhdllib_timing_xgen "false" -#@ set vhdllib_timing_checks "true" -#@ set vhdllib_negative_constraint "false" -#@ set vhdllib_glitch_handle "true" -#@ set vhdllib_pulse_handle "use_vhdllib_glitch_handle" -#@ # /*vhdllib_architecture = {FTBM, UDSM, FTSM, FTGS, VITAL}; */ -#@ set vhdllib_architecture {VITAL} -#@ set vhdllib_tb_compare 0 -#@ set vhdllib_tb_x_eq_dontcare FALSE -#@ set vhdllib_logic_system "ieee-1164" -#@ set vhdllib_logical_name "" -#@ -#@ # variables pertaining to technology library processing -#@ set read_db_lib_warnings FALSE -#@ set read_translate_msff TRUE -#@ set libgen_max_differences -1 -#@ -#@ # -#@ # Gui Variable Group -#@ # used for design_vision and psyn_gui -#@ # -#@ set gui_auto_start 0 -#@ set gui_start_option_no_windows 0 -#@ group_variable gui_variables "gui_auto_start" -#@ group_variable gui_variables "gui_start_option_no_windows" -#@ -#@ # -#@ # If you like emacs, uncomment the next line -#@ # set text_editor_command "emacs -fn 8x13 %s &" ; -#@ -#@ # You can delete pairs from this list, but you can't add new ones -#@ # unless you also update the UIL files. So, customers can not add -#@ # dialogs to this list, only Synopsys can do that. -#@ # -#@ set view_independent_dialogs { "test_report" " Test Reports " "report_print" " Report " "report_options" " Report Options " "report_win" " Report Output " "manual_page" " Manual Page " } -#@ -#@ # if color Silicon Graphics workstation -#@ if { [info exists x11_vendor_string] && [info exists x11_is_color]} { -#@ if { $x11_vendor_string == "Silicon" && $x11_is_color == "true" } { -#@ set x11_set_cursor_foreground "magenta" -#@ set view_use_small_cursor "true" -#@ set view_set_selecting_color "white" -#@ } -#@ } -#@ -#@ # if running on an Apollo machine -#@ set found_x11_vendor_string_apollo 0 -#@ set found_arch_apollo 0 -#@ if { [info exists x11_vendor_string]} { -#@ if { $x11_vendor_string == "Apollo "} { -#@ set found_x11_vendor_string_apollo 1 -#@ } -#@ } -#@ if { [info exists arch]} { -#@ if { $arch == "apollo"} { -#@ set found_arch_apollo 1 -#@ } -#@ } -#@ if { $found_x11_vendor_string_apollo == 1 || $found_arch_apollo == 1} { -#@ set enable_page_mode "false" -#@ } else { -#@ set enable_page_mode "true" -#@ } -#@ -#@ # don't work around this bug on the Apollo -#@ if { $found_x11_vendor_string_apollo == 1} { -#@ set view_extend_thick_lines "false" -#@ } else { -#@ set view_extend_thick_lines "true" -#@ } -#@ -#@ # -#@ # Suffix Variable Group: -#@ # -#@ # Suffixes recognized by the Design Analyzer menu in file choices -#@ # -#@ if { $synopsys_program_name == "design_vision" || $synopsys_program_name == "psyn_gui" } { -#@ # For star 93040 do NOT include NET in list, 108991 : pdb suffix added -#@ set view_read_file_suffix {db gdb sdb pdb edif eqn fnc lsi mif pla st tdl v vhd vhdl xnf} -#@ } else { -#@ set view_read_file_suffix {db gdb sdb edif eqn fnc lsi mif NET pla st tdl v vhd vhdl xnf} -#@ } -#@ -#@ set view_analyze_file_suffix {v vhd vhdl} -#@ set view_write_file_suffix {gdb db sdb do edif eqn fnc lsi NET neted pla st tdl v vhd vhdl xnf} -#@ set view_execute_script_suffix {.script .scr .dcs .dcv .dc .con} -#@ set view_arch_types {sparcOS5 hpux10 rs6000 sgimips} -#@ -#@ # -#@ # links_to_layout Variable Group: -#@ # -#@ # These variables affect the read_timing, write_timing -#@ # set_annotated_delay, compile, create_wire_load and reoptimize_design -#@ # commands. -#@ # -#@ if {$synopsys_program_name != "dc_sms_shell"} { -#@ set auto_wire_load_selection "true" -#@ set compile_create_wire_load_table "false" -#@ } -#@ set rtl_load_resistance_factor 0.0 -#@ -#@ # power Variable Group: -#@ # -#@ # These variables affect the behavior of power optimization and analysis. -#@ # -#@ -#@ set power_keep_license_after_power_commands "false" -#@ set power_rtl_saif_file "power_rtl.saif" -#@ set power_sdpd_saif_file "power_sdpd.saif" -#@ set power_preserve_rtl_hier_names "false" -#@ set power_do_not_size_icg_cells "true" -#@ set power_hdlc_do_not_split_cg_cells "false" -#@ set power_cg_flatten "false" -#@ set power_opto_extra_high_dynamic_power_effort "false" -#@ set power_default_static_probability 0.5 -#@ set power_default_toggle_rate 0.1 -#@ set power_default_toggle_rate_type "fastest_clock" -#@ set power_model_preference "nlpm" -#@ set power_sa_propagation_effort "low" -#@ set power_sa_propagation_verbose "false" -#@ set power_fix_sdpd_annotation "true" -#@ set power_fix_sdpd_annotation_verbose "false" -#@ set power_sdpd_message_tolerance 0.00001 -#@ set do_operand_isolation "false" -#@ set power_cg_module_naming_style "" -#@ set power_cg_cell_naming_style "" -#@ set power_cg_gated_clock_net_naming_style "" -#@ set power_rclock_use_asynch_inputs "false" -#@ set power_rclock_inputs_use_clocks_fanout "true" -#@ set power_rclock_unrelated_use_fastest "true" -#@ set power_lib2saif_rise_fall_pd "false" -#@ set power_min_internal_power_threshold "" -#@ -#@ -#@ # SystemC related variables -#@ set systemcout_levelize "true" -#@ set systemcout_debug_mode "false" -#@ -#@ # ACS Variables -#@ if { [info exists acs_work_dir] } { -#@ set acs_area_report_suffix "area" -#@ set acs_autopart_max_area "0.0" -#@ set acs_autopart_max_percent "0.0" -#@ set acs_budgeted_cstr_suffix "con" -#@ set acs_compile_script_suffix "autoscr" -#@ set acs_constraint_file_suffix "con" -#@ set acs_cstr_report_suffix "cstr" -#@ set acs_db_suffix "db" -#@ set acs_dc_exec "" -#@ set acs_default_pass_name "pass" -#@ set acs_exclude_extensions {} -#@ set acs_exclude_list [list $synopsys_root] -#@ set acs_global_user_compile_strategy_script "default" -#@ set acs_hdl_verilog_define_list {} -#@ set acs_hdl_source {} -#@ set acs_lic_wait 0 -#@ set acs_log_file_suffix "log" -#@ set acs_make_args "set acs_make_args" -#@ set acs_make_exec "gmake" -#@ set acs_makefile_name "Makefile" -#@ set acs_num_parallel_jobs 1 -#@ set acs_override_report_suffix "report" -#@ set acs_override_script_suffix "scr" -#@ set acs_qor_report_suffix "qor" -#@ set acs_timing_report_suffix "tim" -#@ set acs_use_autopartition "false" -#@ set acs_use_default_delays "false" -#@ set acs_user_budgeting_script "budget.scr" -#@ set acs_user_compile_strategy_script_suffix "compile" -#@ set acs_verilog_extensions {.v} -#@ set acs_vhdl_extensions {.vhd} -#@ set acs_work_dir [pwd] -#@ set check_error_list [list CMD-004 CMD-006 CMD-007 CMD-008 CMD-009 CMD-010 CMD-011 CMD-012 CMD-014 CMD-015 CMD-016 CMD-019 CMD-026 CMD-031 CMD-037 DB-1 DCSH-11 DES-001 ACS-193 FILE-1 FILE-2 FILE-3 FILE-4 LINK-7 LINT-7 LINT-20 LNK-023 OPT-100 OPT-101 OPT-102 OPT-114 OPT-124 OPT-127 OPT-128 OPT-155 OPT-157 OPT-181 OPT-462 UI-11 UI-14 UI-15 UI-16 UI-17 UI-19 UI-20 UI-21 UI-22 UI-23 UI-40 UI-41 UID-4 UID-6 UID-7 UID-8 UID-9 UID-13 UID-14 UID-15 UID-19 UID-20 UID-25 UID-27 UID-28 UID-29 UID-30 UID-32 UID-58 UID-87 UID-103 UID-109 UID-270 UID-272 UID-403 UID-440 UID-444 UIO-2 UIO-3 UIO-4 UIO-25 UIO-65 UIO-66 UIO-75 UIO-94 UIO-95 EQN-6 EQN-11 EQN-15 EQN-16 EQN-18 EQN-20 ] -#@ set ilm_preserve_core_constraints "false" -#@ } -#@ -#@ # -#@ # -#@ # DesignTime Variable Group -#@ # -#@ # The variables which affect the DesignTime timing engine -#@ # -#@ -#@ set case_analysis_log_file "" -#@ set case_analysis_sequential_propagate "false" -#@ set create_clock_no_input_delay "false" -#@ set disable_auto_time_borrow "false" -#@ set disable_case_analysis "false" -#@ set disable_conditional_mode_analysis "false" -#@ set disable_library_transition_degradation "false" -#@ set dont_bind_unused_pins_to_logic_constant "false" -#@ set enable_slew_degradation "true" -#@ set high_fanout_net_pin_capacitance 1.000000 -#@ set high_fanout_net_threshold 1000 -#@ set lib_thresholds_per_lib "true" -#@ set rc_adjust_rd_when_less_than_rnet "true" -#@ set rc_ceff_delay_min_diff_ps 0.250000 -#@ set rc_degrade_min_slew_when_rd_less_than_rnet "false" -#@ set rc_driver_model_max_error_pct 0.160000 -#@ set rc_filter_rd_less_than_rnet "true" -#@ set rc_input_threshold_pct_fall 50.000000 -#@ set rc_input_threshold_pct_rise 50.000000 -#@ set rc_output_threshold_pct_fall 50.000000 -#@ set rc_output_threshold_pct_rise 50.000000 -#@ set rc_rd_less_than_rnet_threshold 0.450000 -#@ set rc_slew_derate_from_library 1.000000 -#@ set rc_slew_lower_threshold_pct_fall 20.000000 -#@ set rc_slew_lower_threshold_pct_rise 20.000000 -#@ set rc_slew_upper_threshold_pct_fall 80.000000 -#@ set rc_slew_upper_threshold_pct_rise 80.000000 -#@ set timing_disable_cond_default_arcs "false" -#@ #timing_enable_multiple_clocks_per_reg is on by default -#@ #set timing_enable_multiple_clocks_per_reg "false" -#@ set timing_report_attributes {dont_touch dont_use map_only size_only ideal_net infeasible_paths} -#@ set timing_self_loops_no_skew "false" -#@ set when_analysis_permitted "true" -#@ set when_analysis_without_case_analysis "false" -#@ -#@ -#@ # -#@ # Variable Group Definitions: -#@ # -#@ # The group_variable() command groups variables for display -#@ # in the "File/Defaults" dialog and defines groups of variables -#@ # for the list() command. -#@ # -#@ -#@ set enable_instances_in_report_net "true" -#@ # Set report options env variables -#@ set view_report_interactive "true" -#@ set view_report_output2file "false" -#@ set view_report_append "true" -#@ -#@ if { $synopsys_program_name != "ptxr" } { -#@ -#@ group_variable report_variables "enable_instances_in_report_net" -#@ group_variable report_variables "view_report_interactive" -#@ group_variable report_variables "view_report_output2file" -#@ group_variable report_variables "view_report_append" -#@ -#@ # "links_to_layout" variables are used by multiple commands -#@ # auto_wire_load_selection is also in the "compile" variable group. -#@ group_variable links_to_layout "auto_wire_load_selection" -#@ -#@ # variables starting with "compile" are also in the compile variable group -#@ group_variable links_to_layout "compile_dont_touch_annotated_cell_during_inplace_opt" -#@ -#@ group_variable links_to_layout "compile_update_annotated_delays_during_inplace_opt" -#@ group_variable links_to_layout "compile_create_wire_load_table" -#@ -#@ group_variable links_to_layout "reoptimize_design_changed_list_file_name" -#@ group_variable links_to_layout "sdfout_allow_non_positive_constraints" -#@ -#@ } ;# $synopsys_program_name != "ptxr" -#@ -#@ # -#@ # to find the XErrorDB and XKeySymDB for X11 file -#@ set motif_files ${synopsys_root}/admin/setup -#@ # set filename for logging input file -#@ set filename_log_file "filenames.log" -#@ # whether to delete the filename log after the normal exits -#@ set exit_delete_filename_log_file "true" -#@ -#@ # executable to fire off RTLA/BCV -#@ set xterm_executable "xterm" -#@ -#@ if { $synopsys_program_name != "ptxr" } { -#@ -#@ # "system" variables are used by multiple commands -#@ group_variable system auto_link_disable -#@ group_variable system auto_link_options -#@ group_variable system command_log_file -#@ group_variable system company -#@ group_variable system compatibility_version -#@ -#@ if { [string compare $dc_shell_mode "default"] == 0 } { -#@ group_variable system "current_design" -#@ group_variable system "current_instance" -#@ group_variable system "dc_shell_status" -#@ } else { -#@ set current_design "" -#@ set current_instance "" -#@ group_variable system "current_design" -#@ group_variable system "current_instance" -#@ } -#@ -#@ group_variable system "designer" -#@ group_variable system "echo_include_commands" -#@ group_variable system "enable_page_mode" -#@ group_variable system "change_names_update_inst_tree" -#@ group_variable system "change_names_dont_change_bus_members" -#@ group_variable system "default_name_rules" -#@ group_variable system "verbose_messages" -#@ group_variable system "link_library" -#@ group_variable system "link_force_case" -#@ group_variable system "search_path" -#@ group_variable system "synthetic_library" -#@ group_variable system "target_library" -#@ group_variable system "uniquify_naming_style" -#@ group_variable system "suppress_errors" -#@ group_variable system "find_converts_name_lists" -#@ group_variable system "filename_log_file" -#@ group_variable system "exit_delete_filename_log_file" -#@ group_variable system "syntax_check_status" -#@ group_variable system "context_check_status" -#@ -#@ #/* "compile" variables are used by the compile command */ -#@ group_variable compile "compile_assume_fully_decoded_three_state_busses" -#@ group_variable compile "compile_no_new_cells_at_top_level" -#@ group_variable compile "compile_dont_touch_annotated_cell_during_inplace_opt" -#@ group_variable compile "reoptimize_design_changed_list_file_name" -#@ group_variable compile "compile_create_wire_load_table" -#@ group_variable compile "compile_update_annotated_delays_during_inplace_opt" -#@ group_variable compile "compile_instance_name_prefix" -#@ group_variable compile "compile_instance_name_suffix" -#@ group_variable compile "compile_negative_logic_methodology" -#@ group_variable compile "compile_disable_hierarchical_inverter_opt" -#@ -#@ group_variable compile "port_complement_naming_style" -#@ group_variable compile "auto_wire_load_selection" -#@ group_variable compile "rtl_load_resistance_factor" -#@ group_variable compile "compile_implementation_selection" -#@ group_variable compile "compile_use_low_timing_effort" -#@ group_variable compile "compile_fix_cell_degradation" -#@ group_variable compile "compile_preserve_subdesign_interfaces" -#@ group_variable compile "compile_enable_constant_propagation_with_no_boundary_opt" -#@ group_variable compile "compile_delete_unloaded_sequential_cells" -#@ group_variable compile "enable_recovery_removal_arcs" -#@ group_variable compile "compile_checkpoint_phases" -#@ group_variable compile "compile_cpu_limit" -#@ group_variable compile "compile_top_all_paths" -#@ group_variable compile "compile_top_all_paths" -#@ group_variable compile "compile_top_acs_partition" -#@ group_variable compile "default_port_connection_class" -#@ group_variable compile "compile_retime_license_behavior" -#@ group_variable compile "dont_touch_nets_with_size_only_cells" -#@ group_variable compile "compile_seqmap_no_scan_cell" -#@ -#@ if { $synopsys_program_name == "dc_shell" && [shell_is_in_topographical_mode] } { -#@ group_variable compile "dct_prioritize_area_correlation" -#@ group_variable compile "compile_error_on_missing_physical_cells" -#@ } -#@ -#@ # "multibit" variables are used by the the multibit mapping functionality -#@ -#@ group_variable multibit "bus_multiple_separator_style" -#@ -#@ # "ilm" variables are used by Interface Logic Model functionality -#@ -#@ group_variable ilm "ilm_ignore_percentage" -#@ -#@ # "estimate" variables are used by the estimate command -#@ # The estimate command also recognizes the "compile" variables. -#@ group_variable estimate "estimate_resource_preference" -#@ -#@ # "synthetic_library" variables -#@ group_variable synlib "cache_dir_chmod_octal" -#@ group_variable synlib "cache_file_chmod_octal" -#@ group_variable synlib "cache_read" -#@ group_variable synlib "cache_read_info" -#@ group_variable synlib "cache_write" -#@ group_variable synlib "cache_write_info" -#@ group_variable synlib "synlib_dont_get_license" -#@ group_variable synlib "synlib_wait_for_design_license" -#@ group_variable synlib "synthetic_library" -#@ -#@ # "insert_dft" variables are used by the insert_dft and preview_dft commands -#@ #group_variable insert_dft "test_default_client_order" -#@ group_variable insert_dft "insert_dft_clean_up" -#@ group_variable insert_dft "insert_test_design_naming_style" -#@ group_variable insert_dft "test_clock_port_naming_style" -#@ group_variable insert_dft "test_default_min_fault_coverage" -#@ group_variable insert_dft "test_scan_clock_a_port_naming_style" -#@ group_variable insert_dft "test_scan_clock_b_port_naming_style" -#@ group_variable insert_dft "test_scan_clock_port_naming_style" -#@ group_variable insert_dft "test_scan_enable_inverted_port_naming_style" -#@ group_variable insert_dft "test_scan_enable_port_naming_style" -#@ group_variable insert_dft "test_scan_in_port_naming_style" -#@ group_variable insert_dft "test_scan_out_port_naming_style" -#@ group_variable insert_dft "test_non_scan_clock_port_naming_style" -#@ group_variable insert_dft "test_dedicated_subdesign_scan_outs" -#@ group_variable insert_dft "test_disable_find_best_scan_out" -#@ group_variable insert_dft "test_dont_fix_constraint_violations" -#@ group_variable insert_dft "test_isolate_hier_scan_out" -#@ group_variable insert_dft "test_mode_port_naming_style" -#@ group_variable insert_dft "test_mode_port_inverted_naming_style" -#@ group_variable insert_dft "compile_dont_use_dedicated_scanout" -#@ group_variable insert_dft "test_mux_constant_si" -#@ -#@ # "preview_scan" variables are used by the preview_scan command -#@ group_variable preview_scan "test_preview_scan_shows_cell_types" -#@ group_variable preview_scan "test_scan_link_so_lockup_key" -#@ group_variable preview_scan "test_scan_link_wire_key" -#@ group_variable preview_scan "test_scan_segment_key" -#@ group_variable preview_scan "test_scan_true_key" -#@ -#@ # "bsd" variables are used by the check_bsd and write_bsdl commands -#@ group_variable bsd "test_user_test_data_register_naming_style" -#@ group_variable bsd "test_user_defined_instruction_naming_style" -#@ group_variable bsd "test_bsdl_default_suffix_name" -#@ group_variable bsd "test_bsdl_max_line_length" -#@ group_variable bsd "test_cc_ir_masked_bits" -#@ group_variable bsd "test_cc_ir_value_of_masked_bits" -#@ -#@ group_variable bsd "test_bsd_allow_tolerable_violations" -#@ group_variable bsd "test_bsd_optimize_control_cell" -#@ group_variable bsd "test_bsd_control_cell_drive_limit" -#@ group_variable bsd "test_bsd_manufacturer_id" -#@ group_variable bsd "test_bsd_part_number" -#@ group_variable bsd "test_bsd_version_number" -#@ group_variable bsd "bsd_max_in_switching_limit" -#@ group_variable bsd "bsd_max_out_switching_limit" -#@ -#@ # testmanager variables -#@ group_variable testmanager "multi_pass_test_generation" -#@ -#@ # "testsim" variables -#@ # group_variable testsim "testsim_print_stats_file" -#@ -#@ # "test" variables -#@ group_variable test "test_default_bidir_delay" -#@ group_variable test "test_default_delay" -#@ group_variable test "test_default_period" -#@ group_variable test "test_default_strobe" -#@ group_variable test "test_default_strobe_width" -#@ group_variable test "test_capture_clock_skew" -#@ group_variable test "test_allow_clock_reconvergence" -#@ group_variable test "test_check_port_changes_in_capture" -#@ group_variable test "test_stil_max_line_length" -#@ group_variable test "test_infer_slave_clock_pulse_after_capture" -#@ group_variable test "test_rtldrc_latch_check_style" -#@ group_variable test "test_enable_capture_checks" -#@ -#@ # "write_test" variables are used by the write_test command -#@ group_variable write_test "write_test_formats" -#@ group_variable write_test "write_test_include_scan_cell_info" -#@ group_variable write_test "write_test_input_dont_care_value" -#@ group_variable write_test "write_test_max_cycles" -#@ group_variable write_test "write_test_max_scan_patterns" -#@ group_variable write_test "write_test_pattern_set_naming_style" -#@ group_variable write_test "write_test_scan_check_file_naming_style" -#@ group_variable write_test "write_test_vector_file_naming_style" -#@ group_variable write_test "write_test_round_timing_values" -#@ -#@ group_variable view "test_design_analyzer_uses_insert_scan" -#@ -#@ # "io" variables are used by the read, read_lib, db2sge and write commands -#@ group_variable io "bus_inference_descending_sort" -#@ group_variable io "bus_inference_style" -#@ #group_variable io "db2sge_output_directory" -#@ #group_variable io "db2sge_scale" -#@ #group_variable io "db2sge_overwrite" -#@ #group_variable io "db2sge_display_symbol_names" -#@ #group_variable io "db2sge_display_pin_names" -#@ #group_variable io "db2sge_display_instance_names" -#@ #group_variable io "db2sge_use_bustaps" -#@ #group_variable io "db2sge_use_compound_names" -#@ #group_variable io "db2sge_bit_type" -#@ #group_variable io "db2sge_bit_vector_type" -#@ #group_variable io "db2sge_one_name" -#@ #group_variable io "db2sge_zero_name" -#@ #group_variable io "db2sge_unknown_name" -#@ #group_variable io "db2sge_target_xp" -#@ #group_variable io "db2sge_tcf_package_file" -#@ #group_variable io "db2sge_use_lib_section" -#@ #group_variable io "db2sge_script" -#@ #group_variable io "db2sge_command" -#@ -#@ # group_variable io "equationout_and_sign" -#@ # group_variable io "equationout_or_sign" -#@ # group_variable io "equationout_postfix_negation" -#@ -#@ # group_variable io "lsiin_net_name_prefix" -#@ # group_variable io "lsiout_inverter_cell" -#@ # group_variable io "lsiout_upcase" -#@ -#@ #group_variable io "mentor_bidirect_value" -#@ #group_variable io "mentor_do_path" -#@ #group_variable io "mentor_input_output_property_name" -#@ #group_variable io "mentor_input_value" -#@ #group_variable io "mentor_logic_one_value" -#@ #group_variable io "mentor_logic_zero_one_property_name" -#@ #group_variable io "mentor_logic_zero_value" -#@ #group_variable io "mentor_output_value" -#@ #group_variable io "mentor_primitive_property_name" -#@ #group_variable io "mentor_primitive_property_value" -#@ #group_variable io "mentor_reference_property_name" -#@ #group_variable io "mentor_search_path" -#@ #group_variable io "mentor_write_symbols" -#@ # group_variable io "pla_read_create_flip_flop" -#@ # group_variable io "tdlout_upcase" -#@ group_variable io "write_name_nets_same_as_ports" -#@ -#@ # # [wjchen] 2006/08/14: The following 4 variables are obsoleted for DC simpilification. -#@ -#@ # group_variable io "xnfout_constraints_per_endpoint" -#@ # group_variable io "xnfout_default_time_constraints" -#@ # group_variable io "xnfout_clock_attribute_style" -#@ # group_variable io "xnfout_library_version" -#@ -#@ # # [wjchen] 2006/08/11: The following 8 variables are obsoleted for DC simpilification. -#@ # group_variable io "xnfin_family" -#@ # group_variable io "xnfin_ignore_pins" -#@ # group_variable io "xnfin_dff_reset_pin_name" -#@ # group_variable io "xnfin_dff_set_pin_name" -#@ # group_variable io "xnfin_dff_clock_enable_pin_name" -#@ # group_variable io "xnfin_dff_data_pin_name" -#@ # group_variable io "xnfin_dff_clock_pin_name" ; -#@ # group_variable io "xnfin_dff_q_pin_name"; -#@ -#@ group_variable io "sdfin_min_rise_net_delay" ; -#@ group_variable io "sdfin_min_fall_net_delay" ; -#@ group_variable io "sdfin_min_rise_cell_delay" ; -#@ group_variable io "sdfin_min_fall_cell_delay" ; -#@ group_variable io "sdfin_rise_net_delay_type" ; -#@ group_variable io "sdfin_fall_net_delay_type" ; -#@ group_variable io "sdfin_rise_cell_delay_type" ; -#@ group_variable io "sdfin_fall_cell_delay_type" ; -#@ group_variable io "sdfin_top_instance_name" ; -#@ group_variable io "sdfout_time_scale" ; -#@ group_variable io "sdfout_write_to_output" ; -#@ group_variable io "sdfout_top_instance_name" ; -#@ group_variable io "sdfout_min_rise_net_delay" ; -#@ group_variable io "sdfout_min_fall_net_delay" ; -#@ group_variable io "sdfout_min_rise_cell_delay" ; -#@ group_variable io "sdfout_min_fall_cell_delay" ; -#@ group_variable io "read_db_lib_warnings" ; -#@ group_variable io "read_translate_msff" ; -#@ group_variable io "libgen_max_differences" ; -#@ -#@ # #[wjchen] 2006/08/22: The following variables are hidden for XG mode for DC simpilification. -#@ # group_variable io "read_name_mapping_nowarn_libraries" ; -#@ # group_variable io "write_name_mapping_nowarn_libraries" ; -#@ -#@ -#@ # "edif" variables are used by the EDIF format read, read_lib, write, -#@ # and write_lib commands -#@ # group_variable edif "bus_dimension_separator_style" ; -#@ # group_variable edif "bus_extraction_style" ; -#@ group_variable edif "bus_inference_descending_sort" ; -#@ group_variable edif "bus_inference_style" ; -#@ group_variable edif "bus_naming_style" ; -#@ group_variable edif "bus_range_separator_style" ; -#@ # group_variable edif "edifin_autoconnect_offpageconnectors" ; -#@ # group_variable edif "edifin_autoconnect_ports" ; -#@ # group_variable edif "edifin_delete_empty_cells" ; -#@ # group_variable edif "edifin_delete_ripper_cells" ; -#@ # group_variable edif "edifin_ground_net_name" ; -#@ # group_variable edif "edifin_ground_net_property_name" ; -#@ # group_variable edif "edifin_ground_net_property_value" ; -#@ # group_variable edif "edifin_ground_port_name" ; -#@ # group_variable edif "edifin_instance_property_name" ; -#@ # group_variable edif "edifin_portinstance_disabled_property_name" ; -#@ # group_variable edif "edifin_portinstance_disabled_property_value" ; -#@ # group_variable edif "edifin_portinstance_property_name" ; -#@ # group_variable edif "edifin_power_net_name" ; -#@ # group_variable edif "edifin_power_net_property_name" ; -#@ # group_variable edif "edifin_power_net_property_value" ; -#@ # group_variable edif "edifin_power_port_name" ; -#@ # group_variable edif "edifin_use_identifier_in_rename" ; -#@ # group_variable edif "edifin_view_identifier_property_name" ; -#@ # group_variable edif "edifin_dc_script_flag" ; -#@ # group_variable edif "edifin_lib_logic_1_symbol" ; -#@ # group_variable edif "edifin_lib_logic_0_symbol" ; -#@ # group_variable edif "edifin_lib_in_port_symbol" ; -#@ # group_variable edif "edifin_lib_out_port_symbol" ; -#@ # group_variable edif "edifin_lib_inout_port_symbol" ; -#@ # group_variable edif "edifin_lib_in_osc_symbol" ; -#@ # group_variable edif "edifin_lib_out_osc_symbol" ; -#@ # group_variable edif "edifin_lib_inout_osc_symbol" ; -#@ # group_variable edif "edifin_lib_mentor_netcon_symbol" ; -#@ # group_variable edif "edifin_lib_ripper_bits_property" ; -#@ # group_variable edif "edifin_lib_ripper_bus_end" ; -#@ # group_variable edif "edifin_lib_ripper_cell_name" ; -#@ # group_variable edif "edifin_lib_ripper_view_name" ; -#@ # group_variable edif "edifin_lib_route_grid" ; -#@ # group_variable edif "edifin_lib_templates" ; -#@ # group_variable edif "edifout_dc_script_flag" ; -#@ # group_variable edif "edifout_design_name" ; -#@ # group_variable edif "edifout_designs_library_name" ; -#@ # group_variable edif "edifout_display_instance_names" ; -#@ # group_variable edif "edifout_display_net_names" ; -#@ # group_variable edif "edifout_external" ; -#@ # group_variable edif "edifout_external_graphic_view_name" ; -#@ # group_variable edif "edifout_external_netlist_view_name" ; -#@ # group_variable edif "edifout_external_schematic_view_name" ; -#@ # group_variable edif "edifout_ground_name" ; -#@ # group_variable edif "edifout_ground_net_name" ; -#@ # group_variable edif "edifout_ground_net_property_name" ; -#@ # group_variable edif "edifout_ground_net_property_value" ; -#@ # group_variable edif "edifout_ground_pin_name" ; -#@ # group_variable edif "edifout_ground_port_name" ; -#@ # group_variable edif "edifout_instance_property_name" ; -#@ # group_variable edif "edifout_instantiate_ports" ; -#@ # group_variable edif "edifout_library_graphic_view_name" ; -#@ # group_variable edif "edifout_library_netlist_view_name" ; -#@ # group_variable edif "edifout_library_schematic_view_name" ; -#@ # group_variable edif "edifout_merge_libraries" ; -#@ # group_variable edif "edifout_multidimension_arrays" ; -#@ # group_variable edif "edifout_name_oscs_different_from_ports" ; -#@ # group_variable edif "edifout_name_rippers_same_as_wires" ; -#@ # group_variable edif "edifout_netlist_only" ; -#@ # group_variable edif "edifout_no_array" ; -#@ # group_variable edif "edifout_numerical_array_members" ; -#@ # group_variable edif "edifout_pin_direction_property_name" ; -#@ # group_variable edif "edifout_pin_direction_in_value" ; -#@ # group_variable edif "edifout_pin_direction_inout_value" ; -#@ # group_variable edif "edifout_pin_direction_out_value" ; -#@ # group_variable edif "edifout_pin_name_property_name" ; -#@ # group_variable edif "edifout_portinstance_disabled_property_name" ; -#@ # group_variable edif "edifout_portinstance_disabled_property_value" ; -#@ # group_variable edif "edifout_portinstance_property_name" -#@ # group_variable edif "edifout_power_and_ground_representation" -#@ # group_variable edif "edifout_power_name" -#@ # group_variable edif "edifout_power_net_name" -#@ # group_variable edif "edifout_power_net_property_name" -#@ # group_variable edif "edifout_power_net_property_value" -#@ # group_variable edif "edifout_power_pin_name" -#@ # group_variable edif "edifout_power_port_name" -#@ # group_variable edif "edifout_skip_port_implementations" -#@ # group_variable edif "edifout_target_system" -#@ # group_variable edif "edifout_top_level_symbol" -#@ # group_variable edif "edifout_translate_origin" -#@ # group_variable edif "edifout_unused_property_value" -#@ # group_variable edif "edifout_write_attributes" -#@ # group_variable edif "edifout_write_constraints" -#@ # group_variable edif "edifout_write_properties_list" -#@ # group_variable edif "write_name_nets_same_as_ports" -#@ -#@ # "hdl" variables are variables pertaining to hdl reading and optimizing -#@ group_variable hdl "bus_dimension_separator_style" -#@ group_variable hdl "bus_minus_style" -#@ group_variable hdl "bus_naming_style" -#@ group_variable hdl "hdlin_ignore_textio_constructs" -#@ group_variable hdl "hdlin_latch_always_async_set_reset" -#@ group_variable hdl "hdlin_ff_always_sync_set_reset" -#@ group_variable hdl "hdlin_ff_always_async_set_reset" -#@ group_variable hdl "hdlin_check_input_netlist" -#@ group_variable hdl "hdlin_check_no_latch" -#@ group_variable hdl "hdlin_reporting_level" -#@ group_variable hdl "hdlin_infer_mux" -#@ group_variable hdl "hdlin_mux_oversize_ratio" -#@ group_variable hdl "hdlin_mux_size_limit" -#@ group_variable hdl "hdlin_infer_multibit" -#@ group_variable hdl "hdl_preferred_license" -#@ group_variable hdl "hdl_keep_licenses" -#@ group_variable hdl "hlo_resource_allocation" -#@ group_variable hdl "template_naming_style" -#@ group_variable hdl "template_parameter_style" -#@ group_variable hdl "template_separator_style" -#@ group_variable hdl "verilogout_equation" -#@ group_variable hdl "verilogout_ignore_case" -#@ group_variable hdl "verilogout_no_tri" -#@ group_variable hdl "verilogout_inout_is_in" -#@ group_variable hdl "verilogout_single_bit" -#@ group_variable hdl "verilogout_higher_designs_first" -#@ # group_variable hdl "verilogout_levelize" -#@ group_variable hdl "verilogout_include_files" -#@ group_variable hdl "verilogout_unconnected_prefix" -#@ group_variable hdl "verilogout_show_unconnected_pins" -#@ group_variable hdl "verilogout_no_negative_index" -#@ group_variable hdl "hdlin_enable_rtldrc_info" -#@ group_variable hdl "hdlin_sv_blackbox_modules" -#@ group_variable hdl "hdlin_infer_function_local_latches" -#@ group_variable hdl "hdlin_module_arch_name_splitting" -#@ group_variable hdl "hdlin_mux_size_min" -#@ group_variable hdl "hdlin_prohibit_nontri_multiple_drivers" -#@ group_variable hdl "hdlin_subprogram_default_values" -#@ group_variable hdl "hdlin_upcase_names" -#@ group_variable hdl "hdlin_vhdl_std" -#@ group_variable hdl "hdlin_vhdl93_concat" -#@ group_variable hdl "hdlin_vhdl_syntax_extensions" -#@ group_variable hdl "hdlin_vrlg_std" -#@ group_variable hdl "hdlin_while_loop_iterations" -#@ group_variable hdl "hdlin_auto_save_templates" -#@ group_variable hdl "hdlin_elab_errors_deep" -#@ group_variable hdl "hdlin_enable_assertions" -#@ group_variable hdl "hdlin_enable_configurations" -#@ group_variable hdl "hdlin_field_naming_style" -#@ group_variable hdl "hdlin_generate_naming_style" -#@ group_variable hdl "hdlin_generate_separator_style" -#@ group_variable hdl "hdlin_enable_relative_placement" -#@ group_variable hdl "hdlin_mux_rp_limit" -#@ group_variable hdl "hdlin_keep_signal_name" -#@ group_variable hdl "hdlin_module_name_limit" -#@ group_variable hdl "hdlin_mux_size_only" -#@ group_variable hdl "hdlin_preserve_sequential" -#@ group_variable hdl "hdlin_presto_cell_name_prefix" -#@ group_variable hdl "hdlin_presto_net_name_prefix" -#@ group_variable hdl "hdlin_strict_verilog_reader" -#@ group_variable hdl "hdlin_shorten_long_module_name" -#@ group_variable hdl "hdlin_sv_packages" -#@ group_variable hdl "hdlin_sv_tokens" -#@ group_variable hdl "hdlin_enable_elaborate_ref_linking" -#@ group_variable hdl "hdlin_enable_hier_naming" -#@ group_variable hdl "hdlin_autoread_verilog_extensions" -#@ group_variable hdl "hdlin_autoread_sverilog_extensions" -#@ group_variable hdl "hdlin_autoread_vhdl_extensions" -#@ group_variable hdl "hdlin_autoread_exclude_extensions" -#@ group_variable hdl "hdlin_enable_upf_compatible_naming" -#@ group_variable hdl "hdlin_report_sequential_pruning" -#@ group_variable hdl "hdlin_analyze_verbose_mode" -#@ -#@ # "vhdlio" variables are variables pertaining to VHDL generation -#@ group_variable vhdlio "vhdllib_timing_mesg" -#@ group_variable vhdlio "vhdllib_timing_xgen" -#@ group_variable vhdlio "vhdllib_timing_checks" -#@ group_variable vhdlio "vhdllib_negative_constraint" -#@ group_variable vhdlio "vhdllib_pulse_handle" -#@ group_variable vhdlio "vhdllib_glitch_handle" -#@ group_variable vhdlio "vhdllib_architecture" -#@ group_variable vhdlio "vhdllib_tb_compare" -#@ group_variable vhdlio "vhdllib_tb_x_eq_dontcare" -#@ group_variable vhdlio "vhdllib_logic_system" -#@ group_variable vhdlio "vhdllib_logical_name" -#@ -#@ # group_variable vhdlio "vhdlout_architecture_name" -#@ group_variable vhdlio "vhdlout_bit_type" -#@ # group_variable vhdlio "vhdlout_bit_type_resolved" -#@ group_variable vhdlio "vhdlout_bit_vector_type" -#@ # group_variable vhdlio "vhdlout_conversion_functions" -#@ # group_variable vhdlio "vhdlout_dont_write_types" -#@ group_variable vhdlio "vhdlout_equations" -#@ group_variable vhdlio "vhdlout_one_name" -#@ group_variable vhdlio "vhdlout_package_naming_style" -#@ group_variable vhdlio "vhdlout_preserve_hierarchical_types" -#@ group_variable vhdlio "vhdlout_separate_scan_in" -#@ group_variable vhdlio "vhdlout_single_bit" -#@ group_variable vhdlio "vhdlout_target_simulator" -#@ group_variable vhdlio "vhdlout_top_configuration_arch_name" -#@ group_variable vhdlio "vhdlout_top_configuration_entity_name" -#@ group_variable vhdlio "vhdlout_top_configuration_name" -#@ group_variable vhdlio "vhdlout_three_state_name" -#@ group_variable vhdlio "vhdlout_three_state_res_func" -#@ # group_variable vhdlio "vhdlout_time_scale" -#@ group_variable vhdlio "vhdlout_unknown_name" -#@ group_variable vhdlio "vhdlout_use_packages" -#@ group_variable vhdlio "vhdlout_wired_and_res_func" -#@ group_variable vhdlio "vhdlout_wired_or_res_func" -#@ group_variable vhdlio "vhdlout_write_architecture" -#@ group_variable vhdlio "vhdlout_write_entity" -#@ group_variable vhdlio "vhdlout_write_top_configuration" -#@ # group_variable vhdlio "vhdlout_synthesis_off" -#@ group_variable vhdlio "vhdlout_write_components" -#@ group_variable vhdlio "vhdlout_zero_name" -#@ # group_variable vhdlio "vhdlout_levelize" -#@ group_variable vhdlio "vhdlout_dont_create_dummy_nets" -#@ group_variable vhdlio "vhdlout_follow_vector_direction" -#@ -#@ # "suffix" variables are used to find the suffixes of different file types -#@ group_variable suffix "view_execute_script_suffix" -#@ group_variable suffix "view_read_file_suffix" -#@ group_variable suffix "view_analyze_file_suffix" -#@ group_variable suffix "view_write_file_suffix" -#@ -#@ # Meenakshi: Added new group scc (for SystemC compiler) -#@ group_variable scc {systemcout_levelize} -#@ group_variable scc {systemcout_debug_mode} -#@ -#@ # "power" variables are for power-analysis. -#@ group_variable power {power_keep_license_after_power_commands} -#@ group_variable power {power_preserve_rtl_hier_names} -#@ group_variable power {power_do_not_size_icg_cells} -#@ group_variable power {power_hdlc_do_not_split_cg_cells} -#@ group_variable power {power_rtl_saif_file} -#@ group_variable power {power_sdpd_saif_file} -#@ group_variable power {power_cg_flatten} -#@ group_variable power {power_opto_extra_high_dynamic_power_effort} -#@ group_variable power {power_default_static_probability} -#@ group_variable power {power_default_toggle_rate} -#@ group_variable power {power_default_toggle_rate_type} -#@ group_variable power {power_model_preference} -#@ group_variable power {power_sa_propagation_effort} -#@ group_variable power {power_sa_propagation_verbose} -#@ group_variable power {power_fix_sdpd_annotation} -#@ group_variable power {power_fix_sdpd_annotation_verbose} -#@ group_variable power {power_sdpd_message_tolerance} -#@ group_variable power {power_rclock_use_asynch_inputs} -#@ group_variable power {power_rclock_inputs_use_clocks_fanout} -#@ group_variable power {power_rclock_unrelated_use_fastest} -#@ group_variable power {power_lib2saif_rise_fall_pd} -#@ group_variable power {power_min_internal_power_threshold} -#@ group_variable power {power_cg_module_naming_style} -#@ group_variable power {power_cg_cell_naming_style} -#@ group_variable power {power_cg_gated_clock_net_naming_style} -#@ group_variable power {do_operand_isolation} -#@ -#@ # dpcm variables are used by DPCM lib and controllong DC when using DPCM -#@ -#@ if { [info exists dpcm_debuglevel] } { -#@ group_variable dpcm "dpcm_debuglevel" -#@ group_variable dpcm "dpcm_rulespath" -#@ group_variable dpcm "dpcm_rulepath" -#@ group_variable dpcm "dpcm_tablepath" -#@ group_variable dpcm "dpcm_libraries" -#@ group_variable dpcm "dpcm_version" -#@ group_variable dpcm "dpcm_level" -#@ group_variable dpcm "dpcm_temperaturescope" -#@ group_variable dpcm "dpcm_voltagescope" -#@ group_variable dpcm "dpcm_functionscope" -#@ group_variable dpcm "dpcm_wireloadscope" -#@ group_variable dpcm "dpcm_slewlimit" -#@ group_variable dpcm "dpcm_arc_sense_mapping" -#@ -#@ } -#@ -#@ set dpcm_slewlimit "TRUE" -#@ -#@ # executable to fire off RTLA/BCV -#@ group_variable hdl {xterm_executable} -#@ -#@ # Variable group for Chip Compiler -#@ if {[info exists acs_work_dir]} { -#@ group_variable acs acs_area_report_suffix -#@ group_variable acs acs_autopart_max_area -#@ group_variable acs acs_autopart_max_percent -#@ group_variable acs acs_budgeted_cstr_suffix -#@ group_variable acs acs_compile_script_suffix -#@ group_variable acs acs_constraint_file_suffix -#@ group_variable acs acs_cstr_report_suffix -#@ group_variable acs acs_db_suffix -#@ group_variable acs acs_dc_exec -#@ group_variable acs acs_default_pass_name -#@ group_variable acs acs_exclude_extensions -#@ group_variable acs acs_exclude_list -#@ group_variable acs acs_global_user_compile_strategy_script -#@ group_variable acs acs_hdl_verilog_define_list -#@ group_variable acs acs_hdl_source -#@ group_variable acs acs_lic_wait -#@ group_variable acs acs_log_file_suffix -#@ group_variable acs acs_make_args -#@ group_variable acs acs_make_exec -#@ group_variable acs acs_makefile_name -#@ group_variable acs acs_num_parallel_jobs -#@ group_variable acs acs_override_report_suffix -#@ group_variable acs acs_override_script_suffix -#@ group_variable acs acs_qor_report_suffix -#@ group_variable acs acs_timing_report_suffix -#@ group_variable acs acs_use_autopartition -#@ group_variable acs acs_use_default_delays -#@ group_variable acs acs_user_budgeting_script -#@ group_variable acs acs_user_compile_strategy_script_suffix -#@ group_variable acs acs_verilog_extensions -#@ group_variable acs acs_vhdl_extensions -#@ group_variable acs acs_work_dir -#@ group_variable acs check_error_list -#@ group_variable acs ilm_preserve_core_constraints -#@ -#@ } -#@ -#@ # -#@ # DesignTime Variable Group timing -#@ # -#@ -#@ group_variable timing case_analysis_log_file -#@ group_variable timing case_analysis_sequential_propagate -#@ group_variable timing case_analysis_with_logic_constants -#@ group_variable timing create_clock_no_input_delay -#@ group_variable timing disable_auto_time_borrow -#@ group_variable timing disable_case_analysis -#@ group_variable timing disable_conditional_mode_analysis -#@ group_variable timing disable_library_transition_degradation -#@ group_variable timing dont_bind_unused_pins_to_logic_constant -#@ group_variable timing enable_slew_degradation -#@ group_variable timing high_fanout_net_pin_capacitance -#@ group_variable timing high_fanout_net_threshold -#@ group_variable timing lib_thresholds_per_lib -#@ group_variable timing rc_adjust_rd_when_less_than_rnet -#@ group_variable timing rc_ceff_delay_min_diff_ps -#@ group_variable timing rc_degrade_min_slew_when_rd_less_than_rnet -#@ group_variable timing rc_driver_model_max_error_pct -#@ group_variable timing rc_filter_rd_less_than_rnet -#@ group_variable timing rc_input_threshold_pct_fall -#@ group_variable timing rc_input_threshold_pct_rise -#@ group_variable timing rc_output_threshold_pct_fall -#@ group_variable timing rc_output_threshold_pct_rise -#@ group_variable timing rc_rd_less_than_rnet_threshold -#@ group_variable timing rc_slew_derate_from_library -#@ group_variable timing rc_slew_lower_threshold_pct_fall -#@ group_variable timing rc_slew_lower_threshold_pct_rise -#@ group_variable timing rc_slew_upper_threshold_pct_fall -#@ group_variable timing rc_slew_upper_threshold_pct_rise -#@ group_variable timing timing_disable_cond_default_arcs -#@ # group_variable timing timing_enable_multiple_clocks_per_reg -#@ group_variable timing timing_report_attributes -#@ group_variable timing timing_self_loops_no_skew -#@ group_variable timing when_analysis_permitted -#@ group_variable timing when_analysis_without_case_analysis -#@ -#@ } ;# $synopsys_program_name != "ptxr" -#@ -#@ if { $synopsys_program_name == "icc_shell"} { -#@ # -#@ # IC Compile Variable Group: -#@ # -#@ # These variables affect the designs created by the route_opt command. -#@ # -#@ group_variable routeopt routeopt_checkpoint -#@ group_variable routeopt routeopt_disable_cpulimit -#@ } -#@ -#@ if { $synopsys_program_name == "icc_shell"} { -#@ # -#@ # IC Compiler Variable Group: MCMM -#@ # -#@ # These variables affect Multi-Corner/Multi-Mode. Currently, MCMM is -#@ # only supported in ICC--hence the "icc_shell" qualification, above -#@ # -#@ group_variable MCMM mcmm_enable_high_capacity_flow -#@ } -#@ -#@ # Aliases for backwards compatibility or other reasons -#@ group_variable compile {compile_log_format} -#@ alias view_cursor_number x11_set_cursor_number -#@ alias set_internal_load set_load -#@ alias set_internal_arrival set_arrival -#@ alias set_connect_delay "set_annotated_delay -net" -#@ alias create_test_vectors create_test_patterns -#@ alias compile_test insert_test -#@ alias check_clocks check_timing -#@ alias lint check_design -#@ # gen removed; alias gen create_schematic -#@ alias free remove_design -#@ alias group_bus create_bus -#@ alias ungroup_bus remove_bus -#@ alias groupvar group_variable -#@ alias report_constraints report_constraint -#@ alias report_attributes report_attribute -#@ alias fsm_reduce reduce_fsm -#@ alias fsm_minimize minimize_fsm -#@ alias disable_timing set_disable_timing -#@ alias dont_touch set_dont_touch -#@ alias dont_touch_network set_dont_touch_network -#@ alias dont_use set_dont_use -#@ alias fix_hold set_fix_hold -#@ alias prefer set_prefer -#@ alias remove_package "echo remove_package command is obsolete: packages are stored on disk not in-memory:" -#@ alias analyze_scan preview_scan -#@ alias get_clock get_clocks -#@ alias dc_shell_is_in_incr_mode shell_is_in_xg_mode -#@ alias set_vh_module_options set_dps_module_options -#@ alias set_vh_physopt_options set_dps_options -#@ alias update_vh_design update_dps_design -#@ alias vh_start dps_start -#@ alias vh_end dps_end -#@ alias all_vh_modules all_dps_modules -#@ alias all_designs_of_vh all_designs_of_dps -#@ alias vh_use_auto_partitioning dps_auto_partitioning -#@ alias vh_write_changes dps_write_changes -#@ alias vh_read_changes dps_read_changes -#@ alias vh_write_module_clock dps_write_module_clock -#@ alias get_lib get_libs -#@ -#@ # Enable unsupported psyn commands -#@ if { $synopsys_program_name == "psyn_shell" || $synopsys_program_name == "icc_shell"} { -#@ proc enable_unsupported_commands { { arg "default" } } { -#@ global cgpi_use_new_wire_factors -#@ global cgpi_use_relative_wire_factors -#@ global cgpi_use_new_path_factors -#@ global pwlm_use_new_wire_factors -#@ global pwlm_use_relative_wire_factors -#@ global pwlm_use_new_path_factors -#@ global psyn_unsupported_commands_dir -#@ global synopsys_root -#@ if {![info exists psyn_unsupported_commands_dir]} { -#@ set psyn_unsupported_commands_dir $synopsys_root/auxx/syn/psyn/unsupported_commands -#@ } -#@ set psyn_unsupported_commands_option1 $arg -#@ if {[file readable $psyn_unsupported_commands_dir/setup.tcl]} { -#@ source $psyn_unsupported_commands_dir/setup.tcl -#@ } else { -#@ source -encrypted $psyn_unsupported_commands_dir/setup.tcl.e -#@ } -#@ } -#@ } -#@ # For Intel -#@ if { $synopsys_program_name == "icc_shell"} { -#@ set psyn_unsupported_commands_dir $synopsys_root/auxx/syn/psyn/unsupported_commands -#@ source -encrypted $psyn_unsupported_commands_dir/max_dist.tcl.e -#@ } -#@ -#@ -#@ if { $synopsys_program_name == "icc_shell"} { -#@ # to enable CLE readline-ish terminal by default for ICC -#@ set sh_enable_line_editing true -#@ -#@ # Astro forms create an enormous number of new variables which are -#@ # very annoying for users to see, so the default of this variable -#@ # for ICC is false -#@ set sh_new_variable_message false -#@ } -#@ -#@ if { $synopsys_program_name == "icc_shell" || (($synopsys_program_name == "dc_shell") && ([shell_is_in_topographical_mode])) } { -#@ source $synopsys_root/auxx/syn/psyn/verify_ilm.tcl -#@ } -#@ -#@ # Enable vh psyn commands -#@ if { $synopsys_program_name == "psyn_shell" } { -#@ proc enable_vh_flow { } { -#@ global VH_SCRIPT_FILE -#@ global synopsys_root -#@ global suppress_errors -#@ set suppress_errors "$suppress_errors CMD-041 UID-95 SEL-003 SEL-005" -#@ if {![info exists VH_SCRIPT_FILE]} { -#@ set VH_SCRIPT_FILE $synopsys_root/auxx/syn/psyn/vh_pc.tcl.e -#@ } -#@ if {[file readable $VH_SCRIPT_FILE]} { -#@ if {[string match *.tcl $VH_SCRIPT_FILE]} { -#@ source $VH_SCRIPT_FILE -#@ } else { -#@ source -encrypted $VH_SCRIPT_FILE -#@ } -#@ } else { -#@ puts "Error: VH script file $VH_SCRIPT_FILE not found." -#@ } -#@ } -#@ } -#@ -#@ -#@ #Turn on enable_netl_view to true by default. -#@ set enable_netl_view "TRUE" -#@ -#@ -#@ #Turn on physopt_bypass_multiple_plib_check by default -#@ if { $synopsys_program_name == "psyn_shell" } { -#@ set physopt_bypass_multiple_plib_check TRUE -#@ } -#@ -#@ # The ls command is gone, now it is just an alias for dc_shell eqn mode -#@ -#@ if { [string compare $dc_shell_mode "default"] == 0 } { -#@ if { ( $sh_arch == {mips}) && ( ( $synopsys_program_name == {design_analyzer}) || ( $isatty == 0)) } { -#@ alias ls "sh ls -a " -#@ } else { -#@ if { ( $sh_arch == {mips}) || ( $sh_arch == {necmips}) } { -#@ alias ls "sh ls -aC " -#@ } else { -#@ alias ls "sh ls -aC " -#@ } -#@ } -#@ } -#@ -#@ # Aliases for RouteCompiler -#@ alias run_rodeo_router route66 -#@ -#@ # Removing route_global from the code. Earlier it was hidden. --Mukesh -#@ #proc route_global {} { -#@ # global route_global_keep_tmp_data -#@ # global rt66_dont_lock_dir -#@ # -#@ # set rt66_dont_lock_dir TRUE -#@ # -#@ # for { set i 0} {1==1} {incr i} { -#@ # set wdir [file join [pwd] ".route_global.$i"] -#@ # if {[file exist $wdir] == 0} { -#@ # break; -#@ # } -#@ # } -#@ # -#@ # set_routing_options -cut_out_covered_port CORE_ONLY -#@ # set_routing_options -internal_routing FALSE -#@ # set_routing_options -stick_routing FALSE -#@ # -#@ # ###puts "wdir = $wdir" -#@ # -#@ # set success [route66 -global -dontstop -dir $wdir] -#@ # -#@ # #clean tmp data if required: -#@ # if { $success == 1 } { -#@ # if [catch {string toupper $route_global_keep_tmp_data} result] { -#@ # #variable is not defined -#@ # ###puts "result_1 = $result => removing dir ..." -#@ # catch { file delete -force $wdir } -#@ # } else { -#@ # #variable is set to FALSE -#@ # if { [string compare $result "TRUE"] != 0} { -#@ # ###puts "result_2 = $result => removing dir ..." -#@ # catch { file delete -force $wdir } -#@ # } -#@ # } -#@ # } -#@ # -#@ # set rt66_dont_lock_dir FALSE -#@ # return 1 -#@ #} -#@ #define_proc_attributes route_global -hidden -#@ -#@ #/* Aliases added for report command */ -#@ alias report_clock_constraint "report_timing -path end -to all_registers(-data_pins)" -#@ alias report_clock_fanout "report_transitive_fanout -clock_tree" -#@ alias report_clocks report_clock -#@ alias report_synthetic report_cell -#@ -#@ # Alias added for Ultra backward compatibility mode -#@ alias set_ultra_mode set_ultra_optimization -#@ -#@ # alias for write_sge and menu item in DA for db2sge -#@ -#@ #if { [string compare $dc_shell_mode "tcl"] == 0 } { -#@ # set db2sge_script ${synopsys_root}/admin/setup/.dc_write_sge.tcl -#@ #} else { -#@ # set db2sge_script ${synopsys_root}/admin/setup/.dc_write_sge -#@ #} -#@ -#@ #set db2sge_command ${synopsys_root}/${sh_arch}/syn/bin/db2sge -#@ set view_script_submenu_items "\"DA to SGE Transfer\" write_sge" -#@ -#@ -#@ if { $synopsys_program_name != "lc_shell"} { -#@ # read schematic annotation setup file -#@ #source ${synopsys_root}/admin/setup/.dc_annotate -#@ -#@ # setup the default layer settings -#@ #source ${synopsys_root}/admin/setup/.dc_layers -#@ -#@ if {$synopsys_program_name != "dc_sms_shell"} { -#@ source ${synopsys_root}/admin/setup/.dc_name_rules -#@ } -#@ } else { -#@ #for read_lib -html -#@ source ${synopsys_root}/auxx/syn/lc/read_lib_html_msg_list.tcl -#@ } -#@ # -- Starting source /tools/synopsys/synthesis/j201409sp3/auxx/syn/lc/read_lib_html_msg_list.tcl - -#@ ############################################################################## -#@ # message ID and descriptions for read_lib -html -#@ ############################################################################## -#@ set read_lib_ccs_noise_msg { -#@ LBDB-660 -#@ LBDB-706 -#@ LBDB-708 -#@ LBDB-709 -#@ LBDB-710 -#@ LBDB-711 -#@ LBDB-712 -#@ LBDB-713 -#@ LBDB-714 -#@ LBDB-715 -#@ LBDB-716 -#@ LBDB-717 -#@ LBDB-718 -#@ LBDB-733 -#@ LBDB-734 -#@ LBDB-784 -#@ LBDB-824 -#@ LBDB-825 -#@ LBDB-858 -#@ LBDB-898 -#@ LBDB-899 -#@ LBDB-908 -#@ LBDB-920 -#@ LBDB-935 -#@ LBDB-936 -#@ LBDB-937 -#@ LBDB-938 -#@ LBDB-939 -#@ } -#@ # -- End source /tools/synopsys/synthesis/j201409sp3/auxx/syn/lc/read_lib_html_msg_list.tcl - -#@ -#@ if { $synopsys_program_name == "psyn_gui"} { -#@ # read RouteCompiler GUI file for timing critical pathes. -#@ source ${synopsys_root}/auxx/syn/route_gui/write_route_timing_path.tcl -#@ } -#@ -#@ # Set physopt_dw_opto to false -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ set physopt_dw_opto FALSE -#@ } -#@ -#@ #/* Read budgeting setup script */ -#@ -#@ if { [string compare $dc_shell_mode "default"] == 0 } { -#@ -#@ # Need a encrypted file in Tcl format for budget.setup.et -#@ if { $sh_arch != "msvc50" && $sh_arch != "alpha_nt" } { -#@ # source -e synopsys_root + "/admin/setup/budget.setup.et" -#@ } -#@ } -#@ -#@ if { $synopsys_program_name == "icc_shell"} { -#@ source $synopsys_root/auxx/syn/.icc_procs.tcl -#@ source -encrypted $synopsys_root/auxx/syn/cts/fast_atomic_cts.tcl.e -#@ } -#@ -#@ if { $synopsys_program_name == "icc_shell"} { -#@ alias report_scenario report_scenarios -#@ } -#@ -#@ # floorplanning preferences globals -#@ global fp_snap_type -#@ -#@ set fp_snap_type(port) wiretrack -#@ set fp_snap_type(cell) litho -#@ set fp_snap_type(pin) wiretrack -#@ set fp_snap_type(movebound) litho -#@ set fp_snap_type(port_shape) wiretrack -#@ set fp_snap_type(wiring_keepout) wiretrack -#@ set fp_snap_type(placement_keepout) litho -#@ set fp_snap_type(net_shape) wiretrack -#@ set fp_snap_type(route_shape) wiretrack -#@ set fp_snap_type(none) litho -#@ -#@ # STAR 9000615813. PWR-18 is no longer internally suppressed. -#@ # Instead call tcl suppress_message so that it can be unsuppressed by users in -#@ # command line if needed -#@ suppress_message PWR-18 -#@ -#@ # alias for write_sge is always the last line of the setup file -#@ #if { [string compare $dc_shell_mode "tcl"] == 0 } { -#@ # alias write_sge "source db2sge_script" -#@ #} else { -#@ # alias write_sge "include db2sge_script" -#@ #} -#@ -#@ if { $dc_shell_mode == "tcl" } { -#@ # Configure Execute script dialog to display .tcl files -#@ set view_execute_script_suffix "$view_execute_script_suffix .tcl" -#@ } -#@ -#@ # -#@ # Shirley Lu 5/15/2007 -#@ # -#@ # Invoke NCX validation/correlation/fomatter from lc_shell: -#@ # -#@ # UNIX shell: -#@ # setenv SYNOPSYS_NCX_ROOT /mydisk/ncx_2007.06 -#@ # -#@ -#@ if {[info exists env(SYNOPSYS_NCX_ROOT)]} { -#@ -#@ set ncx_path $env(SYNOPSYS_NCX_ROOT)/ncx/${sh_arch}/bin -#@ -#@ # -#@ # check_ccs_lib -#@ # use libchecker under $ncx_path defined above -#@ # Disable this command since 2010.12-SP3 (should be done in 2010.12 release) -#@ #proc check_ccs_lib {args} { -#@ # global ncx_path -#@ # set cmdStr [linsert $args 0 ${ncx_path}/libchecker -lc_shell] -#@ # set cmd [open "| $cmdStr 2>@ stdout"] -#@ # catch { -#@ # while {[gets $cmd info] >= 0} { -#@ # echo $info -#@ # } -#@ # } -#@ # if {[catch {close $cmd} msg]} { -#@ # } -#@ #} -#@ -#@ # -#@ # format_lib -#@ # use ncx under $ncx_path defined above -#@ # Disable format_lib command in 2014.09 release -- xwwang, 7/25/2014 -#@ #proc format_lib {args} { -#@ # global ncx_path -#@ # echo "Warning: format_lib command is scheduled to become obsolete in a future production release." -#@ # set cmdStr [linsert $args 0 ${ncx_path}/ncx -lc_shell] -#@ # set cmd [open "| $cmdStr 2>@ stdout"] -#@ # catch { -#@ # while {[gets $cmd info] >= 0} { -#@ # echo $info -#@ # } -#@ # } -#@ # if {[catch {close $cmd} msg]} { -#@ # } -#@ #} -#@ -#@ } -#@ -#@ proc get_nglc_search_path { } { -#@ set exec_path "invalid" -#@ if {[info exists ::env(SYNOPSYS_LC_ROOT)] && [file exists $::env(SYNOPSYS_LC_ROOT)/$::sh_arch/lc/bin/lc_shell_exec]} { -#@ set exec_path $::env(SYNOPSYS_LC_ROOT)/$::sh_arch/lc/bin/lc_shell_exec -#@ } -#@ -#@ return $exec_path -#@ } -#@ -#@ proc get_libra_synopsys_root { } { -#@ return [file dirname [file dirname [file dirname [file dirname $::nglc_search_path] ] ] ] -#@ } -#@ -#@ proc valias {v_orig v_alias} { -#@ uplevel 1 "upvar 0 $v_orig $v_alias" -#@ } -#@ -#@ set nglc_result_path "/tmp" -#@ set nglc_replay_tcl_file "nglc_shell_command.tcl" -#@ set nglc_search_path [get_nglc_search_path] -#@ set lc_run_from_legacy_library_compiler "true" -#@ set nglc_is_none_tech_file "false" -#@ set nglc_keep_nglc_temp_files "false" -#@ set nglc_intermediate_db_files "" -#@ set nglc_log_path "" -#@ set lc_enable_legacy_library_compiler "false" -#@ -#@ valias lc_enable_legacy_library_compiler lc_enable_common_shell_lc -#@ -#@ proc nglc_read_lib { args } { -#@ common_shell_read_lib $args -#@ } -#@ -#@ -#@ proc common_shell_read_lib {args } { -#@ set_folder_var -#@ set tcl_file "$::nglc_result_path/$::nglc_log_path/$::nglc_replay_tcl_file" -#@ set chan [open $tcl_file a] -#@ export_tcl_var $chan -#@ gen_nglc_read_lib_procedure $chan $args -#@ close $chan -#@ run_libra_with_echo $tcl_file -#@ common_shell_read_dbs -#@ set_none_tech_file -#@ } -#@ -#@ # create the unique folder under tmp -#@ proc set_folder_var { } { -#@ set fileName [pid] -#@ set ::nglc_log_path [append fileName "_" [clock microseconds]] -#@ file delete -force $::nglc_result_path/$::nglc_log_path -#@ file mkdir $::nglc_result_path/$::nglc_log_path -#@ } -#@ -#@ # export all the vars -#@ proc export_tcl_var { fileName } { -#@ foreach var [info vars ::* ] { -#@ if [array exists $var] { -#@ continue; -#@ } -#@ puts $fileName "set $var \[list [set $var]\]" -#@ } -#@ } -#@ -#@ # excuted by libra shell to read the dbs generated by common_shell -#@ proc common_shell_read_dbs { } { -#@ set dbNames "" -#@ foreach var [glob -nocomplain -directory $::nglc_result_path/$::nglc_log_path *.db] { -#@ append dbNames " " $var -#@ } -#@ set ::nglc_intermediate_db_files $dbNames -#@ } -#@ -#@ # display the log file genrated by common_shell in Libra and then remove the unique folder -#@ proc common_shell_clean_up { } { -#@ if { $::nglc_keep_nglc_temp_files == "false" } { -#@ file delete -force $::nglc_result_path/$::nglc_log_path -#@ } -#@ } -#@ -#@ proc gen_nglc_read_lib_procedure { fileName args} { -#@ puts $fileName "##@@@## gen_common_shell_read_lib" -#@ puts $fileName "eval [lindex [lindex $args 0] 0]" -#@ puts $fileName "##@@@##" -#@ puts $fileName "set lc_write_view_db_file false" -#@ puts $fileName "set librs \[get_libs\]" -#@ puts $fileName "for {set i 0} {\$i < \[ sizeof \$librs \]} {incr i 1} {" -#@ puts $fileName " set lib \[index_collection \$librs \$i]" -#@ puts $fileName " redirect -var a \"query_object \$lib\" " -#@ puts $fileName " if \[regexp {{(\")?(gtech)(\")?}} \$a\] { " -#@ puts $fileName " } elseif \[regexp {{(\")?(standard.sldb)(\")?}} \$a] { " -#@ puts $fileName " } else {" -#@ puts $fileName " regexp {{(\")?(\[^\"\]*)(\")?}} \$a b c d e " -#@ puts $fileName " write_lib \$d -o \$nglc_result_path/\$nglc_log_path/\$d.db" -#@ puts $fileName " }" -#@ puts $fileName "}" -#@ puts $fileName "exit" -#@ } -#@ -#@ proc set_none_tech_file { } { -#@ if { [file exists $::nglc_result_path/$::nglc_log_path/is_non_tech_file] } { -#@ set ::nglc_is_none_tech_file true; -#@ } else { -#@ set ::nglc_is_none_tech_file false; -#@ } -#@ } -#@ -#@ proc run_libra_with_echo {tcl_file} { -#@ set chan [open "|$::nglc_search_path -r [get_libra_synopsys_root] -f $tcl_file" r] -#@ # things to do: In debug mode, we want copy the whole output (beginning to end) -#@ # to a file -#@ if {$::nglc_keep_nglc_temp_files} { -#@ set log [open $::nglc_result_path/$::nglc_log_path/libra.log w] -#@ } -#@ set echo 0 -#@ set firstLine true -#@ while {[gets $chan line] >= 0} { -#@ if {$::nglc_keep_nglc_temp_files} { puts $log $line } -#@ if {[string equal -length 7 $line "##@@@##"]} { -#@ set echo [expr ! $echo] -#@ continue; -#@ } -#@ if {$echo} { -#@ if { $firstLine } { -#@ set firstLine false -#@ continue; -#@ } else { -#@ puts $line -#@ } -#@ } -#@ } -#@ close $chan -#@ if {$::nglc_keep_nglc_temp_files} { -#@ close $log -#@ } -#@ } -#@ -#@ # -- End source /tools/synopsys/synthesis/j201409sp3/admin/setup/.synopsys_dc.setup - -source -echo -verbose /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/rf2_256x128_wm1/../convert_lib_to_db.tcl -#@ # -- Starting source /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/rf2_256x128_wm1/../convert_lib_to_db.tcl - -#@ set SOURCE_FILES [glob *.lib] -#@ foreach FILE ${SOURCE_FILES} { -#@ read_lib $FILE -#@ redirect -variable CURR_LIB {get_lib} -#@ -#@ set CURR_LIB [string range $CURR_LIB 2 end-3] -#@ set CURR_LIB [lindex $CURR_LIB 0] -#@ set FILENAME [string range $FILE 0 end-4] -#@ write_lib $CURR_LIB -output ${FILENAME}.db -#@ remove_lib $CURR_LIB -#@ } -#@ -#@ exit diff --git a/hw/models/memory/cln28hpm/rf2_256x19_wm0/command.log b/hw/models/memory/cln28hpm/rf2_256x19_wm0/command.log deleted file mode 100644 index 8e4bd85a..00000000 --- a/hw/models/memory/cln28hpm/rf2_256x19_wm0/command.log +++ /dev/null @@ -1,3759 +0,0 @@ -#@ # -#@ # Running lc_shell Version J-2014.09-SP3 for amd64 -- Jan 19, 2015 -#@ # Date: Mon Oct 28 14:40:13 2019 -#@ # Run by: lzhu308@gtcad-srv1 -#@ - -source /tools/synopsys/synthesis/j201409sp3/admin/setup/.synopsys_dc.setup -#@ # -- Starting source /tools/synopsys/synthesis/j201409sp3/admin/setup/.synopsys_dc.setup - -#@ # -#@ # ".synopsys_dc.setup" Initialization File for -#@ # -#@ # Dc_Shell and Design_Analyzer -#@ # -#@ # The variables in this file define the behavior of many parts -#@ # of the Synopsys Synthesis Tools. Upon installation, they should -#@ # be reviewed and modified to fit your site's needs. Each engineer -#@ # can have a .synopsys file in his/her home directory or current -#@ # directory to override variable settings in this file. -#@ # -#@ # Each logical grouping of variables is commented as to their -#@ # nature and effect on the Synthesis Commands. Examples of -#@ # variable groups are the Compile Variable Group, which affects -#@ # the designs produced by the COMPILE command, and the Schematic -#@ # Variable Group, which affects the output of the create_schematic -#@ # command. -#@ # -#@ # You can type "man _variables" in dc_shell or -#@ # design_analyzer to get help about a group of variables. -#@ # For instance, to get help about the "system" variable group, -#@ # type "help system_variables". You can also type -#@ # "man ", to get help on the that variable's -#@ # group. -#@ # -#@ -#@ # System variables -#@ set sh_command_abbrev_mode "Anywhere" -#@ set sh_continue_on_error "true" -#@ update_app_var -default true sh_continue_on_error -#@ set sh_enable_page_mode "true" -#@ update_app_var -default true sh_enable_page_mode -#@ set sh_source_uses_search_path "true" -#@ update_app_var -default true sh_source_uses_search_path -#@ if {$synopsys_program_name == "dc_shell" || $synopsys_program_name == "de_shell" || $synopsys_program_name == "dc_sms_shell" } { -#@ set sh_new_variable_message "false" -#@ update_app_var -default false sh_new_variable_message -#@ } else { -#@ set sh_new_variable_message "true" -#@ update_app_var -default true sh_new_variable_message -#@ } -#@ -#@ if {$synopsys_program_name == "dc_shell"} { -#@ set html_log_enable "false" -#@ set html_log_filename "default.html" -#@ } -#@ -#@ if {$synopsys_program_name == "de_shell"} { -#@ set de_log_html_filename "default.html" -#@ } -#@ -#@ if { [string compare $dc_shell_mode "tcl"] == 0 } { -#@ set sh_enable_line_editing "true" -#@ set sh_line_editing_mode "emacs" -#@ } -#@ -#@ if {$synopsys_program_name == "icc_shell"} { -#@ if {"$sh_output_log_file" == ""} { -#@ set sh_output_log_file "icc_output.txt" -#@ } -#@ -#@ ## the variable sh_redirect_progress_messages only makes it possible -#@ ## for some commands to redirect progress messages to the log file,thereby -#@ ## bypassing the console and reducing the volume of messages on the console. -#@ set sh_redirect_progress_messages true -#@ } -#@ -#@ -#@ # Suppress new variable messages for the following variables -#@ array set auto_index {} -#@ set auto_oldpath "" -#@ -#@ # Enable customer support banner on fatal -#@ if { $sh_arch == "linux" || $sh_arch == "amd64" || $sh_arch == "suse32" || $sh_arch == "suse64" || $sh_arch == "sparcOS5" || $sh_arch == "sparc64" || $sh_arch == "x86sol32" || $sh_arch == "x86sol64" || $sh_arch == "rs6000" || $sh_arch == "aix64" } { -#@ setenv SYNOPSYS_TRACE "" -#@ } -#@ -#@ # -#@ # Load the procedures which make up part of the user interface. -#@ # -#@ if { [string compare $dc_shell_mode "tcl"] == 0 } { -#@ source $synopsys_root/auxx/syn/.dc_common_procs.tcl -#@ if {$synopsys_program_name != "dc_sms_shell"} { -#@ source $synopsys_root/auxx/syn/.dc_procs.tcl -#@ } -#@ alias list_commands help -#@ } -#@ # -- Starting source /tools/synopsys/synthesis/j201409sp3/auxx/syn/.dc_common_procs.tcl - -#@ ############################################################################## -#@ # -#@ # -#@ # FILE: auxx/syn/.dc_common_procs.tcl -#@ # -#@ # ABSTRACT: These procedures are part of the PrimeTime and DC -#@ # user interface. -#@ # They are loaded by .synopsys_pt.setup and .synopsys_dc.setup. -#@ # -#@ ############################################################################## -#@ # -#@ # -#@ -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: group_variable -#@ # -#@ # ABSTRACT: Add a variable to the specified variable group. -#@ # This command is typically used by the system -#@ # administrator only. -#@ # -#@ # Below the proc is the command which creates the command -#@ # help information and semantic data for the argument. -#@ # -#@ # RETURNS: 1 if it is successful. -#@ # error code if the variable does not exist. -#@ # error code of the variable is already in the group. -#@ # -#@ # SYNTAX: group_variable group_name variable_name -#@ # -#@ ############################################################################## -#@ # -#@ -#@ -#@ proc group_variable { args } { -#@ global _Variable_Groups -#@ -#@ parse_proc_arguments -args $args resarr -#@ set group $resarr(group) -#@ set var $resarr(variable_name) -#@ -#@ if { ![info exists _Variable_Groups($group)] } { -#@ set _Variable_Groups($group) "" -#@ } -#@ -#@ # Verify that var exists as a global variable -#@ -#@ set cmd "uplevel #0 \{info exists $var\}" -#@ if { ![eval $cmd] } { -#@ return -code error "Variable '$var' is not defined." -#@ } -#@ -#@ # Only add it if it's not already there -#@ -#@ if { [lsearch $_Variable_Groups($group) $var] == -1 } { -#@ lappend _Variable_Groups($group) $var -#@ } -#@ -#@ return 1 -#@ } -#@ -#@ define_proc_attributes group_variable -info "Add a variable to a variable group" -command_group "Builtins" -permanent -dont_abbrev -define_args { -#@ {group "Variable group name" group} -#@ {variable_name "Variable name" variable_name}} -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: print_variable_group -#@ # -#@ # ABSTRACT: Shows variables and their values defined in the given group. -#@ -#@ # -#@ # Below the proc is the command which creates the command -#@ # help information and semantic data for the argument. -#@ # -#@ # RETURNS: 1 if it is successful. -#@ # error code of the variable group does not exist. -#@ # -#@ # SYNTAX: print_variable_group group_name -#@ # -#@ ############################################################################## -#@ # -#@ -#@ proc print_variable_group { args } { -#@ global _Variable_Groups -#@ -#@ parse_proc_arguments -args $args resarr -#@ set group $resarr(group) -#@ -#@ if { [string compare $group "all"] == 0 } { -#@ set cmd "uplevel #0 \{printvar\}" -#@ return [eval $cmd] -#@ } -#@ -#@ if { ![info exists _Variable_Groups($group)] } { -#@ return -code error "Variable group '$group' does not exist." -#@ } -#@ -#@ # Print out each global variable in the list. To be totally bulletproof, -#@ # test that each variable in the group is still defined. If not, remove -#@ # it from the list. -#@ -#@ foreach var [lsort $_Variable_Groups($group)] { -#@ set cmd "uplevel #0 \{info exists $var\}" -#@ if { ![eval $cmd] } { -#@ # Remove it -#@ set n [lsearch $_Variable_Groups($group) $var] -#@ set $_Variable_Groups($group) [lreplace $_Variable_Groups($group) $n $n] -#@ } else { -#@ # Print it. -#@ set cmd "uplevel #0 \{set $var\}" -#@ set val [eval $cmd] -#@ echo [format "%-25s = \"%s\"" $var $val] -#@ } -#@ } -#@ -#@ return 1 -#@ } -#@ -#@ define_proc_attributes print_variable_group -info "Print the contents of a variable group" -command_group "Builtins" -permanent -define_args {{group "Variable group name" group}} -#@ -#@ -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: _Variable_Groups_Get_Groups -#@ # -#@ # ABSTRACT: Return a list of all variable groups. This command is hidden -#@ # and is used by Design Vision. -#@ # -#@ # RETURNS: Tcl list of all variable groups including group all -#@ # -#@ # SYNTAX: _Variable_Groups_Get_Groups -#@ ############################################################################## -#@ # -#@ -#@ proc _Variable_Groups_Get_Groups { } { -#@ global _Variable_Groups -#@ -#@ set groups [array names _Variable_Groups] -#@ append groups " all" -#@ return $groups -#@ } -#@ define_proc_attributes _Variable_Groups_Get_Groups -hidden -#@ -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: _Variable_Groups_Get_Variables_Of_Group -#@ # -#@ # ABSTRACT: Return a list of all variables of a variable group. -#@ # It also works for pseudo group all. -#@ # -#@ # RETURNS: Tcl list of all variables of a variable group including -#@ # pseudo group all -#@ # -#@ # SYNTAX: _Variable_Groups_Get_Groups -#@ ############################################################################## -#@ # -#@ -#@ proc _Variable_Groups_Get_Variables_Of_Group { group } { -#@ global _Variable_Groups -#@ -#@ if { [string compare $group "all"] == 0 } { -#@ set itr [array startsearch _Variable_Groups] -#@ for { } { [array anymore _Variable_Groups $itr]} { } { -#@ set index [array nextelement _Variable_Groups $itr] -#@ append vars $_Variable_Groups($index) -#@ } -#@ array donesearch _Variable_Groups $itr -#@ return $vars -#@ } -#@ -#@ if { ![info exists _Variable_Groups($group)] } { -#@ return -code error "Variable group '$group' does not exist." -#@ } -#@ -#@ # Test if all variables in the list of variables are still defined. -#@ # Remove not existing variables. -#@ foreach var [lsort $_Variable_Groups($group)] { -#@ set cmd "uplevel #0 \{info exists $var\}" -#@ if { ![eval $cmd] } { -#@ # Remove it -#@ set n [lsearch $_Variable_Groups($group) $var] -#@ set $_Variable_Groups($group) [lreplace $_Variable_Groups($group) $n $n] -#@ } -#@ } -#@ return $_Variable_Groups($group) -#@ } -#@ define_proc_attributes _Variable_Groups_Get_Variables_Of_Group -hidden -#@ -#@ # -- End source /tools/synopsys/synthesis/j201409sp3/auxx/syn/.dc_common_procs.tcl - -#@ # -- Starting source /tools/synopsys/synthesis/j201409sp3/auxx/syn/.dc_procs.tcl - -#@ ############################################################################## -#@ # -#@ # -#@ # FILE: auxx/syn/.dc_procs.tcl -#@ # -#@ # ABSTRACT: These procedures are part of the Design Compiler Tcl -#@ # user interface. -#@ # They are loaded by .synopsys_dc.setup. -#@ # -#@ ############################################################################## -#@ # -#@ # -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: read_verilog -#@ # -#@ # ABSTRACT: Emulate PT's read_verilog command in DC: -#@ # -#@ # Usage: read_verilog # Read one or more verilog files -#@ # *[-hdl_compiler] (Use HDL Compiler (ignored)) -#@ # file_names (Files to read) -#@ # -#@ # Modified: Bharat 11/17/99. Use uplevel to ensure that the command -#@ # sees user/hidden variables from the top level. Star 92970. -#@ # -#@ # Modified: Evan Rosser, 12/5/01. Support -netlist and -rtl flags. -#@ # -#@ ############################################################################## -#@ # -#@ -#@ if { $synopsys_program_name != "icc_shell" } { -#@ proc read_verilog { args } { -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {read_file -format verilog %s %s [list %s]} [array names ra -rtl] [array names ra -netlist] $ra(file_names)] -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes read_verilog -info " Read one or more verilog files" -permanent -define_args { -#@ {file_names "Files to read" file_names list required} -#@ {-netlist "Use structural Verilog netlist reader" "" boolean optional} -#@ {-rtl "Use RTL Verilog compiler (Presto or HDLC)" "" boolean optional} -#@ {-hdl_compiler "Use HDL Compiler (ignored)" "" boolean {hidden optional}} -#@ } -#@ } -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: read_sverilog -#@ # -#@ # ABSTRACT: Emulate PT's read_sverilog command in DC: -#@ # -#@ # Usage: read_sverilog # Read one or more systemverilog files -#@ # *[-hdl_compiler] (Use HDL Compiler (ignored)) -#@ # file_names (Files to read) -#@ # -#@ # Modified: Yong Xiao, 01/31/2003: Copied from read_verilog to support -#@ # systemverilog input. -#@ # -#@ ############################################################################## -#@ # -#@ -#@ proc read_sverilog { args } { -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {read_file -format sverilog %s %s [list %s]} [array names ra -rtl] [array names ra -netlist] $ra(file_names)] -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes read_sverilog -info " Read one or more systemverilog files" -permanent -define_args { -#@ {file_names "Files to read" file_names list required} -#@ {-netlist "Use structural Verilog netlist reader" "" boolean optional} -#@ {-rtl "Use RTL Systemverilog compiler (Presto or HDLC)" "" boolean optional} -#@ {-hdl_compiler "Use HDL Compiler (ignored)" "" boolean {hidden optional}} -#@ } -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: read_vhdl -#@ # -#@ # ABSTRACT: Emulate PT's read_vhdl command in DC: -#@ # -#@ # Usage: read_vhdl # Read one or more vhdl files -#@ # file_names (Files to read) -#@ # -#@ # -#@ ############################################################################## -#@ # -#@ -#@ proc read_vhdl { args } { -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {read_file -format vhdl %s [list %s]} [array names ra -netlist] $ra(file_names)] -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes read_vhdl -info " Read one or more vhdl files" -permanent -define_args { -#@ {file_names "Files to read" file_names list required} -#@ {-netlist "Use structural VHDL netlist reader" "" boolean optional} -#@ } -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: read_db -#@ # -#@ # ABSTRACT: Emulate PT's read_db command in DC: -#@ # -#@ # Usage: -#@ # read_db # Read one or more db files -#@ # *[-netlist_only] (Do not read any attributes from db (ignored)) -#@ # *[-library] (File is a library DB (ignored)) -#@ # file_names (Files to read) -#@ # -#@ # -#@ ############################################################################## -#@ # -#@ -#@ proc read_db { args } { -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {read_file -format db [list %s]} $ra(file_names)] -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes read_db -info " Read one or more db files" -permanent -define_args { -#@ {file_names "Files to read" file_names list required} -#@ {-netlist_only "Do not read any attributes from db (ignored)" "" boolean {hidden optional}} -#@ {-library "File is a library DB (ignored)" "" boolean {hidden optional}} -#@ } -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: read_edif -#@ # -#@ # ABSTRACT: Emulate PT's read_edif command in DC: -#@ # -#@ # Usage: -#@ # read_edif # Read one or more edif files -#@ # *[-complete_language] (Use ptxr to read the file (ignored)) -#@ # file_names (Files to read) -#@ # -#@ # -#@ ############################################################################## -#@ # -#@ proc read_edif { args } { -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {read_file -format edif [list %s]} $ra(file_names)] -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes read_edif -info " Read one or more edif files" -permanent -define_args { -#@ {file_names "Files to read" file_names list required} -#@ {-complete_language "Use ptxr to read the file (ignored)" "" boolean {hidden optional}} -#@ } -#@ -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: read_ddc -#@ # -#@ # ABSTRACT: Shorthand for "read_file -format ddc": -#@ # -#@ # Usage: -#@ # read_ddc # Read one or more ddc files -#@ # *[-scenarios] only read constraints for specified scenarios -#@ # *[-active_scenarios] only activate the specified scenarios -#@ # file_names (Files to read) -#@ # -#@ # -#@ ############################################################################## -#@ # -#@ -#@ proc read_ddc { args } { -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd "read_file -format ddc" -#@ if { [ info exists ra(-scenarios) ] } { -#@ set cmd "$cmd -scenarios { $ra(-scenarios) }" -#@ } -#@ if { [ info exists ra(-active_scenarios) ] } { -#@ set cmd "$cmd -active_scenarios { $ra(-active_scenarios) }" -#@ } -#@ set cmd "$cmd { $ra(file_names) }" -#@ return [uplevel \#0 $cmd] -#@ } -#@ -#@ define_proc_attributes read_ddc -info "Read one or more ddc files" -permanent -define_args { -#@ {file_names "Files to read" file_names list required} -#@ {-scenarios "list of scenarios to be read from ddc file" -#@ scenario_list list optional} -#@ {-active_scenarios "list of scenarios to be made active" -#@ active_scenario_list list optional}} -#@ -#@ -#@ -#@ ############################################################################## -#@ # -#@ # PROCEDURE: source_tcl_file -#@ # -#@ # ABSTRACT: generic procedure to source another tcl file -#@ # -#@ # Arguments: -#@ # filename tcl filename -#@ # dir directory to check for file -#@ # msg verbose message -#@ # verbose verbose mode -#@ # -#@ # Usage: -#@ # -#@ ############################################################################## -#@ # -#@ proc source_tcl_file { filename dir msg {verbose 1} } { -#@ set __qual_pref_file [file join $dir $filename] -#@ if {[file exists $__qual_pref_file]} { -#@ if { $verbose } { -#@ echo $msg $__qual_pref_file -#@ } -#@ # use catch to recover from errors in the pref file -#@ echo_trace "Sourcing " $__qual_pref_file -#@ # to speed up sourcing use read and eval -#@ set f [open $__qual_pref_file] -#@ if {[catch {namespace eval :: [read -nonewline $f]} __msg]} { -#@ echo Error: Error during sourcing of $__qual_pref_file -#@ if {$__msg != ""} { echo $__msg } -#@ # actually, it looks like $__msg is always null after -#@ # source fails -#@ } -#@ close $f -#@ } else { -#@ echo_trace "Info: File '" $__qual_pref_file "' does not exist!" -#@ } -#@ } -#@ define_proc_attributes source_tcl_file -hidden -#@ -#@ -#@ -#@ ############################################################################## -#@ # -#@ # PROCEDURE: echo_trace -#@ # -#@ # ABSTRACT: echo only in trace modus -#@ # -#@ ############################################################################## -#@ # -#@ proc echo_trace { args } { -#@ if { [info exists ::env(TCL_TRACE)] } { -#@ echo TRACE\> [join $args "" ] -#@ } -#@ } -#@ define_proc_attributes echo_trace -hidden -#@ -#@ ############################################################################# -#@ # -#@ # Following procedures added for PC write_script -#@ # -#@ # -#@ # -#@ ############################################################################ -#@ -#@ proc set_cell_restriction { args } { -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {set_attribute %s -type integer restrictions %s } $ra(cell) $ra(value)] -#@ return [uplevel #0 $cmd] -#@ -#@ } -#@ define_proc_attributes set_cell_restriction -hidden -define_args { {cell "cell_name" cell string required} {value "value" value string required} } -#@ -#@ -#@ proc set_cell_soft_keepout {args} { -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {set_keepout_margin -type soft -outer {%d %d %d %d} [list %s] } $ra(llx) $ra(lly) $ra(urx) $ra(ury) $ra(objects)] -#@ return [uplevel #0 $cmd] -#@ -#@ -#@ } -#@ -#@ define_proc_attributes set_cell_soft_keepout -hidden -define_args { {llx "llx" llx float required} {lly "lly" lly float required} {urx "urx" urx float required} {ury "ury" ury float required} {objects "objects" objects list required} } -#@ -#@ proc set_cell_hard_keepout {args} { -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {set_keepout_margin -type soft -outer {%d %d %d %d} [list %s] } $ra(llx) $ra(lly) $ra(urx) $ra(ury) $ra(objects)] -#@ return [uplevel #0 $cmd] -#@ -#@ -#@ } -#@ -#@ define_proc_attributes set_cell_hard_keepout -hidden -define_args { {llx "llx" llx float required} {lly "lly" lly float required} {urx "urx" urx float required} {ury "ury" ury float required} {objects "objects" objects list required} } -#@ -#@ set mw_use_pdb_lib_format false -#@ -#@ ############################################################################## -#@ # -#@ # PROCEDURE: write_milkyway -#@ # -#@ # ABSTRACT: wrapper around save_mw_cel to support original write_milkyway -#@ # interface -#@ # if { [info commands open_mw_cel] == "open_mw_cel" } {} -#@ # -#@ ############################################################################## -#@ -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ -#@ proc write_milkyway args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {save_mw_cel -as %s %s %s %s %s} $ra(-output) [array names ra -overwrite] [array names ra -create] [array names ra -all] [array names ra -dps]] -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes write_milkyway -hidden -info " Saves the design as milkyway CEL" -define_args {{-output fileName "Name" string {optional}} {-overwrite "Overwrite the current version" "" boolean {optional}} {-create "Create from scratch" "" boolean {hidden optional}} {-all "Save all modified cells" "" boolean {hidden optional}} {-dps "Save internal DPS design" "" boolean {hidden optional}}} -#@ -#@ ############################################################################## -#@ # -#@ # PROCEDURE: read_milkyway -#@ # -#@ # ABSTRACT: wrapper around open_mw_cel to support original read_milkyway -#@ # interface -#@ # MODIFIED: To support DPS in Galileo we need to pass the filtering -#@ # parameters to the DPS command. (Pankaj Goswami, Mar09 2005) -#@ # -#@ ############################################################################## -#@ -#@ proc read_milkyway args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {open_mw_cel %s} $ra() ] -#@ -#@ if {[info exists ra(-library)]} { -#@ set cmd [concat [concat $cmd " -library " ] " $ra(-library) "] -#@ } -#@ -#@ if {[info exists ra(-read_only)]} { -#@ lappend cmd {-readonly} -#@ } -#@ -#@ # DPS specific stuff -#@ set dps_cmd "vh_set_current_partition " -#@ set read_mw_with_dps_filter false -#@ -#@ if {[info exists ra(-vh_module_only)]} { -#@ append dps_cmd "-vh_module_only " -#@ set read_mw_with_dps_filter true -#@ } -#@ -#@ if {[info exists ra(-vh_include)]} { -#@ append dps_cmd [concat " -vh_include " " \{ $ra(-vh_include) \}"] -#@ append dps_cmd " " -#@ set read_mw_with_dps_filter true -#@ } -#@ -#@ if {[info exists ra(-vh_exclude)]} { -#@ append dps_cmd [concat " -vh_exclude" " \{ $ra(-vh_exclude) \}"] -#@ set read_mw_with_dps_filter true -#@ } -#@ -#@ if { $read_mw_with_dps_filter == true } { -#@ # Call the DPS command to store the DPS filtering params. -#@ uplevel #0 $dps_cmd -#@ } else { -#@ # If there is no DPS filtering params, then we need to reset the -#@ # params which might have been stored from the provious command. -#@ append dps_cmd " -vh_reset_partition" -#@ uplevel #0 $dps_cmd -#@ } -#@ # End of DPS stuff -#@ -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes read_milkyway -hidden -info " Read milkyway CEL from disk" -define_args {{-library "library name" "lib_name" string {optional}} {-read_only "open design in read only mode" "" boolean {optional}} {-version "version number of the CEL" "number" string {optional}} {-vh_module_only "open design for DPS module only partition" "" boolean {hidden optional}} {-vh_include "list of designs to be included in the DPS partition" "include_designs" list {hidden optional}} {-vh_exclude "list of designs to be excluded in the DPS partition" "exclude_designs" list {hidden optional}} {"" fileName "CEL name" string {required}}} -#@ -#@ } -#@ -#@ ############################################################################## -#@ # -#@ # PROCEDURE: set_mw_technology_file -#@ # -#@ # ABSTRACT: wrapper around update_mw_lib -#@ # -#@ # HISTORY : 2009/6/21, yunz, support ALF reader in ICC -#@ # -#@ ############################################################################## -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] || -#@ ([string match -nocase {*d[ce]_shell*} $synopsys_program_name] && [shell_is_mwlib_enabled]) } { -#@ -#@ proc set_mw_technology_file args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd "" -#@ set lib_name "" -#@ set pdb_file "tech.pdb" -#@ set log_file "log_file" -#@ set alf_file "" -#@ -#@ if {[info exists ra(-technology)] && [info exists ra(-plib)]} { -#@ echo "Error: the $ra(-technology) and $ra(-plib) options are mutually exclusive." -#@ return [uplevel #0 $cmd] -#@ } elseif {[info exists ra(-technology)] && [info exists ra(-alf)]} { -#@ echo "Error: the $ra(-technology) and $ra(-alf) options are mutually exclusive." -#@ return [uplevel #0 $cmd] -#@ } elseif {[info exists ra(-plib)] && [info exists ra(-alf)]} { -#@ echo "Error: the $ra(-plib) and $ra(-alf) options are mutually exclusive." -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ if {[info exists ra(-technology)]} { -#@ -#@ set cmd [format {update_mw_lib -technology %s %s} $ra(-technology) $ra() ] -#@ } -#@ -#@ if {[info exists ra(-plib)]} { -#@ -#@ set cmd [format {update_mw_lib %s} $ra() ] -#@ -#@ if {[string match -nocase {*.pdb} $ra(-plib) ] } { -#@ set cmd [concat [concat $cmd " -plib " ] " $ra(-plib) "] -#@ } -#@ if {[string match -nocase {*.plib} $ra(-plib) ] } { -#@ set subcmd [format {set lc_enable_legacy_library_compiler true;read_lib %s} $ra(-plib)] -#@ redirect -file log_file {uplevel #0 $subcmd} -#@ set f1 [open $log_file] -#@ while {[gets $f1 line] >= 0} { -#@ set msg1 [lindex $line 3] -#@ set msg2 [lindex $line 4] -#@ if {[string match {read} $msg1] && -#@ [string match {successfully} $msg2] } { -#@ set msg [lindex $line 2] -#@ set len [string length $msg] -#@ set lib_name [string range $msg 1 [expr $len-2] ] -#@ break -#@ } -#@ if {[string match {old} $msg1] && -#@ [string match {technology} $msg2] } { -#@ set msg [lindex $line 6] -#@ set len [string length $msg] -#@ set path [string range $msg 1 [expr $len-2] ] -#@ set name1 [lindex [split $path {/}] end] -#@ regexp {(.+?).pdb} $name1 match lib_name -#@ break -#@ } -#@ } -#@ if {$lib_name != ""} { -#@ set subcmd [format {write_lib %s -output %s} $lib_name $pdb_file] -#@ uplevel #0 $subcmd -#@ -#@ echo "Command is : " -#@ echo $cmd -#@ -#@ set cmd [concat [concat $cmd " -plib " ] " $pdb_file "] -#@ -#@ echo "Command is : " -#@ echo $cmd -#@ -#@ } else { -#@ echo "Error: Can not compile $ra(-plib) to pdb successfully" -#@ return 0; -#@ } -#@ } -#@ } -#@ if {[info exists ra(-alf)]} { -#@ -#@ set cmd [format {update_mw_lib %s} $ra() ] -#@ -#@ set cmd [concat [concat $cmd " -alf " ] " $ra(-alf) "] -#@ } -#@ -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes set_mw_technology_file -hide_body -info " Set technology file for the library " -define_args {{-technology "Technology file name" "tech_file" string {optional}} {-plib "Plib file name" "file_name" string {optional}} {-alf "alf file name" "file_name" string {optional}} {"" "Library name" "libName" string {required}}} -#@ -#@ ############################################################################## -#@ # -#@ # PROCEDURE: rebuild_mw_lib -#@ # -#@ # ABSTRACT: wrapper around update_mw_lib -#@ # -#@ ############################################################################## -#@ -#@ proc rebuild_mw_lib args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {update_mw_lib -rebuild %s} $ra() ] -#@ -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes rebuild_mw_lib -hide_body -info " Rebuild the library " -define_args {{"" "Library name" "libName" string {required}}} -#@ -#@ ############################################################################## -#@ # -#@ # PROCEDURE: set_mw_lib_reference -#@ # -#@ # ABSTRACT: Procedure to set ref lib list or ref ctrl file -#@ # -#@ ############################################################################## -#@ -#@ proc set_mw_lib_reference args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd "" -#@ -#@ if {[info exists ra(-mw_reference_library)]} { -#@ set cmd [format {set_reference_control_file -reference_libraries {%s} %s} $ra(-mw_reference_library) $ra() ] -#@ } -#@ -#@ if {[info exists ra(-reference_control_file)]} { -#@ set cmd [format {set_reference_control_file -file %s %s} $ra(-reference_control_file) $ra() ] -#@ } -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes set_mw_lib_reference -hide_body -info " Set reference for the library " -define_args {{-mw_reference_library "List of reference libraries" "lib_list" list {optional}} {-reference_control_file "Reference control file" "file_name" string {optional}} {"" "Library name" "libName" string {required}}} -#@ -#@ # -#@ ############################################################################## -#@ # -#@ # PROCEDURE: create_mw_lib -#@ # -#@ # ABSTRACT: wrapper around MWUI create_mw_lib -#@ # -#@ ############################################################################## -#@ -#@ proc create_mw_lib args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd "" -#@ set lib_name "" -#@ set pdb_file "tech.pdb" -#@ set log_file "log_file" -#@ -#@ if {[info exists ra(-ignore_case)]} { -#@ set cmd [format {org_create_mw_lib %s} $ra() ] -#@ } else { -#@ set cmd [format {org_create_mw_lib -case_sensitive %s} $ra() ] -#@ } -#@ -#@ if {[info exists ra(-technology)]} { -#@ set cmd [concat [concat $cmd " -technology " ] " $ra(-technology) "] -#@ } -#@ -#@ if {[info exists ra(-ignore_tf_error)]} { -#@ set cmd [concat $cmd " -ignore_tf_error " ] -#@ } -#@ -#@ if {[info exists ra(-hier_separator)]} { -#@ set cmd [concat [concat $cmd " -hier_seperator " ] " $ra(-hier_separator) "] -#@ } -#@ -#@ if {[info exists ra(-bus_naming_style)]} { -#@ set cmd [concat [concat $cmd " -bus_naming_style " ] " {$ra(-bus_naming_style)} "] -#@ } -#@ -#@ -#@ if {[info exists ra(-reference_control_file)]} { -#@ set cmd [concat [concat $cmd " -reference_control_file " ] " $ra(-reference_control_file) "] -#@ } -#@ -#@ if {[info exists ra(-mw_reference_library)]} { -#@ set cmd [concat [concat [concat $cmd " -mw_reference_library {" ] " $ra(-mw_reference_library) "] "}"] -#@ } -#@ -#@ if {[info exists ra(-plib)]} { -#@ if {[string match -nocase {*.pdb} $ra(-plib) ] } { -#@ set cmd [concat [concat $cmd " -plib " ] " $ra(-plib) "] -#@ } -#@ if {[string match -nocase {*.plib} $ra(-plib) ] } { -#@ set subcmd [format {set lc_enable_legacy_library_compiler true; read_lib %s} $ra(-plib)] -#@ redirect -file log_file {uplevel #0 $subcmd} -#@ set f1 [open $log_file] -#@ while {[gets $f1 line] >= 0} { -#@ set msg1 [lindex $line 3] -#@ set msg2 [lindex $line 4] -#@ if {[string match {read} $msg1] && -#@ [string match {successfully} $msg2] } { -#@ set msg [lindex $line 2] -#@ set len [string length $msg] -#@ set lib_name [string range $msg 1 [expr $len-2] ] -#@ break -#@ } -#@ if {[string match {old} $msg1] && -#@ [string match {technology} $msg2] } { -#@ set msg [lindex $line 6] -#@ set len [string length $msg] -#@ set path [string range $msg 1 [expr $len-2] ] -#@ set name1 [lindex [split $path {/}] end] -#@ regexp {(.+?).pdb} $name1 match lib_name -#@ break -#@ } -#@ } -#@ if {$lib_name != ""} { -#@ set subcmd [format {write_lib %s -output %s} $lib_name $pdb_file] -#@ uplevel #0 $subcmd -#@ set cmd [concat [concat $cmd " -plib " ] " $pdb_file "] -#@ } else { -#@ echo "Error: Can not compile $ra(-plib) to pdb successfully" -#@ return 0; -#@ } -#@ } -#@ } -#@ -#@ if { ![uplevel #0 $cmd] } { -#@ return 0 -#@ } -#@ -#@ set cmd "" -#@ -#@ if {[info exists ra(-open)]} { -#@ uplevel #0 $cmd -#@ set cmd [format {open_mw_lib %s} $ra() ] -#@ } -#@ -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes create_mw_lib -hide_body -info " Create a milkyway library " -define_args {{-technology "Technology file name" "file_name" string {optional}} {-ignore_tf_error "Ignore the error in technology file" "" boolean {hidden optional}} {-plib "Plib file name" "file_name" string {optional}} {-hier_separator "Hierarchical separator, default is backslash / " "separator" string {hidden optional}} {-bus_naming_style "Bus naming style" "bus_naming_style" string {optional}} {-ignore_case "Make case insensitive" "" boolean {hidden optional}} {-case_sensitive "Make case sensitive" "" boolean {hidden optional}} {-mw_reference_library "List of reference libraries" "lib_list" list {optional}} {-reference_control_file "Reference control file" "file_name" string {optional}} {-open "Open the library after creation" "" boolean {optional}} {"" "Library name to create" "libName" string {required}}} -#@ -#@ # -#@ ############################################################################## -#@ # -#@ # PROCEDURE: report_mw_lib -#@ # -#@ # ABSTRACT: wrapper around MWUI report_mw_lib -#@ # -#@ ############################################################################## -#@ -#@ proc report_mw_lib args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd "" -#@ -#@ if {[info exists ra(-mw_reference_library)]} { -#@ if {[info exists ra()]} { -#@ set cmd [format {org_report_mw_lib -mw_reference_library %s} $ra() ] -#@ } else { -#@ set cmd [format {org_report_mw_lib -mw_reference_library} ] -#@ } -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ if {[info exists ra(-unit_range)]} { -#@ if {[info exists ra()]} { -#@ set cmd [format {org_report_mw_lib -unit_range %s} $ra() ] -#@ } else { -#@ echo "Error : Library name must be specified when using this option" -#@ return 0; -#@ } -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ } -#@ -#@ define_proc_attributes report_mw_lib -hide_body -info " Report information about the library " -define_args {{-unit_range "Report unit range of library" "" boolean {optional}} {-mw_reference_library "Report list of reference libraries" "" boolean {optional}} {"" "Library to be reported" "libName" string {optional}}} -#@ -#@ ############################################################################## -#@ # -#@ # PROCEDURE: close_mw_lib -#@ # -#@ # ABSTRACT: Wrapper around close_mw_lib to handle -save option properly -#@ # - save_mw_cel to save current cel with dc_netlist -#@ # - close_mw_cel to close current cel -#@ # - save_open_cels to save other open cels before closing library -#@ # -#@ ############################################################################## -#@ -#@ proc close_mw_lib args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ if {$args == ""} { -#@ set cmd [format {icc_is_dc_up} ] -#@ if {[uplevel #0 $cmd]} { -#@ set cmd [format {remove_design -quiet -designs} ] -#@ if {[uplevel #0 $cmd]} { -#@ set cmd [format {org_close_mw_lib } ] -#@ return [uplevel #0 $cmd] -#@ } else { -#@ return 0 -#@ } -#@ } else { -#@ set cmd [format {org_close_mw_lib } ] -#@ return [uplevel #0 $cmd] -#@ } -#@ } -#@ -#@ if {[info exists ra(-save)]} { -#@ -#@ set cmd [format {save_mw_cel} ] -#@ if {![uplevel #0 $cmd]} { -#@ return -#@ } -#@ -#@ set cmd [format {close_mw_cel} ] -#@ if {![uplevel #0 $cmd]} { -#@ return -#@ } -#@ -#@ set cmd [format {save_open_cels} ] -#@ if {![uplevel #0 $cmd]} { -#@ return -#@ } -#@ } -#@ -#@ set cmd [format {org_close_mw_lib} ] -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ define_proc_attributes close_mw_lib -hide_body -info " Closes the milkyway library " -define_args {{-save "Save open cels" "" boolean {optional}} {"" "libraries to be closed" "lib list" list {hidden optional}}} -#@ } else { -#@ define_proc_attributes close_mw_lib -hide_body -info " Closes the milkyway library " -define_args {{-no_save "Don't save open cels" "" boolean {hidden optional}} {"" "libraries to be closed" "lib list" list {hidden optional}}} -#@ } -#@ ############################################################################## -#@ # -#@ # PROCEDURE: write_mw_lib_files -#@ # -#@ # ABSTRACT: Write technology or reference control file -#@ # History: Yun Zhang 2012/12/11, public option -stream_layer_map_file -#@ # History: Yun Zhang 2012/9/5. support new hidden option -vt_cell_placement_properties -#@ # History: Yun Zhang 2011/12/5. add new hidden option -stream_layer_map_file -#@ # -#@ ############################################################################## -#@ proc write_mw_lib_files args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd "" -#@ -#@ if {[info exists ra(-reference_control_file)]} { -#@ #Option -reference_contrl_file, -plib and -technology are exclusive. -#@ # If both of them are set at the same time, error reported. -#@ # 9000273455, by xqsun, 2009/2/4 -#@ if {[info exists ra(-technology)]} { -#@ echo "Error: Cannot specify '-reference_control_file' with '-technology'.(CMD-001)" -#@ return 0 -#@ } elseif {[info exists ra(-plib)]} { -#@ echo "Error: Cannot specify '-reference_control_file' with '-plib'.(CMD-001)" -#@ return 0 -#@ } elseif {[info exists ra(-vt_cell_placement_properties)]} { -#@ echo "Error: Cannot specify '-reference_control_file' with '-vt_cell_placement_properties'.(CMD-001)" -#@ return 0 -#@ } elseif {[info exists ra(-stream_layer_map_file)]} { -#@ echo "Error: Cannot specify '-reference_control_file' with '-stream_layer_map_file'.(CMD-001)" -#@ return 0 -#@ } else { -#@ set cmd [format {report_mw_lib_ref_ctrl_file -output %s %s} $ra(-output) $ra() ] -#@ return [uplevel #0 $cmd] -#@ } -#@ } -#@ -#@ if {[info exists ra(-technology)]} { -#@ if {[info exists ra(-plib)]} { -#@ echo "Error: Cannot specify '-technology' with '-plib'.(CMD-001)" -#@ return 0 -#@ } elseif {[info exists ra(-vt_cell_placement_properties)]} { -#@ echo "Error: Cannot specify '-technology' with '-vt_cell_placement_properties'.(CMD-001)" -#@ return 0 -#@ } elseif {[info exists ra(-stream_layer_map_file)]} { -#@ echo "Error: Cannot specify '-technology' with '-stream_layer_map_file'.(CMD-001)" -#@ return 0 -#@ } else { -#@ set cmd [format {org_report_mw_lib -output %s %s} $ra(-output) $ra() ] -#@ return [uplevel #0 $cmd] -#@ } -#@ } -#@ -#@ if {[info exists ra(-plib)]} { -#@ if {[info exists ra(-stream_layer_map_file)]} { -#@ echo "Error: Cannot specify '-plib' with '-stream_layer_map_file'.(CMD-001)" -#@ return 0 -#@ } elseif {[info exists ra(-vt_cell_placement_properties)]} { -#@ echo "Error: Cannot specify '-plib' with '-vt_cell_placement_properties'.(CMD-001)" -#@ return 0 -#@ } else { -#@ set cmd [format {write_plib -lib_name %s %s} $ra() $ra(-output) ] -#@ return [uplevel #0 $cmd] -#@ } -#@ } -#@ -#@ if {[info exists ra(-vt_cell_placement_properties)]} { -#@ if {[info exists ra(-stream_layer_map_file)]} { -#@ echo "Error: Cannot specify '-vt_cell_placement_properties' with '-stream_layer_map_file'.(CMD-001)" -#@ return 0 -#@ } else { -#@ set cmd [format {org_report_mw_lib -vt_cell_placement_properties -output %s %s} $ra(-output) $ra() ] -#@ return [uplevel #0 $cmd] -#@ } -#@ } -#@ -#@ if {[info exists ra(-stream_layer_map_file)]} { -#@ set cmd [format {org_report_mw_lib -stream_layer_map_file %s -output %s %s} $ra(-stream_layer_map_file) $ra(-output) $ra() ] -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ } -#@ -#@ define_proc_attributes write_mw_lib_files -hide_body -info " Write technology or reference control file " -define_args {{-technology "Dump technology file" "" boolean {optional}} {-plib "Dump plib file" "" boolean {optional}} {-vt_cell_placement_properties "Dump multi-VT cells' implant layer information of library" "" boolean {optional hidden}} {-reference_control_file "Dump reference control file" "" boolean {optional}} {-stream_layer_map_file "Dump layer map file during stream in/out" "" string {optional}} {-output "Output file" "file_name" string {required}} {"" "Library to be reported" "libName" string {required}}} -#@ } -#@ ############################################################################## -#@ # -#@ # PROCEDURE: close_mw_cel -#@ # -#@ # ABSTRACT: Wrapper around close_mw_cel to add -save option -#@ # remove_timing_design is the command to shutdown dc netlist -#@ # -#@ ############################################################################## -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ -#@ proc close_mw_cel args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ global mw_is_all_views -#@ set cmd [format {icc_is_dc_up} ] -#@ set dc_is_up [uplevel #0 $cmd] -#@ -#@ set cmd_close [format {org_close_mw_cel} ] -#@ -#@ if {[info exists ra(-all_views)]} { -#@ set cmd_close [format {%s -all_views} $cmd_close] -#@ set mw_is_all_views 1 -#@ } -#@ if {[info exists ra(-all_versions)]} { -#@ set cmd_close [format {%s -all_versions} $cmd_close] -#@ } -#@ if {[info exists ra(-save)]} { -#@ set cmd_close [format {%s -save} $cmd_close] -#@ } -#@ if {[info exists ra(-verbose)]} { -#@ set cmd_close [format {%s -verbose} $cmd_close] -#@ } -#@ if {[info exists ra(-hierarchy)]} { -#@ set cmd_close [format {%s -hierarchy} $cmd_close] -#@ } -#@ -#@ ui_util_clean_saved_lib_attr $args -#@ -#@ set cmd "" -#@ set lcels "" -#@ set is_current_closed 1 -#@ -#@ if {[info exists ra()]} { -#@ set lcels $ra() -#@ } -#@ set len [string length $lcels] -#@ if {$len > 0} { -#@ set is_current_closed [is_current_mw_cel $lcels] -#@ set cmd_close [format {%s {%s}} $cmd_close $lcels] -#@ } -#@ if {[uplevel #0 $cmd_close]} { -#@ set mw_is_all_views 0 -#@ if {$dc_is_up == 1} { -#@ if {$is_current_closed == 1} { -#@ set cmd [format {remove_design -quiet -designs} ] -#@ return [uplevel #0 $cmd] -#@ } -#@ return 1 -#@ } else { -#@ return 1 -#@ } -#@ } else { -#@ set mw_is_all_views 0 -#@ return 0 -#@ } -#@ } -#@ -#@ define_proc_attributes close_mw_cel -hide_body -info " Closes the design " -define_args {{-save "Save the design" "" boolean {optional}} {-discard "Discard any changes" "" boolean {optional hidden}} {-verbose "Print out debugging messages" "" boolean {optional hidden}} {-hierarchy "Close top design and its child designs" "" boolean {optional}} {-all_views "Close all views of the design" "" boolean {optional}} {-all_versions "Close all versions of the design" "" boolean {optional}} {"" "designs to be closed" "design list" list {optional}}} -#@ -#@ ############################################################################## -#@ # -#@ # PROCEDURE: save_all_mw_cel -#@ # -#@ # ABSTRACT: Wrapper around save_mw_cel to save all the open cels. Needed for Black box flow. -#@ # -#@ ############################################################################## -#@ -#@ proc save_all_mw_cels { } { -#@ set top_cel [get_attribute [current_mw_cel] name] -#@ -#@ set cels [fp_get_open_cells] -#@ -#@ foreach cel $cels { -#@ if {$cel != $top_cel} { -#@ current_mw_cel $cel -#@ -#@ save_mw_cel -#@ } -#@ } -#@ -#@ current_mw_cel $top_cel -#@ -#@ save_mw_cel -#@ } -#@ -#@ icc_hide_cmd save_all_mw_cels -#@ -#@ ############################################################################## -#@ # PROCEDURE: execute_command_and_create_cel_from_scratch -#@ # ABSTRACT: This procedure executes the given command and creates the CEL -#@ # from scratch after executing this command. -#@ ############################################################################## -#@ proc execute_command_and_create_cel_from_scratch {org_cmd_name args} { -#@ global mw_create_cel_force -#@ global mw_enable_auto_cel -#@ global mw_force_auto_cel -#@ -#@ set lib [current_mw_lib] -#@ -#@ # If no MW lib, design is not from MW. Execute the original command -#@ # and return. -#@ if {$lib == ""} { -#@ return [eval $org_cmd_name $args] -#@ } -#@ -#@ # Get values of few variables. -#@ set incr_mode $mw_create_cel_force -#@ set mw_create_cel_force TRUE -#@ -#@ # Get auto cel mode, disable it temporarily if enabled. -#@ set auto_cel_mode $mw_enable_auto_cel -#@ set mw_enable_auto_cel FALSE -#@ -#@ # Check if the already existing CEL is auto-CEL. -#@ set auto_cel 0 -#@ if {[is_cel_auto_cel]} { -#@ set auto_cel 1 -#@ } elseif {![get_top_cel_mwid]} { -#@ set auto_cel 1 -#@ } -#@ -#@ -#@ # Run the original command, if not successful restore the incr_mode -#@ # variable and return. No CEL is created. -#@ if {![eval $org_cmd_name $args]} { -#@ set mw_create_cel_force $incr_mode -#@ set mw_enable_auto_cel $auto_cel_mode -#@ return 0 -#@ } -#@ -#@ # Restore auto_cel mode -#@ set mw_enable_auto_cel $auto_cel_mode -#@ -#@ # Now create auto or real CEL depending on what the original CEL was. -#@ if {$auto_cel == "1"} { -#@ # Force creation of auto-CEL, since commands other than read_def/pdef -#@ # do not decouple CEL from DC. -#@ -#@ set mw_force_auto_cel TRUE -#@ set cmd [format {save_mw_cel -auto}] -#@ } else { -#@ if [get_top_cel_mwid] { -#@ set cmd [format {save_mw_cel -create}] -#@ echo "Information: Command not supported by incr. update or write-thru." -#@ echo " Creating new CEL from scratch, old CEL will be closed." -#@ } -#@ } -#@ -#@ # Create the Auto CEL or normal CEL from scratch. -#@ if {![uplevel #0 $cmd]} { -#@ set mw_create_cel_force $incr_mode -#@ set mw_force_auto_cel FALSE -#@ return 0 -#@ } -#@ -#@ set mw_create_cel_force $incr_mode -#@ set mw_force_auto_cel FALSE -#@ return 1 -#@ } -#@ -#@ define_proc_attributes execute_command_and_create_cel_from_scratch -hidden -hide_body -#@ -#@ ############################################################################## -#@ # PROCEDURE: read_def -#@ # ABSTRACT: Wrapper around read_def to handle incremental update properly -#@ # if MW based read_def is used, bypass the wrapper -#@ # enable_milkyway_def_reader_writer must be TRUE and use_pdb_lib_format must -#@ # be false for MW read_Def to be run, use wrapper if either condition fails -#@ ############################################################################## -#@ rename -force dc_read_def org_read_def -#@ icc_hide_cmd org_read_def -#@ proc dc_read_def args { -#@ parse_proc_arguments -args $args ra -#@ -#@ return [eval execute_command_and_create_cel_from_scratch "org_read_def" $args] -#@ } -#@ -#@ define_proc_attributes dc_read_def -hide_body -info " Read a def file " -define_args {{-design "name of design for which clusters are to be read" "" string {optional}} {-quiet "do not print out any warnings" "" boolean {optional}} {-verbose "print out more warnings" "" boolean {optional}} {-allow_physical_cells "allow physical cells" "" boolean {optional}} {-allow_physical_ports "allow physical ports" "" boolean {optional}} {-allow_physical_nets "allow physical nets" "" boolean {optional}} {-skip_signal_nets "skip signal nets" "" boolean {optional}} {-incremental "incremental" "" boolean {optional}} {-enforce_scaling "enforce_scaling" "" boolean {optional}} {-move_bounds "move bounds" "" boolean {optional}} {"" "input def file names" "input_def_file_name" string {required}}} -#@ -#@ -#@ ############################################################################## -#@ # PROCEDURE: group -#@ # ABSTRACT: Wrapper around group to handle incremental update properly -#@ ############################################################################## -#@ rename -force group org_group -#@ icc_hide_cmd org_group -#@ proc group args { -#@ parse_proc_arguments -args $args ra -#@ return [eval execute_command_and_create_cel_from_scratch "org_group" $args] -#@ } -#@ -#@ define_proc_attributes group -hide_body -info " create new hierarchy" -define_args {{-except "cells not to be included in the group" "exclude_list" list {optional}} -#@ {-design_name "name of design created for new hierarchy" "design_name" string {optional}} -#@ {-cell_name "name of cell created for new hierarchy" "cell_name" string {optional}} -#@ {-logic "group any combinational elements" "" boolean {optional}} -#@ {-pla "group any PLA elements" "" boolean {optional}} -#@ {-fsm "group all elements part of a finite state machine" "" boolean {optional}} -#@ {-hdl_block "name of hdl_block to group" "" string {optional}} -#@ {-hdl_bussed "group all bussed gates under this block" "" boolean {optional}} -#@ {-hdl_all_blocks "group all hdl blocks under this block" "" boolean {optional}} -#@ {-soft "set the group_name attribute" "" boolean {optional}} -#@ {"" "cells to be included in the group" "cell_list" list {optional}}} -#@ -#@ ############################################################################## -#@ # PROCEDURE: copy_design -#@ # ABSTRACT: Wrapper around copy_design to handle incremental update properly -#@ ############################################################################## -#@ rename -force copy_design org_copy_design -#@ icc_hide_cmd org_copy_design -#@ proc copy_design args { -#@ parse_proc_arguments -args $args ra -#@ return [eval execute_command_and_create_cel_from_scratch "org_copy_design" $args] -#@ } -#@ -#@ define_proc_attributes copy_design -hide_body -info " copy_design" -define_args {{"" "List of designs to be copied" "design_list" list {required}} -#@ {"" "Name of new design or target file" "target_name" string {required}}} -#@ -#@ ############################################################################## -#@ # PROCEDURE: create_design -#@ # ABSTRACT: Wrapper around create_design to handle incremental update properly -#@ ############################################################################## -#@ rename -force create_design org_create_design -#@ icc_hide_cmd org_create_design -#@ proc create_design args { -#@ parse_proc_arguments -args $args ra -#@ return [eval execute_command_and_create_cel_from_scratch "org_create_design" $args] -#@ } -#@ -#@ define_proc_attributes create_design -hide_body -info " Creates a design in dc_shell memory" -define_args {{"" "name of the design to create" "" string {required}} -#@ {"" "name of file for design; optional" "" string {optional}}} -#@ -#@ ############################################################################## -#@ # PROCEDURE: reset_design -#@ # ABSTRACT: Wrapper around reset_design to handle incremental update properly -#@ ############################################################################## -#@ #rename -force reset_design org_reset_design -#@ #icc_hide_cmd org_reset_design -#@ #proc reset_design args { -#@ # parse_proc_arguments -args $args ra -#@ # return [eval execute_command_and_create_cel_from_scratch "org_reset_design" $args] -#@ #} -#@ -#@ ############################################################################## -#@ # PROCEDURE: rename_design -#@ # ABSTRACT: Wrapper around rename_design to handle incremental update properly -#@ ############################################################################## -#@ rename -force rename_design org_rename_design -#@ icc_hide_cmd org_rename_design -#@ proc rename_design args { -#@ parse_proc_arguments -args $args ra -#@ return [eval execute_command_and_create_cel_from_scratch "org_rename_design" $args] -#@ } -#@ -#@ define_proc_attributes rename_design -hide_body -info " rename_design" -define_args {{"" "List of designs to be renamed" "design_list" list {required}} -#@ {"" "Name of new design or target file" "target_name" string {required}}} -#@ -#@ } -#@ -#@ ############################################################################## -#@ # If we are in icc_shell (i.e. Galileo) then -#@ # load the procedures to switch between DC and Milkyway collections. -#@ # Set the default to MW collection unless otherwise specified. -#@ ############################################################################## -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ # load the procedures that switch between DC and MW collections -#@ source $synopsys_root/auxx/syn/collection_procs.tcl -#@ -#@ set CS mw -#@ -#@ # see if the user wants DC -#@ if {! [catch {getenv USE_DC_COLLECTIONS_ONLY}] && -#@ [getenv USE_DC_COLLECTIONS_ONLY] } { -#@ set CS dc -#@ } -#@ -#@ # set the collection source now -#@ redirect /dev/null { -#@ if {[catch {set_collection_mode -handle $CS}]} { -#@ catch {set_collection_option -handle $CS} -#@ } -#@ } -#@ -#@ unset CS -#@ } -#@ -#@ ############################################################################## -#@ # procedure for route command -#@ # echo the command to a temp tcl file for seperate process to pick up -#@ ############################################################################## -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ rename -force route org_route -#@ icc_hide_cmd org_route -#@ proc route args { -#@ set route_cmd_file_name ".route_cmd.tcl" -#@ set route_cmd_temp_file_name ".route_cmd.tcl.temp" -#@ set fp [open $route_cmd_file_name "w"] -#@ set route_cmd [concat "sep_proc_route " $args " -child"] -#@ puts $fp $route_cmd -#@ close $fp -#@ -#@ uplevel #0 rename -force route route_temp_proc -#@ uplevel #0 rename -force org_route route -#@ set status [ uplevel #0 route $args ] -#@ uplevel #0 rename -force route org_route -#@ uplevel #0 rename -force route_temp_proc route -#@ -#@ if { [info exist status ] == 1 } { -#@ return $status -#@ } -#@ return -#@ } -#@ } -#@ -#@ ############################################################################## -#@ # Tcl Command: set_ignore_cell -#@ # Description: Load the command only in IC Compiler (icc_shell) -#@ ############################################################################## -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ source $synopsys_root/auxx/syn/psyn/ideal_cell.tcl.e -#@ } -#@ -#@ ############################################################################## -#@ # Tcl Command: check_physical_design -#@ # Description: Load the command only in IC Compiler (icc_shell) -#@ ############################################################################## -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ # Load the compiled Tcl byte-code: -#@ # 9000784997: Do not log to command.log when sourcing .tbc files -#@ set prev_sh_source_logging [get_app_var sh_source_logging] -#@ set_app_var sh_source_logging 0 -#@ source $synopsys_root/auxx/syn/psyn/check_physical_design_core.tbc -#@ source $synopsys_root/auxx/syn/psyn/check_physical_design_utils.tbc -#@ source $synopsys_root/auxx/syn/psyn/check_physical_design_flows.tbc -#@ source $synopsys_root/auxx/syn/psyn/check_physical_design_reports.tbc -#@ source $synopsys_root/auxx/syn/psyn/check_physical_design_ui.tbc -#@ source $synopsys_root/auxx/syn/psyn/create_qor_snapshot.tbc -#@ source $synopsys_root/auxx/syn/psyn/report_qor_snapshot.tbc -#@ source $synopsys_root/auxx/syn/psyn/msgParser.tbc -#@ source $synopsys_root/auxx/syn/psyn/displacement_gui.tbc -#@ source $synopsys_root/auxx/syn/psyn/categorize_timing_gui.tbc -#@ set_app_var sh_source_logging $prev_sh_source_logging -#@ -#@ source $synopsys_root/auxx/syn/psyn/mcmm_utils.tcl.e -#@ source $synopsys_root/auxx/syn/psyn/propagate_all_clocks.tcl.e -#@ } -#@ -#@ if { [string match -nocase {*dc_shell*} $synopsys_program_name] && [shell_is_in_topographical_mode] } { -#@ # 9000784997: Do not log to command.log when sourcing .tbc files -#@ set prev_sh_source_logging [get_app_var sh_source_logging] -#@ set_app_var sh_source_logging 0 -#@ source $synopsys_root/auxx/syn/psyn/create_qor_snapshot.tbc -#@ source $synopsys_root/auxx/syn/psyn/report_qor_snapshot.tbc -#@ set_app_var sh_source_logging $prev_sh_source_logging -#@ -#@ source $synopsys_root/auxx/syn/psyn/mcmm_utils.tcl.e -#@ } -#@ -#@ if { $synopsys_program_name == "de_shell" } { -#@ # 9000784997: Do not log to command.log when sourcing .tbc files -#@ set prev_sh_source_logging [get_app_var sh_source_logging] -#@ set_app_var sh_source_logging 0 -#@ source $synopsys_root/auxx/syn/psyn/create_qor_snapshot.tbc -#@ source $synopsys_root/auxx/syn/psyn/report_qor_snapshot.tbc -#@ set_app_var sh_source_logging $prev_sh_source_logging -#@ -#@ source $synopsys_root/auxx/syn/psyn/mcmm_utils.tcl.e -#@ } -#@ -#@ ############################################################################## -#@ # ICC setup and hiding commands/procs etc -#@ ############################################################################## -#@ -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ #set save_mw_cel_lib_setup TRUE -#@ #set auto_restore_mw_cel_lib_setup FALSE -#@ -#@ alias create_wiring_keepout create_wiring_keepouts -#@ alias get_wiring_keepout get_wiring_keepouts -#@ alias get_placement_keepout get_placement_keepouts -#@ alias create_placement_keepout create_placement_keepouts -#@ -#@ icc_hide_cmd execute_command_and_create_cel_from_scratch -#@ icc_hide_cmd dc_read_def -#@ icc_hide_cmd read_edif -#@ icc_hide_cmd read_sverilog -#@ icc_hide_cmd read_vhdl -#@ icc_hide_cmd set_collection_mode -#@ icc_hide_cmd return_dc_collection -#@ icc_hide_cmd return_mw_collection -#@ set mw_use_pdb_lib_format true -#@ } -#@ -#@ -#@ ############################################################################## -#@ # Tcl Command: get_dont_touch_nets -#@ # Description: wrapper of "get_nets -filter dont_touch_reason==mv" -#@ ############################################################################## -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ -#@ proc get_dont_touch_nets args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {get_nets}] -#@ -#@ if {[info exists ra()]} { -#@ set cmd [format {%s {%s}} $cmd $ra()] -#@ } -#@ if {[info exists ra(-type)]} { -#@ set cmd [format {%s -filter dont_touch_reasons=~*%s*} $cmd $ra(-type)] -#@ } -#@ if {[info exists ra(-hierarchical)]} { -#@ set cmd [format {%s -hierarchical} $cmd] -#@ } -#@ if {[info exists ra(-quiet)]} { -#@ set cmd [format {%s -quiet} $cmd] -#@ } -#@ if {[info exists ra(-regexp)]} { -#@ set cmd [format {%s -regexp} $cmd] -#@ } -#@ if {[info exists ra(-nocase)]} { -#@ set cmd [format {%s -nocase} $cmd] -#@ } -#@ if {[info exists ra(-exact)]} { -#@ set cmd [format {%s -exact} $cmd] -#@ } -#@ -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes get_dont_touch_nets -info " Get dont_touch nets " -permanent -define_args { {"" "Match net names against patterns" "patterns" list {optional}} {-type "Match net dont_touch reasons" "reasons" list {required}} {-hierarchical "Search level-by-level in current instance" "" boolean {optional}} {-quiet "Suppress all messages" "" boolean {optional hidden}} {-regexp "Patterns are full regular expressions" "" boolean {optional hidden}} {-nocase "With -regexp, matches are case-insensitive" "" boolean {optional hidden}} {-exact "Wildcards are considered as plain characters" "" boolean {optional hidden}} } -#@ -#@ alias get_dont_touch_net get_dont_touch_nets -#@ } -#@ -#@ -#@ ############################################################################## -#@ # return the first {index value} pair in Tcl array ary. -#@ ############################################################################## -#@ proc _snps_array_peek { level ary } { -#@ upvar #$level $ary loc_ary -#@ set ret [list] -#@ set token [array startsearch loc_ary] -#@ while {[array anymore loc_ary $token]} { -#@ set k [array nextelement loc_ary $token] -#@ set v $loc_ary($k) -#@ set ret [list $k $v] -#@ break -#@ } -#@ array donesearch loc_ary $token -#@ return $ret; -#@ } -#@ define_proc_attributes _snps_array_peek -hidden -#@ # -- End source /tools/synopsys/synthesis/j201409sp3/auxx/syn/.dc_procs.tcl - -#@ -#@ # Temporary fix for the LMC_HOME variable- set it to an empty string -#@ -#@ if { [catch {getenv LMC_HOME } __err ] != 0 } { -#@ setenv LMC_HOME "" -#@ } -#@ -#@ -#@ # -#@ # -#@ # Site-Specific Variables -#@ # -#@ # These are the variables that are most commonly changed at a -#@ # specific site, either upon installation of the Synopsys software, -#@ # or by specific engineers in their local .synopsys files. -#@ # -#@ # -#@ -#@ # from the System Variable Group -#@ set link_library { * your_library.db } -#@ -#@ set search_path [list . ${synopsys_root}/libraries/syn ${synopsys_root}/minpower/syn ${synopsys_root}/dw/syn_ver ${synopsys_root}/dw/sim_ver] -#@ set target_library your_library.db -#@ set synthetic_library "" -#@ set command_log_file "./command.log" -#@ set designer "" -#@ set company "" -#@ set find_converts_name_lists "false" -#@ -#@ set symbol_library your_library.sdb -#@ -#@ # Turn on Formality SVF recording -#@ if { $synopsys_program_name == "dc_shell" || $synopsys_program_name == "de_shell" || $synopsys_program_name == "design_vision" } { -#@ set_svf -default default.svf -#@ } -#@ -#@ # from the Schematic Variable Group -#@ -#@ # from the Plot Variable Group -#@ # [froi] 07/06/2012: Remove old Design Analyzer plot_command variable -#@ #if { $sh_arch == "hp700" } { -#@ # set plot_command "lp -d" -#@ #} else { -#@ # set plot_command "lpr -Plw" -#@ #} -#@ -#@ set view_command_log_file "./view_command.log" -#@ -#@ # from the View Variable group -#@ if { $sh_arch == "hp700" } { -#@ set text_print_command "lp -d" -#@ } else { -#@ set text_print_command "lpr -Plw" -#@ } -#@ # -#@ # System Variable Group: -#@ # -#@ # These variables are system-wide variables. -#@ # -#@ set arch_init_path ${synopsys_root}/${sh_arch}/motif/syn/uid -#@ set auto_link_disable "false" -#@ set auto_link_options "-all" -#@ set uniquify_naming_style "%s_%d" -#@ set verbose_messages "true" -#@ set echo_include_commands "true" -#@ set svf_file_records_change_names_changes "true" -#@ set change_names_update_inst_tree "true" -#@ set change_names_dont_change_bus_members false -#@ set default_name_rules "" -#@ #set tdrc_enable_clock_table_creation "true" -#@ -#@ # -#@ # Compile Variable Group: -#@ # -#@ # These variables affect the designs created by the COMPILE command. -#@ # -#@ set compile_assume_fully_decoded_three_state_busses "false" -#@ set compile_no_new_cells_at_top_level "false" -#@ set compile_dont_touch_annotated_cell_during_inplace_opt "false" -#@ set compile_update_annotated_delays_during_inplace_opt "true" -#@ set compile_instance_name_prefix "U" -#@ set compile_instance_name_suffix "" -#@ set compile_negative_logic_methodology "false" -#@ set compile_disable_hierarchical_inverter_opt "false" -#@ set compile_use_low_timing_effort "false" -#@ set compile_fix_cell_degradation "false" -#@ set compile_preserve_subdesign_interfaces "false" -#@ set compile_enable_constant_propagation_with_no_boundary_opt "true" -#@ set port_complement_naming_style "%s_BAR" -#@ set compile_implementation_selection "true" -#@ set compile_delete_unloaded_sequential_cells "true" -#@ set reoptimize_design_changed_list_file_name "" -#@ set compile_checkpoint_phases "false" -#@ set compile_cpu_limit 0.0 -#@ set compile_log_format " %elap_time %area %wns %tns %drc %endpoint"; -#@ set compile_top_all_paths "false" -#@ set compile_top_acs_partition "false" -#@ set default_port_connection_class "universal" -#@ set compile_hold_reduce_cell_count "false" -#@ set compile_retime_license_behavior "wait" -#@ set dont_touch_nets_with_size_only_cells "false" -#@ if { $synopsys_program_name == "dc_shell" && [shell_is_in_topographical_mode] } { -#@ set dct_prioritize_area_correlation "false" -#@ set compile_error_on_missing_physical_cells "false" -#@ } -#@ -#@ set ldd_return_val 0 -#@ if { [string compare $dc_shell_mode "default"] == 0 } { -#@ set ldd_script ${synopsys_root}/auxx/syn/scripts/list_duplicate_designs.dcsh -#@ alias list_duplicate_designs "include -quiet ldd_script; dc_shell_status = ldd_return_val " -#@ -#@ } -#@ if { [string compare $dc_shell_mode "tcl"] == 0 } { -#@ if {$synopsys_program_name != "dc_sms_shell"} { -#@ source ${synopsys_root}/auxx/syn/scripts/list_duplicate_designs.tcl -#@ # 9000784997: Do not log to command.log when sourcing .tbc files -#@ set prev_sh_source_logging [get_app_var sh_source_logging] -#@ set_app_var sh_source_logging 0 -#@ source ${synopsys_root}/auxx/syn/scripts/analyze_datapath.tbc -#@ set_app_var sh_source_logging $prev_sh_source_logging -#@ } -#@ } -#@ # -- Starting source /tools/synopsys/synthesis/j201409sp3/auxx/syn/scripts/list_duplicate_designs.tcl - -#@ ####################################################################### -#@ # -#@ # list_duplicate_designs.tcl 21 Sept. 2006 -#@ # -#@ # List designs in dc_shell memory that have the same design name -#@ # -#@ # COPYRIGHT (C) 2006, SYNOPSYS INC., ALL RIGHTS RESERVED. -#@ # -#@ ####################################################################### -#@ -#@ proc list_duplicate_designs { args } { -#@ parse_proc_arguments -args $args ra -#@ -#@ # Get the list of duplicate designs -#@ set the_pid [pid] -#@ set rand_1 [expr int(rand() * 100000)] -#@ set temp_file_1 [format "/tmp/ldd_design_%s_%s" $the_pid $rand_1] -#@ -#@ redirect $temp_file_1 { foreach_in_collection ldd_design [find design "*"] { -#@ echo [get_object_name $ldd_design] -#@ } } -#@ -#@ set rand_2 [expr int(rand() * 100000)] -#@ set temp_file_2 [format "/tmp/ldd_design_%s_%s" $the_pid $rand_2] -#@ -#@ sh sort $temp_file_1 | uniq -d | tee $temp_file_2 -#@ file delete $temp_file_1 -#@ -#@ # Report duplicates -#@ if { ! [file size $temp_file_2] } { -#@ echo [concat {No duplicate designs found.}] -#@ set ldd_return_val 0 -#@ } else { -#@ set rand_3 [expr int(rand() * 100000)] -#@ set temp_file_3 [format "/tmp/ldd_design_%s_%s" $the_pid $rand_3] -#@ echo {Warning: Multiple designs in memory with the same design name.} -#@ echo {} -#@ echo { Design File Path} -#@ echo { ------ ---- ----} -#@ list_designs -table > $temp_file_3 -#@ echo [sh fgrep -f $temp_file_2 $temp_file_3 | sort | grep -v 'Design.*File.*Path'] -#@ file delete $temp_file_3 -#@ set ldd_return_val 1 -#@ } -#@ -#@ # Clean up -#@ file delete $temp_file_2 -#@ -#@ set list_duplicate_designs1 $ldd_return_val -#@ } -#@ -#@ define_proc_attributes list_duplicate_designs -info " List designs of same names" -permanent -define_args { -#@ } -#@ # -- End source /tools/synopsys/synthesis/j201409sp3/auxx/syn/scripts/list_duplicate_designs.tcl - -#@ -#@ -#@ set compile_log_format " %elap_time %area %wns %tns %drc %endpoint"; -#@ -#@ set compile_top_all_paths "false" -#@ alias compile_inplace_changed_list_file_name reoptimize_design_changed_list_file_name -#@ -#@ # -#@ # These variables affects compile, report_timing and report_constraints -#@ # commands. -#@ # -#@ set enable_recovery_removal_arcs "false" -#@ set timing_report_attributes {dont_touch dont_use map_only size_only ideal_net infeasible_paths} -#@ -#@ # -#@ # Multibit Variable Group: -#@ # -#@ # These variables affect the multibit mapping functionality -#@ # -#@ -#@ set bus_multiple_separator_style "," -#@ -#@ # -#@ # ILM Variable Group: -#@ # -#@ # These variables affect Interface Logic Model functionality -#@ # -#@ -#@ set ilm_ignore_percentage 25 -#@ -#@ # -#@ # Estimator Variable Group: -#@ # -#@ # These variables affect the designs created by the ESTIMATE command. -#@ # -#@ set estimate_resource_preference "fast" -#@ alias est_resource_preference estimate_resource_preference -#@ set lbo_lfo_enable_at_pin_count 3 -#@ set lbo_cells_in_regions "false" -#@ -#@ # Synthetic Library Group: -#@ # -#@ # These variable affect synthetic library processing. -#@ # -#@ set cache_dir_chmod_octal "777" -#@ set cache_file_chmod_octal "666" -#@ set cache_read "~" -#@ set cache_read_info "false" -#@ set cache_write "~" -#@ set cache_write_info "false" -#@ set synlib_dont_get_license {} -#@ set synlib_library_list {DW01 DW02 DW03 DW04 DW05 DW06 DW07} -#@ set synlib_wait_for_design_license {} -#@ set synlib_dwhomeip {} -#@ -#@ # -#@ # Insert_DFT Variable Group: -#@ # -#@ #set test_default_client_order [list] -#@ set insert_dft_clean_up "true" -#@ set insert_test_design_naming_style "%s_test_%d" -#@ # /*insert_test_scan_chain_only_one_clock = "false" -#@ # Replace by command line option (star 17215) -- Denis Martin 28-Jan-93*/ -#@ set test_clock_port_naming_style "test_c%s" -#@ set test_scan_clock_a_port_naming_style "test_sca%s" -#@ set test_scan_clock_b_port_naming_style "test_scb%s" -#@ set test_scan_clock_port_naming_style "test_sc%s" -#@ set test_scan_enable_inverted_port_naming_style "test_sei%s" -#@ set test_scan_enable_port_naming_style "test_se%s" -#@ set test_scan_in_port_naming_style "test_si%s%s" -#@ set test_scan_out_port_naming_style "test_so%s%s" -#@ set test_non_scan_clock_port_naming_style "test_nsc_%s" -#@ set test_default_min_fault_coverage 95 -#@ set test_dedicated_subdesign_scan_outs "false" -#@ set test_disable_find_best_scan_out "false" -#@ set test_dont_fix_constraint_violations "false" -#@ set test_isolate_hier_scan_out 0 -#@ set test_mode_port_naming_style "test_mode%s" -#@ set test_mode_port_inverted_naming_style "test_mode_i%s" -#@ set compile_dont_use_dedicated_scanout 1 -#@ set test_mux_constant_si "false" -#@ -#@ # -#@ # Analyze_Scan Variable Group: -#@ # -#@ # These variables affect the designs created by the PREVIEW_SCAN command. -#@ # -#@ set test_preview_scan_shows_cell_types "false" -#@ set test_scan_link_so_lockup_key "l" -#@ set test_scan_link_wire_key "w" -#@ set test_scan_segment_key "s" -#@ set test_scan_true_key "t" -#@ -#@ # -#@ # bsd Variable Group: -#@ -#@ # These variables affect the report generated by the check_bsd command -#@ # and the BSDLout generated by the write_bsdl command. -#@ # -#@ set test_user_test_data_register_naming_style "UTDR%d" -#@ -#@ set test_user_defined_instruction_naming_style "USER%d" -#@ -#@ set test_bsdl_default_suffix_name "bsdl" -#@ -#@ set test_bsdl_max_line_length 80 -#@ -#@ set test_cc_ir_masked_bits 0 -#@ -#@ set test_cc_ir_value_of_masked_bits 0 -#@ -#@ set test_bsd_allow_tolerable_violations "false" -#@ set test_bsd_optimize_control_cell "false" -#@ set test_bsd_control_cell_drive_limit 0 -#@ set test_bsd_manufacturer_id 0 -#@ set test_bsd_part_number 0 -#@ set test_bsd_version_number 0 -#@ set bsd_max_in_switching_limit 60000 -#@ set bsd_max_out_switching_limit 60000 -#@ -#@ # -#@ # TestManager Variable Group: -#@ # -#@ # These variables affect the TestManager methodology. -#@ # -#@ set multi_pass_test_generation "false" -#@ -#@ # -#@ # TestSim Variable Group: -#@ # -#@ # These variables affect the TestSim behavior. -#@ # -#@ # set testsim_print_stats_file "true" -#@ -#@ # Test DRC Variable Group: -#@ # -#@ # These variables affect the check_test command. -#@ # -#@ set test_capture_clock_skew "small_skew" -#@ set test_allow_clock_reconvergence "true" -#@ set test_check_port_changes_in_capture "true" -#@ set test_infer_slave_clock_pulse_after_capture "infer" -#@ -#@ # -#@ # Test Variable Group: -#@ # -#@ # These variables affect the rtldrc, check_test, write_test_protocol -#@ # and write_test command. -#@ # -#@ set test_default_delay 0.0 -#@ set test_default_bidir_delay 0.0 -#@ set test_default_strobe 40.0 -#@ set test_default_strobe_width 0.0 -#@ set test_default_period 100.0 -#@ set test_stil_max_line_length 72 -#@ -#@ #added for B-2008.09-place_opt-004 to disable this option in ICC -#@ -#@ if { $synopsys_program_name != "icc_shell"} { -#@ set test_write_four_cycle_stil_protocol "false" -#@ set test_protocol_add_cycle "true" -#@ set test_stil_multiclock_capture_procedures "false" -#@ set write_test_new_translation_engine "false" -#@ set test_default_scan_style "multiplexed_flip_flop" -#@ set test_jump_over_bufs_invs "true" -#@ set test_point_keep_hierarchy "false" -#@ set test_mux_constant_so "false" -#@ set test_use_test_models "false" -#@ set test_stil_netlist_format "db" -#@ group_variable test "test_protocol_add_cycle" -#@ group_variable test "test_write_four_cycle_stil_protocol" -#@ group_variable test "test_stil_multiclock_capture_procedures" -#@ group_variable test "test_default_scan_style" -#@ group_variable preview_scan "test_jump_over_bufs_invs" -#@ group_variable insert_dft "test_point_keep_hierarchy" -#@ group_variable insert_dft "test_mux_constant_so" -#@ group_variable test "test_stil_netlist_format" -#@ } -#@ set test_rtldrc_latch_check_style "default" -#@ set test_enable_capture_checks "true" -#@ set ctldb_use_old_prot_flow "false" -#@ set test_bsd_default_delay 0.0 -#@ set test_bsd_default_bidir_delay 0.0 -#@ set test_bsd_default_strobe 95.0 -#@ set test_bsd_default_strobe_width 0.0 -#@ -#@ # -#@ # Test Variable Group: -#@ # -#@ # These variables affects the set_scan_state command. -#@ # -#@ -#@ set compile_seqmap_identify_shift_registers_with_synchronous_logic_ascii false -#@ -#@ # -#@ # Write_Test Variable Group: -#@ # -#@ # These variables affect output of the WRITE_TEST command. -#@ # -#@ set write_test_input_dont_care_value "X" -#@ set write_test_vector_file_naming_style "%s_%d.%s" -#@ set write_test_scan_check_file_naming_style "%s_schk.%s" -#@ set write_test_pattern_set_naming_style "TC_Syn_%d" -#@ set write_test_max_cycles 0 -#@ set write_test_max_scan_patterns 0 -#@ # /*retain "tssi_ascii" (equivalent to "tds") for backward compatability */ -#@ set write_test_formats {synopsys tssi_ascii tds verilog vhdl wgl} -#@ set write_test_include_scan_cell_info "true" -#@ set write_test_round_timing_values "true" -#@ -#@ -#@ # -#@ # Schematic and EDIF and Hdl Variable Groups: -#@ # -#@ # These variables affect the schematics created by the -#@ # create_schematic command, define the behavior of the -#@ # DC system EDIF interface, and are for controlling hdl -#@ # reading. -#@ # -#@ set bus_dimension_separator_style {][} -#@ set bus_naming_style {%s[%d]} -#@ -#@ -#@ # -#@ # Schematic and EDIF Variable Groups: -#@ # -#@ # These variables affect the schematics created by the -#@ # create_schematic command and define the behavior of -#@ # the DC system EDIF interface. -#@ # -#@ set bus_range_separator_style ":" -#@ -#@ -#@ # -#@ # EDIF and Io Variable Groups: -#@ # -#@ # These variables define the behavior of the DC system EDIF interface and -#@ # define the behavior of the DC system interfaces, i.e. LSI, Mentor, TDL, SGE,# etc. -#@ -#@ set bus_inference_descending_sort "true" -#@ set bus_inference_style "" -#@ set write_name_nets_same_as_ports "false" -#@ # -#@ # Schematic Variable Group: -#@ # -#@ # These variables affect the schematics created by the -#@ # create_schematic command. -#@ # -#@ set font_library "1_25.font" -#@ set generic_symbol_library "generic.sdb" -#@ -#@ # -#@ # Io Variable Group: -#@ # -#@ # These variables define the behavior of the DC system -#@ # interfaces, i.e. LSI, Mentor, TDL, SGE, etc. -#@ # -#@ #set db2sge_output_directory "" -#@ #set db2sge_scale "2" -#@ #set db2sge_overwrite "true" -#@ #set db2sge_display_symbol_names "false" -#@ -#@ -#@ #set db2sge_display_pin_names "false" -#@ #set db2sge_display_instance_names "false" -#@ #set db2sge_use_bustaps "false" -#@ #set db2sge_use_compound_names "true" -#@ #set db2sge_bit_type "std_logic" -#@ #set db2sge_bit_vector_type "std_logic_vector" -#@ #set db2sge_one_name "'1'" -#@ #set db2sge_zero_name "'0'" -#@ #set db2sge_unknown_name "'X'" -#@ #set db2sge_target_xp "false" -#@ #set db2sge_tcf_package_file "synopsys_tcf.vhd" -#@ #set db2sge_use_lib_section "" -#@ #set db2sge_script "" -#@ #set db2sge_command "" -#@ -#@ # set equationout_and_sign "*" -#@ # set equationout_or_sign "+" -#@ # set equationout_postfix_negation "true" -#@ -#@ # # [wjchen] 2006/08/14: The following variables are obsoleted for DC simpilification. -#@ #set lsiin_net_name_prefix "NET_" -#@ #set lsiout_inverter_cell "" -#@ #set lsiout_upcase "true" -#@ -#@ #set mentor_bidirect_value "INOUT" -#@ #set mentor_do_path "" -#@ #set mentor_input_output_property_name "PINTYPE" -#@ #set mentor_input_value "IN" -#@ #set mentor_logic_one_value "1SF" -#@ #set mentor_logic_zero_one_property_name "INIT" -#@ #set mentor_logic_zero_value "0SF" -#@ #set mentor_output_value "OUT" -#@ #set mentor_primitive_property_name "PRIMITIVE" -#@ #set mentor_primitive_property_value "MODULE" -#@ #set mentor_reference_property_name "COMP" -#@ #set mentor_search_path "" -#@ #set mentor_write_symbols "true" -#@ -#@ ## [wjchen] 0606_simp -#@ #set pla_read_create_flip_flop "false" -#@ #set tdlout_upcase "true" -#@ -#@ # # [wjchen] 2006/08/14: The following4 variables are obsoleted for DC simpilification. -#@ # set xnfout_constraints_per_endpoint "50" -#@ # set xnfout_default_time_constraints true -#@ # set xnfout_clock_attribute_style "CLK_ONLY" -#@ # set xnfout_library_version "" -#@ -#@ # # [wjchen] 2006/08/11: The following 8 variables are obsoleted for DC simpilification. -#@ # set xnfin_family "4000" -#@ # set xnfin_ignore_pins "GTS GSR GR" -#@ # set xnfin_dff_reset_pin_name "RD" -#@ # set xnfin_dff_set_pin_name "SD" -#@ # set xnfin_dff_clock_enable_pin_name "CE" -#@ # set xnfin_dff_data_pin_name "D" -#@ # set xnfin_dff_clock_pin_name "C" -#@ # set xnfin_dff_q_pin_name "Q" -#@ # -#@ -#@ # -#@ # EDIF Variable Group: -#@ # -#@ # These variables define the behavior of the DC system -#@ # EDIF interface. -#@ # -#@ -#@ ##[wjchen] 2006/08/24 -#@ -#@ # set bus_extraction_style {%s[%d:%d]} -#@ -#@ ##[wjchen] 2006/08/24 -#@ #set edifin_autoconnect_offpageconnectors "false" -#@ #set edifin_autoconnect_ports "false" -#@ #set edifin_dc_script_flag "" -#@ #set edifin_delete_empty_cells "true" -#@ #set edifin_delete_ripper_cells "true" -#@ #set edifin_ground_net_name "" -#@ #set edifin_ground_net_property_name "" -#@ #set edifin_ground_net_property_value "" -#@ #set edifin_ground_port_name "" -#@ #set edifin_instance_property_name "" -#@ #set edifin_portinstance_disabled_property_name "" -#@ #set edifin_portinstance_disabled_property_value "" -#@ #set edifin_portinstance_property_name "" -#@ #set edifin_power_net_name "" -#@ #set edifin_power_net_property_name "" -#@ #set edifin_power_net_property_value "" -#@ #set edifin_power_port_name "" -#@ #set edifin_use_identifier_in_rename "false" -#@ #set edifin_view_identifier_property_name "" -#@ #set edifin_lib_logic_1_symbol "" -#@ #set edifin_lib_logic_0_symbol "" -#@ #set edifin_lib_in_port_symbol "" -#@ #set edifin_lib_out_port_symbol "" -#@ #set edifin_lib_inout_port_symbol "" -#@ #set edifin_lib_in_osc_symbol "" -#@ #set edifin_lib_out_osc_symbol "" -#@ #set edifin_lib_inout_osc_symbol "" -#@ #set edifin_lib_mentor_netcon_symbol "" -#@ #set edifin_lib_ripper_bits_property "" -#@ #set edifin_lib_ripper_bus_end "" -#@ #set edifin_lib_ripper_cell_name "" -#@ #set edifin_lib_ripper_view_name "" -#@ #set edifin_lib_route_grid 1024 -#@ #set edifin_lib_templates {} -#@ #set edifout_dc_script_flag "" -#@ #set edifout_design_name "Synopsys_edif" -#@ #set edifout_designs_library_name "DESIGNS" -#@ #set edifout_display_instance_names "false" -#@ #set edifout_display_net_names "false" -#@ #set edifout_external "true" -#@ #set edifout_external_graphic_view_name "Graphic_representation" -#@ #set edifout_external_netlist_view_name "Netlist_representation" -#@ #set edifout_external_schematic_view_name "Schematic_representation" -#@ #set edifout_ground_name "logic_0" -#@ #set edifout_ground_net_name "" -#@ #set edifout_ground_net_property_name "" -#@ #set edifout_ground_net_property_value "" -#@ #set edifout_ground_pin_name "logic_0_pin" -#@ #set edifout_ground_port_name "GND" -#@ #set edifout_instance_property_name "" -#@ #set edifout_instantiate_ports "false" -#@ #set edifout_library_graphic_view_name "Graphic_representation" -#@ #set edifout_library_netlist_view_name "Netlist_representation" -#@ #set edifout_library_schematic_view_name "Schematic_representation" -#@ #set edifout_merge_libraries "false" -#@ #set edifout_multidimension_arrays "false" -#@ #set edifout_name_oscs_different_from_ports "false" -#@ #set edifout_name_rippers_same_as_wires "false" -#@ #set edifout_netlist_only "false" -#@ #set edifout_no_array "false" -#@ #set edifout_numerical_array_members "false" -#@ #set edifout_pin_direction_in_value "" -#@ #set edifout_pin_direction_inout_value "" -#@ #set edifout_pin_direction_out_value "" -#@ #set edifout_pin_direction_property_name "" -#@ #set edifout_pin_name_property_name "" -#@ #set edifout_portinstance_disabled_property_name "" -#@ #set edifout_portinstance_disabled_property_value "" -#@ #set edifout_portinstance_property_name "" -#@ #set edifout_power_and_ground_representation "cell" -#@ #set edifout_power_name "logic_1" -#@ #set edifout_power_net_name "" -#@ #set edifout_power_net_property_name "" -#@ #set edifout_power_net_property_value "" -#@ #set edifout_power_pin_name "logic_1_pin" -#@ #set edifout_power_port_name "VDD" -#@ #set edifout_skip_port_implementations "false" -#@ #set edifout_target_system "" -#@ #set edifout_top_level_symbol "true" -#@ #set edifout_translate_origin "" -#@ #set edifout_unused_property_value "" -#@ #set edifout_write_attributes "false" -#@ #set edifout_write_constraints "false" -#@ #set edifout_write_properties_list {} -#@ #set read_name_mapping_nowarn_libraries {} -#@ #set write_name_mapping_nowarn_libraries {} -#@ -#@ # -#@ # Hdl and Vhdlio Variable Groups: -#@ # -#@ # These variables are for controlling hdl reading, writing, -#@ # and optimizing. -#@ # -#@ set hdlin_enable_upf_compatible_naming "FALSE" -#@ set hdlin_auto_save_templates "FALSE" -#@ set hdlin_generate_naming_style "%s_%d" -#@ set hdlin_enable_relative_placement "rb" -#@ set hdlin_mux_rp_limit "128x4" -#@ set hdlin_generate_separator_style "_" -#@ set hdlin_ignore_textio_constructs "TRUE" -#@ set hdlin_infer_function_local_latches "FALSE" -#@ set hdlin_keep_signal_name "all_driving" -#@ set hdlin_module_arch_name_splitting "FALSE" -#@ set hdlin_preserve_sequential "none" -#@ set hdlin_presto_net_name_prefix "N" -#@ set hdlin_presto_cell_name_prefix "C" -#@ set hdlin_strict_verilog_reader "FALSE" -#@ set hdlin_prohibit_nontri_multiple_drivers "TRUE" -#@ if { $synopsys_program_name == "de_shell" } { -#@ set hdlin_elab_errors_deep "TRUE" -#@ } else { -#@ set hdlin_elab_errors_deep "FALSE" -#@ } -#@ set hdlin_mux_size_min 2 -#@ set hdlin_subprogram_default_values "FALSE" -#@ set hdlin_field_naming_style "" -#@ set hdlin_upcase_names "FALSE" -#@ set hdlin_sv_union_member_naming "FALSE" -#@ set hdlin_vhdl_std 2008 -#@ set hdlin_vhdl93_concat "TRUE" -#@ set hdlin_vhdl_syntax_extensions "FALSE" -#@ set hdlin_analyze_verbose_mode 0 -#@ set hdlin_report_sequential_pruning "FALSE" -#@ set hdlin_vrlg_std 2005 -#@ set hdlin_sverilog_std 2012 -#@ set hdlin_while_loop_iterations 4096 -#@ set hdlin_reporting_level "basic" -#@ set hdlin_autoread_verilog_extensions ".v" -#@ set hdlin_autoread_sverilog_extensions ".sv .sverilog" -#@ set hdlin_autoread_vhdl_extensions ".vhd .vhdl" -#@ set hdlin_autoread_exclude_extensions "" -#@ -#@ set bus_minus_style "-%d" -#@ set hdlin_latch_always_async_set_reset FALSE -#@ set hdlin_ff_always_sync_set_reset FALSE -#@ set hdlin_ff_always_async_set_reset TRUE -#@ set hdlin_check_input_netlist FALSE -#@ set hdlin_check_no_latch FALSE -#@ set hdlin_mux_for_array_read_sparseness_limit 90 -#@ set hdlin_infer_mux "default" -#@ set hdlin_mux_oversize_ratio 100 -#@ set hdlin_mux_size_limit 32 -#@ set hdlin_mux_size_only 1 -#@ set hdlin_infer_multibit "default_none" -#@ set hdlin_enable_rtldrc_info "false" -#@ set hdlin_interface_port_ABI 3 -#@ set hdlin_shorten_long_module_name "false" -#@ set hdlin_module_name_limit 256 -#@ set hdlin_enable_assertions "FALSE" -#@ set hdlin_enable_configurations "FALSE" -#@ set hdlin_sv_blackbox_modules "" -#@ set hdlin_sv_tokens "FALSE" -#@ set hdlin_sv_packages "enable" -#@ set hdlin_verification_priority "FALSE" -#@ set hdlin_enable_elaborate_ref_linking "FALSE" -#@ set hdlin_enable_hier_naming "FALSE" -#@ set hdlin_vhdl_mixed_language_instantiation "FALSE" -#@ set hdl_preferred_license "" -#@ set hdl_keep_licenses "true" -#@ set hlo_resource_allocation "constraint_driven" -#@ set sdfout_top_instance_name "" -#@ set sdfout_time_scale 1.0 -#@ set sdfout_min_rise_net_delay 0. -#@ set sdfout_min_fall_net_delay 0. -#@ set sdfout_min_rise_cell_delay 0. -#@ set sdfout_min_fall_cell_delay 0. -#@ set sdfout_write_to_output "false" -#@ set sdfout_allow_non_positive_constraints "false" -#@ set sdfin_top_instance_name "" -#@ set sdfin_min_rise_net_delay 0. -#@ set sdfin_min_fall_net_delay 0. -#@ set sdfin_min_rise_cell_delay 0. -#@ set sdfin_min_fall_cell_delay 0. -#@ set sdfin_rise_net_delay_type "maximum" -#@ set sdfin_fall_net_delay_type "maximum" -#@ set sdfin_rise_cell_delay_type "maximum" -#@ set sdfin_fall_cell_delay_type "maximum" -#@ set site_info_file ${synopsys_root}/admin/license/site_info -#@ if { [string compare $dc_shell_mode "tcl"] == 0 } { -#@ alias site_info sh cat $site_info_file -#@ } else { -#@ alias site_info "sh cat site_info_file" -#@ } -#@ set template_naming_style "%s_%p" -#@ set template_parameter_style "%s%d" -#@ set template_separator_style "_" -#@ set verilogout_equation "false" -#@ set verilogout_ignore_case "false" -#@ set verilogout_no_tri "false" -#@ set verilogout_inout_is_in "false" -#@ set verilogout_single_bit "false" -#@ set verilogout_higher_designs_first "FALSE" -#@ # set verilogout_levelize "FALSE" -#@ set verilogout_include_files {} -#@ set verilogout_unconnected_prefix "SYNOPSYS_UNCONNECTED_" -#@ set verilogout_show_unconnected_pins "FALSE" -#@ set verilogout_no_negative_index "FALSE" -#@ #set enable_2003.03_verilog_reader TRUE -#@ # to have a net instead of 1'b0 and 1'b1 in inouts: -#@ set verilogout_indirect_inout_connection "FALSE" -#@ -#@ # set vhdlout_architecture_name "SYN_%a_%u" -#@ set vhdlout_bit_type "std_logic" -#@ # set vhdlout_bit_type_resolved "TRUE" -#@ set vhdlout_bit_vector_type "std_logic_vector" -#@ # set vhdlout_conversion_functions {} -#@ # set vhdlout_dont_write_types "FALSE" -#@ set vhdlout_equations "FALSE" -#@ set vhdlout_one_name "'1'" -#@ set vhdlout_package_naming_style "CONV_PACK_%d" -#@ set vhdlout_preserve_hierarchical_types "VECTOR" -#@ set vhdlout_separate_scan_in "FALSE" -#@ set vhdlout_single_bit "USER" -#@ set vhdlout_target_simulator "" -#@ set vhdlout_three_state_name "'Z'" -#@ set vhdlout_three_state_res_func "" -#@ # set vhdlout_time_scale 1.0 -#@ set vhdlout_top_configuration_arch_name "A" -#@ set vhdlout_top_configuration_entity_name "E" -#@ set vhdlout_top_configuration_name "CFG_TB_E" -#@ set vhdlout_unknown_name "'X'" -#@ set vhdlout_upcase "FALSE" -#@ set vhdlout_use_packages {IEEE.std_logic_1164} -#@ set vhdlout_wired_and_res_func "" -#@ set vhdlout_wired_or_res_func "" -#@ set vhdlout_write_architecture "TRUE" -#@ set vhdlout_write_components "TRUE" -#@ set vhdlout_write_entity "TRUE" -#@ set vhdlout_write_top_configuration "FALSE" -#@ # set vhdlout_synthesis_off "TRUE" -#@ set vhdlout_zero_name "'0'" -#@ #set vhdlout_levelize "FALSE" -#@ set vhdlout_dont_create_dummy_nets "FALSE" -#@ set vhdlout_follow_vector_direction "TRUE" -#@ -#@ -#@ # vhdl netlist reader variables -#@ set enable_vhdl_netlist_reader "FALSE" -#@ -#@ # variables pertaining to VHDL library generation -#@ set vhdllib_timing_mesg "true" -#@ set vhdllib_timing_xgen "false" -#@ set vhdllib_timing_checks "true" -#@ set vhdllib_negative_constraint "false" -#@ set vhdllib_glitch_handle "true" -#@ set vhdllib_pulse_handle "use_vhdllib_glitch_handle" -#@ # /*vhdllib_architecture = {FTBM, UDSM, FTSM, FTGS, VITAL}; */ -#@ set vhdllib_architecture {VITAL} -#@ set vhdllib_tb_compare 0 -#@ set vhdllib_tb_x_eq_dontcare FALSE -#@ set vhdllib_logic_system "ieee-1164" -#@ set vhdllib_logical_name "" -#@ -#@ # variables pertaining to technology library processing -#@ set read_db_lib_warnings FALSE -#@ set read_translate_msff TRUE -#@ set libgen_max_differences -1 -#@ -#@ # -#@ # Gui Variable Group -#@ # used for design_vision and psyn_gui -#@ # -#@ set gui_auto_start 0 -#@ set gui_start_option_no_windows 0 -#@ group_variable gui_variables "gui_auto_start" -#@ group_variable gui_variables "gui_start_option_no_windows" -#@ -#@ # -#@ # If you like emacs, uncomment the next line -#@ # set text_editor_command "emacs -fn 8x13 %s &" ; -#@ -#@ # You can delete pairs from this list, but you can't add new ones -#@ # unless you also update the UIL files. So, customers can not add -#@ # dialogs to this list, only Synopsys can do that. -#@ # -#@ set view_independent_dialogs { "test_report" " Test Reports " "report_print" " Report " "report_options" " Report Options " "report_win" " Report Output " "manual_page" " Manual Page " } -#@ -#@ # if color Silicon Graphics workstation -#@ if { [info exists x11_vendor_string] && [info exists x11_is_color]} { -#@ if { $x11_vendor_string == "Silicon" && $x11_is_color == "true" } { -#@ set x11_set_cursor_foreground "magenta" -#@ set view_use_small_cursor "true" -#@ set view_set_selecting_color "white" -#@ } -#@ } -#@ -#@ # if running on an Apollo machine -#@ set found_x11_vendor_string_apollo 0 -#@ set found_arch_apollo 0 -#@ if { [info exists x11_vendor_string]} { -#@ if { $x11_vendor_string == "Apollo "} { -#@ set found_x11_vendor_string_apollo 1 -#@ } -#@ } -#@ if { [info exists arch]} { -#@ if { $arch == "apollo"} { -#@ set found_arch_apollo 1 -#@ } -#@ } -#@ if { $found_x11_vendor_string_apollo == 1 || $found_arch_apollo == 1} { -#@ set enable_page_mode "false" -#@ } else { -#@ set enable_page_mode "true" -#@ } -#@ -#@ # don't work around this bug on the Apollo -#@ if { $found_x11_vendor_string_apollo == 1} { -#@ set view_extend_thick_lines "false" -#@ } else { -#@ set view_extend_thick_lines "true" -#@ } -#@ -#@ # -#@ # Suffix Variable Group: -#@ # -#@ # Suffixes recognized by the Design Analyzer menu in file choices -#@ # -#@ if { $synopsys_program_name == "design_vision" || $synopsys_program_name == "psyn_gui" } { -#@ # For star 93040 do NOT include NET in list, 108991 : pdb suffix added -#@ set view_read_file_suffix {db gdb sdb pdb edif eqn fnc lsi mif pla st tdl v vhd vhdl xnf} -#@ } else { -#@ set view_read_file_suffix {db gdb sdb edif eqn fnc lsi mif NET pla st tdl v vhd vhdl xnf} -#@ } -#@ -#@ set view_analyze_file_suffix {v vhd vhdl} -#@ set view_write_file_suffix {gdb db sdb do edif eqn fnc lsi NET neted pla st tdl v vhd vhdl xnf} -#@ set view_execute_script_suffix {.script .scr .dcs .dcv .dc .con} -#@ set view_arch_types {sparcOS5 hpux10 rs6000 sgimips} -#@ -#@ # -#@ # links_to_layout Variable Group: -#@ # -#@ # These variables affect the read_timing, write_timing -#@ # set_annotated_delay, compile, create_wire_load and reoptimize_design -#@ # commands. -#@ # -#@ if {$synopsys_program_name != "dc_sms_shell"} { -#@ set auto_wire_load_selection "true" -#@ set compile_create_wire_load_table "false" -#@ } -#@ set rtl_load_resistance_factor 0.0 -#@ -#@ # power Variable Group: -#@ # -#@ # These variables affect the behavior of power optimization and analysis. -#@ # -#@ -#@ set power_keep_license_after_power_commands "false" -#@ set power_rtl_saif_file "power_rtl.saif" -#@ set power_sdpd_saif_file "power_sdpd.saif" -#@ set power_preserve_rtl_hier_names "false" -#@ set power_do_not_size_icg_cells "true" -#@ set power_hdlc_do_not_split_cg_cells "false" -#@ set power_cg_flatten "false" -#@ set power_opto_extra_high_dynamic_power_effort "false" -#@ set power_default_static_probability 0.5 -#@ set power_default_toggle_rate 0.1 -#@ set power_default_toggle_rate_type "fastest_clock" -#@ set power_model_preference "nlpm" -#@ set power_sa_propagation_effort "low" -#@ set power_sa_propagation_verbose "false" -#@ set power_fix_sdpd_annotation "true" -#@ set power_fix_sdpd_annotation_verbose "false" -#@ set power_sdpd_message_tolerance 0.00001 -#@ set do_operand_isolation "false" -#@ set power_cg_module_naming_style "" -#@ set power_cg_cell_naming_style "" -#@ set power_cg_gated_clock_net_naming_style "" -#@ set power_rclock_use_asynch_inputs "false" -#@ set power_rclock_inputs_use_clocks_fanout "true" -#@ set power_rclock_unrelated_use_fastest "true" -#@ set power_lib2saif_rise_fall_pd "false" -#@ set power_min_internal_power_threshold "" -#@ -#@ -#@ # SystemC related variables -#@ set systemcout_levelize "true" -#@ set systemcout_debug_mode "false" -#@ -#@ # ACS Variables -#@ if { [info exists acs_work_dir] } { -#@ set acs_area_report_suffix "area" -#@ set acs_autopart_max_area "0.0" -#@ set acs_autopart_max_percent "0.0" -#@ set acs_budgeted_cstr_suffix "con" -#@ set acs_compile_script_suffix "autoscr" -#@ set acs_constraint_file_suffix "con" -#@ set acs_cstr_report_suffix "cstr" -#@ set acs_db_suffix "db" -#@ set acs_dc_exec "" -#@ set acs_default_pass_name "pass" -#@ set acs_exclude_extensions {} -#@ set acs_exclude_list [list $synopsys_root] -#@ set acs_global_user_compile_strategy_script "default" -#@ set acs_hdl_verilog_define_list {} -#@ set acs_hdl_source {} -#@ set acs_lic_wait 0 -#@ set acs_log_file_suffix "log" -#@ set acs_make_args "set acs_make_args" -#@ set acs_make_exec "gmake" -#@ set acs_makefile_name "Makefile" -#@ set acs_num_parallel_jobs 1 -#@ set acs_override_report_suffix "report" -#@ set acs_override_script_suffix "scr" -#@ set acs_qor_report_suffix "qor" -#@ set acs_timing_report_suffix "tim" -#@ set acs_use_autopartition "false" -#@ set acs_use_default_delays "false" -#@ set acs_user_budgeting_script "budget.scr" -#@ set acs_user_compile_strategy_script_suffix "compile" -#@ set acs_verilog_extensions {.v} -#@ set acs_vhdl_extensions {.vhd} -#@ set acs_work_dir [pwd] -#@ set check_error_list [list CMD-004 CMD-006 CMD-007 CMD-008 CMD-009 CMD-010 CMD-011 CMD-012 CMD-014 CMD-015 CMD-016 CMD-019 CMD-026 CMD-031 CMD-037 DB-1 DCSH-11 DES-001 ACS-193 FILE-1 FILE-2 FILE-3 FILE-4 LINK-7 LINT-7 LINT-20 LNK-023 OPT-100 OPT-101 OPT-102 OPT-114 OPT-124 OPT-127 OPT-128 OPT-155 OPT-157 OPT-181 OPT-462 UI-11 UI-14 UI-15 UI-16 UI-17 UI-19 UI-20 UI-21 UI-22 UI-23 UI-40 UI-41 UID-4 UID-6 UID-7 UID-8 UID-9 UID-13 UID-14 UID-15 UID-19 UID-20 UID-25 UID-27 UID-28 UID-29 UID-30 UID-32 UID-58 UID-87 UID-103 UID-109 UID-270 UID-272 UID-403 UID-440 UID-444 UIO-2 UIO-3 UIO-4 UIO-25 UIO-65 UIO-66 UIO-75 UIO-94 UIO-95 EQN-6 EQN-11 EQN-15 EQN-16 EQN-18 EQN-20 ] -#@ set ilm_preserve_core_constraints "false" -#@ } -#@ -#@ # -#@ # -#@ # DesignTime Variable Group -#@ # -#@ # The variables which affect the DesignTime timing engine -#@ # -#@ -#@ set case_analysis_log_file "" -#@ set case_analysis_sequential_propagate "false" -#@ set create_clock_no_input_delay "false" -#@ set disable_auto_time_borrow "false" -#@ set disable_case_analysis "false" -#@ set disable_conditional_mode_analysis "false" -#@ set disable_library_transition_degradation "false" -#@ set dont_bind_unused_pins_to_logic_constant "false" -#@ set enable_slew_degradation "true" -#@ set high_fanout_net_pin_capacitance 1.000000 -#@ set high_fanout_net_threshold 1000 -#@ set lib_thresholds_per_lib "true" -#@ set rc_adjust_rd_when_less_than_rnet "true" -#@ set rc_ceff_delay_min_diff_ps 0.250000 -#@ set rc_degrade_min_slew_when_rd_less_than_rnet "false" -#@ set rc_driver_model_max_error_pct 0.160000 -#@ set rc_filter_rd_less_than_rnet "true" -#@ set rc_input_threshold_pct_fall 50.000000 -#@ set rc_input_threshold_pct_rise 50.000000 -#@ set rc_output_threshold_pct_fall 50.000000 -#@ set rc_output_threshold_pct_rise 50.000000 -#@ set rc_rd_less_than_rnet_threshold 0.450000 -#@ set rc_slew_derate_from_library 1.000000 -#@ set rc_slew_lower_threshold_pct_fall 20.000000 -#@ set rc_slew_lower_threshold_pct_rise 20.000000 -#@ set rc_slew_upper_threshold_pct_fall 80.000000 -#@ set rc_slew_upper_threshold_pct_rise 80.000000 -#@ set timing_disable_cond_default_arcs "false" -#@ #timing_enable_multiple_clocks_per_reg is on by default -#@ #set timing_enable_multiple_clocks_per_reg "false" -#@ set timing_report_attributes {dont_touch dont_use map_only size_only ideal_net infeasible_paths} -#@ set timing_self_loops_no_skew "false" -#@ set when_analysis_permitted "true" -#@ set when_analysis_without_case_analysis "false" -#@ -#@ -#@ # -#@ # Variable Group Definitions: -#@ # -#@ # The group_variable() command groups variables for display -#@ # in the "File/Defaults" dialog and defines groups of variables -#@ # for the list() command. -#@ # -#@ -#@ set enable_instances_in_report_net "true" -#@ # Set report options env variables -#@ set view_report_interactive "true" -#@ set view_report_output2file "false" -#@ set view_report_append "true" -#@ -#@ if { $synopsys_program_name != "ptxr" } { -#@ -#@ group_variable report_variables "enable_instances_in_report_net" -#@ group_variable report_variables "view_report_interactive" -#@ group_variable report_variables "view_report_output2file" -#@ group_variable report_variables "view_report_append" -#@ -#@ # "links_to_layout" variables are used by multiple commands -#@ # auto_wire_load_selection is also in the "compile" variable group. -#@ group_variable links_to_layout "auto_wire_load_selection" -#@ -#@ # variables starting with "compile" are also in the compile variable group -#@ group_variable links_to_layout "compile_dont_touch_annotated_cell_during_inplace_opt" -#@ -#@ group_variable links_to_layout "compile_update_annotated_delays_during_inplace_opt" -#@ group_variable links_to_layout "compile_create_wire_load_table" -#@ -#@ group_variable links_to_layout "reoptimize_design_changed_list_file_name" -#@ group_variable links_to_layout "sdfout_allow_non_positive_constraints" -#@ -#@ } ;# $synopsys_program_name != "ptxr" -#@ -#@ # -#@ # to find the XErrorDB and XKeySymDB for X11 file -#@ set motif_files ${synopsys_root}/admin/setup -#@ # set filename for logging input file -#@ set filename_log_file "filenames.log" -#@ # whether to delete the filename log after the normal exits -#@ set exit_delete_filename_log_file "true" -#@ -#@ # executable to fire off RTLA/BCV -#@ set xterm_executable "xterm" -#@ -#@ if { $synopsys_program_name != "ptxr" } { -#@ -#@ # "system" variables are used by multiple commands -#@ group_variable system auto_link_disable -#@ group_variable system auto_link_options -#@ group_variable system command_log_file -#@ group_variable system company -#@ group_variable system compatibility_version -#@ -#@ if { [string compare $dc_shell_mode "default"] == 0 } { -#@ group_variable system "current_design" -#@ group_variable system "current_instance" -#@ group_variable system "dc_shell_status" -#@ } else { -#@ set current_design "" -#@ set current_instance "" -#@ group_variable system "current_design" -#@ group_variable system "current_instance" -#@ } -#@ -#@ group_variable system "designer" -#@ group_variable system "echo_include_commands" -#@ group_variable system "enable_page_mode" -#@ group_variable system "change_names_update_inst_tree" -#@ group_variable system "change_names_dont_change_bus_members" -#@ group_variable system "default_name_rules" -#@ group_variable system "verbose_messages" -#@ group_variable system "link_library" -#@ group_variable system "link_force_case" -#@ group_variable system "search_path" -#@ group_variable system "synthetic_library" -#@ group_variable system "target_library" -#@ group_variable system "uniquify_naming_style" -#@ group_variable system "suppress_errors" -#@ group_variable system "find_converts_name_lists" -#@ group_variable system "filename_log_file" -#@ group_variable system "exit_delete_filename_log_file" -#@ group_variable system "syntax_check_status" -#@ group_variable system "context_check_status" -#@ -#@ #/* "compile" variables are used by the compile command */ -#@ group_variable compile "compile_assume_fully_decoded_three_state_busses" -#@ group_variable compile "compile_no_new_cells_at_top_level" -#@ group_variable compile "compile_dont_touch_annotated_cell_during_inplace_opt" -#@ group_variable compile "reoptimize_design_changed_list_file_name" -#@ group_variable compile "compile_create_wire_load_table" -#@ group_variable compile "compile_update_annotated_delays_during_inplace_opt" -#@ group_variable compile "compile_instance_name_prefix" -#@ group_variable compile "compile_instance_name_suffix" -#@ group_variable compile "compile_negative_logic_methodology" -#@ group_variable compile "compile_disable_hierarchical_inverter_opt" -#@ -#@ group_variable compile "port_complement_naming_style" -#@ group_variable compile "auto_wire_load_selection" -#@ group_variable compile "rtl_load_resistance_factor" -#@ group_variable compile "compile_implementation_selection" -#@ group_variable compile "compile_use_low_timing_effort" -#@ group_variable compile "compile_fix_cell_degradation" -#@ group_variable compile "compile_preserve_subdesign_interfaces" -#@ group_variable compile "compile_enable_constant_propagation_with_no_boundary_opt" -#@ group_variable compile "compile_delete_unloaded_sequential_cells" -#@ group_variable compile "enable_recovery_removal_arcs" -#@ group_variable compile "compile_checkpoint_phases" -#@ group_variable compile "compile_cpu_limit" -#@ group_variable compile "compile_top_all_paths" -#@ group_variable compile "compile_top_all_paths" -#@ group_variable compile "compile_top_acs_partition" -#@ group_variable compile "default_port_connection_class" -#@ group_variable compile "compile_retime_license_behavior" -#@ group_variable compile "dont_touch_nets_with_size_only_cells" -#@ group_variable compile "compile_seqmap_no_scan_cell" -#@ -#@ if { $synopsys_program_name == "dc_shell" && [shell_is_in_topographical_mode] } { -#@ group_variable compile "dct_prioritize_area_correlation" -#@ group_variable compile "compile_error_on_missing_physical_cells" -#@ } -#@ -#@ # "multibit" variables are used by the the multibit mapping functionality -#@ -#@ group_variable multibit "bus_multiple_separator_style" -#@ -#@ # "ilm" variables are used by Interface Logic Model functionality -#@ -#@ group_variable ilm "ilm_ignore_percentage" -#@ -#@ # "estimate" variables are used by the estimate command -#@ # The estimate command also recognizes the "compile" variables. -#@ group_variable estimate "estimate_resource_preference" -#@ -#@ # "synthetic_library" variables -#@ group_variable synlib "cache_dir_chmod_octal" -#@ group_variable synlib "cache_file_chmod_octal" -#@ group_variable synlib "cache_read" -#@ group_variable synlib "cache_read_info" -#@ group_variable synlib "cache_write" -#@ group_variable synlib "cache_write_info" -#@ group_variable synlib "synlib_dont_get_license" -#@ group_variable synlib "synlib_wait_for_design_license" -#@ group_variable synlib "synthetic_library" -#@ -#@ # "insert_dft" variables are used by the insert_dft and preview_dft commands -#@ #group_variable insert_dft "test_default_client_order" -#@ group_variable insert_dft "insert_dft_clean_up" -#@ group_variable insert_dft "insert_test_design_naming_style" -#@ group_variable insert_dft "test_clock_port_naming_style" -#@ group_variable insert_dft "test_default_min_fault_coverage" -#@ group_variable insert_dft "test_scan_clock_a_port_naming_style" -#@ group_variable insert_dft "test_scan_clock_b_port_naming_style" -#@ group_variable insert_dft "test_scan_clock_port_naming_style" -#@ group_variable insert_dft "test_scan_enable_inverted_port_naming_style" -#@ group_variable insert_dft "test_scan_enable_port_naming_style" -#@ group_variable insert_dft "test_scan_in_port_naming_style" -#@ group_variable insert_dft "test_scan_out_port_naming_style" -#@ group_variable insert_dft "test_non_scan_clock_port_naming_style" -#@ group_variable insert_dft "test_dedicated_subdesign_scan_outs" -#@ group_variable insert_dft "test_disable_find_best_scan_out" -#@ group_variable insert_dft "test_dont_fix_constraint_violations" -#@ group_variable insert_dft "test_isolate_hier_scan_out" -#@ group_variable insert_dft "test_mode_port_naming_style" -#@ group_variable insert_dft "test_mode_port_inverted_naming_style" -#@ group_variable insert_dft "compile_dont_use_dedicated_scanout" -#@ group_variable insert_dft "test_mux_constant_si" -#@ -#@ # "preview_scan" variables are used by the preview_scan command -#@ group_variable preview_scan "test_preview_scan_shows_cell_types" -#@ group_variable preview_scan "test_scan_link_so_lockup_key" -#@ group_variable preview_scan "test_scan_link_wire_key" -#@ group_variable preview_scan "test_scan_segment_key" -#@ group_variable preview_scan "test_scan_true_key" -#@ -#@ # "bsd" variables are used by the check_bsd and write_bsdl commands -#@ group_variable bsd "test_user_test_data_register_naming_style" -#@ group_variable bsd "test_user_defined_instruction_naming_style" -#@ group_variable bsd "test_bsdl_default_suffix_name" -#@ group_variable bsd "test_bsdl_max_line_length" -#@ group_variable bsd "test_cc_ir_masked_bits" -#@ group_variable bsd "test_cc_ir_value_of_masked_bits" -#@ -#@ group_variable bsd "test_bsd_allow_tolerable_violations" -#@ group_variable bsd "test_bsd_optimize_control_cell" -#@ group_variable bsd "test_bsd_control_cell_drive_limit" -#@ group_variable bsd "test_bsd_manufacturer_id" -#@ group_variable bsd "test_bsd_part_number" -#@ group_variable bsd "test_bsd_version_number" -#@ group_variable bsd "bsd_max_in_switching_limit" -#@ group_variable bsd "bsd_max_out_switching_limit" -#@ -#@ # testmanager variables -#@ group_variable testmanager "multi_pass_test_generation" -#@ -#@ # "testsim" variables -#@ # group_variable testsim "testsim_print_stats_file" -#@ -#@ # "test" variables -#@ group_variable test "test_default_bidir_delay" -#@ group_variable test "test_default_delay" -#@ group_variable test "test_default_period" -#@ group_variable test "test_default_strobe" -#@ group_variable test "test_default_strobe_width" -#@ group_variable test "test_capture_clock_skew" -#@ group_variable test "test_allow_clock_reconvergence" -#@ group_variable test "test_check_port_changes_in_capture" -#@ group_variable test "test_stil_max_line_length" -#@ group_variable test "test_infer_slave_clock_pulse_after_capture" -#@ group_variable test "test_rtldrc_latch_check_style" -#@ group_variable test "test_enable_capture_checks" -#@ -#@ # "write_test" variables are used by the write_test command -#@ group_variable write_test "write_test_formats" -#@ group_variable write_test "write_test_include_scan_cell_info" -#@ group_variable write_test "write_test_input_dont_care_value" -#@ group_variable write_test "write_test_max_cycles" -#@ group_variable write_test "write_test_max_scan_patterns" -#@ group_variable write_test "write_test_pattern_set_naming_style" -#@ group_variable write_test "write_test_scan_check_file_naming_style" -#@ group_variable write_test "write_test_vector_file_naming_style" -#@ group_variable write_test "write_test_round_timing_values" -#@ -#@ group_variable view "test_design_analyzer_uses_insert_scan" -#@ -#@ # "io" variables are used by the read, read_lib, db2sge and write commands -#@ group_variable io "bus_inference_descending_sort" -#@ group_variable io "bus_inference_style" -#@ #group_variable io "db2sge_output_directory" -#@ #group_variable io "db2sge_scale" -#@ #group_variable io "db2sge_overwrite" -#@ #group_variable io "db2sge_display_symbol_names" -#@ #group_variable io "db2sge_display_pin_names" -#@ #group_variable io "db2sge_display_instance_names" -#@ #group_variable io "db2sge_use_bustaps" -#@ #group_variable io "db2sge_use_compound_names" -#@ #group_variable io "db2sge_bit_type" -#@ #group_variable io "db2sge_bit_vector_type" -#@ #group_variable io "db2sge_one_name" -#@ #group_variable io "db2sge_zero_name" -#@ #group_variable io "db2sge_unknown_name" -#@ #group_variable io "db2sge_target_xp" -#@ #group_variable io "db2sge_tcf_package_file" -#@ #group_variable io "db2sge_use_lib_section" -#@ #group_variable io "db2sge_script" -#@ #group_variable io "db2sge_command" -#@ -#@ # group_variable io "equationout_and_sign" -#@ # group_variable io "equationout_or_sign" -#@ # group_variable io "equationout_postfix_negation" -#@ -#@ # group_variable io "lsiin_net_name_prefix" -#@ # group_variable io "lsiout_inverter_cell" -#@ # group_variable io "lsiout_upcase" -#@ -#@ #group_variable io "mentor_bidirect_value" -#@ #group_variable io "mentor_do_path" -#@ #group_variable io "mentor_input_output_property_name" -#@ #group_variable io "mentor_input_value" -#@ #group_variable io "mentor_logic_one_value" -#@ #group_variable io "mentor_logic_zero_one_property_name" -#@ #group_variable io "mentor_logic_zero_value" -#@ #group_variable io "mentor_output_value" -#@ #group_variable io "mentor_primitive_property_name" -#@ #group_variable io "mentor_primitive_property_value" -#@ #group_variable io "mentor_reference_property_name" -#@ #group_variable io "mentor_search_path" -#@ #group_variable io "mentor_write_symbols" -#@ # group_variable io "pla_read_create_flip_flop" -#@ # group_variable io "tdlout_upcase" -#@ group_variable io "write_name_nets_same_as_ports" -#@ -#@ # # [wjchen] 2006/08/14: The following 4 variables are obsoleted for DC simpilification. -#@ -#@ # group_variable io "xnfout_constraints_per_endpoint" -#@ # group_variable io "xnfout_default_time_constraints" -#@ # group_variable io "xnfout_clock_attribute_style" -#@ # group_variable io "xnfout_library_version" -#@ -#@ # # [wjchen] 2006/08/11: The following 8 variables are obsoleted for DC simpilification. -#@ # group_variable io "xnfin_family" -#@ # group_variable io "xnfin_ignore_pins" -#@ # group_variable io "xnfin_dff_reset_pin_name" -#@ # group_variable io "xnfin_dff_set_pin_name" -#@ # group_variable io "xnfin_dff_clock_enable_pin_name" -#@ # group_variable io "xnfin_dff_data_pin_name" -#@ # group_variable io "xnfin_dff_clock_pin_name" ; -#@ # group_variable io "xnfin_dff_q_pin_name"; -#@ -#@ group_variable io "sdfin_min_rise_net_delay" ; -#@ group_variable io "sdfin_min_fall_net_delay" ; -#@ group_variable io "sdfin_min_rise_cell_delay" ; -#@ group_variable io "sdfin_min_fall_cell_delay" ; -#@ group_variable io "sdfin_rise_net_delay_type" ; -#@ group_variable io "sdfin_fall_net_delay_type" ; -#@ group_variable io "sdfin_rise_cell_delay_type" ; -#@ group_variable io "sdfin_fall_cell_delay_type" ; -#@ group_variable io "sdfin_top_instance_name" ; -#@ group_variable io "sdfout_time_scale" ; -#@ group_variable io "sdfout_write_to_output" ; -#@ group_variable io "sdfout_top_instance_name" ; -#@ group_variable io "sdfout_min_rise_net_delay" ; -#@ group_variable io "sdfout_min_fall_net_delay" ; -#@ group_variable io "sdfout_min_rise_cell_delay" ; -#@ group_variable io "sdfout_min_fall_cell_delay" ; -#@ group_variable io "read_db_lib_warnings" ; -#@ group_variable io "read_translate_msff" ; -#@ group_variable io "libgen_max_differences" ; -#@ -#@ # #[wjchen] 2006/08/22: The following variables are hidden for XG mode for DC simpilification. -#@ # group_variable io "read_name_mapping_nowarn_libraries" ; -#@ # group_variable io "write_name_mapping_nowarn_libraries" ; -#@ -#@ -#@ # "edif" variables are used by the EDIF format read, read_lib, write, -#@ # and write_lib commands -#@ # group_variable edif "bus_dimension_separator_style" ; -#@ # group_variable edif "bus_extraction_style" ; -#@ group_variable edif "bus_inference_descending_sort" ; -#@ group_variable edif "bus_inference_style" ; -#@ group_variable edif "bus_naming_style" ; -#@ group_variable edif "bus_range_separator_style" ; -#@ # group_variable edif "edifin_autoconnect_offpageconnectors" ; -#@ # group_variable edif "edifin_autoconnect_ports" ; -#@ # group_variable edif "edifin_delete_empty_cells" ; -#@ # group_variable edif "edifin_delete_ripper_cells" ; -#@ # group_variable edif "edifin_ground_net_name" ; -#@ # group_variable edif "edifin_ground_net_property_name" ; -#@ # group_variable edif "edifin_ground_net_property_value" ; -#@ # group_variable edif "edifin_ground_port_name" ; -#@ # group_variable edif "edifin_instance_property_name" ; -#@ # group_variable edif "edifin_portinstance_disabled_property_name" ; -#@ # group_variable edif "edifin_portinstance_disabled_property_value" ; -#@ # group_variable edif "edifin_portinstance_property_name" ; -#@ # group_variable edif "edifin_power_net_name" ; -#@ # group_variable edif "edifin_power_net_property_name" ; -#@ # group_variable edif "edifin_power_net_property_value" ; -#@ # group_variable edif "edifin_power_port_name" ; -#@ # group_variable edif "edifin_use_identifier_in_rename" ; -#@ # group_variable edif "edifin_view_identifier_property_name" ; -#@ # group_variable edif "edifin_dc_script_flag" ; -#@ # group_variable edif "edifin_lib_logic_1_symbol" ; -#@ # group_variable edif "edifin_lib_logic_0_symbol" ; -#@ # group_variable edif "edifin_lib_in_port_symbol" ; -#@ # group_variable edif "edifin_lib_out_port_symbol" ; -#@ # group_variable edif "edifin_lib_inout_port_symbol" ; -#@ # group_variable edif "edifin_lib_in_osc_symbol" ; -#@ # group_variable edif "edifin_lib_out_osc_symbol" ; -#@ # group_variable edif "edifin_lib_inout_osc_symbol" ; -#@ # group_variable edif "edifin_lib_mentor_netcon_symbol" ; -#@ # group_variable edif "edifin_lib_ripper_bits_property" ; -#@ # group_variable edif "edifin_lib_ripper_bus_end" ; -#@ # group_variable edif "edifin_lib_ripper_cell_name" ; -#@ # group_variable edif "edifin_lib_ripper_view_name" ; -#@ # group_variable edif "edifin_lib_route_grid" ; -#@ # group_variable edif "edifin_lib_templates" ; -#@ # group_variable edif "edifout_dc_script_flag" ; -#@ # group_variable edif "edifout_design_name" ; -#@ # group_variable edif "edifout_designs_library_name" ; -#@ # group_variable edif "edifout_display_instance_names" ; -#@ # group_variable edif "edifout_display_net_names" ; -#@ # group_variable edif "edifout_external" ; -#@ # group_variable edif "edifout_external_graphic_view_name" ; -#@ # group_variable edif "edifout_external_netlist_view_name" ; -#@ # group_variable edif "edifout_external_schematic_view_name" ; -#@ # group_variable edif "edifout_ground_name" ; -#@ # group_variable edif "edifout_ground_net_name" ; -#@ # group_variable edif "edifout_ground_net_property_name" ; -#@ # group_variable edif "edifout_ground_net_property_value" ; -#@ # group_variable edif "edifout_ground_pin_name" ; -#@ # group_variable edif "edifout_ground_port_name" ; -#@ # group_variable edif "edifout_instance_property_name" ; -#@ # group_variable edif "edifout_instantiate_ports" ; -#@ # group_variable edif "edifout_library_graphic_view_name" ; -#@ # group_variable edif "edifout_library_netlist_view_name" ; -#@ # group_variable edif "edifout_library_schematic_view_name" ; -#@ # group_variable edif "edifout_merge_libraries" ; -#@ # group_variable edif "edifout_multidimension_arrays" ; -#@ # group_variable edif "edifout_name_oscs_different_from_ports" ; -#@ # group_variable edif "edifout_name_rippers_same_as_wires" ; -#@ # group_variable edif "edifout_netlist_only" ; -#@ # group_variable edif "edifout_no_array" ; -#@ # group_variable edif "edifout_numerical_array_members" ; -#@ # group_variable edif "edifout_pin_direction_property_name" ; -#@ # group_variable edif "edifout_pin_direction_in_value" ; -#@ # group_variable edif "edifout_pin_direction_inout_value" ; -#@ # group_variable edif "edifout_pin_direction_out_value" ; -#@ # group_variable edif "edifout_pin_name_property_name" ; -#@ # group_variable edif "edifout_portinstance_disabled_property_name" ; -#@ # group_variable edif "edifout_portinstance_disabled_property_value" ; -#@ # group_variable edif "edifout_portinstance_property_name" -#@ # group_variable edif "edifout_power_and_ground_representation" -#@ # group_variable edif "edifout_power_name" -#@ # group_variable edif "edifout_power_net_name" -#@ # group_variable edif "edifout_power_net_property_name" -#@ # group_variable edif "edifout_power_net_property_value" -#@ # group_variable edif "edifout_power_pin_name" -#@ # group_variable edif "edifout_power_port_name" -#@ # group_variable edif "edifout_skip_port_implementations" -#@ # group_variable edif "edifout_target_system" -#@ # group_variable edif "edifout_top_level_symbol" -#@ # group_variable edif "edifout_translate_origin" -#@ # group_variable edif "edifout_unused_property_value" -#@ # group_variable edif "edifout_write_attributes" -#@ # group_variable edif "edifout_write_constraints" -#@ # group_variable edif "edifout_write_properties_list" -#@ # group_variable edif "write_name_nets_same_as_ports" -#@ -#@ # "hdl" variables are variables pertaining to hdl reading and optimizing -#@ group_variable hdl "bus_dimension_separator_style" -#@ group_variable hdl "bus_minus_style" -#@ group_variable hdl "bus_naming_style" -#@ group_variable hdl "hdlin_ignore_textio_constructs" -#@ group_variable hdl "hdlin_latch_always_async_set_reset" -#@ group_variable hdl "hdlin_ff_always_sync_set_reset" -#@ group_variable hdl "hdlin_ff_always_async_set_reset" -#@ group_variable hdl "hdlin_check_input_netlist" -#@ group_variable hdl "hdlin_check_no_latch" -#@ group_variable hdl "hdlin_reporting_level" -#@ group_variable hdl "hdlin_infer_mux" -#@ group_variable hdl "hdlin_mux_oversize_ratio" -#@ group_variable hdl "hdlin_mux_size_limit" -#@ group_variable hdl "hdlin_infer_multibit" -#@ group_variable hdl "hdl_preferred_license" -#@ group_variable hdl "hdl_keep_licenses" -#@ group_variable hdl "hlo_resource_allocation" -#@ group_variable hdl "template_naming_style" -#@ group_variable hdl "template_parameter_style" -#@ group_variable hdl "template_separator_style" -#@ group_variable hdl "verilogout_equation" -#@ group_variable hdl "verilogout_ignore_case" -#@ group_variable hdl "verilogout_no_tri" -#@ group_variable hdl "verilogout_inout_is_in" -#@ group_variable hdl "verilogout_single_bit" -#@ group_variable hdl "verilogout_higher_designs_first" -#@ # group_variable hdl "verilogout_levelize" -#@ group_variable hdl "verilogout_include_files" -#@ group_variable hdl "verilogout_unconnected_prefix" -#@ group_variable hdl "verilogout_show_unconnected_pins" -#@ group_variable hdl "verilogout_no_negative_index" -#@ group_variable hdl "hdlin_enable_rtldrc_info" -#@ group_variable hdl "hdlin_sv_blackbox_modules" -#@ group_variable hdl "hdlin_infer_function_local_latches" -#@ group_variable hdl "hdlin_module_arch_name_splitting" -#@ group_variable hdl "hdlin_mux_size_min" -#@ group_variable hdl "hdlin_prohibit_nontri_multiple_drivers" -#@ group_variable hdl "hdlin_subprogram_default_values" -#@ group_variable hdl "hdlin_upcase_names" -#@ group_variable hdl "hdlin_vhdl_std" -#@ group_variable hdl "hdlin_vhdl93_concat" -#@ group_variable hdl "hdlin_vhdl_syntax_extensions" -#@ group_variable hdl "hdlin_vrlg_std" -#@ group_variable hdl "hdlin_while_loop_iterations" -#@ group_variable hdl "hdlin_auto_save_templates" -#@ group_variable hdl "hdlin_elab_errors_deep" -#@ group_variable hdl "hdlin_enable_assertions" -#@ group_variable hdl "hdlin_enable_configurations" -#@ group_variable hdl "hdlin_field_naming_style" -#@ group_variable hdl "hdlin_generate_naming_style" -#@ group_variable hdl "hdlin_generate_separator_style" -#@ group_variable hdl "hdlin_enable_relative_placement" -#@ group_variable hdl "hdlin_mux_rp_limit" -#@ group_variable hdl "hdlin_keep_signal_name" -#@ group_variable hdl "hdlin_module_name_limit" -#@ group_variable hdl "hdlin_mux_size_only" -#@ group_variable hdl "hdlin_preserve_sequential" -#@ group_variable hdl "hdlin_presto_cell_name_prefix" -#@ group_variable hdl "hdlin_presto_net_name_prefix" -#@ group_variable hdl "hdlin_strict_verilog_reader" -#@ group_variable hdl "hdlin_shorten_long_module_name" -#@ group_variable hdl "hdlin_sv_packages" -#@ group_variable hdl "hdlin_sv_tokens" -#@ group_variable hdl "hdlin_enable_elaborate_ref_linking" -#@ group_variable hdl "hdlin_enable_hier_naming" -#@ group_variable hdl "hdlin_autoread_verilog_extensions" -#@ group_variable hdl "hdlin_autoread_sverilog_extensions" -#@ group_variable hdl "hdlin_autoread_vhdl_extensions" -#@ group_variable hdl "hdlin_autoread_exclude_extensions" -#@ group_variable hdl "hdlin_enable_upf_compatible_naming" -#@ group_variable hdl "hdlin_report_sequential_pruning" -#@ group_variable hdl "hdlin_analyze_verbose_mode" -#@ -#@ # "vhdlio" variables are variables pertaining to VHDL generation -#@ group_variable vhdlio "vhdllib_timing_mesg" -#@ group_variable vhdlio "vhdllib_timing_xgen" -#@ group_variable vhdlio "vhdllib_timing_checks" -#@ group_variable vhdlio "vhdllib_negative_constraint" -#@ group_variable vhdlio "vhdllib_pulse_handle" -#@ group_variable vhdlio "vhdllib_glitch_handle" -#@ group_variable vhdlio "vhdllib_architecture" -#@ group_variable vhdlio "vhdllib_tb_compare" -#@ group_variable vhdlio "vhdllib_tb_x_eq_dontcare" -#@ group_variable vhdlio "vhdllib_logic_system" -#@ group_variable vhdlio "vhdllib_logical_name" -#@ -#@ # group_variable vhdlio "vhdlout_architecture_name" -#@ group_variable vhdlio "vhdlout_bit_type" -#@ # group_variable vhdlio "vhdlout_bit_type_resolved" -#@ group_variable vhdlio "vhdlout_bit_vector_type" -#@ # group_variable vhdlio "vhdlout_conversion_functions" -#@ # group_variable vhdlio "vhdlout_dont_write_types" -#@ group_variable vhdlio "vhdlout_equations" -#@ group_variable vhdlio "vhdlout_one_name" -#@ group_variable vhdlio "vhdlout_package_naming_style" -#@ group_variable vhdlio "vhdlout_preserve_hierarchical_types" -#@ group_variable vhdlio "vhdlout_separate_scan_in" -#@ group_variable vhdlio "vhdlout_single_bit" -#@ group_variable vhdlio "vhdlout_target_simulator" -#@ group_variable vhdlio "vhdlout_top_configuration_arch_name" -#@ group_variable vhdlio "vhdlout_top_configuration_entity_name" -#@ group_variable vhdlio "vhdlout_top_configuration_name" -#@ group_variable vhdlio "vhdlout_three_state_name" -#@ group_variable vhdlio "vhdlout_three_state_res_func" -#@ # group_variable vhdlio "vhdlout_time_scale" -#@ group_variable vhdlio "vhdlout_unknown_name" -#@ group_variable vhdlio "vhdlout_use_packages" -#@ group_variable vhdlio "vhdlout_wired_and_res_func" -#@ group_variable vhdlio "vhdlout_wired_or_res_func" -#@ group_variable vhdlio "vhdlout_write_architecture" -#@ group_variable vhdlio "vhdlout_write_entity" -#@ group_variable vhdlio "vhdlout_write_top_configuration" -#@ # group_variable vhdlio "vhdlout_synthesis_off" -#@ group_variable vhdlio "vhdlout_write_components" -#@ group_variable vhdlio "vhdlout_zero_name" -#@ # group_variable vhdlio "vhdlout_levelize" -#@ group_variable vhdlio "vhdlout_dont_create_dummy_nets" -#@ group_variable vhdlio "vhdlout_follow_vector_direction" -#@ -#@ # "suffix" variables are used to find the suffixes of different file types -#@ group_variable suffix "view_execute_script_suffix" -#@ group_variable suffix "view_read_file_suffix" -#@ group_variable suffix "view_analyze_file_suffix" -#@ group_variable suffix "view_write_file_suffix" -#@ -#@ # Meenakshi: Added new group scc (for SystemC compiler) -#@ group_variable scc {systemcout_levelize} -#@ group_variable scc {systemcout_debug_mode} -#@ -#@ # "power" variables are for power-analysis. -#@ group_variable power {power_keep_license_after_power_commands} -#@ group_variable power {power_preserve_rtl_hier_names} -#@ group_variable power {power_do_not_size_icg_cells} -#@ group_variable power {power_hdlc_do_not_split_cg_cells} -#@ group_variable power {power_rtl_saif_file} -#@ group_variable power {power_sdpd_saif_file} -#@ group_variable power {power_cg_flatten} -#@ group_variable power {power_opto_extra_high_dynamic_power_effort} -#@ group_variable power {power_default_static_probability} -#@ group_variable power {power_default_toggle_rate} -#@ group_variable power {power_default_toggle_rate_type} -#@ group_variable power {power_model_preference} -#@ group_variable power {power_sa_propagation_effort} -#@ group_variable power {power_sa_propagation_verbose} -#@ group_variable power {power_fix_sdpd_annotation} -#@ group_variable power {power_fix_sdpd_annotation_verbose} -#@ group_variable power {power_sdpd_message_tolerance} -#@ group_variable power {power_rclock_use_asynch_inputs} -#@ group_variable power {power_rclock_inputs_use_clocks_fanout} -#@ group_variable power {power_rclock_unrelated_use_fastest} -#@ group_variable power {power_lib2saif_rise_fall_pd} -#@ group_variable power {power_min_internal_power_threshold} -#@ group_variable power {power_cg_module_naming_style} -#@ group_variable power {power_cg_cell_naming_style} -#@ group_variable power {power_cg_gated_clock_net_naming_style} -#@ group_variable power {do_operand_isolation} -#@ -#@ # dpcm variables are used by DPCM lib and controllong DC when using DPCM -#@ -#@ if { [info exists dpcm_debuglevel] } { -#@ group_variable dpcm "dpcm_debuglevel" -#@ group_variable dpcm "dpcm_rulespath" -#@ group_variable dpcm "dpcm_rulepath" -#@ group_variable dpcm "dpcm_tablepath" -#@ group_variable dpcm "dpcm_libraries" -#@ group_variable dpcm "dpcm_version" -#@ group_variable dpcm "dpcm_level" -#@ group_variable dpcm "dpcm_temperaturescope" -#@ group_variable dpcm "dpcm_voltagescope" -#@ group_variable dpcm "dpcm_functionscope" -#@ group_variable dpcm "dpcm_wireloadscope" -#@ group_variable dpcm "dpcm_slewlimit" -#@ group_variable dpcm "dpcm_arc_sense_mapping" -#@ -#@ } -#@ -#@ set dpcm_slewlimit "TRUE" -#@ -#@ # executable to fire off RTLA/BCV -#@ group_variable hdl {xterm_executable} -#@ -#@ # Variable group for Chip Compiler -#@ if {[info exists acs_work_dir]} { -#@ group_variable acs acs_area_report_suffix -#@ group_variable acs acs_autopart_max_area -#@ group_variable acs acs_autopart_max_percent -#@ group_variable acs acs_budgeted_cstr_suffix -#@ group_variable acs acs_compile_script_suffix -#@ group_variable acs acs_constraint_file_suffix -#@ group_variable acs acs_cstr_report_suffix -#@ group_variable acs acs_db_suffix -#@ group_variable acs acs_dc_exec -#@ group_variable acs acs_default_pass_name -#@ group_variable acs acs_exclude_extensions -#@ group_variable acs acs_exclude_list -#@ group_variable acs acs_global_user_compile_strategy_script -#@ group_variable acs acs_hdl_verilog_define_list -#@ group_variable acs acs_hdl_source -#@ group_variable acs acs_lic_wait -#@ group_variable acs acs_log_file_suffix -#@ group_variable acs acs_make_args -#@ group_variable acs acs_make_exec -#@ group_variable acs acs_makefile_name -#@ group_variable acs acs_num_parallel_jobs -#@ group_variable acs acs_override_report_suffix -#@ group_variable acs acs_override_script_suffix -#@ group_variable acs acs_qor_report_suffix -#@ group_variable acs acs_timing_report_suffix -#@ group_variable acs acs_use_autopartition -#@ group_variable acs acs_use_default_delays -#@ group_variable acs acs_user_budgeting_script -#@ group_variable acs acs_user_compile_strategy_script_suffix -#@ group_variable acs acs_verilog_extensions -#@ group_variable acs acs_vhdl_extensions -#@ group_variable acs acs_work_dir -#@ group_variable acs check_error_list -#@ group_variable acs ilm_preserve_core_constraints -#@ -#@ } -#@ -#@ # -#@ # DesignTime Variable Group timing -#@ # -#@ -#@ group_variable timing case_analysis_log_file -#@ group_variable timing case_analysis_sequential_propagate -#@ group_variable timing case_analysis_with_logic_constants -#@ group_variable timing create_clock_no_input_delay -#@ group_variable timing disable_auto_time_borrow -#@ group_variable timing disable_case_analysis -#@ group_variable timing disable_conditional_mode_analysis -#@ group_variable timing disable_library_transition_degradation -#@ group_variable timing dont_bind_unused_pins_to_logic_constant -#@ group_variable timing enable_slew_degradation -#@ group_variable timing high_fanout_net_pin_capacitance -#@ group_variable timing high_fanout_net_threshold -#@ group_variable timing lib_thresholds_per_lib -#@ group_variable timing rc_adjust_rd_when_less_than_rnet -#@ group_variable timing rc_ceff_delay_min_diff_ps -#@ group_variable timing rc_degrade_min_slew_when_rd_less_than_rnet -#@ group_variable timing rc_driver_model_max_error_pct -#@ group_variable timing rc_filter_rd_less_than_rnet -#@ group_variable timing rc_input_threshold_pct_fall -#@ group_variable timing rc_input_threshold_pct_rise -#@ group_variable timing rc_output_threshold_pct_fall -#@ group_variable timing rc_output_threshold_pct_rise -#@ group_variable timing rc_rd_less_than_rnet_threshold -#@ group_variable timing rc_slew_derate_from_library -#@ group_variable timing rc_slew_lower_threshold_pct_fall -#@ group_variable timing rc_slew_lower_threshold_pct_rise -#@ group_variable timing rc_slew_upper_threshold_pct_fall -#@ group_variable timing rc_slew_upper_threshold_pct_rise -#@ group_variable timing timing_disable_cond_default_arcs -#@ # group_variable timing timing_enable_multiple_clocks_per_reg -#@ group_variable timing timing_report_attributes -#@ group_variable timing timing_self_loops_no_skew -#@ group_variable timing when_analysis_permitted -#@ group_variable timing when_analysis_without_case_analysis -#@ -#@ } ;# $synopsys_program_name != "ptxr" -#@ -#@ if { $synopsys_program_name == "icc_shell"} { -#@ # -#@ # IC Compile Variable Group: -#@ # -#@ # These variables affect the designs created by the route_opt command. -#@ # -#@ group_variable routeopt routeopt_checkpoint -#@ group_variable routeopt routeopt_disable_cpulimit -#@ } -#@ -#@ if { $synopsys_program_name == "icc_shell"} { -#@ # -#@ # IC Compiler Variable Group: MCMM -#@ # -#@ # These variables affect Multi-Corner/Multi-Mode. Currently, MCMM is -#@ # only supported in ICC--hence the "icc_shell" qualification, above -#@ # -#@ group_variable MCMM mcmm_enable_high_capacity_flow -#@ } -#@ -#@ # Aliases for backwards compatibility or other reasons -#@ group_variable compile {compile_log_format} -#@ alias view_cursor_number x11_set_cursor_number -#@ alias set_internal_load set_load -#@ alias set_internal_arrival set_arrival -#@ alias set_connect_delay "set_annotated_delay -net" -#@ alias create_test_vectors create_test_patterns -#@ alias compile_test insert_test -#@ alias check_clocks check_timing -#@ alias lint check_design -#@ # gen removed; alias gen create_schematic -#@ alias free remove_design -#@ alias group_bus create_bus -#@ alias ungroup_bus remove_bus -#@ alias groupvar group_variable -#@ alias report_constraints report_constraint -#@ alias report_attributes report_attribute -#@ alias fsm_reduce reduce_fsm -#@ alias fsm_minimize minimize_fsm -#@ alias disable_timing set_disable_timing -#@ alias dont_touch set_dont_touch -#@ alias dont_touch_network set_dont_touch_network -#@ alias dont_use set_dont_use -#@ alias fix_hold set_fix_hold -#@ alias prefer set_prefer -#@ alias remove_package "echo remove_package command is obsolete: packages are stored on disk not in-memory:" -#@ alias analyze_scan preview_scan -#@ alias get_clock get_clocks -#@ alias dc_shell_is_in_incr_mode shell_is_in_xg_mode -#@ alias set_vh_module_options set_dps_module_options -#@ alias set_vh_physopt_options set_dps_options -#@ alias update_vh_design update_dps_design -#@ alias vh_start dps_start -#@ alias vh_end dps_end -#@ alias all_vh_modules all_dps_modules -#@ alias all_designs_of_vh all_designs_of_dps -#@ alias vh_use_auto_partitioning dps_auto_partitioning -#@ alias vh_write_changes dps_write_changes -#@ alias vh_read_changes dps_read_changes -#@ alias vh_write_module_clock dps_write_module_clock -#@ alias get_lib get_libs -#@ -#@ # Enable unsupported psyn commands -#@ if { $synopsys_program_name == "psyn_shell" || $synopsys_program_name == "icc_shell"} { -#@ proc enable_unsupported_commands { { arg "default" } } { -#@ global cgpi_use_new_wire_factors -#@ global cgpi_use_relative_wire_factors -#@ global cgpi_use_new_path_factors -#@ global pwlm_use_new_wire_factors -#@ global pwlm_use_relative_wire_factors -#@ global pwlm_use_new_path_factors -#@ global psyn_unsupported_commands_dir -#@ global synopsys_root -#@ if {![info exists psyn_unsupported_commands_dir]} { -#@ set psyn_unsupported_commands_dir $synopsys_root/auxx/syn/psyn/unsupported_commands -#@ } -#@ set psyn_unsupported_commands_option1 $arg -#@ if {[file readable $psyn_unsupported_commands_dir/setup.tcl]} { -#@ source $psyn_unsupported_commands_dir/setup.tcl -#@ } else { -#@ source -encrypted $psyn_unsupported_commands_dir/setup.tcl.e -#@ } -#@ } -#@ } -#@ # For Intel -#@ if { $synopsys_program_name == "icc_shell"} { -#@ set psyn_unsupported_commands_dir $synopsys_root/auxx/syn/psyn/unsupported_commands -#@ source -encrypted $psyn_unsupported_commands_dir/max_dist.tcl.e -#@ } -#@ -#@ -#@ if { $synopsys_program_name == "icc_shell"} { -#@ # to enable CLE readline-ish terminal by default for ICC -#@ set sh_enable_line_editing true -#@ -#@ # Astro forms create an enormous number of new variables which are -#@ # very annoying for users to see, so the default of this variable -#@ # for ICC is false -#@ set sh_new_variable_message false -#@ } -#@ -#@ if { $synopsys_program_name == "icc_shell" || (($synopsys_program_name == "dc_shell") && ([shell_is_in_topographical_mode])) } { -#@ source $synopsys_root/auxx/syn/psyn/verify_ilm.tcl -#@ } -#@ -#@ # Enable vh psyn commands -#@ if { $synopsys_program_name == "psyn_shell" } { -#@ proc enable_vh_flow { } { -#@ global VH_SCRIPT_FILE -#@ global synopsys_root -#@ global suppress_errors -#@ set suppress_errors "$suppress_errors CMD-041 UID-95 SEL-003 SEL-005" -#@ if {![info exists VH_SCRIPT_FILE]} { -#@ set VH_SCRIPT_FILE $synopsys_root/auxx/syn/psyn/vh_pc.tcl.e -#@ } -#@ if {[file readable $VH_SCRIPT_FILE]} { -#@ if {[string match *.tcl $VH_SCRIPT_FILE]} { -#@ source $VH_SCRIPT_FILE -#@ } else { -#@ source -encrypted $VH_SCRIPT_FILE -#@ } -#@ } else { -#@ puts "Error: VH script file $VH_SCRIPT_FILE not found." -#@ } -#@ } -#@ } -#@ -#@ -#@ #Turn on enable_netl_view to true by default. -#@ set enable_netl_view "TRUE" -#@ -#@ -#@ #Turn on physopt_bypass_multiple_plib_check by default -#@ if { $synopsys_program_name == "psyn_shell" } { -#@ set physopt_bypass_multiple_plib_check TRUE -#@ } -#@ -#@ # The ls command is gone, now it is just an alias for dc_shell eqn mode -#@ -#@ if { [string compare $dc_shell_mode "default"] == 0 } { -#@ if { ( $sh_arch == {mips}) && ( ( $synopsys_program_name == {design_analyzer}) || ( $isatty == 0)) } { -#@ alias ls "sh ls -a " -#@ } else { -#@ if { ( $sh_arch == {mips}) || ( $sh_arch == {necmips}) } { -#@ alias ls "sh ls -aC " -#@ } else { -#@ alias ls "sh ls -aC " -#@ } -#@ } -#@ } -#@ -#@ # Aliases for RouteCompiler -#@ alias run_rodeo_router route66 -#@ -#@ # Removing route_global from the code. Earlier it was hidden. --Mukesh -#@ #proc route_global {} { -#@ # global route_global_keep_tmp_data -#@ # global rt66_dont_lock_dir -#@ # -#@ # set rt66_dont_lock_dir TRUE -#@ # -#@ # for { set i 0} {1==1} {incr i} { -#@ # set wdir [file join [pwd] ".route_global.$i"] -#@ # if {[file exist $wdir] == 0} { -#@ # break; -#@ # } -#@ # } -#@ # -#@ # set_routing_options -cut_out_covered_port CORE_ONLY -#@ # set_routing_options -internal_routing FALSE -#@ # set_routing_options -stick_routing FALSE -#@ # -#@ # ###puts "wdir = $wdir" -#@ # -#@ # set success [route66 -global -dontstop -dir $wdir] -#@ # -#@ # #clean tmp data if required: -#@ # if { $success == 1 } { -#@ # if [catch {string toupper $route_global_keep_tmp_data} result] { -#@ # #variable is not defined -#@ # ###puts "result_1 = $result => removing dir ..." -#@ # catch { file delete -force $wdir } -#@ # } else { -#@ # #variable is set to FALSE -#@ # if { [string compare $result "TRUE"] != 0} { -#@ # ###puts "result_2 = $result => removing dir ..." -#@ # catch { file delete -force $wdir } -#@ # } -#@ # } -#@ # } -#@ # -#@ # set rt66_dont_lock_dir FALSE -#@ # return 1 -#@ #} -#@ #define_proc_attributes route_global -hidden -#@ -#@ #/* Aliases added for report command */ -#@ alias report_clock_constraint "report_timing -path end -to all_registers(-data_pins)" -#@ alias report_clock_fanout "report_transitive_fanout -clock_tree" -#@ alias report_clocks report_clock -#@ alias report_synthetic report_cell -#@ -#@ # Alias added for Ultra backward compatibility mode -#@ alias set_ultra_mode set_ultra_optimization -#@ -#@ # alias for write_sge and menu item in DA for db2sge -#@ -#@ #if { [string compare $dc_shell_mode "tcl"] == 0 } { -#@ # set db2sge_script ${synopsys_root}/admin/setup/.dc_write_sge.tcl -#@ #} else { -#@ # set db2sge_script ${synopsys_root}/admin/setup/.dc_write_sge -#@ #} -#@ -#@ #set db2sge_command ${synopsys_root}/${sh_arch}/syn/bin/db2sge -#@ set view_script_submenu_items "\"DA to SGE Transfer\" write_sge" -#@ -#@ -#@ if { $synopsys_program_name != "lc_shell"} { -#@ # read schematic annotation setup file -#@ #source ${synopsys_root}/admin/setup/.dc_annotate -#@ -#@ # setup the default layer settings -#@ #source ${synopsys_root}/admin/setup/.dc_layers -#@ -#@ if {$synopsys_program_name != "dc_sms_shell"} { -#@ source ${synopsys_root}/admin/setup/.dc_name_rules -#@ } -#@ } else { -#@ #for read_lib -html -#@ source ${synopsys_root}/auxx/syn/lc/read_lib_html_msg_list.tcl -#@ } -#@ # -- Starting source /tools/synopsys/synthesis/j201409sp3/auxx/syn/lc/read_lib_html_msg_list.tcl - -#@ ############################################################################## -#@ # message ID and descriptions for read_lib -html -#@ ############################################################################## -#@ set read_lib_ccs_noise_msg { -#@ LBDB-660 -#@ LBDB-706 -#@ LBDB-708 -#@ LBDB-709 -#@ LBDB-710 -#@ LBDB-711 -#@ LBDB-712 -#@ LBDB-713 -#@ LBDB-714 -#@ LBDB-715 -#@ LBDB-716 -#@ LBDB-717 -#@ LBDB-718 -#@ LBDB-733 -#@ LBDB-734 -#@ LBDB-784 -#@ LBDB-824 -#@ LBDB-825 -#@ LBDB-858 -#@ LBDB-898 -#@ LBDB-899 -#@ LBDB-908 -#@ LBDB-920 -#@ LBDB-935 -#@ LBDB-936 -#@ LBDB-937 -#@ LBDB-938 -#@ LBDB-939 -#@ } -#@ # -- End source /tools/synopsys/synthesis/j201409sp3/auxx/syn/lc/read_lib_html_msg_list.tcl - -#@ -#@ if { $synopsys_program_name == "psyn_gui"} { -#@ # read RouteCompiler GUI file for timing critical pathes. -#@ source ${synopsys_root}/auxx/syn/route_gui/write_route_timing_path.tcl -#@ } -#@ -#@ # Set physopt_dw_opto to false -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ set physopt_dw_opto FALSE -#@ } -#@ -#@ #/* Read budgeting setup script */ -#@ -#@ if { [string compare $dc_shell_mode "default"] == 0 } { -#@ -#@ # Need a encrypted file in Tcl format for budget.setup.et -#@ if { $sh_arch != "msvc50" && $sh_arch != "alpha_nt" } { -#@ # source -e synopsys_root + "/admin/setup/budget.setup.et" -#@ } -#@ } -#@ -#@ if { $synopsys_program_name == "icc_shell"} { -#@ source $synopsys_root/auxx/syn/.icc_procs.tcl -#@ source -encrypted $synopsys_root/auxx/syn/cts/fast_atomic_cts.tcl.e -#@ } -#@ -#@ if { $synopsys_program_name == "icc_shell"} { -#@ alias report_scenario report_scenarios -#@ } -#@ -#@ # floorplanning preferences globals -#@ global fp_snap_type -#@ -#@ set fp_snap_type(port) wiretrack -#@ set fp_snap_type(cell) litho -#@ set fp_snap_type(pin) wiretrack -#@ set fp_snap_type(movebound) litho -#@ set fp_snap_type(port_shape) wiretrack -#@ set fp_snap_type(wiring_keepout) wiretrack -#@ set fp_snap_type(placement_keepout) litho -#@ set fp_snap_type(net_shape) wiretrack -#@ set fp_snap_type(route_shape) wiretrack -#@ set fp_snap_type(none) litho -#@ -#@ # STAR 9000615813. PWR-18 is no longer internally suppressed. -#@ # Instead call tcl suppress_message so that it can be unsuppressed by users in -#@ # command line if needed -#@ suppress_message PWR-18 -#@ -#@ # alias for write_sge is always the last line of the setup file -#@ #if { [string compare $dc_shell_mode "tcl"] == 0 } { -#@ # alias write_sge "source db2sge_script" -#@ #} else { -#@ # alias write_sge "include db2sge_script" -#@ #} -#@ -#@ if { $dc_shell_mode == "tcl" } { -#@ # Configure Execute script dialog to display .tcl files -#@ set view_execute_script_suffix "$view_execute_script_suffix .tcl" -#@ } -#@ -#@ # -#@ # Shirley Lu 5/15/2007 -#@ # -#@ # Invoke NCX validation/correlation/fomatter from lc_shell: -#@ # -#@ # UNIX shell: -#@ # setenv SYNOPSYS_NCX_ROOT /mydisk/ncx_2007.06 -#@ # -#@ -#@ if {[info exists env(SYNOPSYS_NCX_ROOT)]} { -#@ -#@ set ncx_path $env(SYNOPSYS_NCX_ROOT)/ncx/${sh_arch}/bin -#@ -#@ # -#@ # check_ccs_lib -#@ # use libchecker under $ncx_path defined above -#@ # Disable this command since 2010.12-SP3 (should be done in 2010.12 release) -#@ #proc check_ccs_lib {args} { -#@ # global ncx_path -#@ # set cmdStr [linsert $args 0 ${ncx_path}/libchecker -lc_shell] -#@ # set cmd [open "| $cmdStr 2>@ stdout"] -#@ # catch { -#@ # while {[gets $cmd info] >= 0} { -#@ # echo $info -#@ # } -#@ # } -#@ # if {[catch {close $cmd} msg]} { -#@ # } -#@ #} -#@ -#@ # -#@ # format_lib -#@ # use ncx under $ncx_path defined above -#@ # Disable format_lib command in 2014.09 release -- xwwang, 7/25/2014 -#@ #proc format_lib {args} { -#@ # global ncx_path -#@ # echo "Warning: format_lib command is scheduled to become obsolete in a future production release." -#@ # set cmdStr [linsert $args 0 ${ncx_path}/ncx -lc_shell] -#@ # set cmd [open "| $cmdStr 2>@ stdout"] -#@ # catch { -#@ # while {[gets $cmd info] >= 0} { -#@ # echo $info -#@ # } -#@ # } -#@ # if {[catch {close $cmd} msg]} { -#@ # } -#@ #} -#@ -#@ } -#@ -#@ proc get_nglc_search_path { } { -#@ set exec_path "invalid" -#@ if {[info exists ::env(SYNOPSYS_LC_ROOT)] && [file exists $::env(SYNOPSYS_LC_ROOT)/$::sh_arch/lc/bin/lc_shell_exec]} { -#@ set exec_path $::env(SYNOPSYS_LC_ROOT)/$::sh_arch/lc/bin/lc_shell_exec -#@ } -#@ -#@ return $exec_path -#@ } -#@ -#@ proc get_libra_synopsys_root { } { -#@ return [file dirname [file dirname [file dirname [file dirname $::nglc_search_path] ] ] ] -#@ } -#@ -#@ proc valias {v_orig v_alias} { -#@ uplevel 1 "upvar 0 $v_orig $v_alias" -#@ } -#@ -#@ set nglc_result_path "/tmp" -#@ set nglc_replay_tcl_file "nglc_shell_command.tcl" -#@ set nglc_search_path [get_nglc_search_path] -#@ set lc_run_from_legacy_library_compiler "true" -#@ set nglc_is_none_tech_file "false" -#@ set nglc_keep_nglc_temp_files "false" -#@ set nglc_intermediate_db_files "" -#@ set nglc_log_path "" -#@ set lc_enable_legacy_library_compiler "false" -#@ -#@ valias lc_enable_legacy_library_compiler lc_enable_common_shell_lc -#@ -#@ proc nglc_read_lib { args } { -#@ common_shell_read_lib $args -#@ } -#@ -#@ -#@ proc common_shell_read_lib {args } { -#@ set_folder_var -#@ set tcl_file "$::nglc_result_path/$::nglc_log_path/$::nglc_replay_tcl_file" -#@ set chan [open $tcl_file a] -#@ export_tcl_var $chan -#@ gen_nglc_read_lib_procedure $chan $args -#@ close $chan -#@ run_libra_with_echo $tcl_file -#@ common_shell_read_dbs -#@ set_none_tech_file -#@ } -#@ -#@ # create the unique folder under tmp -#@ proc set_folder_var { } { -#@ set fileName [pid] -#@ set ::nglc_log_path [append fileName "_" [clock microseconds]] -#@ file delete -force $::nglc_result_path/$::nglc_log_path -#@ file mkdir $::nglc_result_path/$::nglc_log_path -#@ } -#@ -#@ # export all the vars -#@ proc export_tcl_var { fileName } { -#@ foreach var [info vars ::* ] { -#@ if [array exists $var] { -#@ continue; -#@ } -#@ puts $fileName "set $var \[list [set $var]\]" -#@ } -#@ } -#@ -#@ # excuted by libra shell to read the dbs generated by common_shell -#@ proc common_shell_read_dbs { } { -#@ set dbNames "" -#@ foreach var [glob -nocomplain -directory $::nglc_result_path/$::nglc_log_path *.db] { -#@ append dbNames " " $var -#@ } -#@ set ::nglc_intermediate_db_files $dbNames -#@ } -#@ -#@ # display the log file genrated by common_shell in Libra and then remove the unique folder -#@ proc common_shell_clean_up { } { -#@ if { $::nglc_keep_nglc_temp_files == "false" } { -#@ file delete -force $::nglc_result_path/$::nglc_log_path -#@ } -#@ } -#@ -#@ proc gen_nglc_read_lib_procedure { fileName args} { -#@ puts $fileName "##@@@## gen_common_shell_read_lib" -#@ puts $fileName "eval [lindex [lindex $args 0] 0]" -#@ puts $fileName "##@@@##" -#@ puts $fileName "set lc_write_view_db_file false" -#@ puts $fileName "set librs \[get_libs\]" -#@ puts $fileName "for {set i 0} {\$i < \[ sizeof \$librs \]} {incr i 1} {" -#@ puts $fileName " set lib \[index_collection \$librs \$i]" -#@ puts $fileName " redirect -var a \"query_object \$lib\" " -#@ puts $fileName " if \[regexp {{(\")?(gtech)(\")?}} \$a\] { " -#@ puts $fileName " } elseif \[regexp {{(\")?(standard.sldb)(\")?}} \$a] { " -#@ puts $fileName " } else {" -#@ puts $fileName " regexp {{(\")?(\[^\"\]*)(\")?}} \$a b c d e " -#@ puts $fileName " write_lib \$d -o \$nglc_result_path/\$nglc_log_path/\$d.db" -#@ puts $fileName " }" -#@ puts $fileName "}" -#@ puts $fileName "exit" -#@ } -#@ -#@ proc set_none_tech_file { } { -#@ if { [file exists $::nglc_result_path/$::nglc_log_path/is_non_tech_file] } { -#@ set ::nglc_is_none_tech_file true; -#@ } else { -#@ set ::nglc_is_none_tech_file false; -#@ } -#@ } -#@ -#@ proc run_libra_with_echo {tcl_file} { -#@ set chan [open "|$::nglc_search_path -r [get_libra_synopsys_root] -f $tcl_file" r] -#@ # things to do: In debug mode, we want copy the whole output (beginning to end) -#@ # to a file -#@ if {$::nglc_keep_nglc_temp_files} { -#@ set log [open $::nglc_result_path/$::nglc_log_path/libra.log w] -#@ } -#@ set echo 0 -#@ set firstLine true -#@ while {[gets $chan line] >= 0} { -#@ if {$::nglc_keep_nglc_temp_files} { puts $log $line } -#@ if {[string equal -length 7 $line "##@@@##"]} { -#@ set echo [expr ! $echo] -#@ continue; -#@ } -#@ if {$echo} { -#@ if { $firstLine } { -#@ set firstLine false -#@ continue; -#@ } else { -#@ puts $line -#@ } -#@ } -#@ } -#@ close $chan -#@ if {$::nglc_keep_nglc_temp_files} { -#@ close $log -#@ } -#@ } -#@ -#@ # -- End source /tools/synopsys/synthesis/j201409sp3/admin/setup/.synopsys_dc.setup - -source -echo -verbose /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/rf2_256x19_wm0/../convert_lib_to_db.tcl -#@ # -- Starting source /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/rf2_256x19_wm0/../convert_lib_to_db.tcl - -#@ set SOURCE_FILES [glob *.lib] -#@ foreach FILE ${SOURCE_FILES} { -#@ read_lib $FILE -#@ redirect -variable CURR_LIB {get_lib} -#@ -#@ set CURR_LIB [string range $CURR_LIB 2 end-3] -#@ set CURR_LIB [lindex $CURR_LIB 0] -#@ set FILENAME [string range $FILE 0 end-4] -#@ write_lib $CURR_LIB -output ${FILENAME}.db -#@ remove_lib $CURR_LIB -#@ } -#@ -#@ exit diff --git a/hw/models/memory/cln28hpm/rf2_32x128_wm1/command.log b/hw/models/memory/cln28hpm/rf2_32x128_wm1/command.log deleted file mode 100644 index fded0a8b..00000000 --- a/hw/models/memory/cln28hpm/rf2_32x128_wm1/command.log +++ /dev/null @@ -1,3759 +0,0 @@ -#@ # -#@ # Running lc_shell Version J-2014.09-SP3 for amd64 -- Jan 19, 2015 -#@ # Date: Mon Oct 28 14:40:20 2019 -#@ # Run by: lzhu308@gtcad-srv1 -#@ - -source /tools/synopsys/synthesis/j201409sp3/admin/setup/.synopsys_dc.setup -#@ # -- Starting source /tools/synopsys/synthesis/j201409sp3/admin/setup/.synopsys_dc.setup - -#@ # -#@ # ".synopsys_dc.setup" Initialization File for -#@ # -#@ # Dc_Shell and Design_Analyzer -#@ # -#@ # The variables in this file define the behavior of many parts -#@ # of the Synopsys Synthesis Tools. Upon installation, they should -#@ # be reviewed and modified to fit your site's needs. Each engineer -#@ # can have a .synopsys file in his/her home directory or current -#@ # directory to override variable settings in this file. -#@ # -#@ # Each logical grouping of variables is commented as to their -#@ # nature and effect on the Synthesis Commands. Examples of -#@ # variable groups are the Compile Variable Group, which affects -#@ # the designs produced by the COMPILE command, and the Schematic -#@ # Variable Group, which affects the output of the create_schematic -#@ # command. -#@ # -#@ # You can type "man _variables" in dc_shell or -#@ # design_analyzer to get help about a group of variables. -#@ # For instance, to get help about the "system" variable group, -#@ # type "help system_variables". You can also type -#@ # "man ", to get help on the that variable's -#@ # group. -#@ # -#@ -#@ # System variables -#@ set sh_command_abbrev_mode "Anywhere" -#@ set sh_continue_on_error "true" -#@ update_app_var -default true sh_continue_on_error -#@ set sh_enable_page_mode "true" -#@ update_app_var -default true sh_enable_page_mode -#@ set sh_source_uses_search_path "true" -#@ update_app_var -default true sh_source_uses_search_path -#@ if {$synopsys_program_name == "dc_shell" || $synopsys_program_name == "de_shell" || $synopsys_program_name == "dc_sms_shell" } { -#@ set sh_new_variable_message "false" -#@ update_app_var -default false sh_new_variable_message -#@ } else { -#@ set sh_new_variable_message "true" -#@ update_app_var -default true sh_new_variable_message -#@ } -#@ -#@ if {$synopsys_program_name == "dc_shell"} { -#@ set html_log_enable "false" -#@ set html_log_filename "default.html" -#@ } -#@ -#@ if {$synopsys_program_name == "de_shell"} { -#@ set de_log_html_filename "default.html" -#@ } -#@ -#@ if { [string compare $dc_shell_mode "tcl"] == 0 } { -#@ set sh_enable_line_editing "true" -#@ set sh_line_editing_mode "emacs" -#@ } -#@ -#@ if {$synopsys_program_name == "icc_shell"} { -#@ if {"$sh_output_log_file" == ""} { -#@ set sh_output_log_file "icc_output.txt" -#@ } -#@ -#@ ## the variable sh_redirect_progress_messages only makes it possible -#@ ## for some commands to redirect progress messages to the log file,thereby -#@ ## bypassing the console and reducing the volume of messages on the console. -#@ set sh_redirect_progress_messages true -#@ } -#@ -#@ -#@ # Suppress new variable messages for the following variables -#@ array set auto_index {} -#@ set auto_oldpath "" -#@ -#@ # Enable customer support banner on fatal -#@ if { $sh_arch == "linux" || $sh_arch == "amd64" || $sh_arch == "suse32" || $sh_arch == "suse64" || $sh_arch == "sparcOS5" || $sh_arch == "sparc64" || $sh_arch == "x86sol32" || $sh_arch == "x86sol64" || $sh_arch == "rs6000" || $sh_arch == "aix64" } { -#@ setenv SYNOPSYS_TRACE "" -#@ } -#@ -#@ # -#@ # Load the procedures which make up part of the user interface. -#@ # -#@ if { [string compare $dc_shell_mode "tcl"] == 0 } { -#@ source $synopsys_root/auxx/syn/.dc_common_procs.tcl -#@ if {$synopsys_program_name != "dc_sms_shell"} { -#@ source $synopsys_root/auxx/syn/.dc_procs.tcl -#@ } -#@ alias list_commands help -#@ } -#@ # -- Starting source /tools/synopsys/synthesis/j201409sp3/auxx/syn/.dc_common_procs.tcl - -#@ ############################################################################## -#@ # -#@ # -#@ # FILE: auxx/syn/.dc_common_procs.tcl -#@ # -#@ # ABSTRACT: These procedures are part of the PrimeTime and DC -#@ # user interface. -#@ # They are loaded by .synopsys_pt.setup and .synopsys_dc.setup. -#@ # -#@ ############################################################################## -#@ # -#@ # -#@ -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: group_variable -#@ # -#@ # ABSTRACT: Add a variable to the specified variable group. -#@ # This command is typically used by the system -#@ # administrator only. -#@ # -#@ # Below the proc is the command which creates the command -#@ # help information and semantic data for the argument. -#@ # -#@ # RETURNS: 1 if it is successful. -#@ # error code if the variable does not exist. -#@ # error code of the variable is already in the group. -#@ # -#@ # SYNTAX: group_variable group_name variable_name -#@ # -#@ ############################################################################## -#@ # -#@ -#@ -#@ proc group_variable { args } { -#@ global _Variable_Groups -#@ -#@ parse_proc_arguments -args $args resarr -#@ set group $resarr(group) -#@ set var $resarr(variable_name) -#@ -#@ if { ![info exists _Variable_Groups($group)] } { -#@ set _Variable_Groups($group) "" -#@ } -#@ -#@ # Verify that var exists as a global variable -#@ -#@ set cmd "uplevel #0 \{info exists $var\}" -#@ if { ![eval $cmd] } { -#@ return -code error "Variable '$var' is not defined." -#@ } -#@ -#@ # Only add it if it's not already there -#@ -#@ if { [lsearch $_Variable_Groups($group) $var] == -1 } { -#@ lappend _Variable_Groups($group) $var -#@ } -#@ -#@ return 1 -#@ } -#@ -#@ define_proc_attributes group_variable -info "Add a variable to a variable group" -command_group "Builtins" -permanent -dont_abbrev -define_args { -#@ {group "Variable group name" group} -#@ {variable_name "Variable name" variable_name}} -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: print_variable_group -#@ # -#@ # ABSTRACT: Shows variables and their values defined in the given group. -#@ -#@ # -#@ # Below the proc is the command which creates the command -#@ # help information and semantic data for the argument. -#@ # -#@ # RETURNS: 1 if it is successful. -#@ # error code of the variable group does not exist. -#@ # -#@ # SYNTAX: print_variable_group group_name -#@ # -#@ ############################################################################## -#@ # -#@ -#@ proc print_variable_group { args } { -#@ global _Variable_Groups -#@ -#@ parse_proc_arguments -args $args resarr -#@ set group $resarr(group) -#@ -#@ if { [string compare $group "all"] == 0 } { -#@ set cmd "uplevel #0 \{printvar\}" -#@ return [eval $cmd] -#@ } -#@ -#@ if { ![info exists _Variable_Groups($group)] } { -#@ return -code error "Variable group '$group' does not exist." -#@ } -#@ -#@ # Print out each global variable in the list. To be totally bulletproof, -#@ # test that each variable in the group is still defined. If not, remove -#@ # it from the list. -#@ -#@ foreach var [lsort $_Variable_Groups($group)] { -#@ set cmd "uplevel #0 \{info exists $var\}" -#@ if { ![eval $cmd] } { -#@ # Remove it -#@ set n [lsearch $_Variable_Groups($group) $var] -#@ set $_Variable_Groups($group) [lreplace $_Variable_Groups($group) $n $n] -#@ } else { -#@ # Print it. -#@ set cmd "uplevel #0 \{set $var\}" -#@ set val [eval $cmd] -#@ echo [format "%-25s = \"%s\"" $var $val] -#@ } -#@ } -#@ -#@ return 1 -#@ } -#@ -#@ define_proc_attributes print_variable_group -info "Print the contents of a variable group" -command_group "Builtins" -permanent -define_args {{group "Variable group name" group}} -#@ -#@ -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: _Variable_Groups_Get_Groups -#@ # -#@ # ABSTRACT: Return a list of all variable groups. This command is hidden -#@ # and is used by Design Vision. -#@ # -#@ # RETURNS: Tcl list of all variable groups including group all -#@ # -#@ # SYNTAX: _Variable_Groups_Get_Groups -#@ ############################################################################## -#@ # -#@ -#@ proc _Variable_Groups_Get_Groups { } { -#@ global _Variable_Groups -#@ -#@ set groups [array names _Variable_Groups] -#@ append groups " all" -#@ return $groups -#@ } -#@ define_proc_attributes _Variable_Groups_Get_Groups -hidden -#@ -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: _Variable_Groups_Get_Variables_Of_Group -#@ # -#@ # ABSTRACT: Return a list of all variables of a variable group. -#@ # It also works for pseudo group all. -#@ # -#@ # RETURNS: Tcl list of all variables of a variable group including -#@ # pseudo group all -#@ # -#@ # SYNTAX: _Variable_Groups_Get_Groups -#@ ############################################################################## -#@ # -#@ -#@ proc _Variable_Groups_Get_Variables_Of_Group { group } { -#@ global _Variable_Groups -#@ -#@ if { [string compare $group "all"] == 0 } { -#@ set itr [array startsearch _Variable_Groups] -#@ for { } { [array anymore _Variable_Groups $itr]} { } { -#@ set index [array nextelement _Variable_Groups $itr] -#@ append vars $_Variable_Groups($index) -#@ } -#@ array donesearch _Variable_Groups $itr -#@ return $vars -#@ } -#@ -#@ if { ![info exists _Variable_Groups($group)] } { -#@ return -code error "Variable group '$group' does not exist." -#@ } -#@ -#@ # Test if all variables in the list of variables are still defined. -#@ # Remove not existing variables. -#@ foreach var [lsort $_Variable_Groups($group)] { -#@ set cmd "uplevel #0 \{info exists $var\}" -#@ if { ![eval $cmd] } { -#@ # Remove it -#@ set n [lsearch $_Variable_Groups($group) $var] -#@ set $_Variable_Groups($group) [lreplace $_Variable_Groups($group) $n $n] -#@ } -#@ } -#@ return $_Variable_Groups($group) -#@ } -#@ define_proc_attributes _Variable_Groups_Get_Variables_Of_Group -hidden -#@ -#@ # -- End source /tools/synopsys/synthesis/j201409sp3/auxx/syn/.dc_common_procs.tcl - -#@ # -- Starting source /tools/synopsys/synthesis/j201409sp3/auxx/syn/.dc_procs.tcl - -#@ ############################################################################## -#@ # -#@ # -#@ # FILE: auxx/syn/.dc_procs.tcl -#@ # -#@ # ABSTRACT: These procedures are part of the Design Compiler Tcl -#@ # user interface. -#@ # They are loaded by .synopsys_dc.setup. -#@ # -#@ ############################################################################## -#@ # -#@ # -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: read_verilog -#@ # -#@ # ABSTRACT: Emulate PT's read_verilog command in DC: -#@ # -#@ # Usage: read_verilog # Read one or more verilog files -#@ # *[-hdl_compiler] (Use HDL Compiler (ignored)) -#@ # file_names (Files to read) -#@ # -#@ # Modified: Bharat 11/17/99. Use uplevel to ensure that the command -#@ # sees user/hidden variables from the top level. Star 92970. -#@ # -#@ # Modified: Evan Rosser, 12/5/01. Support -netlist and -rtl flags. -#@ # -#@ ############################################################################## -#@ # -#@ -#@ if { $synopsys_program_name != "icc_shell" } { -#@ proc read_verilog { args } { -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {read_file -format verilog %s %s [list %s]} [array names ra -rtl] [array names ra -netlist] $ra(file_names)] -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes read_verilog -info " Read one or more verilog files" -permanent -define_args { -#@ {file_names "Files to read" file_names list required} -#@ {-netlist "Use structural Verilog netlist reader" "" boolean optional} -#@ {-rtl "Use RTL Verilog compiler (Presto or HDLC)" "" boolean optional} -#@ {-hdl_compiler "Use HDL Compiler (ignored)" "" boolean {hidden optional}} -#@ } -#@ } -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: read_sverilog -#@ # -#@ # ABSTRACT: Emulate PT's read_sverilog command in DC: -#@ # -#@ # Usage: read_sverilog # Read one or more systemverilog files -#@ # *[-hdl_compiler] (Use HDL Compiler (ignored)) -#@ # file_names (Files to read) -#@ # -#@ # Modified: Yong Xiao, 01/31/2003: Copied from read_verilog to support -#@ # systemverilog input. -#@ # -#@ ############################################################################## -#@ # -#@ -#@ proc read_sverilog { args } { -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {read_file -format sverilog %s %s [list %s]} [array names ra -rtl] [array names ra -netlist] $ra(file_names)] -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes read_sverilog -info " Read one or more systemverilog files" -permanent -define_args { -#@ {file_names "Files to read" file_names list required} -#@ {-netlist "Use structural Verilog netlist reader" "" boolean optional} -#@ {-rtl "Use RTL Systemverilog compiler (Presto or HDLC)" "" boolean optional} -#@ {-hdl_compiler "Use HDL Compiler (ignored)" "" boolean {hidden optional}} -#@ } -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: read_vhdl -#@ # -#@ # ABSTRACT: Emulate PT's read_vhdl command in DC: -#@ # -#@ # Usage: read_vhdl # Read one or more vhdl files -#@ # file_names (Files to read) -#@ # -#@ # -#@ ############################################################################## -#@ # -#@ -#@ proc read_vhdl { args } { -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {read_file -format vhdl %s [list %s]} [array names ra -netlist] $ra(file_names)] -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes read_vhdl -info " Read one or more vhdl files" -permanent -define_args { -#@ {file_names "Files to read" file_names list required} -#@ {-netlist "Use structural VHDL netlist reader" "" boolean optional} -#@ } -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: read_db -#@ # -#@ # ABSTRACT: Emulate PT's read_db command in DC: -#@ # -#@ # Usage: -#@ # read_db # Read one or more db files -#@ # *[-netlist_only] (Do not read any attributes from db (ignored)) -#@ # *[-library] (File is a library DB (ignored)) -#@ # file_names (Files to read) -#@ # -#@ # -#@ ############################################################################## -#@ # -#@ -#@ proc read_db { args } { -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {read_file -format db [list %s]} $ra(file_names)] -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes read_db -info " Read one or more db files" -permanent -define_args { -#@ {file_names "Files to read" file_names list required} -#@ {-netlist_only "Do not read any attributes from db (ignored)" "" boolean {hidden optional}} -#@ {-library "File is a library DB (ignored)" "" boolean {hidden optional}} -#@ } -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: read_edif -#@ # -#@ # ABSTRACT: Emulate PT's read_edif command in DC: -#@ # -#@ # Usage: -#@ # read_edif # Read one or more edif files -#@ # *[-complete_language] (Use ptxr to read the file (ignored)) -#@ # file_names (Files to read) -#@ # -#@ # -#@ ############################################################################## -#@ # -#@ proc read_edif { args } { -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {read_file -format edif [list %s]} $ra(file_names)] -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes read_edif -info " Read one or more edif files" -permanent -define_args { -#@ {file_names "Files to read" file_names list required} -#@ {-complete_language "Use ptxr to read the file (ignored)" "" boolean {hidden optional}} -#@ } -#@ -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: read_ddc -#@ # -#@ # ABSTRACT: Shorthand for "read_file -format ddc": -#@ # -#@ # Usage: -#@ # read_ddc # Read one or more ddc files -#@ # *[-scenarios] only read constraints for specified scenarios -#@ # *[-active_scenarios] only activate the specified scenarios -#@ # file_names (Files to read) -#@ # -#@ # -#@ ############################################################################## -#@ # -#@ -#@ proc read_ddc { args } { -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd "read_file -format ddc" -#@ if { [ info exists ra(-scenarios) ] } { -#@ set cmd "$cmd -scenarios { $ra(-scenarios) }" -#@ } -#@ if { [ info exists ra(-active_scenarios) ] } { -#@ set cmd "$cmd -active_scenarios { $ra(-active_scenarios) }" -#@ } -#@ set cmd "$cmd { $ra(file_names) }" -#@ return [uplevel \#0 $cmd] -#@ } -#@ -#@ define_proc_attributes read_ddc -info "Read one or more ddc files" -permanent -define_args { -#@ {file_names "Files to read" file_names list required} -#@ {-scenarios "list of scenarios to be read from ddc file" -#@ scenario_list list optional} -#@ {-active_scenarios "list of scenarios to be made active" -#@ active_scenario_list list optional}} -#@ -#@ -#@ -#@ ############################################################################## -#@ # -#@ # PROCEDURE: source_tcl_file -#@ # -#@ # ABSTRACT: generic procedure to source another tcl file -#@ # -#@ # Arguments: -#@ # filename tcl filename -#@ # dir directory to check for file -#@ # msg verbose message -#@ # verbose verbose mode -#@ # -#@ # Usage: -#@ # -#@ ############################################################################## -#@ # -#@ proc source_tcl_file { filename dir msg {verbose 1} } { -#@ set __qual_pref_file [file join $dir $filename] -#@ if {[file exists $__qual_pref_file]} { -#@ if { $verbose } { -#@ echo $msg $__qual_pref_file -#@ } -#@ # use catch to recover from errors in the pref file -#@ echo_trace "Sourcing " $__qual_pref_file -#@ # to speed up sourcing use read and eval -#@ set f [open $__qual_pref_file] -#@ if {[catch {namespace eval :: [read -nonewline $f]} __msg]} { -#@ echo Error: Error during sourcing of $__qual_pref_file -#@ if {$__msg != ""} { echo $__msg } -#@ # actually, it looks like $__msg is always null after -#@ # source fails -#@ } -#@ close $f -#@ } else { -#@ echo_trace "Info: File '" $__qual_pref_file "' does not exist!" -#@ } -#@ } -#@ define_proc_attributes source_tcl_file -hidden -#@ -#@ -#@ -#@ ############################################################################## -#@ # -#@ # PROCEDURE: echo_trace -#@ # -#@ # ABSTRACT: echo only in trace modus -#@ # -#@ ############################################################################## -#@ # -#@ proc echo_trace { args } { -#@ if { [info exists ::env(TCL_TRACE)] } { -#@ echo TRACE\> [join $args "" ] -#@ } -#@ } -#@ define_proc_attributes echo_trace -hidden -#@ -#@ ############################################################################# -#@ # -#@ # Following procedures added for PC write_script -#@ # -#@ # -#@ # -#@ ############################################################################ -#@ -#@ proc set_cell_restriction { args } { -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {set_attribute %s -type integer restrictions %s } $ra(cell) $ra(value)] -#@ return [uplevel #0 $cmd] -#@ -#@ } -#@ define_proc_attributes set_cell_restriction -hidden -define_args { {cell "cell_name" cell string required} {value "value" value string required} } -#@ -#@ -#@ proc set_cell_soft_keepout {args} { -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {set_keepout_margin -type soft -outer {%d %d %d %d} [list %s] } $ra(llx) $ra(lly) $ra(urx) $ra(ury) $ra(objects)] -#@ return [uplevel #0 $cmd] -#@ -#@ -#@ } -#@ -#@ define_proc_attributes set_cell_soft_keepout -hidden -define_args { {llx "llx" llx float required} {lly "lly" lly float required} {urx "urx" urx float required} {ury "ury" ury float required} {objects "objects" objects list required} } -#@ -#@ proc set_cell_hard_keepout {args} { -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {set_keepout_margin -type soft -outer {%d %d %d %d} [list %s] } $ra(llx) $ra(lly) $ra(urx) $ra(ury) $ra(objects)] -#@ return [uplevel #0 $cmd] -#@ -#@ -#@ } -#@ -#@ define_proc_attributes set_cell_hard_keepout -hidden -define_args { {llx "llx" llx float required} {lly "lly" lly float required} {urx "urx" urx float required} {ury "ury" ury float required} {objects "objects" objects list required} } -#@ -#@ set mw_use_pdb_lib_format false -#@ -#@ ############################################################################## -#@ # -#@ # PROCEDURE: write_milkyway -#@ # -#@ # ABSTRACT: wrapper around save_mw_cel to support original write_milkyway -#@ # interface -#@ # if { [info commands open_mw_cel] == "open_mw_cel" } {} -#@ # -#@ ############################################################################## -#@ -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ -#@ proc write_milkyway args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {save_mw_cel -as %s %s %s %s %s} $ra(-output) [array names ra -overwrite] [array names ra -create] [array names ra -all] [array names ra -dps]] -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes write_milkyway -hidden -info " Saves the design as milkyway CEL" -define_args {{-output fileName "Name" string {optional}} {-overwrite "Overwrite the current version" "" boolean {optional}} {-create "Create from scratch" "" boolean {hidden optional}} {-all "Save all modified cells" "" boolean {hidden optional}} {-dps "Save internal DPS design" "" boolean {hidden optional}}} -#@ -#@ ############################################################################## -#@ # -#@ # PROCEDURE: read_milkyway -#@ # -#@ # ABSTRACT: wrapper around open_mw_cel to support original read_milkyway -#@ # interface -#@ # MODIFIED: To support DPS in Galileo we need to pass the filtering -#@ # parameters to the DPS command. (Pankaj Goswami, Mar09 2005) -#@ # -#@ ############################################################################## -#@ -#@ proc read_milkyway args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {open_mw_cel %s} $ra() ] -#@ -#@ if {[info exists ra(-library)]} { -#@ set cmd [concat [concat $cmd " -library " ] " $ra(-library) "] -#@ } -#@ -#@ if {[info exists ra(-read_only)]} { -#@ lappend cmd {-readonly} -#@ } -#@ -#@ # DPS specific stuff -#@ set dps_cmd "vh_set_current_partition " -#@ set read_mw_with_dps_filter false -#@ -#@ if {[info exists ra(-vh_module_only)]} { -#@ append dps_cmd "-vh_module_only " -#@ set read_mw_with_dps_filter true -#@ } -#@ -#@ if {[info exists ra(-vh_include)]} { -#@ append dps_cmd [concat " -vh_include " " \{ $ra(-vh_include) \}"] -#@ append dps_cmd " " -#@ set read_mw_with_dps_filter true -#@ } -#@ -#@ if {[info exists ra(-vh_exclude)]} { -#@ append dps_cmd [concat " -vh_exclude" " \{ $ra(-vh_exclude) \}"] -#@ set read_mw_with_dps_filter true -#@ } -#@ -#@ if { $read_mw_with_dps_filter == true } { -#@ # Call the DPS command to store the DPS filtering params. -#@ uplevel #0 $dps_cmd -#@ } else { -#@ # If there is no DPS filtering params, then we need to reset the -#@ # params which might have been stored from the provious command. -#@ append dps_cmd " -vh_reset_partition" -#@ uplevel #0 $dps_cmd -#@ } -#@ # End of DPS stuff -#@ -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes read_milkyway -hidden -info " Read milkyway CEL from disk" -define_args {{-library "library name" "lib_name" string {optional}} {-read_only "open design in read only mode" "" boolean {optional}} {-version "version number of the CEL" "number" string {optional}} {-vh_module_only "open design for DPS module only partition" "" boolean {hidden optional}} {-vh_include "list of designs to be included in the DPS partition" "include_designs" list {hidden optional}} {-vh_exclude "list of designs to be excluded in the DPS partition" "exclude_designs" list {hidden optional}} {"" fileName "CEL name" string {required}}} -#@ -#@ } -#@ -#@ ############################################################################## -#@ # -#@ # PROCEDURE: set_mw_technology_file -#@ # -#@ # ABSTRACT: wrapper around update_mw_lib -#@ # -#@ # HISTORY : 2009/6/21, yunz, support ALF reader in ICC -#@ # -#@ ############################################################################## -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] || -#@ ([string match -nocase {*d[ce]_shell*} $synopsys_program_name] && [shell_is_mwlib_enabled]) } { -#@ -#@ proc set_mw_technology_file args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd "" -#@ set lib_name "" -#@ set pdb_file "tech.pdb" -#@ set log_file "log_file" -#@ set alf_file "" -#@ -#@ if {[info exists ra(-technology)] && [info exists ra(-plib)]} { -#@ echo "Error: the $ra(-technology) and $ra(-plib) options are mutually exclusive." -#@ return [uplevel #0 $cmd] -#@ } elseif {[info exists ra(-technology)] && [info exists ra(-alf)]} { -#@ echo "Error: the $ra(-technology) and $ra(-alf) options are mutually exclusive." -#@ return [uplevel #0 $cmd] -#@ } elseif {[info exists ra(-plib)] && [info exists ra(-alf)]} { -#@ echo "Error: the $ra(-plib) and $ra(-alf) options are mutually exclusive." -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ if {[info exists ra(-technology)]} { -#@ -#@ set cmd [format {update_mw_lib -technology %s %s} $ra(-technology) $ra() ] -#@ } -#@ -#@ if {[info exists ra(-plib)]} { -#@ -#@ set cmd [format {update_mw_lib %s} $ra() ] -#@ -#@ if {[string match -nocase {*.pdb} $ra(-plib) ] } { -#@ set cmd [concat [concat $cmd " -plib " ] " $ra(-plib) "] -#@ } -#@ if {[string match -nocase {*.plib} $ra(-plib) ] } { -#@ set subcmd [format {set lc_enable_legacy_library_compiler true;read_lib %s} $ra(-plib)] -#@ redirect -file log_file {uplevel #0 $subcmd} -#@ set f1 [open $log_file] -#@ while {[gets $f1 line] >= 0} { -#@ set msg1 [lindex $line 3] -#@ set msg2 [lindex $line 4] -#@ if {[string match {read} $msg1] && -#@ [string match {successfully} $msg2] } { -#@ set msg [lindex $line 2] -#@ set len [string length $msg] -#@ set lib_name [string range $msg 1 [expr $len-2] ] -#@ break -#@ } -#@ if {[string match {old} $msg1] && -#@ [string match {technology} $msg2] } { -#@ set msg [lindex $line 6] -#@ set len [string length $msg] -#@ set path [string range $msg 1 [expr $len-2] ] -#@ set name1 [lindex [split $path {/}] end] -#@ regexp {(.+?).pdb} $name1 match lib_name -#@ break -#@ } -#@ } -#@ if {$lib_name != ""} { -#@ set subcmd [format {write_lib %s -output %s} $lib_name $pdb_file] -#@ uplevel #0 $subcmd -#@ -#@ echo "Command is : " -#@ echo $cmd -#@ -#@ set cmd [concat [concat $cmd " -plib " ] " $pdb_file "] -#@ -#@ echo "Command is : " -#@ echo $cmd -#@ -#@ } else { -#@ echo "Error: Can not compile $ra(-plib) to pdb successfully" -#@ return 0; -#@ } -#@ } -#@ } -#@ if {[info exists ra(-alf)]} { -#@ -#@ set cmd [format {update_mw_lib %s} $ra() ] -#@ -#@ set cmd [concat [concat $cmd " -alf " ] " $ra(-alf) "] -#@ } -#@ -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes set_mw_technology_file -hide_body -info " Set technology file for the library " -define_args {{-technology "Technology file name" "tech_file" string {optional}} {-plib "Plib file name" "file_name" string {optional}} {-alf "alf file name" "file_name" string {optional}} {"" "Library name" "libName" string {required}}} -#@ -#@ ############################################################################## -#@ # -#@ # PROCEDURE: rebuild_mw_lib -#@ # -#@ # ABSTRACT: wrapper around update_mw_lib -#@ # -#@ ############################################################################## -#@ -#@ proc rebuild_mw_lib args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {update_mw_lib -rebuild %s} $ra() ] -#@ -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes rebuild_mw_lib -hide_body -info " Rebuild the library " -define_args {{"" "Library name" "libName" string {required}}} -#@ -#@ ############################################################################## -#@ # -#@ # PROCEDURE: set_mw_lib_reference -#@ # -#@ # ABSTRACT: Procedure to set ref lib list or ref ctrl file -#@ # -#@ ############################################################################## -#@ -#@ proc set_mw_lib_reference args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd "" -#@ -#@ if {[info exists ra(-mw_reference_library)]} { -#@ set cmd [format {set_reference_control_file -reference_libraries {%s} %s} $ra(-mw_reference_library) $ra() ] -#@ } -#@ -#@ if {[info exists ra(-reference_control_file)]} { -#@ set cmd [format {set_reference_control_file -file %s %s} $ra(-reference_control_file) $ra() ] -#@ } -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes set_mw_lib_reference -hide_body -info " Set reference for the library " -define_args {{-mw_reference_library "List of reference libraries" "lib_list" list {optional}} {-reference_control_file "Reference control file" "file_name" string {optional}} {"" "Library name" "libName" string {required}}} -#@ -#@ # -#@ ############################################################################## -#@ # -#@ # PROCEDURE: create_mw_lib -#@ # -#@ # ABSTRACT: wrapper around MWUI create_mw_lib -#@ # -#@ ############################################################################## -#@ -#@ proc create_mw_lib args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd "" -#@ set lib_name "" -#@ set pdb_file "tech.pdb" -#@ set log_file "log_file" -#@ -#@ if {[info exists ra(-ignore_case)]} { -#@ set cmd [format {org_create_mw_lib %s} $ra() ] -#@ } else { -#@ set cmd [format {org_create_mw_lib -case_sensitive %s} $ra() ] -#@ } -#@ -#@ if {[info exists ra(-technology)]} { -#@ set cmd [concat [concat $cmd " -technology " ] " $ra(-technology) "] -#@ } -#@ -#@ if {[info exists ra(-ignore_tf_error)]} { -#@ set cmd [concat $cmd " -ignore_tf_error " ] -#@ } -#@ -#@ if {[info exists ra(-hier_separator)]} { -#@ set cmd [concat [concat $cmd " -hier_seperator " ] " $ra(-hier_separator) "] -#@ } -#@ -#@ if {[info exists ra(-bus_naming_style)]} { -#@ set cmd [concat [concat $cmd " -bus_naming_style " ] " {$ra(-bus_naming_style)} "] -#@ } -#@ -#@ -#@ if {[info exists ra(-reference_control_file)]} { -#@ set cmd [concat [concat $cmd " -reference_control_file " ] " $ra(-reference_control_file) "] -#@ } -#@ -#@ if {[info exists ra(-mw_reference_library)]} { -#@ set cmd [concat [concat [concat $cmd " -mw_reference_library {" ] " $ra(-mw_reference_library) "] "}"] -#@ } -#@ -#@ if {[info exists ra(-plib)]} { -#@ if {[string match -nocase {*.pdb} $ra(-plib) ] } { -#@ set cmd [concat [concat $cmd " -plib " ] " $ra(-plib) "] -#@ } -#@ if {[string match -nocase {*.plib} $ra(-plib) ] } { -#@ set subcmd [format {set lc_enable_legacy_library_compiler true; read_lib %s} $ra(-plib)] -#@ redirect -file log_file {uplevel #0 $subcmd} -#@ set f1 [open $log_file] -#@ while {[gets $f1 line] >= 0} { -#@ set msg1 [lindex $line 3] -#@ set msg2 [lindex $line 4] -#@ if {[string match {read} $msg1] && -#@ [string match {successfully} $msg2] } { -#@ set msg [lindex $line 2] -#@ set len [string length $msg] -#@ set lib_name [string range $msg 1 [expr $len-2] ] -#@ break -#@ } -#@ if {[string match {old} $msg1] && -#@ [string match {technology} $msg2] } { -#@ set msg [lindex $line 6] -#@ set len [string length $msg] -#@ set path [string range $msg 1 [expr $len-2] ] -#@ set name1 [lindex [split $path {/}] end] -#@ regexp {(.+?).pdb} $name1 match lib_name -#@ break -#@ } -#@ } -#@ if {$lib_name != ""} { -#@ set subcmd [format {write_lib %s -output %s} $lib_name $pdb_file] -#@ uplevel #0 $subcmd -#@ set cmd [concat [concat $cmd " -plib " ] " $pdb_file "] -#@ } else { -#@ echo "Error: Can not compile $ra(-plib) to pdb successfully" -#@ return 0; -#@ } -#@ } -#@ } -#@ -#@ if { ![uplevel #0 $cmd] } { -#@ return 0 -#@ } -#@ -#@ set cmd "" -#@ -#@ if {[info exists ra(-open)]} { -#@ uplevel #0 $cmd -#@ set cmd [format {open_mw_lib %s} $ra() ] -#@ } -#@ -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes create_mw_lib -hide_body -info " Create a milkyway library " -define_args {{-technology "Technology file name" "file_name" string {optional}} {-ignore_tf_error "Ignore the error in technology file" "" boolean {hidden optional}} {-plib "Plib file name" "file_name" string {optional}} {-hier_separator "Hierarchical separator, default is backslash / " "separator" string {hidden optional}} {-bus_naming_style "Bus naming style" "bus_naming_style" string {optional}} {-ignore_case "Make case insensitive" "" boolean {hidden optional}} {-case_sensitive "Make case sensitive" "" boolean {hidden optional}} {-mw_reference_library "List of reference libraries" "lib_list" list {optional}} {-reference_control_file "Reference control file" "file_name" string {optional}} {-open "Open the library after creation" "" boolean {optional}} {"" "Library name to create" "libName" string {required}}} -#@ -#@ # -#@ ############################################################################## -#@ # -#@ # PROCEDURE: report_mw_lib -#@ # -#@ # ABSTRACT: wrapper around MWUI report_mw_lib -#@ # -#@ ############################################################################## -#@ -#@ proc report_mw_lib args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd "" -#@ -#@ if {[info exists ra(-mw_reference_library)]} { -#@ if {[info exists ra()]} { -#@ set cmd [format {org_report_mw_lib -mw_reference_library %s} $ra() ] -#@ } else { -#@ set cmd [format {org_report_mw_lib -mw_reference_library} ] -#@ } -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ if {[info exists ra(-unit_range)]} { -#@ if {[info exists ra()]} { -#@ set cmd [format {org_report_mw_lib -unit_range %s} $ra() ] -#@ } else { -#@ echo "Error : Library name must be specified when using this option" -#@ return 0; -#@ } -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ } -#@ -#@ define_proc_attributes report_mw_lib -hide_body -info " Report information about the library " -define_args {{-unit_range "Report unit range of library" "" boolean {optional}} {-mw_reference_library "Report list of reference libraries" "" boolean {optional}} {"" "Library to be reported" "libName" string {optional}}} -#@ -#@ ############################################################################## -#@ # -#@ # PROCEDURE: close_mw_lib -#@ # -#@ # ABSTRACT: Wrapper around close_mw_lib to handle -save option properly -#@ # - save_mw_cel to save current cel with dc_netlist -#@ # - close_mw_cel to close current cel -#@ # - save_open_cels to save other open cels before closing library -#@ # -#@ ############################################################################## -#@ -#@ proc close_mw_lib args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ if {$args == ""} { -#@ set cmd [format {icc_is_dc_up} ] -#@ if {[uplevel #0 $cmd]} { -#@ set cmd [format {remove_design -quiet -designs} ] -#@ if {[uplevel #0 $cmd]} { -#@ set cmd [format {org_close_mw_lib } ] -#@ return [uplevel #0 $cmd] -#@ } else { -#@ return 0 -#@ } -#@ } else { -#@ set cmd [format {org_close_mw_lib } ] -#@ return [uplevel #0 $cmd] -#@ } -#@ } -#@ -#@ if {[info exists ra(-save)]} { -#@ -#@ set cmd [format {save_mw_cel} ] -#@ if {![uplevel #0 $cmd]} { -#@ return -#@ } -#@ -#@ set cmd [format {close_mw_cel} ] -#@ if {![uplevel #0 $cmd]} { -#@ return -#@ } -#@ -#@ set cmd [format {save_open_cels} ] -#@ if {![uplevel #0 $cmd]} { -#@ return -#@ } -#@ } -#@ -#@ set cmd [format {org_close_mw_lib} ] -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ define_proc_attributes close_mw_lib -hide_body -info " Closes the milkyway library " -define_args {{-save "Save open cels" "" boolean {optional}} {"" "libraries to be closed" "lib list" list {hidden optional}}} -#@ } else { -#@ define_proc_attributes close_mw_lib -hide_body -info " Closes the milkyway library " -define_args {{-no_save "Don't save open cels" "" boolean {hidden optional}} {"" "libraries to be closed" "lib list" list {hidden optional}}} -#@ } -#@ ############################################################################## -#@ # -#@ # PROCEDURE: write_mw_lib_files -#@ # -#@ # ABSTRACT: Write technology or reference control file -#@ # History: Yun Zhang 2012/12/11, public option -stream_layer_map_file -#@ # History: Yun Zhang 2012/9/5. support new hidden option -vt_cell_placement_properties -#@ # History: Yun Zhang 2011/12/5. add new hidden option -stream_layer_map_file -#@ # -#@ ############################################################################## -#@ proc write_mw_lib_files args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd "" -#@ -#@ if {[info exists ra(-reference_control_file)]} { -#@ #Option -reference_contrl_file, -plib and -technology are exclusive. -#@ # If both of them are set at the same time, error reported. -#@ # 9000273455, by xqsun, 2009/2/4 -#@ if {[info exists ra(-technology)]} { -#@ echo "Error: Cannot specify '-reference_control_file' with '-technology'.(CMD-001)" -#@ return 0 -#@ } elseif {[info exists ra(-plib)]} { -#@ echo "Error: Cannot specify '-reference_control_file' with '-plib'.(CMD-001)" -#@ return 0 -#@ } elseif {[info exists ra(-vt_cell_placement_properties)]} { -#@ echo "Error: Cannot specify '-reference_control_file' with '-vt_cell_placement_properties'.(CMD-001)" -#@ return 0 -#@ } elseif {[info exists ra(-stream_layer_map_file)]} { -#@ echo "Error: Cannot specify '-reference_control_file' with '-stream_layer_map_file'.(CMD-001)" -#@ return 0 -#@ } else { -#@ set cmd [format {report_mw_lib_ref_ctrl_file -output %s %s} $ra(-output) $ra() ] -#@ return [uplevel #0 $cmd] -#@ } -#@ } -#@ -#@ if {[info exists ra(-technology)]} { -#@ if {[info exists ra(-plib)]} { -#@ echo "Error: Cannot specify '-technology' with '-plib'.(CMD-001)" -#@ return 0 -#@ } elseif {[info exists ra(-vt_cell_placement_properties)]} { -#@ echo "Error: Cannot specify '-technology' with '-vt_cell_placement_properties'.(CMD-001)" -#@ return 0 -#@ } elseif {[info exists ra(-stream_layer_map_file)]} { -#@ echo "Error: Cannot specify '-technology' with '-stream_layer_map_file'.(CMD-001)" -#@ return 0 -#@ } else { -#@ set cmd [format {org_report_mw_lib -output %s %s} $ra(-output) $ra() ] -#@ return [uplevel #0 $cmd] -#@ } -#@ } -#@ -#@ if {[info exists ra(-plib)]} { -#@ if {[info exists ra(-stream_layer_map_file)]} { -#@ echo "Error: Cannot specify '-plib' with '-stream_layer_map_file'.(CMD-001)" -#@ return 0 -#@ } elseif {[info exists ra(-vt_cell_placement_properties)]} { -#@ echo "Error: Cannot specify '-plib' with '-vt_cell_placement_properties'.(CMD-001)" -#@ return 0 -#@ } else { -#@ set cmd [format {write_plib -lib_name %s %s} $ra() $ra(-output) ] -#@ return [uplevel #0 $cmd] -#@ } -#@ } -#@ -#@ if {[info exists ra(-vt_cell_placement_properties)]} { -#@ if {[info exists ra(-stream_layer_map_file)]} { -#@ echo "Error: Cannot specify '-vt_cell_placement_properties' with '-stream_layer_map_file'.(CMD-001)" -#@ return 0 -#@ } else { -#@ set cmd [format {org_report_mw_lib -vt_cell_placement_properties -output %s %s} $ra(-output) $ra() ] -#@ return [uplevel #0 $cmd] -#@ } -#@ } -#@ -#@ if {[info exists ra(-stream_layer_map_file)]} { -#@ set cmd [format {org_report_mw_lib -stream_layer_map_file %s -output %s %s} $ra(-stream_layer_map_file) $ra(-output) $ra() ] -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ } -#@ -#@ define_proc_attributes write_mw_lib_files -hide_body -info " Write technology or reference control file " -define_args {{-technology "Dump technology file" "" boolean {optional}} {-plib "Dump plib file" "" boolean {optional}} {-vt_cell_placement_properties "Dump multi-VT cells' implant layer information of library" "" boolean {optional hidden}} {-reference_control_file "Dump reference control file" "" boolean {optional}} {-stream_layer_map_file "Dump layer map file during stream in/out" "" string {optional}} {-output "Output file" "file_name" string {required}} {"" "Library to be reported" "libName" string {required}}} -#@ } -#@ ############################################################################## -#@ # -#@ # PROCEDURE: close_mw_cel -#@ # -#@ # ABSTRACT: Wrapper around close_mw_cel to add -save option -#@ # remove_timing_design is the command to shutdown dc netlist -#@ # -#@ ############################################################################## -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ -#@ proc close_mw_cel args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ global mw_is_all_views -#@ set cmd [format {icc_is_dc_up} ] -#@ set dc_is_up [uplevel #0 $cmd] -#@ -#@ set cmd_close [format {org_close_mw_cel} ] -#@ -#@ if {[info exists ra(-all_views)]} { -#@ set cmd_close [format {%s -all_views} $cmd_close] -#@ set mw_is_all_views 1 -#@ } -#@ if {[info exists ra(-all_versions)]} { -#@ set cmd_close [format {%s -all_versions} $cmd_close] -#@ } -#@ if {[info exists ra(-save)]} { -#@ set cmd_close [format {%s -save} $cmd_close] -#@ } -#@ if {[info exists ra(-verbose)]} { -#@ set cmd_close [format {%s -verbose} $cmd_close] -#@ } -#@ if {[info exists ra(-hierarchy)]} { -#@ set cmd_close [format {%s -hierarchy} $cmd_close] -#@ } -#@ -#@ ui_util_clean_saved_lib_attr $args -#@ -#@ set cmd "" -#@ set lcels "" -#@ set is_current_closed 1 -#@ -#@ if {[info exists ra()]} { -#@ set lcels $ra() -#@ } -#@ set len [string length $lcels] -#@ if {$len > 0} { -#@ set is_current_closed [is_current_mw_cel $lcels] -#@ set cmd_close [format {%s {%s}} $cmd_close $lcels] -#@ } -#@ if {[uplevel #0 $cmd_close]} { -#@ set mw_is_all_views 0 -#@ if {$dc_is_up == 1} { -#@ if {$is_current_closed == 1} { -#@ set cmd [format {remove_design -quiet -designs} ] -#@ return [uplevel #0 $cmd] -#@ } -#@ return 1 -#@ } else { -#@ return 1 -#@ } -#@ } else { -#@ set mw_is_all_views 0 -#@ return 0 -#@ } -#@ } -#@ -#@ define_proc_attributes close_mw_cel -hide_body -info " Closes the design " -define_args {{-save "Save the design" "" boolean {optional}} {-discard "Discard any changes" "" boolean {optional hidden}} {-verbose "Print out debugging messages" "" boolean {optional hidden}} {-hierarchy "Close top design and its child designs" "" boolean {optional}} {-all_views "Close all views of the design" "" boolean {optional}} {-all_versions "Close all versions of the design" "" boolean {optional}} {"" "designs to be closed" "design list" list {optional}}} -#@ -#@ ############################################################################## -#@ # -#@ # PROCEDURE: save_all_mw_cel -#@ # -#@ # ABSTRACT: Wrapper around save_mw_cel to save all the open cels. Needed for Black box flow. -#@ # -#@ ############################################################################## -#@ -#@ proc save_all_mw_cels { } { -#@ set top_cel [get_attribute [current_mw_cel] name] -#@ -#@ set cels [fp_get_open_cells] -#@ -#@ foreach cel $cels { -#@ if {$cel != $top_cel} { -#@ current_mw_cel $cel -#@ -#@ save_mw_cel -#@ } -#@ } -#@ -#@ current_mw_cel $top_cel -#@ -#@ save_mw_cel -#@ } -#@ -#@ icc_hide_cmd save_all_mw_cels -#@ -#@ ############################################################################## -#@ # PROCEDURE: execute_command_and_create_cel_from_scratch -#@ # ABSTRACT: This procedure executes the given command and creates the CEL -#@ # from scratch after executing this command. -#@ ############################################################################## -#@ proc execute_command_and_create_cel_from_scratch {org_cmd_name args} { -#@ global mw_create_cel_force -#@ global mw_enable_auto_cel -#@ global mw_force_auto_cel -#@ -#@ set lib [current_mw_lib] -#@ -#@ # If no MW lib, design is not from MW. Execute the original command -#@ # and return. -#@ if {$lib == ""} { -#@ return [eval $org_cmd_name $args] -#@ } -#@ -#@ # Get values of few variables. -#@ set incr_mode $mw_create_cel_force -#@ set mw_create_cel_force TRUE -#@ -#@ # Get auto cel mode, disable it temporarily if enabled. -#@ set auto_cel_mode $mw_enable_auto_cel -#@ set mw_enable_auto_cel FALSE -#@ -#@ # Check if the already existing CEL is auto-CEL. -#@ set auto_cel 0 -#@ if {[is_cel_auto_cel]} { -#@ set auto_cel 1 -#@ } elseif {![get_top_cel_mwid]} { -#@ set auto_cel 1 -#@ } -#@ -#@ -#@ # Run the original command, if not successful restore the incr_mode -#@ # variable and return. No CEL is created. -#@ if {![eval $org_cmd_name $args]} { -#@ set mw_create_cel_force $incr_mode -#@ set mw_enable_auto_cel $auto_cel_mode -#@ return 0 -#@ } -#@ -#@ # Restore auto_cel mode -#@ set mw_enable_auto_cel $auto_cel_mode -#@ -#@ # Now create auto or real CEL depending on what the original CEL was. -#@ if {$auto_cel == "1"} { -#@ # Force creation of auto-CEL, since commands other than read_def/pdef -#@ # do not decouple CEL from DC. -#@ -#@ set mw_force_auto_cel TRUE -#@ set cmd [format {save_mw_cel -auto}] -#@ } else { -#@ if [get_top_cel_mwid] { -#@ set cmd [format {save_mw_cel -create}] -#@ echo "Information: Command not supported by incr. update or write-thru." -#@ echo " Creating new CEL from scratch, old CEL will be closed." -#@ } -#@ } -#@ -#@ # Create the Auto CEL or normal CEL from scratch. -#@ if {![uplevel #0 $cmd]} { -#@ set mw_create_cel_force $incr_mode -#@ set mw_force_auto_cel FALSE -#@ return 0 -#@ } -#@ -#@ set mw_create_cel_force $incr_mode -#@ set mw_force_auto_cel FALSE -#@ return 1 -#@ } -#@ -#@ define_proc_attributes execute_command_and_create_cel_from_scratch -hidden -hide_body -#@ -#@ ############################################################################## -#@ # PROCEDURE: read_def -#@ # ABSTRACT: Wrapper around read_def to handle incremental update properly -#@ # if MW based read_def is used, bypass the wrapper -#@ # enable_milkyway_def_reader_writer must be TRUE and use_pdb_lib_format must -#@ # be false for MW read_Def to be run, use wrapper if either condition fails -#@ ############################################################################## -#@ rename -force dc_read_def org_read_def -#@ icc_hide_cmd org_read_def -#@ proc dc_read_def args { -#@ parse_proc_arguments -args $args ra -#@ -#@ return [eval execute_command_and_create_cel_from_scratch "org_read_def" $args] -#@ } -#@ -#@ define_proc_attributes dc_read_def -hide_body -info " Read a def file " -define_args {{-design "name of design for which clusters are to be read" "" string {optional}} {-quiet "do not print out any warnings" "" boolean {optional}} {-verbose "print out more warnings" "" boolean {optional}} {-allow_physical_cells "allow physical cells" "" boolean {optional}} {-allow_physical_ports "allow physical ports" "" boolean {optional}} {-allow_physical_nets "allow physical nets" "" boolean {optional}} {-skip_signal_nets "skip signal nets" "" boolean {optional}} {-incremental "incremental" "" boolean {optional}} {-enforce_scaling "enforce_scaling" "" boolean {optional}} {-move_bounds "move bounds" "" boolean {optional}} {"" "input def file names" "input_def_file_name" string {required}}} -#@ -#@ -#@ ############################################################################## -#@ # PROCEDURE: group -#@ # ABSTRACT: Wrapper around group to handle incremental update properly -#@ ############################################################################## -#@ rename -force group org_group -#@ icc_hide_cmd org_group -#@ proc group args { -#@ parse_proc_arguments -args $args ra -#@ return [eval execute_command_and_create_cel_from_scratch "org_group" $args] -#@ } -#@ -#@ define_proc_attributes group -hide_body -info " create new hierarchy" -define_args {{-except "cells not to be included in the group" "exclude_list" list {optional}} -#@ {-design_name "name of design created for new hierarchy" "design_name" string {optional}} -#@ {-cell_name "name of cell created for new hierarchy" "cell_name" string {optional}} -#@ {-logic "group any combinational elements" "" boolean {optional}} -#@ {-pla "group any PLA elements" "" boolean {optional}} -#@ {-fsm "group all elements part of a finite state machine" "" boolean {optional}} -#@ {-hdl_block "name of hdl_block to group" "" string {optional}} -#@ {-hdl_bussed "group all bussed gates under this block" "" boolean {optional}} -#@ {-hdl_all_blocks "group all hdl blocks under this block" "" boolean {optional}} -#@ {-soft "set the group_name attribute" "" boolean {optional}} -#@ {"" "cells to be included in the group" "cell_list" list {optional}}} -#@ -#@ ############################################################################## -#@ # PROCEDURE: copy_design -#@ # ABSTRACT: Wrapper around copy_design to handle incremental update properly -#@ ############################################################################## -#@ rename -force copy_design org_copy_design -#@ icc_hide_cmd org_copy_design -#@ proc copy_design args { -#@ parse_proc_arguments -args $args ra -#@ return [eval execute_command_and_create_cel_from_scratch "org_copy_design" $args] -#@ } -#@ -#@ define_proc_attributes copy_design -hide_body -info " copy_design" -define_args {{"" "List of designs to be copied" "design_list" list {required}} -#@ {"" "Name of new design or target file" "target_name" string {required}}} -#@ -#@ ############################################################################## -#@ # PROCEDURE: create_design -#@ # ABSTRACT: Wrapper around create_design to handle incremental update properly -#@ ############################################################################## -#@ rename -force create_design org_create_design -#@ icc_hide_cmd org_create_design -#@ proc create_design args { -#@ parse_proc_arguments -args $args ra -#@ return [eval execute_command_and_create_cel_from_scratch "org_create_design" $args] -#@ } -#@ -#@ define_proc_attributes create_design -hide_body -info " Creates a design in dc_shell memory" -define_args {{"" "name of the design to create" "" string {required}} -#@ {"" "name of file for design; optional" "" string {optional}}} -#@ -#@ ############################################################################## -#@ # PROCEDURE: reset_design -#@ # ABSTRACT: Wrapper around reset_design to handle incremental update properly -#@ ############################################################################## -#@ #rename -force reset_design org_reset_design -#@ #icc_hide_cmd org_reset_design -#@ #proc reset_design args { -#@ # parse_proc_arguments -args $args ra -#@ # return [eval execute_command_and_create_cel_from_scratch "org_reset_design" $args] -#@ #} -#@ -#@ ############################################################################## -#@ # PROCEDURE: rename_design -#@ # ABSTRACT: Wrapper around rename_design to handle incremental update properly -#@ ############################################################################## -#@ rename -force rename_design org_rename_design -#@ icc_hide_cmd org_rename_design -#@ proc rename_design args { -#@ parse_proc_arguments -args $args ra -#@ return [eval execute_command_and_create_cel_from_scratch "org_rename_design" $args] -#@ } -#@ -#@ define_proc_attributes rename_design -hide_body -info " rename_design" -define_args {{"" "List of designs to be renamed" "design_list" list {required}} -#@ {"" "Name of new design or target file" "target_name" string {required}}} -#@ -#@ } -#@ -#@ ############################################################################## -#@ # If we are in icc_shell (i.e. Galileo) then -#@ # load the procedures to switch between DC and Milkyway collections. -#@ # Set the default to MW collection unless otherwise specified. -#@ ############################################################################## -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ # load the procedures that switch between DC and MW collections -#@ source $synopsys_root/auxx/syn/collection_procs.tcl -#@ -#@ set CS mw -#@ -#@ # see if the user wants DC -#@ if {! [catch {getenv USE_DC_COLLECTIONS_ONLY}] && -#@ [getenv USE_DC_COLLECTIONS_ONLY] } { -#@ set CS dc -#@ } -#@ -#@ # set the collection source now -#@ redirect /dev/null { -#@ if {[catch {set_collection_mode -handle $CS}]} { -#@ catch {set_collection_option -handle $CS} -#@ } -#@ } -#@ -#@ unset CS -#@ } -#@ -#@ ############################################################################## -#@ # procedure for route command -#@ # echo the command to a temp tcl file for seperate process to pick up -#@ ############################################################################## -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ rename -force route org_route -#@ icc_hide_cmd org_route -#@ proc route args { -#@ set route_cmd_file_name ".route_cmd.tcl" -#@ set route_cmd_temp_file_name ".route_cmd.tcl.temp" -#@ set fp [open $route_cmd_file_name "w"] -#@ set route_cmd [concat "sep_proc_route " $args " -child"] -#@ puts $fp $route_cmd -#@ close $fp -#@ -#@ uplevel #0 rename -force route route_temp_proc -#@ uplevel #0 rename -force org_route route -#@ set status [ uplevel #0 route $args ] -#@ uplevel #0 rename -force route org_route -#@ uplevel #0 rename -force route_temp_proc route -#@ -#@ if { [info exist status ] == 1 } { -#@ return $status -#@ } -#@ return -#@ } -#@ } -#@ -#@ ############################################################################## -#@ # Tcl Command: set_ignore_cell -#@ # Description: Load the command only in IC Compiler (icc_shell) -#@ ############################################################################## -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ source $synopsys_root/auxx/syn/psyn/ideal_cell.tcl.e -#@ } -#@ -#@ ############################################################################## -#@ # Tcl Command: check_physical_design -#@ # Description: Load the command only in IC Compiler (icc_shell) -#@ ############################################################################## -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ # Load the compiled Tcl byte-code: -#@ # 9000784997: Do not log to command.log when sourcing .tbc files -#@ set prev_sh_source_logging [get_app_var sh_source_logging] -#@ set_app_var sh_source_logging 0 -#@ source $synopsys_root/auxx/syn/psyn/check_physical_design_core.tbc -#@ source $synopsys_root/auxx/syn/psyn/check_physical_design_utils.tbc -#@ source $synopsys_root/auxx/syn/psyn/check_physical_design_flows.tbc -#@ source $synopsys_root/auxx/syn/psyn/check_physical_design_reports.tbc -#@ source $synopsys_root/auxx/syn/psyn/check_physical_design_ui.tbc -#@ source $synopsys_root/auxx/syn/psyn/create_qor_snapshot.tbc -#@ source $synopsys_root/auxx/syn/psyn/report_qor_snapshot.tbc -#@ source $synopsys_root/auxx/syn/psyn/msgParser.tbc -#@ source $synopsys_root/auxx/syn/psyn/displacement_gui.tbc -#@ source $synopsys_root/auxx/syn/psyn/categorize_timing_gui.tbc -#@ set_app_var sh_source_logging $prev_sh_source_logging -#@ -#@ source $synopsys_root/auxx/syn/psyn/mcmm_utils.tcl.e -#@ source $synopsys_root/auxx/syn/psyn/propagate_all_clocks.tcl.e -#@ } -#@ -#@ if { [string match -nocase {*dc_shell*} $synopsys_program_name] && [shell_is_in_topographical_mode] } { -#@ # 9000784997: Do not log to command.log when sourcing .tbc files -#@ set prev_sh_source_logging [get_app_var sh_source_logging] -#@ set_app_var sh_source_logging 0 -#@ source $synopsys_root/auxx/syn/psyn/create_qor_snapshot.tbc -#@ source $synopsys_root/auxx/syn/psyn/report_qor_snapshot.tbc -#@ set_app_var sh_source_logging $prev_sh_source_logging -#@ -#@ source $synopsys_root/auxx/syn/psyn/mcmm_utils.tcl.e -#@ } -#@ -#@ if { $synopsys_program_name == "de_shell" } { -#@ # 9000784997: Do not log to command.log when sourcing .tbc files -#@ set prev_sh_source_logging [get_app_var sh_source_logging] -#@ set_app_var sh_source_logging 0 -#@ source $synopsys_root/auxx/syn/psyn/create_qor_snapshot.tbc -#@ source $synopsys_root/auxx/syn/psyn/report_qor_snapshot.tbc -#@ set_app_var sh_source_logging $prev_sh_source_logging -#@ -#@ source $synopsys_root/auxx/syn/psyn/mcmm_utils.tcl.e -#@ } -#@ -#@ ############################################################################## -#@ # ICC setup and hiding commands/procs etc -#@ ############################################################################## -#@ -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ #set save_mw_cel_lib_setup TRUE -#@ #set auto_restore_mw_cel_lib_setup FALSE -#@ -#@ alias create_wiring_keepout create_wiring_keepouts -#@ alias get_wiring_keepout get_wiring_keepouts -#@ alias get_placement_keepout get_placement_keepouts -#@ alias create_placement_keepout create_placement_keepouts -#@ -#@ icc_hide_cmd execute_command_and_create_cel_from_scratch -#@ icc_hide_cmd dc_read_def -#@ icc_hide_cmd read_edif -#@ icc_hide_cmd read_sverilog -#@ icc_hide_cmd read_vhdl -#@ icc_hide_cmd set_collection_mode -#@ icc_hide_cmd return_dc_collection -#@ icc_hide_cmd return_mw_collection -#@ set mw_use_pdb_lib_format true -#@ } -#@ -#@ -#@ ############################################################################## -#@ # Tcl Command: get_dont_touch_nets -#@ # Description: wrapper of "get_nets -filter dont_touch_reason==mv" -#@ ############################################################################## -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ -#@ proc get_dont_touch_nets args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {get_nets}] -#@ -#@ if {[info exists ra()]} { -#@ set cmd [format {%s {%s}} $cmd $ra()] -#@ } -#@ if {[info exists ra(-type)]} { -#@ set cmd [format {%s -filter dont_touch_reasons=~*%s*} $cmd $ra(-type)] -#@ } -#@ if {[info exists ra(-hierarchical)]} { -#@ set cmd [format {%s -hierarchical} $cmd] -#@ } -#@ if {[info exists ra(-quiet)]} { -#@ set cmd [format {%s -quiet} $cmd] -#@ } -#@ if {[info exists ra(-regexp)]} { -#@ set cmd [format {%s -regexp} $cmd] -#@ } -#@ if {[info exists ra(-nocase)]} { -#@ set cmd [format {%s -nocase} $cmd] -#@ } -#@ if {[info exists ra(-exact)]} { -#@ set cmd [format {%s -exact} $cmd] -#@ } -#@ -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes get_dont_touch_nets -info " Get dont_touch nets " -permanent -define_args { {"" "Match net names against patterns" "patterns" list {optional}} {-type "Match net dont_touch reasons" "reasons" list {required}} {-hierarchical "Search level-by-level in current instance" "" boolean {optional}} {-quiet "Suppress all messages" "" boolean {optional hidden}} {-regexp "Patterns are full regular expressions" "" boolean {optional hidden}} {-nocase "With -regexp, matches are case-insensitive" "" boolean {optional hidden}} {-exact "Wildcards are considered as plain characters" "" boolean {optional hidden}} } -#@ -#@ alias get_dont_touch_net get_dont_touch_nets -#@ } -#@ -#@ -#@ ############################################################################## -#@ # return the first {index value} pair in Tcl array ary. -#@ ############################################################################## -#@ proc _snps_array_peek { level ary } { -#@ upvar #$level $ary loc_ary -#@ set ret [list] -#@ set token [array startsearch loc_ary] -#@ while {[array anymore loc_ary $token]} { -#@ set k [array nextelement loc_ary $token] -#@ set v $loc_ary($k) -#@ set ret [list $k $v] -#@ break -#@ } -#@ array donesearch loc_ary $token -#@ return $ret; -#@ } -#@ define_proc_attributes _snps_array_peek -hidden -#@ # -- End source /tools/synopsys/synthesis/j201409sp3/auxx/syn/.dc_procs.tcl - -#@ -#@ # Temporary fix for the LMC_HOME variable- set it to an empty string -#@ -#@ if { [catch {getenv LMC_HOME } __err ] != 0 } { -#@ setenv LMC_HOME "" -#@ } -#@ -#@ -#@ # -#@ # -#@ # Site-Specific Variables -#@ # -#@ # These are the variables that are most commonly changed at a -#@ # specific site, either upon installation of the Synopsys software, -#@ # or by specific engineers in their local .synopsys files. -#@ # -#@ # -#@ -#@ # from the System Variable Group -#@ set link_library { * your_library.db } -#@ -#@ set search_path [list . ${synopsys_root}/libraries/syn ${synopsys_root}/minpower/syn ${synopsys_root}/dw/syn_ver ${synopsys_root}/dw/sim_ver] -#@ set target_library your_library.db -#@ set synthetic_library "" -#@ set command_log_file "./command.log" -#@ set designer "" -#@ set company "" -#@ set find_converts_name_lists "false" -#@ -#@ set symbol_library your_library.sdb -#@ -#@ # Turn on Formality SVF recording -#@ if { $synopsys_program_name == "dc_shell" || $synopsys_program_name == "de_shell" || $synopsys_program_name == "design_vision" } { -#@ set_svf -default default.svf -#@ } -#@ -#@ # from the Schematic Variable Group -#@ -#@ # from the Plot Variable Group -#@ # [froi] 07/06/2012: Remove old Design Analyzer plot_command variable -#@ #if { $sh_arch == "hp700" } { -#@ # set plot_command "lp -d" -#@ #} else { -#@ # set plot_command "lpr -Plw" -#@ #} -#@ -#@ set view_command_log_file "./view_command.log" -#@ -#@ # from the View Variable group -#@ if { $sh_arch == "hp700" } { -#@ set text_print_command "lp -d" -#@ } else { -#@ set text_print_command "lpr -Plw" -#@ } -#@ # -#@ # System Variable Group: -#@ # -#@ # These variables are system-wide variables. -#@ # -#@ set arch_init_path ${synopsys_root}/${sh_arch}/motif/syn/uid -#@ set auto_link_disable "false" -#@ set auto_link_options "-all" -#@ set uniquify_naming_style "%s_%d" -#@ set verbose_messages "true" -#@ set echo_include_commands "true" -#@ set svf_file_records_change_names_changes "true" -#@ set change_names_update_inst_tree "true" -#@ set change_names_dont_change_bus_members false -#@ set default_name_rules "" -#@ #set tdrc_enable_clock_table_creation "true" -#@ -#@ # -#@ # Compile Variable Group: -#@ # -#@ # These variables affect the designs created by the COMPILE command. -#@ # -#@ set compile_assume_fully_decoded_three_state_busses "false" -#@ set compile_no_new_cells_at_top_level "false" -#@ set compile_dont_touch_annotated_cell_during_inplace_opt "false" -#@ set compile_update_annotated_delays_during_inplace_opt "true" -#@ set compile_instance_name_prefix "U" -#@ set compile_instance_name_suffix "" -#@ set compile_negative_logic_methodology "false" -#@ set compile_disable_hierarchical_inverter_opt "false" -#@ set compile_use_low_timing_effort "false" -#@ set compile_fix_cell_degradation "false" -#@ set compile_preserve_subdesign_interfaces "false" -#@ set compile_enable_constant_propagation_with_no_boundary_opt "true" -#@ set port_complement_naming_style "%s_BAR" -#@ set compile_implementation_selection "true" -#@ set compile_delete_unloaded_sequential_cells "true" -#@ set reoptimize_design_changed_list_file_name "" -#@ set compile_checkpoint_phases "false" -#@ set compile_cpu_limit 0.0 -#@ set compile_log_format " %elap_time %area %wns %tns %drc %endpoint"; -#@ set compile_top_all_paths "false" -#@ set compile_top_acs_partition "false" -#@ set default_port_connection_class "universal" -#@ set compile_hold_reduce_cell_count "false" -#@ set compile_retime_license_behavior "wait" -#@ set dont_touch_nets_with_size_only_cells "false" -#@ if { $synopsys_program_name == "dc_shell" && [shell_is_in_topographical_mode] } { -#@ set dct_prioritize_area_correlation "false" -#@ set compile_error_on_missing_physical_cells "false" -#@ } -#@ -#@ set ldd_return_val 0 -#@ if { [string compare $dc_shell_mode "default"] == 0 } { -#@ set ldd_script ${synopsys_root}/auxx/syn/scripts/list_duplicate_designs.dcsh -#@ alias list_duplicate_designs "include -quiet ldd_script; dc_shell_status = ldd_return_val " -#@ -#@ } -#@ if { [string compare $dc_shell_mode "tcl"] == 0 } { -#@ if {$synopsys_program_name != "dc_sms_shell"} { -#@ source ${synopsys_root}/auxx/syn/scripts/list_duplicate_designs.tcl -#@ # 9000784997: Do not log to command.log when sourcing .tbc files -#@ set prev_sh_source_logging [get_app_var sh_source_logging] -#@ set_app_var sh_source_logging 0 -#@ source ${synopsys_root}/auxx/syn/scripts/analyze_datapath.tbc -#@ set_app_var sh_source_logging $prev_sh_source_logging -#@ } -#@ } -#@ # -- Starting source /tools/synopsys/synthesis/j201409sp3/auxx/syn/scripts/list_duplicate_designs.tcl - -#@ ####################################################################### -#@ # -#@ # list_duplicate_designs.tcl 21 Sept. 2006 -#@ # -#@ # List designs in dc_shell memory that have the same design name -#@ # -#@ # COPYRIGHT (C) 2006, SYNOPSYS INC., ALL RIGHTS RESERVED. -#@ # -#@ ####################################################################### -#@ -#@ proc list_duplicate_designs { args } { -#@ parse_proc_arguments -args $args ra -#@ -#@ # Get the list of duplicate designs -#@ set the_pid [pid] -#@ set rand_1 [expr int(rand() * 100000)] -#@ set temp_file_1 [format "/tmp/ldd_design_%s_%s" $the_pid $rand_1] -#@ -#@ redirect $temp_file_1 { foreach_in_collection ldd_design [find design "*"] { -#@ echo [get_object_name $ldd_design] -#@ } } -#@ -#@ set rand_2 [expr int(rand() * 100000)] -#@ set temp_file_2 [format "/tmp/ldd_design_%s_%s" $the_pid $rand_2] -#@ -#@ sh sort $temp_file_1 | uniq -d | tee $temp_file_2 -#@ file delete $temp_file_1 -#@ -#@ # Report duplicates -#@ if { ! [file size $temp_file_2] } { -#@ echo [concat {No duplicate designs found.}] -#@ set ldd_return_val 0 -#@ } else { -#@ set rand_3 [expr int(rand() * 100000)] -#@ set temp_file_3 [format "/tmp/ldd_design_%s_%s" $the_pid $rand_3] -#@ echo {Warning: Multiple designs in memory with the same design name.} -#@ echo {} -#@ echo { Design File Path} -#@ echo { ------ ---- ----} -#@ list_designs -table > $temp_file_3 -#@ echo [sh fgrep -f $temp_file_2 $temp_file_3 | sort | grep -v 'Design.*File.*Path'] -#@ file delete $temp_file_3 -#@ set ldd_return_val 1 -#@ } -#@ -#@ # Clean up -#@ file delete $temp_file_2 -#@ -#@ set list_duplicate_designs1 $ldd_return_val -#@ } -#@ -#@ define_proc_attributes list_duplicate_designs -info " List designs of same names" -permanent -define_args { -#@ } -#@ # -- End source /tools/synopsys/synthesis/j201409sp3/auxx/syn/scripts/list_duplicate_designs.tcl - -#@ -#@ -#@ set compile_log_format " %elap_time %area %wns %tns %drc %endpoint"; -#@ -#@ set compile_top_all_paths "false" -#@ alias compile_inplace_changed_list_file_name reoptimize_design_changed_list_file_name -#@ -#@ # -#@ # These variables affects compile, report_timing and report_constraints -#@ # commands. -#@ # -#@ set enable_recovery_removal_arcs "false" -#@ set timing_report_attributes {dont_touch dont_use map_only size_only ideal_net infeasible_paths} -#@ -#@ # -#@ # Multibit Variable Group: -#@ # -#@ # These variables affect the multibit mapping functionality -#@ # -#@ -#@ set bus_multiple_separator_style "," -#@ -#@ # -#@ # ILM Variable Group: -#@ # -#@ # These variables affect Interface Logic Model functionality -#@ # -#@ -#@ set ilm_ignore_percentage 25 -#@ -#@ # -#@ # Estimator Variable Group: -#@ # -#@ # These variables affect the designs created by the ESTIMATE command. -#@ # -#@ set estimate_resource_preference "fast" -#@ alias est_resource_preference estimate_resource_preference -#@ set lbo_lfo_enable_at_pin_count 3 -#@ set lbo_cells_in_regions "false" -#@ -#@ # Synthetic Library Group: -#@ # -#@ # These variable affect synthetic library processing. -#@ # -#@ set cache_dir_chmod_octal "777" -#@ set cache_file_chmod_octal "666" -#@ set cache_read "~" -#@ set cache_read_info "false" -#@ set cache_write "~" -#@ set cache_write_info "false" -#@ set synlib_dont_get_license {} -#@ set synlib_library_list {DW01 DW02 DW03 DW04 DW05 DW06 DW07} -#@ set synlib_wait_for_design_license {} -#@ set synlib_dwhomeip {} -#@ -#@ # -#@ # Insert_DFT Variable Group: -#@ # -#@ #set test_default_client_order [list] -#@ set insert_dft_clean_up "true" -#@ set insert_test_design_naming_style "%s_test_%d" -#@ # /*insert_test_scan_chain_only_one_clock = "false" -#@ # Replace by command line option (star 17215) -- Denis Martin 28-Jan-93*/ -#@ set test_clock_port_naming_style "test_c%s" -#@ set test_scan_clock_a_port_naming_style "test_sca%s" -#@ set test_scan_clock_b_port_naming_style "test_scb%s" -#@ set test_scan_clock_port_naming_style "test_sc%s" -#@ set test_scan_enable_inverted_port_naming_style "test_sei%s" -#@ set test_scan_enable_port_naming_style "test_se%s" -#@ set test_scan_in_port_naming_style "test_si%s%s" -#@ set test_scan_out_port_naming_style "test_so%s%s" -#@ set test_non_scan_clock_port_naming_style "test_nsc_%s" -#@ set test_default_min_fault_coverage 95 -#@ set test_dedicated_subdesign_scan_outs "false" -#@ set test_disable_find_best_scan_out "false" -#@ set test_dont_fix_constraint_violations "false" -#@ set test_isolate_hier_scan_out 0 -#@ set test_mode_port_naming_style "test_mode%s" -#@ set test_mode_port_inverted_naming_style "test_mode_i%s" -#@ set compile_dont_use_dedicated_scanout 1 -#@ set test_mux_constant_si "false" -#@ -#@ # -#@ # Analyze_Scan Variable Group: -#@ # -#@ # These variables affect the designs created by the PREVIEW_SCAN command. -#@ # -#@ set test_preview_scan_shows_cell_types "false" -#@ set test_scan_link_so_lockup_key "l" -#@ set test_scan_link_wire_key "w" -#@ set test_scan_segment_key "s" -#@ set test_scan_true_key "t" -#@ -#@ # -#@ # bsd Variable Group: -#@ -#@ # These variables affect the report generated by the check_bsd command -#@ # and the BSDLout generated by the write_bsdl command. -#@ # -#@ set test_user_test_data_register_naming_style "UTDR%d" -#@ -#@ set test_user_defined_instruction_naming_style "USER%d" -#@ -#@ set test_bsdl_default_suffix_name "bsdl" -#@ -#@ set test_bsdl_max_line_length 80 -#@ -#@ set test_cc_ir_masked_bits 0 -#@ -#@ set test_cc_ir_value_of_masked_bits 0 -#@ -#@ set test_bsd_allow_tolerable_violations "false" -#@ set test_bsd_optimize_control_cell "false" -#@ set test_bsd_control_cell_drive_limit 0 -#@ set test_bsd_manufacturer_id 0 -#@ set test_bsd_part_number 0 -#@ set test_bsd_version_number 0 -#@ set bsd_max_in_switching_limit 60000 -#@ set bsd_max_out_switching_limit 60000 -#@ -#@ # -#@ # TestManager Variable Group: -#@ # -#@ # These variables affect the TestManager methodology. -#@ # -#@ set multi_pass_test_generation "false" -#@ -#@ # -#@ # TestSim Variable Group: -#@ # -#@ # These variables affect the TestSim behavior. -#@ # -#@ # set testsim_print_stats_file "true" -#@ -#@ # Test DRC Variable Group: -#@ # -#@ # These variables affect the check_test command. -#@ # -#@ set test_capture_clock_skew "small_skew" -#@ set test_allow_clock_reconvergence "true" -#@ set test_check_port_changes_in_capture "true" -#@ set test_infer_slave_clock_pulse_after_capture "infer" -#@ -#@ # -#@ # Test Variable Group: -#@ # -#@ # These variables affect the rtldrc, check_test, write_test_protocol -#@ # and write_test command. -#@ # -#@ set test_default_delay 0.0 -#@ set test_default_bidir_delay 0.0 -#@ set test_default_strobe 40.0 -#@ set test_default_strobe_width 0.0 -#@ set test_default_period 100.0 -#@ set test_stil_max_line_length 72 -#@ -#@ #added for B-2008.09-place_opt-004 to disable this option in ICC -#@ -#@ if { $synopsys_program_name != "icc_shell"} { -#@ set test_write_four_cycle_stil_protocol "false" -#@ set test_protocol_add_cycle "true" -#@ set test_stil_multiclock_capture_procedures "false" -#@ set write_test_new_translation_engine "false" -#@ set test_default_scan_style "multiplexed_flip_flop" -#@ set test_jump_over_bufs_invs "true" -#@ set test_point_keep_hierarchy "false" -#@ set test_mux_constant_so "false" -#@ set test_use_test_models "false" -#@ set test_stil_netlist_format "db" -#@ group_variable test "test_protocol_add_cycle" -#@ group_variable test "test_write_four_cycle_stil_protocol" -#@ group_variable test "test_stil_multiclock_capture_procedures" -#@ group_variable test "test_default_scan_style" -#@ group_variable preview_scan "test_jump_over_bufs_invs" -#@ group_variable insert_dft "test_point_keep_hierarchy" -#@ group_variable insert_dft "test_mux_constant_so" -#@ group_variable test "test_stil_netlist_format" -#@ } -#@ set test_rtldrc_latch_check_style "default" -#@ set test_enable_capture_checks "true" -#@ set ctldb_use_old_prot_flow "false" -#@ set test_bsd_default_delay 0.0 -#@ set test_bsd_default_bidir_delay 0.0 -#@ set test_bsd_default_strobe 95.0 -#@ set test_bsd_default_strobe_width 0.0 -#@ -#@ # -#@ # Test Variable Group: -#@ # -#@ # These variables affects the set_scan_state command. -#@ # -#@ -#@ set compile_seqmap_identify_shift_registers_with_synchronous_logic_ascii false -#@ -#@ # -#@ # Write_Test Variable Group: -#@ # -#@ # These variables affect output of the WRITE_TEST command. -#@ # -#@ set write_test_input_dont_care_value "X" -#@ set write_test_vector_file_naming_style "%s_%d.%s" -#@ set write_test_scan_check_file_naming_style "%s_schk.%s" -#@ set write_test_pattern_set_naming_style "TC_Syn_%d" -#@ set write_test_max_cycles 0 -#@ set write_test_max_scan_patterns 0 -#@ # /*retain "tssi_ascii" (equivalent to "tds") for backward compatability */ -#@ set write_test_formats {synopsys tssi_ascii tds verilog vhdl wgl} -#@ set write_test_include_scan_cell_info "true" -#@ set write_test_round_timing_values "true" -#@ -#@ -#@ # -#@ # Schematic and EDIF and Hdl Variable Groups: -#@ # -#@ # These variables affect the schematics created by the -#@ # create_schematic command, define the behavior of the -#@ # DC system EDIF interface, and are for controlling hdl -#@ # reading. -#@ # -#@ set bus_dimension_separator_style {][} -#@ set bus_naming_style {%s[%d]} -#@ -#@ -#@ # -#@ # Schematic and EDIF Variable Groups: -#@ # -#@ # These variables affect the schematics created by the -#@ # create_schematic command and define the behavior of -#@ # the DC system EDIF interface. -#@ # -#@ set bus_range_separator_style ":" -#@ -#@ -#@ # -#@ # EDIF and Io Variable Groups: -#@ # -#@ # These variables define the behavior of the DC system EDIF interface and -#@ # define the behavior of the DC system interfaces, i.e. LSI, Mentor, TDL, SGE,# etc. -#@ -#@ set bus_inference_descending_sort "true" -#@ set bus_inference_style "" -#@ set write_name_nets_same_as_ports "false" -#@ # -#@ # Schematic Variable Group: -#@ # -#@ # These variables affect the schematics created by the -#@ # create_schematic command. -#@ # -#@ set font_library "1_25.font" -#@ set generic_symbol_library "generic.sdb" -#@ -#@ # -#@ # Io Variable Group: -#@ # -#@ # These variables define the behavior of the DC system -#@ # interfaces, i.e. LSI, Mentor, TDL, SGE, etc. -#@ # -#@ #set db2sge_output_directory "" -#@ #set db2sge_scale "2" -#@ #set db2sge_overwrite "true" -#@ #set db2sge_display_symbol_names "false" -#@ -#@ -#@ #set db2sge_display_pin_names "false" -#@ #set db2sge_display_instance_names "false" -#@ #set db2sge_use_bustaps "false" -#@ #set db2sge_use_compound_names "true" -#@ #set db2sge_bit_type "std_logic" -#@ #set db2sge_bit_vector_type "std_logic_vector" -#@ #set db2sge_one_name "'1'" -#@ #set db2sge_zero_name "'0'" -#@ #set db2sge_unknown_name "'X'" -#@ #set db2sge_target_xp "false" -#@ #set db2sge_tcf_package_file "synopsys_tcf.vhd" -#@ #set db2sge_use_lib_section "" -#@ #set db2sge_script "" -#@ #set db2sge_command "" -#@ -#@ # set equationout_and_sign "*" -#@ # set equationout_or_sign "+" -#@ # set equationout_postfix_negation "true" -#@ -#@ # # [wjchen] 2006/08/14: The following variables are obsoleted for DC simpilification. -#@ #set lsiin_net_name_prefix "NET_" -#@ #set lsiout_inverter_cell "" -#@ #set lsiout_upcase "true" -#@ -#@ #set mentor_bidirect_value "INOUT" -#@ #set mentor_do_path "" -#@ #set mentor_input_output_property_name "PINTYPE" -#@ #set mentor_input_value "IN" -#@ #set mentor_logic_one_value "1SF" -#@ #set mentor_logic_zero_one_property_name "INIT" -#@ #set mentor_logic_zero_value "0SF" -#@ #set mentor_output_value "OUT" -#@ #set mentor_primitive_property_name "PRIMITIVE" -#@ #set mentor_primitive_property_value "MODULE" -#@ #set mentor_reference_property_name "COMP" -#@ #set mentor_search_path "" -#@ #set mentor_write_symbols "true" -#@ -#@ ## [wjchen] 0606_simp -#@ #set pla_read_create_flip_flop "false" -#@ #set tdlout_upcase "true" -#@ -#@ # # [wjchen] 2006/08/14: The following4 variables are obsoleted for DC simpilification. -#@ # set xnfout_constraints_per_endpoint "50" -#@ # set xnfout_default_time_constraints true -#@ # set xnfout_clock_attribute_style "CLK_ONLY" -#@ # set xnfout_library_version "" -#@ -#@ # # [wjchen] 2006/08/11: The following 8 variables are obsoleted for DC simpilification. -#@ # set xnfin_family "4000" -#@ # set xnfin_ignore_pins "GTS GSR GR" -#@ # set xnfin_dff_reset_pin_name "RD" -#@ # set xnfin_dff_set_pin_name "SD" -#@ # set xnfin_dff_clock_enable_pin_name "CE" -#@ # set xnfin_dff_data_pin_name "D" -#@ # set xnfin_dff_clock_pin_name "C" -#@ # set xnfin_dff_q_pin_name "Q" -#@ # -#@ -#@ # -#@ # EDIF Variable Group: -#@ # -#@ # These variables define the behavior of the DC system -#@ # EDIF interface. -#@ # -#@ -#@ ##[wjchen] 2006/08/24 -#@ -#@ # set bus_extraction_style {%s[%d:%d]} -#@ -#@ ##[wjchen] 2006/08/24 -#@ #set edifin_autoconnect_offpageconnectors "false" -#@ #set edifin_autoconnect_ports "false" -#@ #set edifin_dc_script_flag "" -#@ #set edifin_delete_empty_cells "true" -#@ #set edifin_delete_ripper_cells "true" -#@ #set edifin_ground_net_name "" -#@ #set edifin_ground_net_property_name "" -#@ #set edifin_ground_net_property_value "" -#@ #set edifin_ground_port_name "" -#@ #set edifin_instance_property_name "" -#@ #set edifin_portinstance_disabled_property_name "" -#@ #set edifin_portinstance_disabled_property_value "" -#@ #set edifin_portinstance_property_name "" -#@ #set edifin_power_net_name "" -#@ #set edifin_power_net_property_name "" -#@ #set edifin_power_net_property_value "" -#@ #set edifin_power_port_name "" -#@ #set edifin_use_identifier_in_rename "false" -#@ #set edifin_view_identifier_property_name "" -#@ #set edifin_lib_logic_1_symbol "" -#@ #set edifin_lib_logic_0_symbol "" -#@ #set edifin_lib_in_port_symbol "" -#@ #set edifin_lib_out_port_symbol "" -#@ #set edifin_lib_inout_port_symbol "" -#@ #set edifin_lib_in_osc_symbol "" -#@ #set edifin_lib_out_osc_symbol "" -#@ #set edifin_lib_inout_osc_symbol "" -#@ #set edifin_lib_mentor_netcon_symbol "" -#@ #set edifin_lib_ripper_bits_property "" -#@ #set edifin_lib_ripper_bus_end "" -#@ #set edifin_lib_ripper_cell_name "" -#@ #set edifin_lib_ripper_view_name "" -#@ #set edifin_lib_route_grid 1024 -#@ #set edifin_lib_templates {} -#@ #set edifout_dc_script_flag "" -#@ #set edifout_design_name "Synopsys_edif" -#@ #set edifout_designs_library_name "DESIGNS" -#@ #set edifout_display_instance_names "false" -#@ #set edifout_display_net_names "false" -#@ #set edifout_external "true" -#@ #set edifout_external_graphic_view_name "Graphic_representation" -#@ #set edifout_external_netlist_view_name "Netlist_representation" -#@ #set edifout_external_schematic_view_name "Schematic_representation" -#@ #set edifout_ground_name "logic_0" -#@ #set edifout_ground_net_name "" -#@ #set edifout_ground_net_property_name "" -#@ #set edifout_ground_net_property_value "" -#@ #set edifout_ground_pin_name "logic_0_pin" -#@ #set edifout_ground_port_name "GND" -#@ #set edifout_instance_property_name "" -#@ #set edifout_instantiate_ports "false" -#@ #set edifout_library_graphic_view_name "Graphic_representation" -#@ #set edifout_library_netlist_view_name "Netlist_representation" -#@ #set edifout_library_schematic_view_name "Schematic_representation" -#@ #set edifout_merge_libraries "false" -#@ #set edifout_multidimension_arrays "false" -#@ #set edifout_name_oscs_different_from_ports "false" -#@ #set edifout_name_rippers_same_as_wires "false" -#@ #set edifout_netlist_only "false" -#@ #set edifout_no_array "false" -#@ #set edifout_numerical_array_members "false" -#@ #set edifout_pin_direction_in_value "" -#@ #set edifout_pin_direction_inout_value "" -#@ #set edifout_pin_direction_out_value "" -#@ #set edifout_pin_direction_property_name "" -#@ #set edifout_pin_name_property_name "" -#@ #set edifout_portinstance_disabled_property_name "" -#@ #set edifout_portinstance_disabled_property_value "" -#@ #set edifout_portinstance_property_name "" -#@ #set edifout_power_and_ground_representation "cell" -#@ #set edifout_power_name "logic_1" -#@ #set edifout_power_net_name "" -#@ #set edifout_power_net_property_name "" -#@ #set edifout_power_net_property_value "" -#@ #set edifout_power_pin_name "logic_1_pin" -#@ #set edifout_power_port_name "VDD" -#@ #set edifout_skip_port_implementations "false" -#@ #set edifout_target_system "" -#@ #set edifout_top_level_symbol "true" -#@ #set edifout_translate_origin "" -#@ #set edifout_unused_property_value "" -#@ #set edifout_write_attributes "false" -#@ #set edifout_write_constraints "false" -#@ #set edifout_write_properties_list {} -#@ #set read_name_mapping_nowarn_libraries {} -#@ #set write_name_mapping_nowarn_libraries {} -#@ -#@ # -#@ # Hdl and Vhdlio Variable Groups: -#@ # -#@ # These variables are for controlling hdl reading, writing, -#@ # and optimizing. -#@ # -#@ set hdlin_enable_upf_compatible_naming "FALSE" -#@ set hdlin_auto_save_templates "FALSE" -#@ set hdlin_generate_naming_style "%s_%d" -#@ set hdlin_enable_relative_placement "rb" -#@ set hdlin_mux_rp_limit "128x4" -#@ set hdlin_generate_separator_style "_" -#@ set hdlin_ignore_textio_constructs "TRUE" -#@ set hdlin_infer_function_local_latches "FALSE" -#@ set hdlin_keep_signal_name "all_driving" -#@ set hdlin_module_arch_name_splitting "FALSE" -#@ set hdlin_preserve_sequential "none" -#@ set hdlin_presto_net_name_prefix "N" -#@ set hdlin_presto_cell_name_prefix "C" -#@ set hdlin_strict_verilog_reader "FALSE" -#@ set hdlin_prohibit_nontri_multiple_drivers "TRUE" -#@ if { $synopsys_program_name == "de_shell" } { -#@ set hdlin_elab_errors_deep "TRUE" -#@ } else { -#@ set hdlin_elab_errors_deep "FALSE" -#@ } -#@ set hdlin_mux_size_min 2 -#@ set hdlin_subprogram_default_values "FALSE" -#@ set hdlin_field_naming_style "" -#@ set hdlin_upcase_names "FALSE" -#@ set hdlin_sv_union_member_naming "FALSE" -#@ set hdlin_vhdl_std 2008 -#@ set hdlin_vhdl93_concat "TRUE" -#@ set hdlin_vhdl_syntax_extensions "FALSE" -#@ set hdlin_analyze_verbose_mode 0 -#@ set hdlin_report_sequential_pruning "FALSE" -#@ set hdlin_vrlg_std 2005 -#@ set hdlin_sverilog_std 2012 -#@ set hdlin_while_loop_iterations 4096 -#@ set hdlin_reporting_level "basic" -#@ set hdlin_autoread_verilog_extensions ".v" -#@ set hdlin_autoread_sverilog_extensions ".sv .sverilog" -#@ set hdlin_autoread_vhdl_extensions ".vhd .vhdl" -#@ set hdlin_autoread_exclude_extensions "" -#@ -#@ set bus_minus_style "-%d" -#@ set hdlin_latch_always_async_set_reset FALSE -#@ set hdlin_ff_always_sync_set_reset FALSE -#@ set hdlin_ff_always_async_set_reset TRUE -#@ set hdlin_check_input_netlist FALSE -#@ set hdlin_check_no_latch FALSE -#@ set hdlin_mux_for_array_read_sparseness_limit 90 -#@ set hdlin_infer_mux "default" -#@ set hdlin_mux_oversize_ratio 100 -#@ set hdlin_mux_size_limit 32 -#@ set hdlin_mux_size_only 1 -#@ set hdlin_infer_multibit "default_none" -#@ set hdlin_enable_rtldrc_info "false" -#@ set hdlin_interface_port_ABI 3 -#@ set hdlin_shorten_long_module_name "false" -#@ set hdlin_module_name_limit 256 -#@ set hdlin_enable_assertions "FALSE" -#@ set hdlin_enable_configurations "FALSE" -#@ set hdlin_sv_blackbox_modules "" -#@ set hdlin_sv_tokens "FALSE" -#@ set hdlin_sv_packages "enable" -#@ set hdlin_verification_priority "FALSE" -#@ set hdlin_enable_elaborate_ref_linking "FALSE" -#@ set hdlin_enable_hier_naming "FALSE" -#@ set hdlin_vhdl_mixed_language_instantiation "FALSE" -#@ set hdl_preferred_license "" -#@ set hdl_keep_licenses "true" -#@ set hlo_resource_allocation "constraint_driven" -#@ set sdfout_top_instance_name "" -#@ set sdfout_time_scale 1.0 -#@ set sdfout_min_rise_net_delay 0. -#@ set sdfout_min_fall_net_delay 0. -#@ set sdfout_min_rise_cell_delay 0. -#@ set sdfout_min_fall_cell_delay 0. -#@ set sdfout_write_to_output "false" -#@ set sdfout_allow_non_positive_constraints "false" -#@ set sdfin_top_instance_name "" -#@ set sdfin_min_rise_net_delay 0. -#@ set sdfin_min_fall_net_delay 0. -#@ set sdfin_min_rise_cell_delay 0. -#@ set sdfin_min_fall_cell_delay 0. -#@ set sdfin_rise_net_delay_type "maximum" -#@ set sdfin_fall_net_delay_type "maximum" -#@ set sdfin_rise_cell_delay_type "maximum" -#@ set sdfin_fall_cell_delay_type "maximum" -#@ set site_info_file ${synopsys_root}/admin/license/site_info -#@ if { [string compare $dc_shell_mode "tcl"] == 0 } { -#@ alias site_info sh cat $site_info_file -#@ } else { -#@ alias site_info "sh cat site_info_file" -#@ } -#@ set template_naming_style "%s_%p" -#@ set template_parameter_style "%s%d" -#@ set template_separator_style "_" -#@ set verilogout_equation "false" -#@ set verilogout_ignore_case "false" -#@ set verilogout_no_tri "false" -#@ set verilogout_inout_is_in "false" -#@ set verilogout_single_bit "false" -#@ set verilogout_higher_designs_first "FALSE" -#@ # set verilogout_levelize "FALSE" -#@ set verilogout_include_files {} -#@ set verilogout_unconnected_prefix "SYNOPSYS_UNCONNECTED_" -#@ set verilogout_show_unconnected_pins "FALSE" -#@ set verilogout_no_negative_index "FALSE" -#@ #set enable_2003.03_verilog_reader TRUE -#@ # to have a net instead of 1'b0 and 1'b1 in inouts: -#@ set verilogout_indirect_inout_connection "FALSE" -#@ -#@ # set vhdlout_architecture_name "SYN_%a_%u" -#@ set vhdlout_bit_type "std_logic" -#@ # set vhdlout_bit_type_resolved "TRUE" -#@ set vhdlout_bit_vector_type "std_logic_vector" -#@ # set vhdlout_conversion_functions {} -#@ # set vhdlout_dont_write_types "FALSE" -#@ set vhdlout_equations "FALSE" -#@ set vhdlout_one_name "'1'" -#@ set vhdlout_package_naming_style "CONV_PACK_%d" -#@ set vhdlout_preserve_hierarchical_types "VECTOR" -#@ set vhdlout_separate_scan_in "FALSE" -#@ set vhdlout_single_bit "USER" -#@ set vhdlout_target_simulator "" -#@ set vhdlout_three_state_name "'Z'" -#@ set vhdlout_three_state_res_func "" -#@ # set vhdlout_time_scale 1.0 -#@ set vhdlout_top_configuration_arch_name "A" -#@ set vhdlout_top_configuration_entity_name "E" -#@ set vhdlout_top_configuration_name "CFG_TB_E" -#@ set vhdlout_unknown_name "'X'" -#@ set vhdlout_upcase "FALSE" -#@ set vhdlout_use_packages {IEEE.std_logic_1164} -#@ set vhdlout_wired_and_res_func "" -#@ set vhdlout_wired_or_res_func "" -#@ set vhdlout_write_architecture "TRUE" -#@ set vhdlout_write_components "TRUE" -#@ set vhdlout_write_entity "TRUE" -#@ set vhdlout_write_top_configuration "FALSE" -#@ # set vhdlout_synthesis_off "TRUE" -#@ set vhdlout_zero_name "'0'" -#@ #set vhdlout_levelize "FALSE" -#@ set vhdlout_dont_create_dummy_nets "FALSE" -#@ set vhdlout_follow_vector_direction "TRUE" -#@ -#@ -#@ # vhdl netlist reader variables -#@ set enable_vhdl_netlist_reader "FALSE" -#@ -#@ # variables pertaining to VHDL library generation -#@ set vhdllib_timing_mesg "true" -#@ set vhdllib_timing_xgen "false" -#@ set vhdllib_timing_checks "true" -#@ set vhdllib_negative_constraint "false" -#@ set vhdllib_glitch_handle "true" -#@ set vhdllib_pulse_handle "use_vhdllib_glitch_handle" -#@ # /*vhdllib_architecture = {FTBM, UDSM, FTSM, FTGS, VITAL}; */ -#@ set vhdllib_architecture {VITAL} -#@ set vhdllib_tb_compare 0 -#@ set vhdllib_tb_x_eq_dontcare FALSE -#@ set vhdllib_logic_system "ieee-1164" -#@ set vhdllib_logical_name "" -#@ -#@ # variables pertaining to technology library processing -#@ set read_db_lib_warnings FALSE -#@ set read_translate_msff TRUE -#@ set libgen_max_differences -1 -#@ -#@ # -#@ # Gui Variable Group -#@ # used for design_vision and psyn_gui -#@ # -#@ set gui_auto_start 0 -#@ set gui_start_option_no_windows 0 -#@ group_variable gui_variables "gui_auto_start" -#@ group_variable gui_variables "gui_start_option_no_windows" -#@ -#@ # -#@ # If you like emacs, uncomment the next line -#@ # set text_editor_command "emacs -fn 8x13 %s &" ; -#@ -#@ # You can delete pairs from this list, but you can't add new ones -#@ # unless you also update the UIL files. So, customers can not add -#@ # dialogs to this list, only Synopsys can do that. -#@ # -#@ set view_independent_dialogs { "test_report" " Test Reports " "report_print" " Report " "report_options" " Report Options " "report_win" " Report Output " "manual_page" " Manual Page " } -#@ -#@ # if color Silicon Graphics workstation -#@ if { [info exists x11_vendor_string] && [info exists x11_is_color]} { -#@ if { $x11_vendor_string == "Silicon" && $x11_is_color == "true" } { -#@ set x11_set_cursor_foreground "magenta" -#@ set view_use_small_cursor "true" -#@ set view_set_selecting_color "white" -#@ } -#@ } -#@ -#@ # if running on an Apollo machine -#@ set found_x11_vendor_string_apollo 0 -#@ set found_arch_apollo 0 -#@ if { [info exists x11_vendor_string]} { -#@ if { $x11_vendor_string == "Apollo "} { -#@ set found_x11_vendor_string_apollo 1 -#@ } -#@ } -#@ if { [info exists arch]} { -#@ if { $arch == "apollo"} { -#@ set found_arch_apollo 1 -#@ } -#@ } -#@ if { $found_x11_vendor_string_apollo == 1 || $found_arch_apollo == 1} { -#@ set enable_page_mode "false" -#@ } else { -#@ set enable_page_mode "true" -#@ } -#@ -#@ # don't work around this bug on the Apollo -#@ if { $found_x11_vendor_string_apollo == 1} { -#@ set view_extend_thick_lines "false" -#@ } else { -#@ set view_extend_thick_lines "true" -#@ } -#@ -#@ # -#@ # Suffix Variable Group: -#@ # -#@ # Suffixes recognized by the Design Analyzer menu in file choices -#@ # -#@ if { $synopsys_program_name == "design_vision" || $synopsys_program_name == "psyn_gui" } { -#@ # For star 93040 do NOT include NET in list, 108991 : pdb suffix added -#@ set view_read_file_suffix {db gdb sdb pdb edif eqn fnc lsi mif pla st tdl v vhd vhdl xnf} -#@ } else { -#@ set view_read_file_suffix {db gdb sdb edif eqn fnc lsi mif NET pla st tdl v vhd vhdl xnf} -#@ } -#@ -#@ set view_analyze_file_suffix {v vhd vhdl} -#@ set view_write_file_suffix {gdb db sdb do edif eqn fnc lsi NET neted pla st tdl v vhd vhdl xnf} -#@ set view_execute_script_suffix {.script .scr .dcs .dcv .dc .con} -#@ set view_arch_types {sparcOS5 hpux10 rs6000 sgimips} -#@ -#@ # -#@ # links_to_layout Variable Group: -#@ # -#@ # These variables affect the read_timing, write_timing -#@ # set_annotated_delay, compile, create_wire_load and reoptimize_design -#@ # commands. -#@ # -#@ if {$synopsys_program_name != "dc_sms_shell"} { -#@ set auto_wire_load_selection "true" -#@ set compile_create_wire_load_table "false" -#@ } -#@ set rtl_load_resistance_factor 0.0 -#@ -#@ # power Variable Group: -#@ # -#@ # These variables affect the behavior of power optimization and analysis. -#@ # -#@ -#@ set power_keep_license_after_power_commands "false" -#@ set power_rtl_saif_file "power_rtl.saif" -#@ set power_sdpd_saif_file "power_sdpd.saif" -#@ set power_preserve_rtl_hier_names "false" -#@ set power_do_not_size_icg_cells "true" -#@ set power_hdlc_do_not_split_cg_cells "false" -#@ set power_cg_flatten "false" -#@ set power_opto_extra_high_dynamic_power_effort "false" -#@ set power_default_static_probability 0.5 -#@ set power_default_toggle_rate 0.1 -#@ set power_default_toggle_rate_type "fastest_clock" -#@ set power_model_preference "nlpm" -#@ set power_sa_propagation_effort "low" -#@ set power_sa_propagation_verbose "false" -#@ set power_fix_sdpd_annotation "true" -#@ set power_fix_sdpd_annotation_verbose "false" -#@ set power_sdpd_message_tolerance 0.00001 -#@ set do_operand_isolation "false" -#@ set power_cg_module_naming_style "" -#@ set power_cg_cell_naming_style "" -#@ set power_cg_gated_clock_net_naming_style "" -#@ set power_rclock_use_asynch_inputs "false" -#@ set power_rclock_inputs_use_clocks_fanout "true" -#@ set power_rclock_unrelated_use_fastest "true" -#@ set power_lib2saif_rise_fall_pd "false" -#@ set power_min_internal_power_threshold "" -#@ -#@ -#@ # SystemC related variables -#@ set systemcout_levelize "true" -#@ set systemcout_debug_mode "false" -#@ -#@ # ACS Variables -#@ if { [info exists acs_work_dir] } { -#@ set acs_area_report_suffix "area" -#@ set acs_autopart_max_area "0.0" -#@ set acs_autopart_max_percent "0.0" -#@ set acs_budgeted_cstr_suffix "con" -#@ set acs_compile_script_suffix "autoscr" -#@ set acs_constraint_file_suffix "con" -#@ set acs_cstr_report_suffix "cstr" -#@ set acs_db_suffix "db" -#@ set acs_dc_exec "" -#@ set acs_default_pass_name "pass" -#@ set acs_exclude_extensions {} -#@ set acs_exclude_list [list $synopsys_root] -#@ set acs_global_user_compile_strategy_script "default" -#@ set acs_hdl_verilog_define_list {} -#@ set acs_hdl_source {} -#@ set acs_lic_wait 0 -#@ set acs_log_file_suffix "log" -#@ set acs_make_args "set acs_make_args" -#@ set acs_make_exec "gmake" -#@ set acs_makefile_name "Makefile" -#@ set acs_num_parallel_jobs 1 -#@ set acs_override_report_suffix "report" -#@ set acs_override_script_suffix "scr" -#@ set acs_qor_report_suffix "qor" -#@ set acs_timing_report_suffix "tim" -#@ set acs_use_autopartition "false" -#@ set acs_use_default_delays "false" -#@ set acs_user_budgeting_script "budget.scr" -#@ set acs_user_compile_strategy_script_suffix "compile" -#@ set acs_verilog_extensions {.v} -#@ set acs_vhdl_extensions {.vhd} -#@ set acs_work_dir [pwd] -#@ set check_error_list [list CMD-004 CMD-006 CMD-007 CMD-008 CMD-009 CMD-010 CMD-011 CMD-012 CMD-014 CMD-015 CMD-016 CMD-019 CMD-026 CMD-031 CMD-037 DB-1 DCSH-11 DES-001 ACS-193 FILE-1 FILE-2 FILE-3 FILE-4 LINK-7 LINT-7 LINT-20 LNK-023 OPT-100 OPT-101 OPT-102 OPT-114 OPT-124 OPT-127 OPT-128 OPT-155 OPT-157 OPT-181 OPT-462 UI-11 UI-14 UI-15 UI-16 UI-17 UI-19 UI-20 UI-21 UI-22 UI-23 UI-40 UI-41 UID-4 UID-6 UID-7 UID-8 UID-9 UID-13 UID-14 UID-15 UID-19 UID-20 UID-25 UID-27 UID-28 UID-29 UID-30 UID-32 UID-58 UID-87 UID-103 UID-109 UID-270 UID-272 UID-403 UID-440 UID-444 UIO-2 UIO-3 UIO-4 UIO-25 UIO-65 UIO-66 UIO-75 UIO-94 UIO-95 EQN-6 EQN-11 EQN-15 EQN-16 EQN-18 EQN-20 ] -#@ set ilm_preserve_core_constraints "false" -#@ } -#@ -#@ # -#@ # -#@ # DesignTime Variable Group -#@ # -#@ # The variables which affect the DesignTime timing engine -#@ # -#@ -#@ set case_analysis_log_file "" -#@ set case_analysis_sequential_propagate "false" -#@ set create_clock_no_input_delay "false" -#@ set disable_auto_time_borrow "false" -#@ set disable_case_analysis "false" -#@ set disable_conditional_mode_analysis "false" -#@ set disable_library_transition_degradation "false" -#@ set dont_bind_unused_pins_to_logic_constant "false" -#@ set enable_slew_degradation "true" -#@ set high_fanout_net_pin_capacitance 1.000000 -#@ set high_fanout_net_threshold 1000 -#@ set lib_thresholds_per_lib "true" -#@ set rc_adjust_rd_when_less_than_rnet "true" -#@ set rc_ceff_delay_min_diff_ps 0.250000 -#@ set rc_degrade_min_slew_when_rd_less_than_rnet "false" -#@ set rc_driver_model_max_error_pct 0.160000 -#@ set rc_filter_rd_less_than_rnet "true" -#@ set rc_input_threshold_pct_fall 50.000000 -#@ set rc_input_threshold_pct_rise 50.000000 -#@ set rc_output_threshold_pct_fall 50.000000 -#@ set rc_output_threshold_pct_rise 50.000000 -#@ set rc_rd_less_than_rnet_threshold 0.450000 -#@ set rc_slew_derate_from_library 1.000000 -#@ set rc_slew_lower_threshold_pct_fall 20.000000 -#@ set rc_slew_lower_threshold_pct_rise 20.000000 -#@ set rc_slew_upper_threshold_pct_fall 80.000000 -#@ set rc_slew_upper_threshold_pct_rise 80.000000 -#@ set timing_disable_cond_default_arcs "false" -#@ #timing_enable_multiple_clocks_per_reg is on by default -#@ #set timing_enable_multiple_clocks_per_reg "false" -#@ set timing_report_attributes {dont_touch dont_use map_only size_only ideal_net infeasible_paths} -#@ set timing_self_loops_no_skew "false" -#@ set when_analysis_permitted "true" -#@ set when_analysis_without_case_analysis "false" -#@ -#@ -#@ # -#@ # Variable Group Definitions: -#@ # -#@ # The group_variable() command groups variables for display -#@ # in the "File/Defaults" dialog and defines groups of variables -#@ # for the list() command. -#@ # -#@ -#@ set enable_instances_in_report_net "true" -#@ # Set report options env variables -#@ set view_report_interactive "true" -#@ set view_report_output2file "false" -#@ set view_report_append "true" -#@ -#@ if { $synopsys_program_name != "ptxr" } { -#@ -#@ group_variable report_variables "enable_instances_in_report_net" -#@ group_variable report_variables "view_report_interactive" -#@ group_variable report_variables "view_report_output2file" -#@ group_variable report_variables "view_report_append" -#@ -#@ # "links_to_layout" variables are used by multiple commands -#@ # auto_wire_load_selection is also in the "compile" variable group. -#@ group_variable links_to_layout "auto_wire_load_selection" -#@ -#@ # variables starting with "compile" are also in the compile variable group -#@ group_variable links_to_layout "compile_dont_touch_annotated_cell_during_inplace_opt" -#@ -#@ group_variable links_to_layout "compile_update_annotated_delays_during_inplace_opt" -#@ group_variable links_to_layout "compile_create_wire_load_table" -#@ -#@ group_variable links_to_layout "reoptimize_design_changed_list_file_name" -#@ group_variable links_to_layout "sdfout_allow_non_positive_constraints" -#@ -#@ } ;# $synopsys_program_name != "ptxr" -#@ -#@ # -#@ # to find the XErrorDB and XKeySymDB for X11 file -#@ set motif_files ${synopsys_root}/admin/setup -#@ # set filename for logging input file -#@ set filename_log_file "filenames.log" -#@ # whether to delete the filename log after the normal exits -#@ set exit_delete_filename_log_file "true" -#@ -#@ # executable to fire off RTLA/BCV -#@ set xterm_executable "xterm" -#@ -#@ if { $synopsys_program_name != "ptxr" } { -#@ -#@ # "system" variables are used by multiple commands -#@ group_variable system auto_link_disable -#@ group_variable system auto_link_options -#@ group_variable system command_log_file -#@ group_variable system company -#@ group_variable system compatibility_version -#@ -#@ if { [string compare $dc_shell_mode "default"] == 0 } { -#@ group_variable system "current_design" -#@ group_variable system "current_instance" -#@ group_variable system "dc_shell_status" -#@ } else { -#@ set current_design "" -#@ set current_instance "" -#@ group_variable system "current_design" -#@ group_variable system "current_instance" -#@ } -#@ -#@ group_variable system "designer" -#@ group_variable system "echo_include_commands" -#@ group_variable system "enable_page_mode" -#@ group_variable system "change_names_update_inst_tree" -#@ group_variable system "change_names_dont_change_bus_members" -#@ group_variable system "default_name_rules" -#@ group_variable system "verbose_messages" -#@ group_variable system "link_library" -#@ group_variable system "link_force_case" -#@ group_variable system "search_path" -#@ group_variable system "synthetic_library" -#@ group_variable system "target_library" -#@ group_variable system "uniquify_naming_style" -#@ group_variable system "suppress_errors" -#@ group_variable system "find_converts_name_lists" -#@ group_variable system "filename_log_file" -#@ group_variable system "exit_delete_filename_log_file" -#@ group_variable system "syntax_check_status" -#@ group_variable system "context_check_status" -#@ -#@ #/* "compile" variables are used by the compile command */ -#@ group_variable compile "compile_assume_fully_decoded_three_state_busses" -#@ group_variable compile "compile_no_new_cells_at_top_level" -#@ group_variable compile "compile_dont_touch_annotated_cell_during_inplace_opt" -#@ group_variable compile "reoptimize_design_changed_list_file_name" -#@ group_variable compile "compile_create_wire_load_table" -#@ group_variable compile "compile_update_annotated_delays_during_inplace_opt" -#@ group_variable compile "compile_instance_name_prefix" -#@ group_variable compile "compile_instance_name_suffix" -#@ group_variable compile "compile_negative_logic_methodology" -#@ group_variable compile "compile_disable_hierarchical_inverter_opt" -#@ -#@ group_variable compile "port_complement_naming_style" -#@ group_variable compile "auto_wire_load_selection" -#@ group_variable compile "rtl_load_resistance_factor" -#@ group_variable compile "compile_implementation_selection" -#@ group_variable compile "compile_use_low_timing_effort" -#@ group_variable compile "compile_fix_cell_degradation" -#@ group_variable compile "compile_preserve_subdesign_interfaces" -#@ group_variable compile "compile_enable_constant_propagation_with_no_boundary_opt" -#@ group_variable compile "compile_delete_unloaded_sequential_cells" -#@ group_variable compile "enable_recovery_removal_arcs" -#@ group_variable compile "compile_checkpoint_phases" -#@ group_variable compile "compile_cpu_limit" -#@ group_variable compile "compile_top_all_paths" -#@ group_variable compile "compile_top_all_paths" -#@ group_variable compile "compile_top_acs_partition" -#@ group_variable compile "default_port_connection_class" -#@ group_variable compile "compile_retime_license_behavior" -#@ group_variable compile "dont_touch_nets_with_size_only_cells" -#@ group_variable compile "compile_seqmap_no_scan_cell" -#@ -#@ if { $synopsys_program_name == "dc_shell" && [shell_is_in_topographical_mode] } { -#@ group_variable compile "dct_prioritize_area_correlation" -#@ group_variable compile "compile_error_on_missing_physical_cells" -#@ } -#@ -#@ # "multibit" variables are used by the the multibit mapping functionality -#@ -#@ group_variable multibit "bus_multiple_separator_style" -#@ -#@ # "ilm" variables are used by Interface Logic Model functionality -#@ -#@ group_variable ilm "ilm_ignore_percentage" -#@ -#@ # "estimate" variables are used by the estimate command -#@ # The estimate command also recognizes the "compile" variables. -#@ group_variable estimate "estimate_resource_preference" -#@ -#@ # "synthetic_library" variables -#@ group_variable synlib "cache_dir_chmod_octal" -#@ group_variable synlib "cache_file_chmod_octal" -#@ group_variable synlib "cache_read" -#@ group_variable synlib "cache_read_info" -#@ group_variable synlib "cache_write" -#@ group_variable synlib "cache_write_info" -#@ group_variable synlib "synlib_dont_get_license" -#@ group_variable synlib "synlib_wait_for_design_license" -#@ group_variable synlib "synthetic_library" -#@ -#@ # "insert_dft" variables are used by the insert_dft and preview_dft commands -#@ #group_variable insert_dft "test_default_client_order" -#@ group_variable insert_dft "insert_dft_clean_up" -#@ group_variable insert_dft "insert_test_design_naming_style" -#@ group_variable insert_dft "test_clock_port_naming_style" -#@ group_variable insert_dft "test_default_min_fault_coverage" -#@ group_variable insert_dft "test_scan_clock_a_port_naming_style" -#@ group_variable insert_dft "test_scan_clock_b_port_naming_style" -#@ group_variable insert_dft "test_scan_clock_port_naming_style" -#@ group_variable insert_dft "test_scan_enable_inverted_port_naming_style" -#@ group_variable insert_dft "test_scan_enable_port_naming_style" -#@ group_variable insert_dft "test_scan_in_port_naming_style" -#@ group_variable insert_dft "test_scan_out_port_naming_style" -#@ group_variable insert_dft "test_non_scan_clock_port_naming_style" -#@ group_variable insert_dft "test_dedicated_subdesign_scan_outs" -#@ group_variable insert_dft "test_disable_find_best_scan_out" -#@ group_variable insert_dft "test_dont_fix_constraint_violations" -#@ group_variable insert_dft "test_isolate_hier_scan_out" -#@ group_variable insert_dft "test_mode_port_naming_style" -#@ group_variable insert_dft "test_mode_port_inverted_naming_style" -#@ group_variable insert_dft "compile_dont_use_dedicated_scanout" -#@ group_variable insert_dft "test_mux_constant_si" -#@ -#@ # "preview_scan" variables are used by the preview_scan command -#@ group_variable preview_scan "test_preview_scan_shows_cell_types" -#@ group_variable preview_scan "test_scan_link_so_lockup_key" -#@ group_variable preview_scan "test_scan_link_wire_key" -#@ group_variable preview_scan "test_scan_segment_key" -#@ group_variable preview_scan "test_scan_true_key" -#@ -#@ # "bsd" variables are used by the check_bsd and write_bsdl commands -#@ group_variable bsd "test_user_test_data_register_naming_style" -#@ group_variable bsd "test_user_defined_instruction_naming_style" -#@ group_variable bsd "test_bsdl_default_suffix_name" -#@ group_variable bsd "test_bsdl_max_line_length" -#@ group_variable bsd "test_cc_ir_masked_bits" -#@ group_variable bsd "test_cc_ir_value_of_masked_bits" -#@ -#@ group_variable bsd "test_bsd_allow_tolerable_violations" -#@ group_variable bsd "test_bsd_optimize_control_cell" -#@ group_variable bsd "test_bsd_control_cell_drive_limit" -#@ group_variable bsd "test_bsd_manufacturer_id" -#@ group_variable bsd "test_bsd_part_number" -#@ group_variable bsd "test_bsd_version_number" -#@ group_variable bsd "bsd_max_in_switching_limit" -#@ group_variable bsd "bsd_max_out_switching_limit" -#@ -#@ # testmanager variables -#@ group_variable testmanager "multi_pass_test_generation" -#@ -#@ # "testsim" variables -#@ # group_variable testsim "testsim_print_stats_file" -#@ -#@ # "test" variables -#@ group_variable test "test_default_bidir_delay" -#@ group_variable test "test_default_delay" -#@ group_variable test "test_default_period" -#@ group_variable test "test_default_strobe" -#@ group_variable test "test_default_strobe_width" -#@ group_variable test "test_capture_clock_skew" -#@ group_variable test "test_allow_clock_reconvergence" -#@ group_variable test "test_check_port_changes_in_capture" -#@ group_variable test "test_stil_max_line_length" -#@ group_variable test "test_infer_slave_clock_pulse_after_capture" -#@ group_variable test "test_rtldrc_latch_check_style" -#@ group_variable test "test_enable_capture_checks" -#@ -#@ # "write_test" variables are used by the write_test command -#@ group_variable write_test "write_test_formats" -#@ group_variable write_test "write_test_include_scan_cell_info" -#@ group_variable write_test "write_test_input_dont_care_value" -#@ group_variable write_test "write_test_max_cycles" -#@ group_variable write_test "write_test_max_scan_patterns" -#@ group_variable write_test "write_test_pattern_set_naming_style" -#@ group_variable write_test "write_test_scan_check_file_naming_style" -#@ group_variable write_test "write_test_vector_file_naming_style" -#@ group_variable write_test "write_test_round_timing_values" -#@ -#@ group_variable view "test_design_analyzer_uses_insert_scan" -#@ -#@ # "io" variables are used by the read, read_lib, db2sge and write commands -#@ group_variable io "bus_inference_descending_sort" -#@ group_variable io "bus_inference_style" -#@ #group_variable io "db2sge_output_directory" -#@ #group_variable io "db2sge_scale" -#@ #group_variable io "db2sge_overwrite" -#@ #group_variable io "db2sge_display_symbol_names" -#@ #group_variable io "db2sge_display_pin_names" -#@ #group_variable io "db2sge_display_instance_names" -#@ #group_variable io "db2sge_use_bustaps" -#@ #group_variable io "db2sge_use_compound_names" -#@ #group_variable io "db2sge_bit_type" -#@ #group_variable io "db2sge_bit_vector_type" -#@ #group_variable io "db2sge_one_name" -#@ #group_variable io "db2sge_zero_name" -#@ #group_variable io "db2sge_unknown_name" -#@ #group_variable io "db2sge_target_xp" -#@ #group_variable io "db2sge_tcf_package_file" -#@ #group_variable io "db2sge_use_lib_section" -#@ #group_variable io "db2sge_script" -#@ #group_variable io "db2sge_command" -#@ -#@ # group_variable io "equationout_and_sign" -#@ # group_variable io "equationout_or_sign" -#@ # group_variable io "equationout_postfix_negation" -#@ -#@ # group_variable io "lsiin_net_name_prefix" -#@ # group_variable io "lsiout_inverter_cell" -#@ # group_variable io "lsiout_upcase" -#@ -#@ #group_variable io "mentor_bidirect_value" -#@ #group_variable io "mentor_do_path" -#@ #group_variable io "mentor_input_output_property_name" -#@ #group_variable io "mentor_input_value" -#@ #group_variable io "mentor_logic_one_value" -#@ #group_variable io "mentor_logic_zero_one_property_name" -#@ #group_variable io "mentor_logic_zero_value" -#@ #group_variable io "mentor_output_value" -#@ #group_variable io "mentor_primitive_property_name" -#@ #group_variable io "mentor_primitive_property_value" -#@ #group_variable io "mentor_reference_property_name" -#@ #group_variable io "mentor_search_path" -#@ #group_variable io "mentor_write_symbols" -#@ # group_variable io "pla_read_create_flip_flop" -#@ # group_variable io "tdlout_upcase" -#@ group_variable io "write_name_nets_same_as_ports" -#@ -#@ # # [wjchen] 2006/08/14: The following 4 variables are obsoleted for DC simpilification. -#@ -#@ # group_variable io "xnfout_constraints_per_endpoint" -#@ # group_variable io "xnfout_default_time_constraints" -#@ # group_variable io "xnfout_clock_attribute_style" -#@ # group_variable io "xnfout_library_version" -#@ -#@ # # [wjchen] 2006/08/11: The following 8 variables are obsoleted for DC simpilification. -#@ # group_variable io "xnfin_family" -#@ # group_variable io "xnfin_ignore_pins" -#@ # group_variable io "xnfin_dff_reset_pin_name" -#@ # group_variable io "xnfin_dff_set_pin_name" -#@ # group_variable io "xnfin_dff_clock_enable_pin_name" -#@ # group_variable io "xnfin_dff_data_pin_name" -#@ # group_variable io "xnfin_dff_clock_pin_name" ; -#@ # group_variable io "xnfin_dff_q_pin_name"; -#@ -#@ group_variable io "sdfin_min_rise_net_delay" ; -#@ group_variable io "sdfin_min_fall_net_delay" ; -#@ group_variable io "sdfin_min_rise_cell_delay" ; -#@ group_variable io "sdfin_min_fall_cell_delay" ; -#@ group_variable io "sdfin_rise_net_delay_type" ; -#@ group_variable io "sdfin_fall_net_delay_type" ; -#@ group_variable io "sdfin_rise_cell_delay_type" ; -#@ group_variable io "sdfin_fall_cell_delay_type" ; -#@ group_variable io "sdfin_top_instance_name" ; -#@ group_variable io "sdfout_time_scale" ; -#@ group_variable io "sdfout_write_to_output" ; -#@ group_variable io "sdfout_top_instance_name" ; -#@ group_variable io "sdfout_min_rise_net_delay" ; -#@ group_variable io "sdfout_min_fall_net_delay" ; -#@ group_variable io "sdfout_min_rise_cell_delay" ; -#@ group_variable io "sdfout_min_fall_cell_delay" ; -#@ group_variable io "read_db_lib_warnings" ; -#@ group_variable io "read_translate_msff" ; -#@ group_variable io "libgen_max_differences" ; -#@ -#@ # #[wjchen] 2006/08/22: The following variables are hidden for XG mode for DC simpilification. -#@ # group_variable io "read_name_mapping_nowarn_libraries" ; -#@ # group_variable io "write_name_mapping_nowarn_libraries" ; -#@ -#@ -#@ # "edif" variables are used by the EDIF format read, read_lib, write, -#@ # and write_lib commands -#@ # group_variable edif "bus_dimension_separator_style" ; -#@ # group_variable edif "bus_extraction_style" ; -#@ group_variable edif "bus_inference_descending_sort" ; -#@ group_variable edif "bus_inference_style" ; -#@ group_variable edif "bus_naming_style" ; -#@ group_variable edif "bus_range_separator_style" ; -#@ # group_variable edif "edifin_autoconnect_offpageconnectors" ; -#@ # group_variable edif "edifin_autoconnect_ports" ; -#@ # group_variable edif "edifin_delete_empty_cells" ; -#@ # group_variable edif "edifin_delete_ripper_cells" ; -#@ # group_variable edif "edifin_ground_net_name" ; -#@ # group_variable edif "edifin_ground_net_property_name" ; -#@ # group_variable edif "edifin_ground_net_property_value" ; -#@ # group_variable edif "edifin_ground_port_name" ; -#@ # group_variable edif "edifin_instance_property_name" ; -#@ # group_variable edif "edifin_portinstance_disabled_property_name" ; -#@ # group_variable edif "edifin_portinstance_disabled_property_value" ; -#@ # group_variable edif "edifin_portinstance_property_name" ; -#@ # group_variable edif "edifin_power_net_name" ; -#@ # group_variable edif "edifin_power_net_property_name" ; -#@ # group_variable edif "edifin_power_net_property_value" ; -#@ # group_variable edif "edifin_power_port_name" ; -#@ # group_variable edif "edifin_use_identifier_in_rename" ; -#@ # group_variable edif "edifin_view_identifier_property_name" ; -#@ # group_variable edif "edifin_dc_script_flag" ; -#@ # group_variable edif "edifin_lib_logic_1_symbol" ; -#@ # group_variable edif "edifin_lib_logic_0_symbol" ; -#@ # group_variable edif "edifin_lib_in_port_symbol" ; -#@ # group_variable edif "edifin_lib_out_port_symbol" ; -#@ # group_variable edif "edifin_lib_inout_port_symbol" ; -#@ # group_variable edif "edifin_lib_in_osc_symbol" ; -#@ # group_variable edif "edifin_lib_out_osc_symbol" ; -#@ # group_variable edif "edifin_lib_inout_osc_symbol" ; -#@ # group_variable edif "edifin_lib_mentor_netcon_symbol" ; -#@ # group_variable edif "edifin_lib_ripper_bits_property" ; -#@ # group_variable edif "edifin_lib_ripper_bus_end" ; -#@ # group_variable edif "edifin_lib_ripper_cell_name" ; -#@ # group_variable edif "edifin_lib_ripper_view_name" ; -#@ # group_variable edif "edifin_lib_route_grid" ; -#@ # group_variable edif "edifin_lib_templates" ; -#@ # group_variable edif "edifout_dc_script_flag" ; -#@ # group_variable edif "edifout_design_name" ; -#@ # group_variable edif "edifout_designs_library_name" ; -#@ # group_variable edif "edifout_display_instance_names" ; -#@ # group_variable edif "edifout_display_net_names" ; -#@ # group_variable edif "edifout_external" ; -#@ # group_variable edif "edifout_external_graphic_view_name" ; -#@ # group_variable edif "edifout_external_netlist_view_name" ; -#@ # group_variable edif "edifout_external_schematic_view_name" ; -#@ # group_variable edif "edifout_ground_name" ; -#@ # group_variable edif "edifout_ground_net_name" ; -#@ # group_variable edif "edifout_ground_net_property_name" ; -#@ # group_variable edif "edifout_ground_net_property_value" ; -#@ # group_variable edif "edifout_ground_pin_name" ; -#@ # group_variable edif "edifout_ground_port_name" ; -#@ # group_variable edif "edifout_instance_property_name" ; -#@ # group_variable edif "edifout_instantiate_ports" ; -#@ # group_variable edif "edifout_library_graphic_view_name" ; -#@ # group_variable edif "edifout_library_netlist_view_name" ; -#@ # group_variable edif "edifout_library_schematic_view_name" ; -#@ # group_variable edif "edifout_merge_libraries" ; -#@ # group_variable edif "edifout_multidimension_arrays" ; -#@ # group_variable edif "edifout_name_oscs_different_from_ports" ; -#@ # group_variable edif "edifout_name_rippers_same_as_wires" ; -#@ # group_variable edif "edifout_netlist_only" ; -#@ # group_variable edif "edifout_no_array" ; -#@ # group_variable edif "edifout_numerical_array_members" ; -#@ # group_variable edif "edifout_pin_direction_property_name" ; -#@ # group_variable edif "edifout_pin_direction_in_value" ; -#@ # group_variable edif "edifout_pin_direction_inout_value" ; -#@ # group_variable edif "edifout_pin_direction_out_value" ; -#@ # group_variable edif "edifout_pin_name_property_name" ; -#@ # group_variable edif "edifout_portinstance_disabled_property_name" ; -#@ # group_variable edif "edifout_portinstance_disabled_property_value" ; -#@ # group_variable edif "edifout_portinstance_property_name" -#@ # group_variable edif "edifout_power_and_ground_representation" -#@ # group_variable edif "edifout_power_name" -#@ # group_variable edif "edifout_power_net_name" -#@ # group_variable edif "edifout_power_net_property_name" -#@ # group_variable edif "edifout_power_net_property_value" -#@ # group_variable edif "edifout_power_pin_name" -#@ # group_variable edif "edifout_power_port_name" -#@ # group_variable edif "edifout_skip_port_implementations" -#@ # group_variable edif "edifout_target_system" -#@ # group_variable edif "edifout_top_level_symbol" -#@ # group_variable edif "edifout_translate_origin" -#@ # group_variable edif "edifout_unused_property_value" -#@ # group_variable edif "edifout_write_attributes" -#@ # group_variable edif "edifout_write_constraints" -#@ # group_variable edif "edifout_write_properties_list" -#@ # group_variable edif "write_name_nets_same_as_ports" -#@ -#@ # "hdl" variables are variables pertaining to hdl reading and optimizing -#@ group_variable hdl "bus_dimension_separator_style" -#@ group_variable hdl "bus_minus_style" -#@ group_variable hdl "bus_naming_style" -#@ group_variable hdl "hdlin_ignore_textio_constructs" -#@ group_variable hdl "hdlin_latch_always_async_set_reset" -#@ group_variable hdl "hdlin_ff_always_sync_set_reset" -#@ group_variable hdl "hdlin_ff_always_async_set_reset" -#@ group_variable hdl "hdlin_check_input_netlist" -#@ group_variable hdl "hdlin_check_no_latch" -#@ group_variable hdl "hdlin_reporting_level" -#@ group_variable hdl "hdlin_infer_mux" -#@ group_variable hdl "hdlin_mux_oversize_ratio" -#@ group_variable hdl "hdlin_mux_size_limit" -#@ group_variable hdl "hdlin_infer_multibit" -#@ group_variable hdl "hdl_preferred_license" -#@ group_variable hdl "hdl_keep_licenses" -#@ group_variable hdl "hlo_resource_allocation" -#@ group_variable hdl "template_naming_style" -#@ group_variable hdl "template_parameter_style" -#@ group_variable hdl "template_separator_style" -#@ group_variable hdl "verilogout_equation" -#@ group_variable hdl "verilogout_ignore_case" -#@ group_variable hdl "verilogout_no_tri" -#@ group_variable hdl "verilogout_inout_is_in" -#@ group_variable hdl "verilogout_single_bit" -#@ group_variable hdl "verilogout_higher_designs_first" -#@ # group_variable hdl "verilogout_levelize" -#@ group_variable hdl "verilogout_include_files" -#@ group_variable hdl "verilogout_unconnected_prefix" -#@ group_variable hdl "verilogout_show_unconnected_pins" -#@ group_variable hdl "verilogout_no_negative_index" -#@ group_variable hdl "hdlin_enable_rtldrc_info" -#@ group_variable hdl "hdlin_sv_blackbox_modules" -#@ group_variable hdl "hdlin_infer_function_local_latches" -#@ group_variable hdl "hdlin_module_arch_name_splitting" -#@ group_variable hdl "hdlin_mux_size_min" -#@ group_variable hdl "hdlin_prohibit_nontri_multiple_drivers" -#@ group_variable hdl "hdlin_subprogram_default_values" -#@ group_variable hdl "hdlin_upcase_names" -#@ group_variable hdl "hdlin_vhdl_std" -#@ group_variable hdl "hdlin_vhdl93_concat" -#@ group_variable hdl "hdlin_vhdl_syntax_extensions" -#@ group_variable hdl "hdlin_vrlg_std" -#@ group_variable hdl "hdlin_while_loop_iterations" -#@ group_variable hdl "hdlin_auto_save_templates" -#@ group_variable hdl "hdlin_elab_errors_deep" -#@ group_variable hdl "hdlin_enable_assertions" -#@ group_variable hdl "hdlin_enable_configurations" -#@ group_variable hdl "hdlin_field_naming_style" -#@ group_variable hdl "hdlin_generate_naming_style" -#@ group_variable hdl "hdlin_generate_separator_style" -#@ group_variable hdl "hdlin_enable_relative_placement" -#@ group_variable hdl "hdlin_mux_rp_limit" -#@ group_variable hdl "hdlin_keep_signal_name" -#@ group_variable hdl "hdlin_module_name_limit" -#@ group_variable hdl "hdlin_mux_size_only" -#@ group_variable hdl "hdlin_preserve_sequential" -#@ group_variable hdl "hdlin_presto_cell_name_prefix" -#@ group_variable hdl "hdlin_presto_net_name_prefix" -#@ group_variable hdl "hdlin_strict_verilog_reader" -#@ group_variable hdl "hdlin_shorten_long_module_name" -#@ group_variable hdl "hdlin_sv_packages" -#@ group_variable hdl "hdlin_sv_tokens" -#@ group_variable hdl "hdlin_enable_elaborate_ref_linking" -#@ group_variable hdl "hdlin_enable_hier_naming" -#@ group_variable hdl "hdlin_autoread_verilog_extensions" -#@ group_variable hdl "hdlin_autoread_sverilog_extensions" -#@ group_variable hdl "hdlin_autoread_vhdl_extensions" -#@ group_variable hdl "hdlin_autoread_exclude_extensions" -#@ group_variable hdl "hdlin_enable_upf_compatible_naming" -#@ group_variable hdl "hdlin_report_sequential_pruning" -#@ group_variable hdl "hdlin_analyze_verbose_mode" -#@ -#@ # "vhdlio" variables are variables pertaining to VHDL generation -#@ group_variable vhdlio "vhdllib_timing_mesg" -#@ group_variable vhdlio "vhdllib_timing_xgen" -#@ group_variable vhdlio "vhdllib_timing_checks" -#@ group_variable vhdlio "vhdllib_negative_constraint" -#@ group_variable vhdlio "vhdllib_pulse_handle" -#@ group_variable vhdlio "vhdllib_glitch_handle" -#@ group_variable vhdlio "vhdllib_architecture" -#@ group_variable vhdlio "vhdllib_tb_compare" -#@ group_variable vhdlio "vhdllib_tb_x_eq_dontcare" -#@ group_variable vhdlio "vhdllib_logic_system" -#@ group_variable vhdlio "vhdllib_logical_name" -#@ -#@ # group_variable vhdlio "vhdlout_architecture_name" -#@ group_variable vhdlio "vhdlout_bit_type" -#@ # group_variable vhdlio "vhdlout_bit_type_resolved" -#@ group_variable vhdlio "vhdlout_bit_vector_type" -#@ # group_variable vhdlio "vhdlout_conversion_functions" -#@ # group_variable vhdlio "vhdlout_dont_write_types" -#@ group_variable vhdlio "vhdlout_equations" -#@ group_variable vhdlio "vhdlout_one_name" -#@ group_variable vhdlio "vhdlout_package_naming_style" -#@ group_variable vhdlio "vhdlout_preserve_hierarchical_types" -#@ group_variable vhdlio "vhdlout_separate_scan_in" -#@ group_variable vhdlio "vhdlout_single_bit" -#@ group_variable vhdlio "vhdlout_target_simulator" -#@ group_variable vhdlio "vhdlout_top_configuration_arch_name" -#@ group_variable vhdlio "vhdlout_top_configuration_entity_name" -#@ group_variable vhdlio "vhdlout_top_configuration_name" -#@ group_variable vhdlio "vhdlout_three_state_name" -#@ group_variable vhdlio "vhdlout_three_state_res_func" -#@ # group_variable vhdlio "vhdlout_time_scale" -#@ group_variable vhdlio "vhdlout_unknown_name" -#@ group_variable vhdlio "vhdlout_use_packages" -#@ group_variable vhdlio "vhdlout_wired_and_res_func" -#@ group_variable vhdlio "vhdlout_wired_or_res_func" -#@ group_variable vhdlio "vhdlout_write_architecture" -#@ group_variable vhdlio "vhdlout_write_entity" -#@ group_variable vhdlio "vhdlout_write_top_configuration" -#@ # group_variable vhdlio "vhdlout_synthesis_off" -#@ group_variable vhdlio "vhdlout_write_components" -#@ group_variable vhdlio "vhdlout_zero_name" -#@ # group_variable vhdlio "vhdlout_levelize" -#@ group_variable vhdlio "vhdlout_dont_create_dummy_nets" -#@ group_variable vhdlio "vhdlout_follow_vector_direction" -#@ -#@ # "suffix" variables are used to find the suffixes of different file types -#@ group_variable suffix "view_execute_script_suffix" -#@ group_variable suffix "view_read_file_suffix" -#@ group_variable suffix "view_analyze_file_suffix" -#@ group_variable suffix "view_write_file_suffix" -#@ -#@ # Meenakshi: Added new group scc (for SystemC compiler) -#@ group_variable scc {systemcout_levelize} -#@ group_variable scc {systemcout_debug_mode} -#@ -#@ # "power" variables are for power-analysis. -#@ group_variable power {power_keep_license_after_power_commands} -#@ group_variable power {power_preserve_rtl_hier_names} -#@ group_variable power {power_do_not_size_icg_cells} -#@ group_variable power {power_hdlc_do_not_split_cg_cells} -#@ group_variable power {power_rtl_saif_file} -#@ group_variable power {power_sdpd_saif_file} -#@ group_variable power {power_cg_flatten} -#@ group_variable power {power_opto_extra_high_dynamic_power_effort} -#@ group_variable power {power_default_static_probability} -#@ group_variable power {power_default_toggle_rate} -#@ group_variable power {power_default_toggle_rate_type} -#@ group_variable power {power_model_preference} -#@ group_variable power {power_sa_propagation_effort} -#@ group_variable power {power_sa_propagation_verbose} -#@ group_variable power {power_fix_sdpd_annotation} -#@ group_variable power {power_fix_sdpd_annotation_verbose} -#@ group_variable power {power_sdpd_message_tolerance} -#@ group_variable power {power_rclock_use_asynch_inputs} -#@ group_variable power {power_rclock_inputs_use_clocks_fanout} -#@ group_variable power {power_rclock_unrelated_use_fastest} -#@ group_variable power {power_lib2saif_rise_fall_pd} -#@ group_variable power {power_min_internal_power_threshold} -#@ group_variable power {power_cg_module_naming_style} -#@ group_variable power {power_cg_cell_naming_style} -#@ group_variable power {power_cg_gated_clock_net_naming_style} -#@ group_variable power {do_operand_isolation} -#@ -#@ # dpcm variables are used by DPCM lib and controllong DC when using DPCM -#@ -#@ if { [info exists dpcm_debuglevel] } { -#@ group_variable dpcm "dpcm_debuglevel" -#@ group_variable dpcm "dpcm_rulespath" -#@ group_variable dpcm "dpcm_rulepath" -#@ group_variable dpcm "dpcm_tablepath" -#@ group_variable dpcm "dpcm_libraries" -#@ group_variable dpcm "dpcm_version" -#@ group_variable dpcm "dpcm_level" -#@ group_variable dpcm "dpcm_temperaturescope" -#@ group_variable dpcm "dpcm_voltagescope" -#@ group_variable dpcm "dpcm_functionscope" -#@ group_variable dpcm "dpcm_wireloadscope" -#@ group_variable dpcm "dpcm_slewlimit" -#@ group_variable dpcm "dpcm_arc_sense_mapping" -#@ -#@ } -#@ -#@ set dpcm_slewlimit "TRUE" -#@ -#@ # executable to fire off RTLA/BCV -#@ group_variable hdl {xterm_executable} -#@ -#@ # Variable group for Chip Compiler -#@ if {[info exists acs_work_dir]} { -#@ group_variable acs acs_area_report_suffix -#@ group_variable acs acs_autopart_max_area -#@ group_variable acs acs_autopart_max_percent -#@ group_variable acs acs_budgeted_cstr_suffix -#@ group_variable acs acs_compile_script_suffix -#@ group_variable acs acs_constraint_file_suffix -#@ group_variable acs acs_cstr_report_suffix -#@ group_variable acs acs_db_suffix -#@ group_variable acs acs_dc_exec -#@ group_variable acs acs_default_pass_name -#@ group_variable acs acs_exclude_extensions -#@ group_variable acs acs_exclude_list -#@ group_variable acs acs_global_user_compile_strategy_script -#@ group_variable acs acs_hdl_verilog_define_list -#@ group_variable acs acs_hdl_source -#@ group_variable acs acs_lic_wait -#@ group_variable acs acs_log_file_suffix -#@ group_variable acs acs_make_args -#@ group_variable acs acs_make_exec -#@ group_variable acs acs_makefile_name -#@ group_variable acs acs_num_parallel_jobs -#@ group_variable acs acs_override_report_suffix -#@ group_variable acs acs_override_script_suffix -#@ group_variable acs acs_qor_report_suffix -#@ group_variable acs acs_timing_report_suffix -#@ group_variable acs acs_use_autopartition -#@ group_variable acs acs_use_default_delays -#@ group_variable acs acs_user_budgeting_script -#@ group_variable acs acs_user_compile_strategy_script_suffix -#@ group_variable acs acs_verilog_extensions -#@ group_variable acs acs_vhdl_extensions -#@ group_variable acs acs_work_dir -#@ group_variable acs check_error_list -#@ group_variable acs ilm_preserve_core_constraints -#@ -#@ } -#@ -#@ # -#@ # DesignTime Variable Group timing -#@ # -#@ -#@ group_variable timing case_analysis_log_file -#@ group_variable timing case_analysis_sequential_propagate -#@ group_variable timing case_analysis_with_logic_constants -#@ group_variable timing create_clock_no_input_delay -#@ group_variable timing disable_auto_time_borrow -#@ group_variable timing disable_case_analysis -#@ group_variable timing disable_conditional_mode_analysis -#@ group_variable timing disable_library_transition_degradation -#@ group_variable timing dont_bind_unused_pins_to_logic_constant -#@ group_variable timing enable_slew_degradation -#@ group_variable timing high_fanout_net_pin_capacitance -#@ group_variable timing high_fanout_net_threshold -#@ group_variable timing lib_thresholds_per_lib -#@ group_variable timing rc_adjust_rd_when_less_than_rnet -#@ group_variable timing rc_ceff_delay_min_diff_ps -#@ group_variable timing rc_degrade_min_slew_when_rd_less_than_rnet -#@ group_variable timing rc_driver_model_max_error_pct -#@ group_variable timing rc_filter_rd_less_than_rnet -#@ group_variable timing rc_input_threshold_pct_fall -#@ group_variable timing rc_input_threshold_pct_rise -#@ group_variable timing rc_output_threshold_pct_fall -#@ group_variable timing rc_output_threshold_pct_rise -#@ group_variable timing rc_rd_less_than_rnet_threshold -#@ group_variable timing rc_slew_derate_from_library -#@ group_variable timing rc_slew_lower_threshold_pct_fall -#@ group_variable timing rc_slew_lower_threshold_pct_rise -#@ group_variable timing rc_slew_upper_threshold_pct_fall -#@ group_variable timing rc_slew_upper_threshold_pct_rise -#@ group_variable timing timing_disable_cond_default_arcs -#@ # group_variable timing timing_enable_multiple_clocks_per_reg -#@ group_variable timing timing_report_attributes -#@ group_variable timing timing_self_loops_no_skew -#@ group_variable timing when_analysis_permitted -#@ group_variable timing when_analysis_without_case_analysis -#@ -#@ } ;# $synopsys_program_name != "ptxr" -#@ -#@ if { $synopsys_program_name == "icc_shell"} { -#@ # -#@ # IC Compile Variable Group: -#@ # -#@ # These variables affect the designs created by the route_opt command. -#@ # -#@ group_variable routeopt routeopt_checkpoint -#@ group_variable routeopt routeopt_disable_cpulimit -#@ } -#@ -#@ if { $synopsys_program_name == "icc_shell"} { -#@ # -#@ # IC Compiler Variable Group: MCMM -#@ # -#@ # These variables affect Multi-Corner/Multi-Mode. Currently, MCMM is -#@ # only supported in ICC--hence the "icc_shell" qualification, above -#@ # -#@ group_variable MCMM mcmm_enable_high_capacity_flow -#@ } -#@ -#@ # Aliases for backwards compatibility or other reasons -#@ group_variable compile {compile_log_format} -#@ alias view_cursor_number x11_set_cursor_number -#@ alias set_internal_load set_load -#@ alias set_internal_arrival set_arrival -#@ alias set_connect_delay "set_annotated_delay -net" -#@ alias create_test_vectors create_test_patterns -#@ alias compile_test insert_test -#@ alias check_clocks check_timing -#@ alias lint check_design -#@ # gen removed; alias gen create_schematic -#@ alias free remove_design -#@ alias group_bus create_bus -#@ alias ungroup_bus remove_bus -#@ alias groupvar group_variable -#@ alias report_constraints report_constraint -#@ alias report_attributes report_attribute -#@ alias fsm_reduce reduce_fsm -#@ alias fsm_minimize minimize_fsm -#@ alias disable_timing set_disable_timing -#@ alias dont_touch set_dont_touch -#@ alias dont_touch_network set_dont_touch_network -#@ alias dont_use set_dont_use -#@ alias fix_hold set_fix_hold -#@ alias prefer set_prefer -#@ alias remove_package "echo remove_package command is obsolete: packages are stored on disk not in-memory:" -#@ alias analyze_scan preview_scan -#@ alias get_clock get_clocks -#@ alias dc_shell_is_in_incr_mode shell_is_in_xg_mode -#@ alias set_vh_module_options set_dps_module_options -#@ alias set_vh_physopt_options set_dps_options -#@ alias update_vh_design update_dps_design -#@ alias vh_start dps_start -#@ alias vh_end dps_end -#@ alias all_vh_modules all_dps_modules -#@ alias all_designs_of_vh all_designs_of_dps -#@ alias vh_use_auto_partitioning dps_auto_partitioning -#@ alias vh_write_changes dps_write_changes -#@ alias vh_read_changes dps_read_changes -#@ alias vh_write_module_clock dps_write_module_clock -#@ alias get_lib get_libs -#@ -#@ # Enable unsupported psyn commands -#@ if { $synopsys_program_name == "psyn_shell" || $synopsys_program_name == "icc_shell"} { -#@ proc enable_unsupported_commands { { arg "default" } } { -#@ global cgpi_use_new_wire_factors -#@ global cgpi_use_relative_wire_factors -#@ global cgpi_use_new_path_factors -#@ global pwlm_use_new_wire_factors -#@ global pwlm_use_relative_wire_factors -#@ global pwlm_use_new_path_factors -#@ global psyn_unsupported_commands_dir -#@ global synopsys_root -#@ if {![info exists psyn_unsupported_commands_dir]} { -#@ set psyn_unsupported_commands_dir $synopsys_root/auxx/syn/psyn/unsupported_commands -#@ } -#@ set psyn_unsupported_commands_option1 $arg -#@ if {[file readable $psyn_unsupported_commands_dir/setup.tcl]} { -#@ source $psyn_unsupported_commands_dir/setup.tcl -#@ } else { -#@ source -encrypted $psyn_unsupported_commands_dir/setup.tcl.e -#@ } -#@ } -#@ } -#@ # For Intel -#@ if { $synopsys_program_name == "icc_shell"} { -#@ set psyn_unsupported_commands_dir $synopsys_root/auxx/syn/psyn/unsupported_commands -#@ source -encrypted $psyn_unsupported_commands_dir/max_dist.tcl.e -#@ } -#@ -#@ -#@ if { $synopsys_program_name == "icc_shell"} { -#@ # to enable CLE readline-ish terminal by default for ICC -#@ set sh_enable_line_editing true -#@ -#@ # Astro forms create an enormous number of new variables which are -#@ # very annoying for users to see, so the default of this variable -#@ # for ICC is false -#@ set sh_new_variable_message false -#@ } -#@ -#@ if { $synopsys_program_name == "icc_shell" || (($synopsys_program_name == "dc_shell") && ([shell_is_in_topographical_mode])) } { -#@ source $synopsys_root/auxx/syn/psyn/verify_ilm.tcl -#@ } -#@ -#@ # Enable vh psyn commands -#@ if { $synopsys_program_name == "psyn_shell" } { -#@ proc enable_vh_flow { } { -#@ global VH_SCRIPT_FILE -#@ global synopsys_root -#@ global suppress_errors -#@ set suppress_errors "$suppress_errors CMD-041 UID-95 SEL-003 SEL-005" -#@ if {![info exists VH_SCRIPT_FILE]} { -#@ set VH_SCRIPT_FILE $synopsys_root/auxx/syn/psyn/vh_pc.tcl.e -#@ } -#@ if {[file readable $VH_SCRIPT_FILE]} { -#@ if {[string match *.tcl $VH_SCRIPT_FILE]} { -#@ source $VH_SCRIPT_FILE -#@ } else { -#@ source -encrypted $VH_SCRIPT_FILE -#@ } -#@ } else { -#@ puts "Error: VH script file $VH_SCRIPT_FILE not found." -#@ } -#@ } -#@ } -#@ -#@ -#@ #Turn on enable_netl_view to true by default. -#@ set enable_netl_view "TRUE" -#@ -#@ -#@ #Turn on physopt_bypass_multiple_plib_check by default -#@ if { $synopsys_program_name == "psyn_shell" } { -#@ set physopt_bypass_multiple_plib_check TRUE -#@ } -#@ -#@ # The ls command is gone, now it is just an alias for dc_shell eqn mode -#@ -#@ if { [string compare $dc_shell_mode "default"] == 0 } { -#@ if { ( $sh_arch == {mips}) && ( ( $synopsys_program_name == {design_analyzer}) || ( $isatty == 0)) } { -#@ alias ls "sh ls -a " -#@ } else { -#@ if { ( $sh_arch == {mips}) || ( $sh_arch == {necmips}) } { -#@ alias ls "sh ls -aC " -#@ } else { -#@ alias ls "sh ls -aC " -#@ } -#@ } -#@ } -#@ -#@ # Aliases for RouteCompiler -#@ alias run_rodeo_router route66 -#@ -#@ # Removing route_global from the code. Earlier it was hidden. --Mukesh -#@ #proc route_global {} { -#@ # global route_global_keep_tmp_data -#@ # global rt66_dont_lock_dir -#@ # -#@ # set rt66_dont_lock_dir TRUE -#@ # -#@ # for { set i 0} {1==1} {incr i} { -#@ # set wdir [file join [pwd] ".route_global.$i"] -#@ # if {[file exist $wdir] == 0} { -#@ # break; -#@ # } -#@ # } -#@ # -#@ # set_routing_options -cut_out_covered_port CORE_ONLY -#@ # set_routing_options -internal_routing FALSE -#@ # set_routing_options -stick_routing FALSE -#@ # -#@ # ###puts "wdir = $wdir" -#@ # -#@ # set success [route66 -global -dontstop -dir $wdir] -#@ # -#@ # #clean tmp data if required: -#@ # if { $success == 1 } { -#@ # if [catch {string toupper $route_global_keep_tmp_data} result] { -#@ # #variable is not defined -#@ # ###puts "result_1 = $result => removing dir ..." -#@ # catch { file delete -force $wdir } -#@ # } else { -#@ # #variable is set to FALSE -#@ # if { [string compare $result "TRUE"] != 0} { -#@ # ###puts "result_2 = $result => removing dir ..." -#@ # catch { file delete -force $wdir } -#@ # } -#@ # } -#@ # } -#@ # -#@ # set rt66_dont_lock_dir FALSE -#@ # return 1 -#@ #} -#@ #define_proc_attributes route_global -hidden -#@ -#@ #/* Aliases added for report command */ -#@ alias report_clock_constraint "report_timing -path end -to all_registers(-data_pins)" -#@ alias report_clock_fanout "report_transitive_fanout -clock_tree" -#@ alias report_clocks report_clock -#@ alias report_synthetic report_cell -#@ -#@ # Alias added for Ultra backward compatibility mode -#@ alias set_ultra_mode set_ultra_optimization -#@ -#@ # alias for write_sge and menu item in DA for db2sge -#@ -#@ #if { [string compare $dc_shell_mode "tcl"] == 0 } { -#@ # set db2sge_script ${synopsys_root}/admin/setup/.dc_write_sge.tcl -#@ #} else { -#@ # set db2sge_script ${synopsys_root}/admin/setup/.dc_write_sge -#@ #} -#@ -#@ #set db2sge_command ${synopsys_root}/${sh_arch}/syn/bin/db2sge -#@ set view_script_submenu_items "\"DA to SGE Transfer\" write_sge" -#@ -#@ -#@ if { $synopsys_program_name != "lc_shell"} { -#@ # read schematic annotation setup file -#@ #source ${synopsys_root}/admin/setup/.dc_annotate -#@ -#@ # setup the default layer settings -#@ #source ${synopsys_root}/admin/setup/.dc_layers -#@ -#@ if {$synopsys_program_name != "dc_sms_shell"} { -#@ source ${synopsys_root}/admin/setup/.dc_name_rules -#@ } -#@ } else { -#@ #for read_lib -html -#@ source ${synopsys_root}/auxx/syn/lc/read_lib_html_msg_list.tcl -#@ } -#@ # -- Starting source /tools/synopsys/synthesis/j201409sp3/auxx/syn/lc/read_lib_html_msg_list.tcl - -#@ ############################################################################## -#@ # message ID and descriptions for read_lib -html -#@ ############################################################################## -#@ set read_lib_ccs_noise_msg { -#@ LBDB-660 -#@ LBDB-706 -#@ LBDB-708 -#@ LBDB-709 -#@ LBDB-710 -#@ LBDB-711 -#@ LBDB-712 -#@ LBDB-713 -#@ LBDB-714 -#@ LBDB-715 -#@ LBDB-716 -#@ LBDB-717 -#@ LBDB-718 -#@ LBDB-733 -#@ LBDB-734 -#@ LBDB-784 -#@ LBDB-824 -#@ LBDB-825 -#@ LBDB-858 -#@ LBDB-898 -#@ LBDB-899 -#@ LBDB-908 -#@ LBDB-920 -#@ LBDB-935 -#@ LBDB-936 -#@ LBDB-937 -#@ LBDB-938 -#@ LBDB-939 -#@ } -#@ # -- End source /tools/synopsys/synthesis/j201409sp3/auxx/syn/lc/read_lib_html_msg_list.tcl - -#@ -#@ if { $synopsys_program_name == "psyn_gui"} { -#@ # read RouteCompiler GUI file for timing critical pathes. -#@ source ${synopsys_root}/auxx/syn/route_gui/write_route_timing_path.tcl -#@ } -#@ -#@ # Set physopt_dw_opto to false -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ set physopt_dw_opto FALSE -#@ } -#@ -#@ #/* Read budgeting setup script */ -#@ -#@ if { [string compare $dc_shell_mode "default"] == 0 } { -#@ -#@ # Need a encrypted file in Tcl format for budget.setup.et -#@ if { $sh_arch != "msvc50" && $sh_arch != "alpha_nt" } { -#@ # source -e synopsys_root + "/admin/setup/budget.setup.et" -#@ } -#@ } -#@ -#@ if { $synopsys_program_name == "icc_shell"} { -#@ source $synopsys_root/auxx/syn/.icc_procs.tcl -#@ source -encrypted $synopsys_root/auxx/syn/cts/fast_atomic_cts.tcl.e -#@ } -#@ -#@ if { $synopsys_program_name == "icc_shell"} { -#@ alias report_scenario report_scenarios -#@ } -#@ -#@ # floorplanning preferences globals -#@ global fp_snap_type -#@ -#@ set fp_snap_type(port) wiretrack -#@ set fp_snap_type(cell) litho -#@ set fp_snap_type(pin) wiretrack -#@ set fp_snap_type(movebound) litho -#@ set fp_snap_type(port_shape) wiretrack -#@ set fp_snap_type(wiring_keepout) wiretrack -#@ set fp_snap_type(placement_keepout) litho -#@ set fp_snap_type(net_shape) wiretrack -#@ set fp_snap_type(route_shape) wiretrack -#@ set fp_snap_type(none) litho -#@ -#@ # STAR 9000615813. PWR-18 is no longer internally suppressed. -#@ # Instead call tcl suppress_message so that it can be unsuppressed by users in -#@ # command line if needed -#@ suppress_message PWR-18 -#@ -#@ # alias for write_sge is always the last line of the setup file -#@ #if { [string compare $dc_shell_mode "tcl"] == 0 } { -#@ # alias write_sge "source db2sge_script" -#@ #} else { -#@ # alias write_sge "include db2sge_script" -#@ #} -#@ -#@ if { $dc_shell_mode == "tcl" } { -#@ # Configure Execute script dialog to display .tcl files -#@ set view_execute_script_suffix "$view_execute_script_suffix .tcl" -#@ } -#@ -#@ # -#@ # Shirley Lu 5/15/2007 -#@ # -#@ # Invoke NCX validation/correlation/fomatter from lc_shell: -#@ # -#@ # UNIX shell: -#@ # setenv SYNOPSYS_NCX_ROOT /mydisk/ncx_2007.06 -#@ # -#@ -#@ if {[info exists env(SYNOPSYS_NCX_ROOT)]} { -#@ -#@ set ncx_path $env(SYNOPSYS_NCX_ROOT)/ncx/${sh_arch}/bin -#@ -#@ # -#@ # check_ccs_lib -#@ # use libchecker under $ncx_path defined above -#@ # Disable this command since 2010.12-SP3 (should be done in 2010.12 release) -#@ #proc check_ccs_lib {args} { -#@ # global ncx_path -#@ # set cmdStr [linsert $args 0 ${ncx_path}/libchecker -lc_shell] -#@ # set cmd [open "| $cmdStr 2>@ stdout"] -#@ # catch { -#@ # while {[gets $cmd info] >= 0} { -#@ # echo $info -#@ # } -#@ # } -#@ # if {[catch {close $cmd} msg]} { -#@ # } -#@ #} -#@ -#@ # -#@ # format_lib -#@ # use ncx under $ncx_path defined above -#@ # Disable format_lib command in 2014.09 release -- xwwang, 7/25/2014 -#@ #proc format_lib {args} { -#@ # global ncx_path -#@ # echo "Warning: format_lib command is scheduled to become obsolete in a future production release." -#@ # set cmdStr [linsert $args 0 ${ncx_path}/ncx -lc_shell] -#@ # set cmd [open "| $cmdStr 2>@ stdout"] -#@ # catch { -#@ # while {[gets $cmd info] >= 0} { -#@ # echo $info -#@ # } -#@ # } -#@ # if {[catch {close $cmd} msg]} { -#@ # } -#@ #} -#@ -#@ } -#@ -#@ proc get_nglc_search_path { } { -#@ set exec_path "invalid" -#@ if {[info exists ::env(SYNOPSYS_LC_ROOT)] && [file exists $::env(SYNOPSYS_LC_ROOT)/$::sh_arch/lc/bin/lc_shell_exec]} { -#@ set exec_path $::env(SYNOPSYS_LC_ROOT)/$::sh_arch/lc/bin/lc_shell_exec -#@ } -#@ -#@ return $exec_path -#@ } -#@ -#@ proc get_libra_synopsys_root { } { -#@ return [file dirname [file dirname [file dirname [file dirname $::nglc_search_path] ] ] ] -#@ } -#@ -#@ proc valias {v_orig v_alias} { -#@ uplevel 1 "upvar 0 $v_orig $v_alias" -#@ } -#@ -#@ set nglc_result_path "/tmp" -#@ set nglc_replay_tcl_file "nglc_shell_command.tcl" -#@ set nglc_search_path [get_nglc_search_path] -#@ set lc_run_from_legacy_library_compiler "true" -#@ set nglc_is_none_tech_file "false" -#@ set nglc_keep_nglc_temp_files "false" -#@ set nglc_intermediate_db_files "" -#@ set nglc_log_path "" -#@ set lc_enable_legacy_library_compiler "false" -#@ -#@ valias lc_enable_legacy_library_compiler lc_enable_common_shell_lc -#@ -#@ proc nglc_read_lib { args } { -#@ common_shell_read_lib $args -#@ } -#@ -#@ -#@ proc common_shell_read_lib {args } { -#@ set_folder_var -#@ set tcl_file "$::nglc_result_path/$::nglc_log_path/$::nglc_replay_tcl_file" -#@ set chan [open $tcl_file a] -#@ export_tcl_var $chan -#@ gen_nglc_read_lib_procedure $chan $args -#@ close $chan -#@ run_libra_with_echo $tcl_file -#@ common_shell_read_dbs -#@ set_none_tech_file -#@ } -#@ -#@ # create the unique folder under tmp -#@ proc set_folder_var { } { -#@ set fileName [pid] -#@ set ::nglc_log_path [append fileName "_" [clock microseconds]] -#@ file delete -force $::nglc_result_path/$::nglc_log_path -#@ file mkdir $::nglc_result_path/$::nglc_log_path -#@ } -#@ -#@ # export all the vars -#@ proc export_tcl_var { fileName } { -#@ foreach var [info vars ::* ] { -#@ if [array exists $var] { -#@ continue; -#@ } -#@ puts $fileName "set $var \[list [set $var]\]" -#@ } -#@ } -#@ -#@ # excuted by libra shell to read the dbs generated by common_shell -#@ proc common_shell_read_dbs { } { -#@ set dbNames "" -#@ foreach var [glob -nocomplain -directory $::nglc_result_path/$::nglc_log_path *.db] { -#@ append dbNames " " $var -#@ } -#@ set ::nglc_intermediate_db_files $dbNames -#@ } -#@ -#@ # display the log file genrated by common_shell in Libra and then remove the unique folder -#@ proc common_shell_clean_up { } { -#@ if { $::nglc_keep_nglc_temp_files == "false" } { -#@ file delete -force $::nglc_result_path/$::nglc_log_path -#@ } -#@ } -#@ -#@ proc gen_nglc_read_lib_procedure { fileName args} { -#@ puts $fileName "##@@@## gen_common_shell_read_lib" -#@ puts $fileName "eval [lindex [lindex $args 0] 0]" -#@ puts $fileName "##@@@##" -#@ puts $fileName "set lc_write_view_db_file false" -#@ puts $fileName "set librs \[get_libs\]" -#@ puts $fileName "for {set i 0} {\$i < \[ sizeof \$librs \]} {incr i 1} {" -#@ puts $fileName " set lib \[index_collection \$librs \$i]" -#@ puts $fileName " redirect -var a \"query_object \$lib\" " -#@ puts $fileName " if \[regexp {{(\")?(gtech)(\")?}} \$a\] { " -#@ puts $fileName " } elseif \[regexp {{(\")?(standard.sldb)(\")?}} \$a] { " -#@ puts $fileName " } else {" -#@ puts $fileName " regexp {{(\")?(\[^\"\]*)(\")?}} \$a b c d e " -#@ puts $fileName " write_lib \$d -o \$nglc_result_path/\$nglc_log_path/\$d.db" -#@ puts $fileName " }" -#@ puts $fileName "}" -#@ puts $fileName "exit" -#@ } -#@ -#@ proc set_none_tech_file { } { -#@ if { [file exists $::nglc_result_path/$::nglc_log_path/is_non_tech_file] } { -#@ set ::nglc_is_none_tech_file true; -#@ } else { -#@ set ::nglc_is_none_tech_file false; -#@ } -#@ } -#@ -#@ proc run_libra_with_echo {tcl_file} { -#@ set chan [open "|$::nglc_search_path -r [get_libra_synopsys_root] -f $tcl_file" r] -#@ # things to do: In debug mode, we want copy the whole output (beginning to end) -#@ # to a file -#@ if {$::nglc_keep_nglc_temp_files} { -#@ set log [open $::nglc_result_path/$::nglc_log_path/libra.log w] -#@ } -#@ set echo 0 -#@ set firstLine true -#@ while {[gets $chan line] >= 0} { -#@ if {$::nglc_keep_nglc_temp_files} { puts $log $line } -#@ if {[string equal -length 7 $line "##@@@##"]} { -#@ set echo [expr ! $echo] -#@ continue; -#@ } -#@ if {$echo} { -#@ if { $firstLine } { -#@ set firstLine false -#@ continue; -#@ } else { -#@ puts $line -#@ } -#@ } -#@ } -#@ close $chan -#@ if {$::nglc_keep_nglc_temp_files} { -#@ close $log -#@ } -#@ } -#@ -#@ # -- End source /tools/synopsys/synthesis/j201409sp3/admin/setup/.synopsys_dc.setup - -source -echo -verbose /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/rf2_32x128_wm1/../convert_lib_to_db.tcl -#@ # -- Starting source /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/rf2_32x128_wm1/../convert_lib_to_db.tcl - -#@ set SOURCE_FILES [glob *.lib] -#@ foreach FILE ${SOURCE_FILES} { -#@ read_lib $FILE -#@ redirect -variable CURR_LIB {get_lib} -#@ -#@ set CURR_LIB [string range $CURR_LIB 2 end-3] -#@ set CURR_LIB [lindex $CURR_LIB 0] -#@ set FILENAME [string range $FILE 0 end-4] -#@ write_lib $CURR_LIB -output ${FILENAME}.db -#@ remove_lib $CURR_LIB -#@ } -#@ -#@ exit diff --git a/hw/modelsim/vortex_tb.v b/hw/modelsim/vortex_tb.v index 64dfef13..4db1dc84 100644 --- a/hw/modelsim/vortex_tb.v +++ b/hw/modelsim/vortex_tb.v @@ -1,4 +1,3 @@ - `include "../VX_define.vh" //`define NUM_BANKS 8 @@ -118,7 +117,7 @@ reg[31:0] io_data; .i_m_readdata_i (i_m_readdata_i), .i_m_ready_i (i_m_ready_i), .out_ebreak (out_ebreak) - ); + ); always @(negedge clk) begin ibus_driver(clk, o_m_read_addr_i, o_m_evict_addr_i, o_m_valid_i, o_m_writedata_i, o_m_read_or_write_i, `ICACHE_BANKS, `ICACHE_NUM_WORDS_PER_BLOCK, i_m_readdata_i, i_m_ready_i); @@ -138,14 +137,13 @@ reg[31:0] io_data; cycle_num = cycle_num + 1; end - always @(clk, posedge reset) begin + always @(clk) begin if (reset) begin reset = 0; clk = 0; end #5 clk <= ~clk; - end endmodule diff --git a/hw/opae/sources.txt b/hw/opae/sources.txt index 69b8f037..47ef4ad5 100644 --- a/hw/opae/sources.txt +++ b/hw/opae/sources.txt @@ -92,7 +92,7 @@ vortex_afu.json ../rtl/interfaces/VX_gpu_dcache_dram_req_inter.v ../rtl/interfaces/VX_csr_req_inter.v ../rtl/interfaces/VX_icache_request_inter.v -../rtl/interfaces/VX_gpu_dcache_res_inter.v +../rtl/interfaces/VX_gpu_dcache_rsp_inter.v ../rtl/interfaces/VX_frE_to_bckE_req_inter.v ../rtl/interfaces/VX_dram_req_rsp_inter.v ../rtl/interfaces/VX_dcache_request_inter.v @@ -113,7 +113,7 @@ vortex_afu.json ../rtl/interfaces/VX_jal_response_inter.v ../rtl/interfaces/VX_warp_ctl_inter.v ../rtl/interfaces/VX_gpu_dcache_snp_req_inter.v -../rtl/interfaces/VX_gpu_dcache_dram_res_inter.v +../rtl/interfaces/VX_gpu_dcache_dram_rsp_inter.v ../rtl/interfaces/VX_inst_mem_wb_inter.v ccip_interface_reg.sv diff --git a/hw/opae/vortex_afu.sv b/hw/opae/vortex_afu.sv index c997fc57..0bc5c813 100644 --- a/hw/opae/vortex_afu.sv +++ b/hw/opae/vortex_afu.sv @@ -70,16 +70,16 @@ logic vx_dram_req_read; logic vx_dram_req_write; logic [31:0] vx_dram_req_addr; logic [31:0] vx_dram_req_data[15:0]; -logic vx_dram_req_delay; +logic vx_dram_req_full; -logic vx_dram_fill_accept; -logic vx_dram_fill_rsp; -logic [31:0] vx_dram_fill_rsp_addr; -logic [31:0] vx_dram_fill_rsp_data[15:0]; +logic vx_dram_rsp_ready; +logic vx_dram_rsp_valid; +logic [31:0] vx_dram_rsp_addr; +logic [31:0] vx_dram_rsp_data[15:0]; logic vx_snp_req; logic [31:0] vx_snp_req_addr; -logic vx_snp_req_delay; +logic vx_snp_req_full; logic vx_ebreak; @@ -316,7 +316,7 @@ begin STATE_RUN, STATE_CLFLUSH: begin if (vx_dram_req_read - && !vx_dram_req_delay) + && !vx_dram_req_full) begin avs_address <= (vx_dram_req_addr >> 6); avs_read <= 1; @@ -324,7 +324,7 @@ begin end if (vx_dram_req_write - && !vx_dram_req_delay) + && !vx_dram_req_full) begin avs_writedata <= {>>{vx_dram_req_data}}; avs_address <= (vx_dram_req_addr >> 6); @@ -348,16 +348,16 @@ logic vortex_enabled; always_comb begin vortex_enabled = (STATE_RUN == state) || (STATE_CLFLUSH == state); - vx_dram_req_delay = !vortex_enabled || avs_waitrequest || avs_raq_full || avs_rdq_full; + vx_dram_req_full = !vortex_enabled || avs_waitrequest || avs_raq_full || avs_rdq_full; end // Vortex DRAM fill response always_comb begin - vx_dram_fill_rsp = vortex_enabled && !avs_rdq_empty && vx_dram_fill_accept; - vx_dram_fill_rsp_addr = (avs_raq_dout << 6); - {>>{vx_dram_fill_rsp_data}} = avs_rdq_dout; + vx_dram_rsp_valid = vortex_enabled && !avs_rdq_empty && vx_dram_rsp_ready; + vx_dram_rsp_addr = (avs_raq_dout << 6); + {>>{vx_dram_rsp_data}} = avs_rdq_dout; end // AVS address read request queue ///////////////////////////////////////////// @@ -366,7 +366,7 @@ logic cci_write_req; always_comb begin - avs_raq_pop = vx_dram_fill_rsp || cci_write_req; + avs_raq_pop = vx_dram_rsp_valid || cci_write_req; avs_raq_din = avs_address; avs_raq_push = avs_read; end @@ -531,7 +531,7 @@ begin if ((STATE_CLFLUSH == state) && vx_snoop_ctr < csr_data_size - && !vx_snp_req_delay) + && !vx_snp_req_full) begin vx_snp_req_addr <= (csr_mem_addr + vx_snoop_ctr) << 6; vx_snp_req <= 1; @@ -548,29 +548,29 @@ end // Vortex binding ///////////////////////////////////////////////////////////// Vortex_Socket #() vx_socket ( - .clk (clk), - .reset (SoftReset || vx_reset), + .clk (clk), + .reset (SoftReset || vx_reset), // DRAM Req - .out_dram_req_write (vx_dram_req_write), - .out_dram_req_read (vx_dram_req_read), - .out_dram_req_addr (vx_dram_req_addr), - .out_dram_req_data (vx_dram_req_data), - .out_dram_req_delay (vx_dram_req_delay), + .dram_req_write (vx_dram_req_write), + .dram_req_read (vx_dram_req_read), + .dram_req_addr (vx_dram_req_addr), + .dram_req_data (vx_dram_req_data), + .dram_req_full (vx_dram_req_full), // DRAM Rsp - .out_dram_fill_accept (vx_dram_fill_accept), - .out_dram_fill_rsp (vx_dram_fill_rsp), - .out_dram_fill_rsp_addr (vx_dram_fill_rsp_addr), - .out_dram_fill_rsp_data (vx_dram_fill_rsp_data), + .out_dram_rsp_ready (vx_dram_rsp_ready), + .dram_rsp_valid (vx_dram_rsp_valid), + .out_dram_rsp_addr (vx_dram_rsp_addr), + .out_dram_rsp_data (vx_dram_rsp_data), // Cache Snooping Req - .llc_snp_req (vx_snp_req), - .llc_snp_req_addr (vx_snp_req_addr), - .llc_snp_req_delay (vx_snp_req_delay), + .llc_snp_req_valid (vx_snp_req), + .llc_snp_req_addr (vx_snp_req_addr), + .llc_snp_req_full (vx_snp_req_full), // program exit signal - .out_ebreak (vx_ebreak) + .out_ebreak (vx_ebreak) ); endmodule diff --git a/hw/opae/wave.do b/hw/opae/wave.do deleted file mode 100644 index aab97878..00000000 --- a/hw/opae/wave.do +++ /dev/null @@ -1,69 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -label clk /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/clk -add wave -noupdate -label reset /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/SoftReset -add wave -noupdate -label state /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/state -add wave -noupdate -label cci_write_pending /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/cci_write_pending -add wave -noupdate -label cci_write_ctr -radix decimal -radixshowbase 0 /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/cci_write_ctr -add wave -noupdate -label csr_data_size -radix decimal -radixshowbase 0 /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/csr_data_size -add wave -noupdate -label avs_read_ctr -radix decimal -radixshowbase 0 /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_read_ctr -add wave -noupdate -label avs_waitrequest /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_waitrequest -add wave -noupdate -label avs_address -radix hexadecimal -radixshowbase 0 /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_address -add wave -noupdate -label avs_readdata -radix hexadecimal /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_readdata -add wave -noupdate -label avs_writedata -radix hexadecimal /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_writedata -add wave -noupdate -label avs_write /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_write -add wave -noupdate -label avs_read /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_read -add wave -noupdate -label avs_readdatavalid /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_readdatavalid -add wave -noupdate -label sRx.c0.rspValid /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/cp2af_sRxPort.c0.rspValid -add wave -noupdate -label sRx.c1.rspValid /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/cp2af_sRxPort.c1.rspValid -add wave -noupdate -label sTx.c0.valid /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/af2cp_sTxPort.c0.valid -add wave -noupdate -label sTx.c1.valid /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/af2cp_sTxPort.c1.valid -add wave -noupdate -label cci_write_req /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/cci_write_req -add wave -noupdate -label avs_raq_push /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_raq_push -add wave -noupdate -label avs_rdq_push /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_rdq_push -add wave -noupdate -label avs_raq_pop /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_raq_pop -add wave -noupdate -label avs_rdq_pop /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_rdq_pop -add wave -noupdate -label avs_raq_full /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_raq_full -add wave -noupdate -label avs_rdq_full /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_rdq_full -add wave -noupdate -label avs_raq_empty /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_raq_empty -add wave -noupdate -label avs_rdq_empty /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_rdq_empty -add wave -noupdate -label vortex_enabled /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vortex_enabled -add wave -noupdate -label vx_reset /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_soc/reset -add wave -noupdate -label vx_dram_req_read /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_dram_req_read -add wave -noupdate -label vx_dram_req_write /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_dram_req_write -add wave -noupdate -label vx_dram_req_delay /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_dram_req_delay -add wave -noupdate -label vx_dram_req_addr -radix hexadecimal /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_dram_req_addr -add wave -noupdate -label vx_draw_req_data -radix hexadecimal /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_dram_req_data -add wave -noupdate -label out_dram_fill_rsp /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_soc/out_dram_fill_rsp -add wave -noupdate -label out_dram_fill_accept /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_soc/out_dram_fill_accept -add wave -noupdate -label vx_draw_fill_rsp_data -radix hexadecimal /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_dram_fill_rsp_data -add wave -noupdate -label vx_dram_fill_rsp_addr -radix hexadecimal /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_dram_fill_rsp_addr -add wave -noupdate -label llc_snp_req /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_soc/llc_snp_req -add wave -noupdate -label llc_snp_req_delay /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_soc/llc_snp_req_delay -add wave -noupdate -label out_break /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_soc/out_ebreak -add wave -noupdate -label warp_pc -radix hexadecimal -radixshowbase 0 {/ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_soc/genblk1/Vortex_Cluster/genblk1[0]/vortex_core/vx_front_end/vx_fetch/warp_pc} -add wave -noupdate -label scheduled_warp {/ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_soc/genblk1/Vortex_Cluster/genblk1[0]/vortex_core/vx_front_end/vx_fetch/scheduled_warp} -add wave -noupdate -label thread_mask {/ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_soc/genblk1/Vortex_Cluster/genblk1[0]/vortex_core/vx_front_end/vx_fetch/thread_mask} -add wave -noupdate -label warp_num {/ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_soc/genblk1/Vortex_Cluster/genblk1[0]/vortex_core/vx_front_end/vx_fetch/warp_num} -add wave -noupdate -label warp_active {/ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_soc/genblk1/Vortex_Cluster/genblk1[0]/vortex_core/vx_front_end/vx_fetch/warp_scheduler/warp_active} -add wave -noupdate -label warp_stalled {/ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_soc/genblk1/Vortex_Cluster/genblk1[0]/vortex_core/vx_front_end/vx_fetch/warp_scheduler/warp_stalled} -add wave -noupdate -label warp_lock {/ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_soc/genblk1/Vortex_Cluster/genblk1[0]/vortex_core/vx_front_end/vx_fetch/warp_scheduler/warp_lock} -add wave -noupdate -label use_active {/ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_soc/genblk1/Vortex_Cluster/genblk1[0]/vortex_core/vx_front_end/vx_fetch/warp_scheduler/use_active} -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 2} {360293 ps} 0} -quietly wave cursor active 1 -configure wave -namecolwidth 195 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -configure wave -timelineunits ps -update -WaveRestoreZoom {346453 ps} {711141 ps} diff --git a/hw/rtl/VX_alu.v b/hw/rtl/VX_alu.v index 9e9c94b8..3bb23f4c 100644 --- a/hw/rtl/VX_alu.v +++ b/hw/rtl/VX_alu.v @@ -14,196 +14,198 @@ module VX_alu( output reg out_alu_stall ); - localparam div_pipeline_len = 20; - localparam mul_pipeline_len = 8; + localparam div_pipeline_len = 20; + localparam mul_pipeline_len = 8; - wire[31:0] unsigned_div_result; - wire[31:0] unsigned_rem_result; - wire[31:0] signed_div_result; - wire[31:0] signed_rem_result; + wire[31:0] unsigned_div_result; + wire[31:0] unsigned_rem_result; + wire[31:0] signed_div_result; + wire[31:0] signed_rem_result; - wire[63:0] mul_data_a, mul_data_b; - wire[63:0] mul_result; + wire[63:0] mul_data_a, mul_data_b; + wire[63:0] mul_result; - wire[31:0] ALU_in1; - wire[31:0] ALU_in2; + wire[31:0] ALU_in1; + wire[31:0] ALU_in2; - VX_divide #( - .WIDTHN(32), - .WIDTHD(32), - .SPEED("HIGHEST"), - .PIPELINE(div_pipeline_len) - ) unsigned_div ( - .clock(clk), - .aclr(1'b0), - .clken(1'b1), // TODO this could be disabled on inactive instructions - .numer(ALU_in1), - .denom(ALU_in2), - .quotient(unsigned_div_result), - .remainder(unsigned_rem_result) - ); + VX_divide #( + .WIDTHN(32), + .WIDTHD(32), + .SPEED("HIGHEST"), + .PIPELINE(div_pipeline_len) + ) unsigned_div ( + .clock(clk), + .aclr(1'b0), + .clken(1'b1), // TODO this could be disabled on inactive instructions + .numer(ALU_in1), + .denom(ALU_in2), + .quotient(unsigned_div_result), + .remainder(unsigned_rem_result) + ); - VX_divide #( - .WIDTHN(32), - .WIDTHD(32), - .NREP("SIGNED"), - .DREP("SIGNED"), - .SPEED("HIGHEST"), - .PIPELINE(div_pipeline_len) - ) signed_div ( - .clock(clk), - .aclr(1'b0), - .clken(1'b1), // TODO this could be disabled on inactive instructions - .numer(ALU_in1), - .denom(ALU_in2), - .quotient(signed_div_result), - .remainder(signed_rem_result) - ); + VX_divide #( + .WIDTHN(32), + .WIDTHD(32), + .NREP("SIGNED"), + .DREP("SIGNED"), + .SPEED("HIGHEST"), + .PIPELINE(div_pipeline_len) + ) signed_div ( + .clock(clk), + .aclr(1'b0), + .clken(1'b1), // TODO this could be disabled on inactive instructions + .numer(ALU_in1), + .denom(ALU_in2), + .quotient(signed_div_result), + .remainder(signed_rem_result) + ); - VX_mult #( - .WIDTHA(64), - .WIDTHB(64), - .WIDTHP(64), - .SPEED("HIGHEST"), - .FORCE_LE("YES"), - .PIPELINE(mul_pipeline_len) - ) multiplier ( - .clock(clk), - .aclr(1'b0), - .clken(1'b1), // TODO this could be disabled on inactive instructions - .dataa(mul_data_a), - .datab(mul_data_b), - .result(mul_result) - ); + VX_mult #( + .WIDTHA(64), + .WIDTHB(64), + .WIDTHP(64), + .SPEED("HIGHEST"), + .FORCE_LE("YES"), + .PIPELINE(mul_pipeline_len) + ) multiplier ( + .clock(clk), + .aclr(1'b0), + .clken(1'b1), // TODO this could be disabled on inactive instructions + .dataa(mul_data_a), + .datab(mul_data_b), + .result(mul_result) + ); - // MUL, MULH (signed*signed), MULHSU (signed*unsigned), MULHU (unsigned*unsigned) - wire[63:0] alu_in1_signed = {{32{ALU_in1[31]}}, ALU_in1}; - wire[63:0] alu_in2_signed = {{32{ALU_in2[31]}}, ALU_in2}; - assign mul_data_a = (in_alu_op == `MULHU) ? {32'b0, ALU_in1} : alu_in1_signed; - assign mul_data_b = (in_alu_op == `MULHU || in_alu_op == `MULHSU) ? {32'b0, ALU_in2} : alu_in2_signed; + // MUL, MULH (signed*signed), MULHSU (signed*unsigned), MULHU (unsigned*unsigned) + wire[63:0] alu_in1_signed = {{32{ALU_in1[31]}}, ALU_in1}; + wire[63:0] alu_in2_signed = {{32{ALU_in2[31]}}, ALU_in2}; + assign mul_data_a = (in_alu_op == `MULHU) ? {32'b0, ALU_in1} : alu_in1_signed; + assign mul_data_b = (in_alu_op == `MULHU || in_alu_op == `MULHSU) ? {32'b0, ALU_in2} : alu_in2_signed; - reg [15:0] curr_inst_delay; - reg [15:0] inst_delay; - reg inst_was_stalling; + reg [15:0] curr_inst_delay; + reg [15:0] inst_delay; + reg inst_was_stalling; - wire inst_delay_stall = inst_was_stalling ? inst_delay != 0 : curr_inst_delay != 0; - assign out_alu_stall = inst_delay_stall; + wire inst_delay_stall = inst_was_stalling ? inst_delay != 0 : curr_inst_delay != 0; + assign out_alu_stall = inst_delay_stall; - always @(*) begin - case(in_alu_op) - `DIV, - `DIVU, - `REM, - `REMU: curr_inst_delay = div_pipeline_len; - `MUL, - `MULH, - `MULHSU, - `MULHU: curr_inst_delay = mul_pipeline_len; - default: curr_inst_delay = 0; - endcase // in_alu_op - end + always @(*) begin + case(in_alu_op) + `DIV, + `DIVU, + `REM, + `REMU: curr_inst_delay = div_pipeline_len; + `MUL, + `MULH, + `MULHSU, + `MULHU: curr_inst_delay = mul_pipeline_len; + default: curr_inst_delay = 0; + endcase // in_alu_op + end - always @(posedge clk or posedge reset) begin - if (reset) begin - inst_delay <= 0; - inst_was_stalling <= 0; - end - else if (inst_delay_stall) begin - if (inst_was_stalling) begin - if (inst_delay > 0) - inst_delay <= inst_delay - 1; - end - else begin - inst_was_stalling <= 1; - inst_delay <= curr_inst_delay - 1; - end - end - else begin - inst_was_stalling <= 0; - end - end - - `ifdef SYN_FUNC - wire which_in2; - wire[31:0] upper_immed; - - assign which_in2 = in_rs2_src == `RS2_IMMED; - - assign ALU_in1 = in_1; - assign ALU_in2 = which_in2 ? in_itype_immed : in_2; - - assign upper_immed = {in_upper_immed, {12{1'b0}}}; - - always @(*) begin - case(in_alu_op) - `ADD: out_alu_result = $signed(ALU_in1) + $signed(ALU_in2); - `SUB: out_alu_result = $signed(ALU_in1) - $signed(ALU_in2); - `SLLA: out_alu_result = ALU_in1 << ALU_in2[4:0]; - `SLT: out_alu_result = ($signed(ALU_in1) < $signed(ALU_in2)) ? 32'h1 : 32'h0; - `SLTU: out_alu_result = ALU_in1 < ALU_in2 ? 32'h1 : 32'h0; - `XOR: out_alu_result = ALU_in1 ^ ALU_in2; - `SRL: out_alu_result = ALU_in1 >> ALU_in2[4:0]; - `SRA: out_alu_result = $signed(ALU_in1) >>> ALU_in2[4:0]; - `OR: out_alu_result = ALU_in1 | ALU_in2; - `AND: out_alu_result = ALU_in2 & ALU_in1; - `SUBU: out_alu_result = (ALU_in1 >= ALU_in2) ? 32'h0 : 32'hffffffff; - `LUI_ALU: out_alu_result = upper_immed; - `AUIPC_ALU: out_alu_result = $signed(in_curr_PC) + $signed(upper_immed); - // TODO profitable to roll these exceptional cases into inst_delay to avoid pipeline when possible? - `MUL: out_alu_result = mul_result[31:0]; - `MULH: out_alu_result = mul_result[63:32]; - `MULHSU: out_alu_result = mul_result[63:32]; - `MULHU: out_alu_result = mul_result[63:32]; - `DIV: out_alu_result = (ALU_in2 == 0) ? 32'hffffffff : signed_div_result; - `DIVU: out_alu_result = (ALU_in2 == 0) ? 32'hffffffff : unsigned_div_result; - `REM: out_alu_result = (ALU_in2 == 0) ? ALU_in1 : signed_rem_result; - `REMU: out_alu_result = (ALU_in2 == 0) ? ALU_in1 : unsigned_rem_result; - default: out_alu_result = 32'h0; - endcase // in_alu_op + always @(posedge clk) begin + if (reset) begin + inst_delay <= 0; + inst_was_stalling <= 0; end - - `else - wire which_in2; - wire[31:0] upper_immed; - - - assign which_in2 = in_rs2_src == `RS2_IMMED; - - assign ALU_in1 = in_1; - - assign ALU_in2 = which_in2 ? in_itype_immed : in_2; - - - assign upper_immed = {in_upper_immed, {12{1'b0}}}; - - always @(*) begin - case(in_alu_op) - `ADD: out_alu_result = $signed(ALU_in1) + $signed(ALU_in2); - `SUB: out_alu_result = $signed(ALU_in1) - $signed(ALU_in2); - `SLLA: out_alu_result = ALU_in1 << ALU_in2[4:0]; - `SLT: out_alu_result = ($signed(ALU_in1) < $signed(ALU_in2)) ? 32'h1 : 32'h0; - `SLTU: out_alu_result = ALU_in1 < ALU_in2 ? 32'h1 : 32'h0; - `XOR: out_alu_result = ALU_in1 ^ ALU_in2; - `SRL: out_alu_result = ALU_in1 >> ALU_in2[4:0]; - `SRA: out_alu_result = $signed(ALU_in1) >>> ALU_in2[4:0]; - `OR: out_alu_result = ALU_in1 | ALU_in2; - `AND: out_alu_result = ALU_in2 & ALU_in1; - `SUBU: out_alu_result = (ALU_in1 >= ALU_in2) ? 32'h0 : 32'hffffffff; - `LUI_ALU: out_alu_result = upper_immed; - `AUIPC_ALU: out_alu_result = $signed(in_curr_PC) + $signed(upper_immed); - // TODO profitable to roll these exceptional cases into inst_delay to avoid pipeline when possible? - `MUL: out_alu_result = mul_result[31:0]; - `MULH: out_alu_result = mul_result[63:32]; - `MULHSU: out_alu_result = mul_result[63:32]; - `MULHU: out_alu_result = mul_result[63:32]; - `DIV: out_alu_result = (ALU_in2 == 0) ? 32'hffffffff : signed_div_result; - `DIVU: out_alu_result = (ALU_in2 == 0) ? 32'hffffffff : unsigned_div_result; - `REM: out_alu_result = (ALU_in2 == 0) ? ALU_in1 : signed_rem_result; - `REMU: out_alu_result = (ALU_in2 == 0) ? ALU_in1 : unsigned_rem_result; - default: out_alu_result = 32'h0; - endcase // in_alu_op + else if (inst_delay_stall) begin + if (inst_was_stalling) begin + if (inst_delay > 0) + inst_delay <= inst_delay - 1; + end + else begin + inst_was_stalling <= 1; + inst_delay <= curr_inst_delay - 1; + end end - `endif + else begin + inst_was_stalling <= 0; + end + end + + `ifdef SYN_FUNC + wire which_in2; + wire[31:0] upper_immed; + + assign which_in2 = in_rs2_src == `RS2_IMMED; + + assign ALU_in1 = in_1; + assign ALU_in2 = which_in2 ? in_itype_immed : in_2; + + assign upper_immed = {in_upper_immed, {12{1'b0}}}; + + always @(*) begin + case(in_alu_op) + `ADD: out_alu_result = $signed(ALU_in1) + $signed(ALU_in2); + `SUB: out_alu_result = $signed(ALU_in1) - $signed(ALU_in2); + `SLLA: out_alu_result = ALU_in1 << ALU_in2[4:0]; + `SLT: out_alu_result = ($signed(ALU_in1) < $signed(ALU_in2)) ? 32'h1 : 32'h0; + `SLTU: out_alu_result = ALU_in1 < ALU_in2 ? 32'h1 : 32'h0; + `XOR: out_alu_result = ALU_in1 ^ ALU_in2; + `SRL: out_alu_result = ALU_in1 >> ALU_in2[4:0]; + `SRA: out_alu_result = $signed(ALU_in1) >>> ALU_in2[4:0]; + `OR: out_alu_result = ALU_in1 | ALU_in2; + `AND: out_alu_result = ALU_in2 & ALU_in1; + `SUBU: out_alu_result = (ALU_in1 >= ALU_in2) ? 32'h0 : 32'hffffffff; + `LUI_ALU: out_alu_result = upper_immed; + `AUIPC_ALU: out_alu_result = $signed(in_curr_PC) + $signed(upper_immed); + // TODO profitable to roll these exceptional cases into inst_delay to avoid pipeline when possible? + `MUL: out_alu_result = mul_result[31:0]; + `MULH: out_alu_result = mul_result[63:32]; + `MULHSU: out_alu_result = mul_result[63:32]; + `MULHU: out_alu_result = mul_result[63:32]; + `DIV: out_alu_result = (ALU_in2 == 0) ? 32'hffffffff : signed_div_result; + `DIVU: out_alu_result = (ALU_in2 == 0) ? 32'hffffffff : unsigned_div_result; + `REM: out_alu_result = (ALU_in2 == 0) ? ALU_in1 : signed_rem_result; + `REMU: out_alu_result = (ALU_in2 == 0) ? ALU_in1 : unsigned_rem_result; + default: out_alu_result = 32'h0; + endcase // in_alu_op + end + +`else + + wire which_in2; + wire[31:0] upper_immed; + + + assign which_in2 = in_rs2_src == `RS2_IMMED; + + assign ALU_in1 = in_1; + + assign ALU_in2 = which_in2 ? in_itype_immed : in_2; + + + assign upper_immed = {in_upper_immed, {12{1'b0}}}; + + always @(*) begin + case(in_alu_op) + `ADD: out_alu_result = $signed(ALU_in1) + $signed(ALU_in2); + `SUB: out_alu_result = $signed(ALU_in1) - $signed(ALU_in2); + `SLLA: out_alu_result = ALU_in1 << ALU_in2[4:0]; + `SLT: out_alu_result = ($signed(ALU_in1) < $signed(ALU_in2)) ? 32'h1 : 32'h0; + `SLTU: out_alu_result = ALU_in1 < ALU_in2 ? 32'h1 : 32'h0; + `XOR: out_alu_result = ALU_in1 ^ ALU_in2; + `SRL: out_alu_result = ALU_in1 >> ALU_in2[4:0]; + `SRA: out_alu_result = $signed(ALU_in1) >>> ALU_in2[4:0]; + `OR: out_alu_result = ALU_in1 | ALU_in2; + `AND: out_alu_result = ALU_in2 & ALU_in1; + `SUBU: out_alu_result = (ALU_in1 >= ALU_in2) ? 32'h0 : 32'hffffffff; + `LUI_ALU: out_alu_result = upper_immed; + `AUIPC_ALU: out_alu_result = $signed(in_curr_PC) + $signed(upper_immed); + // TODO profitable to roll these exceptional cases into inst_delay to avoid pipeline when possible? + `MUL: out_alu_result = mul_result[31:0]; + `MULH: out_alu_result = mul_result[63:32]; + `MULHSU: out_alu_result = mul_result[63:32]; + `MULHU: out_alu_result = mul_result[63:32]; + `DIV: out_alu_result = (ALU_in2 == 0) ? 32'hffffffff : signed_div_result; + `DIVU: out_alu_result = (ALU_in2 == 0) ? 32'hffffffff : unsigned_div_result; + `REM: out_alu_result = (ALU_in2 == 0) ? ALU_in1 : signed_rem_result; + `REMU: out_alu_result = (ALU_in2 == 0) ? ALU_in1 : unsigned_rem_result; + default: out_alu_result = 32'h0; + endcase // in_alu_op + end + +`endif endmodule : VX_alu \ No newline at end of file diff --git a/hw/rtl/VX_back_end.v b/hw/rtl/VX_back_end.v index a29b378c..75ab0dee 100644 --- a/hw/rtl/VX_back_end.v +++ b/hw/rtl/VX_back_end.v @@ -9,71 +9,63 @@ module VX_back_end input wire reset, input wire schedule_delay, - VX_gpu_dcache_res_inter VX_dcache_rsp, - VX_gpu_dcache_req_inter VX_dcache_req, + VX_gpu_dcache_rsp_inter vx_dcache_rsp, + VX_gpu_dcache_req_inter vx_dcache_req, output wire out_mem_delay, output wire out_exec_delay, output wire gpr_stage_delay, - VX_jal_response_inter VX_jal_rsp, - VX_branch_response_inter VX_branch_rsp, + VX_jal_response_inter vx_jal_rsp, + VX_branch_response_inter vx_branch_rsp, - VX_frE_to_bckE_req_inter VX_bckE_req, - VX_wb_inter VX_writeback_inter, + VX_frE_to_bckE_req_inter vx_bckE_req, + VX_wb_inter vx_writeback_inter, - VX_warp_ctl_inter VX_warp_ctl + VX_warp_ctl_inter vx_warp_ctl ); -VX_wb_inter VX_writeback_temp(); -assign VX_writeback_inter.wb = VX_writeback_temp.wb; -assign VX_writeback_inter.rd = VX_writeback_temp.rd; -assign VX_writeback_inter.write_data = VX_writeback_temp.write_data; -assign VX_writeback_inter.wb_valid = VX_writeback_temp.wb_valid; -assign VX_writeback_inter.wb_warp_num = VX_writeback_temp.wb_warp_num; -assign VX_writeback_inter.wb_pc = VX_writeback_temp.wb_pc; +VX_wb_inter vx_writeback_temp(); +assign vx_writeback_inter.wb = vx_writeback_temp.wb; +assign vx_writeback_inter.rd = vx_writeback_temp.rd; +assign vx_writeback_inter.write_data = vx_writeback_temp.write_data; +assign vx_writeback_inter.wb_valid = vx_writeback_temp.wb_valid; +assign vx_writeback_inter.wb_warp_num = vx_writeback_temp.wb_warp_num; +assign vx_writeback_inter.wb_pc = vx_writeback_temp.wb_pc; -// assign VX_writeback_inter(VX_writeback_temp); +// assign VX_writeback_inter(vx_writeback_temp); -VX_mw_wb_inter VX_mw_wb(); wire no_slot_mem; wire no_slot_exec; - -VX_mem_req_inter VX_exe_mem_req(); -VX_mem_req_inter VX_mem_req(); - - - // LSU input + output -VX_lsu_req_inter VX_lsu_req(); -VX_inst_mem_wb_inter VX_mem_wb(); +VX_lsu_req_inter vx_lsu_req(); +VX_inst_mem_wb_inter vx_mem_wb(); // Exec unit input + output -VX_exec_unit_req_inter VX_exec_unit_req(); -VX_inst_exec_wb_inter VX_inst_exec_wb(); - +VX_exec_unit_req_inter vx_exec_unit_req(); +VX_inst_exec_wb_inter vx_inst_exec_wb(); // GPU unit input -VX_gpu_inst_req_inter VX_gpu_inst_req(); +VX_gpu_inst_req_inter vx_gpu_inst_req(); // CSR unit inputs -VX_csr_req_inter VX_csr_req(); -VX_csr_wb_inter VX_csr_wb(); +VX_csr_req_inter vx_csr_req(); +VX_csr_wb_inter vx_csr_wb(); wire no_slot_csr; wire stall_gpr_csr; -VX_gpr_stage VX_gpr_stage( +VX_gpr_stage vx_gpr_stage( .clk (clk), .reset (reset), .schedule_delay (schedule_delay), - .VX_writeback_inter(VX_writeback_temp), - .VX_bckE_req (VX_bckE_req), + .vx_writeback_inter(vx_writeback_temp), + .vx_bckE_req (vx_bckE_req), // New - .VX_exec_unit_req(VX_exec_unit_req), - .VX_lsu_req (VX_lsu_req), - .VX_gpu_inst_req (VX_gpu_inst_req), - .VX_csr_req (VX_csr_req), + .vx_exec_unit_req(vx_exec_unit_req), + .vx_lsu_req (vx_lsu_req), + .vx_gpu_inst_req (vx_gpu_inst_req), + .vx_csr_req (vx_csr_req), .stall_gpr_csr (stall_gpr_csr), // End new .memory_delay (out_mem_delay), @@ -81,62 +73,61 @@ VX_gpr_stage VX_gpr_stage( .gpr_stage_delay (gpr_stage_delay) ); - -VX_lsu load_store_unit( +VX_lsu load_store_unit ( .clk (clk), .reset (reset), - .VX_lsu_req (VX_lsu_req), - .VX_mem_wb (VX_mem_wb), - .VX_dcache_rsp(VX_dcache_rsp), - .VX_dcache_req(VX_dcache_req), + .vx_lsu_req (vx_lsu_req), + .vx_mem_wb (vx_mem_wb), + .vx_dcache_rsp(vx_dcache_rsp), + .vx_dcache_req(vx_dcache_req), .out_delay (out_mem_delay), .no_slot_mem (no_slot_mem) - ); +); - -VX_execute_unit VX_execUnit( +VX_execute_unit vx_execUnit ( .clk (clk), .reset (reset), - .VX_exec_unit_req(VX_exec_unit_req), - .VX_inst_exec_wb (VX_inst_exec_wb), - .VX_jal_rsp (VX_jal_rsp), - .VX_branch_rsp (VX_branch_rsp), + .vx_exec_unit_req(vx_exec_unit_req), + .vx_inst_exec_wb (vx_inst_exec_wb), + .vx_jal_rsp (vx_jal_rsp), + .vx_branch_rsp (vx_branch_rsp), .out_delay (out_exec_delay), .no_slot_exec (no_slot_exec) - ); +); +VX_gpgpu_inst vx_gpgpu_inst ( + .vx_gpu_inst_req(vx_gpu_inst_req), + .vx_warp_ctl (vx_warp_ctl) +); -VX_gpgpu_inst VX_gpgpu_inst( - .VX_gpu_inst_req(VX_gpu_inst_req), - .VX_warp_ctl (VX_warp_ctl) - ); - -// VX_csr_wrapper VX_csr_wrapper( -// .VX_csr_req(VX_csr_req), -// .VX_csr_wb (VX_csr_wb) +// VX_csr_wrapper vx_csr_wrapper( +// .vx_csr_req(vx_csr_req), +// .vx_csr_wb (vx_csr_wb) // ); -VX_csr_pipe #(.CORE_ID(CORE_ID)) VX_csr_pipe( +VX_csr_pipe #( + .CORE_ID(CORE_ID) +) vx_csr_pipe ( .clk (clk), .reset (reset), .no_slot_csr (no_slot_csr), - .VX_csr_req (VX_csr_req), - .VX_writeback(VX_writeback_temp), - .VX_csr_wb (VX_csr_wb), + .vx_csr_req (vx_csr_req), + .vx_writeback(vx_writeback_temp), + .vx_csr_wb (vx_csr_wb), .stall_gpr_csr(stall_gpr_csr) - ); +); -VX_writeback VX_wb( +VX_writeback vx_wb ( .clk (clk), .reset (reset), - .VX_mem_wb (VX_mem_wb), - .VX_inst_exec_wb (VX_inst_exec_wb), - .VX_csr_wb (VX_csr_wb), + .vx_mem_wb (vx_mem_wb), + .vx_inst_exec_wb (vx_inst_exec_wb), + .vx_csr_wb (vx_csr_wb), - .VX_writeback_inter(VX_writeback_temp), + .vx_writeback_inter(vx_writeback_temp), .no_slot_mem (no_slot_mem), .no_slot_exec (no_slot_exec), .no_slot_csr (no_slot_csr) - ); +); endmodule \ No newline at end of file diff --git a/hw/rtl/VX_csr_data.v b/hw/rtl/VX_csr_data.v index 7d8af6a6..0182353f 100644 --- a/hw/rtl/VX_csr_data.v +++ b/hw/rtl/VX_csr_data.v @@ -4,21 +4,20 @@ module VX_csr_data ( input wire clk, // Clock input wire reset, - input wire[11:0] in_read_csr_address, + input wire[`CSR_ADDR_SIZE-1:0] in_read_csr_address, + input wire in_write_valid, + input wire[`CSR_WIDTH-1:0] in_write_csr_data, - input wire in_write_valid, - input wire[31:0] in_write_csr_data, - input wire[11:0] in_write_csr_address, +/* verilator lint_off UNUSED */ + // We use a smaller storage for CSRs than the standard 4KB in RISC-V + input wire[`CSR_ADDR_SIZE-1:0] in_write_csr_address, +/* verilator lint_on UNUSED */ output wire[31:0] out_read_csr_data, // For instruction retire counting input wire in_writeback_valid - ); - - /* verilator lint_off WIDTH */ - // wire[`NUM_THREADS-1:0][31:0] thread_ids; // wire[`NUM_THREADS-1:0][31:0] warp_ids; @@ -32,45 +31,44 @@ module VX_csr_data ( // assign warp_ids[cur_tw] = {{(31-`NW_BITS-1){1'b0}}, in_read_warp_num}; // end - reg[11:0] csr[1023:0]; - reg[63:0] cycle; - reg[63:0] instret; + reg [`CSR_WIDTH-1:0] csr[`NUM_CSRS-1:0]; + reg [63:0] cycle; + reg [63:0] instret; wire read_cycle; wire read_cycleh; wire read_instret; wire read_instreth; - assign read_cycle = in_read_csr_address == 12'hC00; - assign read_cycleh = in_read_csr_address == 12'hC80; - assign read_instret = in_read_csr_address == 12'hC02; - assign read_instreth = in_read_csr_address == 12'hC82; + assign read_cycle = in_read_csr_address == `CSR_CYCL_L; + assign read_cycleh = in_read_csr_address == `CSR_CYCL_H; + assign read_instret = in_read_csr_address == `CSR_INST_L; + assign read_instreth = in_read_csr_address == `CSR_INST_H; + + wire [$clog2(`NUM_CSRS)-1:0] read_addr, write_addr; + + // cast address to physical CSR range + assign read_addr = $size(read_addr)'(in_read_csr_address); + assign write_addr = $size(write_addr)'(in_write_csr_address); // wire thread_select = in_read_csr_address == 12'h20; // wire warp_select = in_read_csr_address == 12'h21; - // assign out_read_csr_data = thread_select ? thread_ids : + // assign out_read_csr_data = thread_select ? thread_ids : // warp_select ? warp_ids : // 0; - integer curr_e; - always @(posedge clk or posedge reset) begin + genvar curr_e; + + always @(posedge clk) begin if (reset) begin - for (curr_e = 0; curr_e < 1024; curr_e=curr_e+1) begin -`ifdef VERILATOR - // - Verilator does not support delayed assignment in loops. - csr[curr_e] = 0; -`else - csr[curr_e] <= 0; -`endif - end cycle <= 0; instret <= 0; end else begin cycle <= cycle + 1; if (in_write_valid) begin - csr[in_write_csr_address] <= in_write_csr_data[11:0]; + csr[write_addr] <= in_write_csr_data; end if (in_writeback_valid) begin instret <= instret + 1; @@ -78,12 +76,9 @@ module VX_csr_data ( end end - - assign out_read_csr_data = read_cycle ? cycle[31:0] : - read_cycleh ? cycle[63:32] : - read_instret ? instret[31:0] : - read_instreth ? instret[63:32] : - {{20{1'b0}}, csr[in_read_csr_address]}; - - /* verilator lint_on WIDTH */ + assign out_read_csr_data = read_cycle ? cycle[31:0] : + read_cycleh ? cycle[63:32] : + read_instret ? instret[31:0] : + read_instreth ? instret[63:32] : + {{20{1'b0}}, csr[read_addr]}; endmodule : VX_csr_data diff --git a/hw/rtl/VX_csr_handler.v b/hw/rtl/VX_csr_handler.v index b6b4e84a..a2458432 100644 --- a/hw/rtl/VX_csr_handler.v +++ b/hw/rtl/VX_csr_handler.v @@ -1,78 +1,63 @@ - - module VX_csr_handler ( - input wire clk, - input wire[11:0] in_decode_csr_address, // done - VX_csr_write_request_inter VX_csr_w_req, - input wire in_wb_valid, - output wire[31:0] out_decode_csr_data // done - ); + input wire clk, + input wire[`CSR_ADDR_SIZE-1:0] in_decode_csr_address, // done + VX_csr_write_request_inter vx_csr_w_req, + input wire in_wb_valid, + output wire[31:0] out_decode_csr_data // done +); + wire in_mem_is_csr; + wire[`CSR_ADDR_SIZE-1:0] in_mem_csr_address; + wire[31:0] in_mem_csr_result; - wire in_mem_is_csr; - wire[11:0] in_mem_csr_address; - /* verilator lint_off UNUSED */ - wire[31:0] in_mem_csr_result; - /* verilator lint_on UNUSED */ + assign in_mem_is_csr = vx_csr_w_req.is_csr; + assign in_mem_csr_address = vx_csr_w_req.csr_address; + assign in_mem_csr_result = vx_csr_w_req.csr_result; + reg [`CSR_WIDTH-1:0] csr [`NUM_CSRS-1:0]; + + reg [63:0] cycle; + reg [63:0] instret; + reg [`CSR_ADDR_SIZE-1:0] decode_csr_address; - assign in_mem_is_csr = VX_csr_w_req.is_csr; - assign in_mem_csr_address = VX_csr_w_req.csr_address; - assign in_mem_csr_result = VX_csr_w_req.csr_result; + wire read_cycle; + wire read_cycleh; + wire read_instret; + wire read_instreth; + initial begin + cycle = 0; + instret = 0; + decode_csr_address = 0; + end - reg[1024:0][11:0] csr; - reg[63:0] cycle; - reg[63:0] instret; - reg[11:0] decode_csr_address; - - - wire read_cycle; - wire read_cycleh; - wire read_instret; - wire read_instreth; - - initial begin - cycle = 0; - instret = 0; - decode_csr_address = 0; + always @(posedge clk) begin + cycle <= cycle + 1; + decode_csr_address <= in_decode_csr_address; + if (in_wb_valid) begin + instret <= instret + 1; end + end + reg[`CSR_WIDTH-1:0] data_read; - always @(posedge clk) begin - cycle <= cycle + 1; - decode_csr_address <= in_decode_csr_address; - if (in_wb_valid) begin - instret <= instret + 1; - end + always @(posedge clk) begin + if (in_mem_is_csr) begin + csr[in_mem_csr_address] <= in_mem_csr_result[11:0]; end + end - reg[11:0] data_read; - always @(posedge clk) begin - if(in_mem_is_csr) begin - csr[in_mem_csr_address] <= in_mem_csr_result[11:0]; - end - end - - assign data_read = csr[decode_csr_address]; - - - assign read_cycle = decode_csr_address == 12'hC00; - assign read_cycleh = decode_csr_address == 12'hC80; - assign read_instret = decode_csr_address == 12'hC02; - assign read_instreth = decode_csr_address == 12'hC82; - - - /* verilator lint_off WIDTH */ - assign out_decode_csr_data = read_cycle ? cycle[31:0] : - read_cycleh ? cycle[63:32] : - read_instret ? instret[31:0] : - read_instreth ? instret[63:32] : - {{20{1'b0}}, data_read}; - /* verilator lint_on WIDTH */ - - + assign data_read = csr[decode_csr_address]; + assign read_cycle = decode_csr_address == `CSR_CYCL_L; + assign read_cycleh = decode_csr_address == `CSR_CYCL_H; + assign read_instret = decode_csr_address == `CSR_INST_L; + assign read_instreth = decode_csr_address == `CSR_INST_H; + assign out_decode_csr_data = read_cycle ? cycle[31:0] : + read_cycleh ? cycle[63:32] : + read_instret ? instret[31:0] : + read_instreth ? instret[63:32] : + {{20{1'b0}}, data_read}; endmodule // VX_csr_handler diff --git a/hw/rtl/VX_csr_pipe.v b/hw/rtl/VX_csr_pipe.v index 6434e671..507ec18f 100644 --- a/hw/rtl/VX_csr_pipe.v +++ b/hw/rtl/VX_csr_pipe.v @@ -1,16 +1,14 @@ `include "VX_define.vh" -module VX_csr_pipe - #( - parameter CORE_ID = 0 - ) - ( +module VX_csr_pipe #( + parameter CORE_ID = 0 +) ( input wire clk, // Clock input wire reset, input wire no_slot_csr, - VX_csr_req_inter VX_csr_req, - VX_wb_inter VX_writeback, - VX_csr_wb_inter VX_csr_wb, + VX_csr_req_inter vx_csr_req, + VX_wb_inter vx_writeback, + VX_csr_wb_inter vx_csr_wb, output wire stall_gpr_csr ); @@ -18,64 +16,61 @@ module VX_csr_pipe wire[`NW_BITS-1:0] warp_num_s2; wire[4:0] rd_s2; wire[1:0] wb_s2; - wire[4:0] alu_op_s2; wire is_csr_s2; - wire[11:0] csr_address_s2; + wire[`CSR_ADDR_SIZE-1:0] csr_address_s2; wire[31:0] csr_read_data_s2; wire[31:0] csr_updated_data_s2; wire[31:0] csr_read_data_unqual; wire[31:0] csr_read_data; - assign stall_gpr_csr = no_slot_csr && VX_csr_req.is_csr && |(VX_csr_req.valid); + assign stall_gpr_csr = no_slot_csr && vx_csr_req.is_csr && |(vx_csr_req.valid); - assign csr_read_data = (csr_address_s2 == VX_csr_req.csr_address) ? csr_updated_data_s2 : csr_read_data_unqual; + assign csr_read_data = (csr_address_s2 == vx_csr_req.csr_address) ? csr_updated_data_s2 : csr_read_data_unqual; - wire writeback = |VX_writeback.wb_valid; - VX_csr_data VX_csr_data( + wire writeback = |vx_writeback.wb_valid; + + VX_csr_data vx_csr_data( .clk (clk), .reset (reset), - .in_read_csr_address (VX_csr_req.csr_address), - + .in_read_csr_address (vx_csr_req.csr_address), .in_write_valid (is_csr_s2), - .in_write_csr_data (csr_updated_data_s2), + .in_write_csr_data (csr_updated_data_s2[`CSR_WIDTH-1:0]), .in_write_csr_address(csr_address_s2), - .out_read_csr_data (csr_read_data_unqual), - .in_writeback_valid (writeback) - ); + ); + reg [31:0] csr_updated_data; - - reg[31:0] csr_updated_data; always @(*) begin - case(VX_csr_req.alu_op) - `CSR_ALU_RW: csr_updated_data = VX_csr_req.csr_mask; - `CSR_ALU_RS: csr_updated_data = csr_read_data | VX_csr_req.csr_mask; - `CSR_ALU_RC: csr_updated_data = csr_read_data & (32'hFFFFFFFF - VX_csr_req.csr_mask); + case (vx_csr_req.alu_op) + `CSR_ALU_RW: csr_updated_data = vx_csr_req.csr_mask; + `CSR_ALU_RS: csr_updated_data = csr_read_data | vx_csr_req.csr_mask; + `CSR_ALU_RC: csr_updated_data = csr_read_data & (32'hFFFFFFFF - vx_csr_req.csr_mask); default: csr_updated_data = 32'hdeadbeef; endcase end wire zero = 0; - VX_generic_register #(.N(32 + 32 + 12 + 1 + 2 + 5 + (`NW_BITS-1+1) + `NUM_THREADS)) csr_reg_s2 ( + VX_generic_register #( + .N(32 + 32 + 12 + 1 + 2 + 5 + (`NW_BITS-1+1) + `NUM_THREADS) + ) csr_reg_s2 ( .clk (clk), .reset(reset), .stall(no_slot_csr), .flush(zero), - .in ({VX_csr_req.valid, VX_csr_req.warp_num, VX_csr_req.rd, VX_csr_req.wb, VX_csr_req.is_csr, VX_csr_req.csr_address, csr_read_data , csr_updated_data }), + .in ({vx_csr_req.valid, vx_csr_req.warp_num, vx_csr_req.rd, vx_csr_req.wb, vx_csr_req.is_csr, vx_csr_req.csr_address, csr_read_data , csr_updated_data }), .out ({valid_s2 , warp_num_s2 , rd_s2 , wb_s2 , is_csr_s2 , csr_address_s2 , csr_read_data_s2, csr_updated_data_s2}) - ); + ); + wire [`NUM_THREADS-1:0][31:0] final_csr_data; - wire[`NUM_THREADS-1:0][31:0] final_csr_data; - - wire[`NUM_THREADS-1:0][31:0] thread_ids; - wire[`NUM_THREADS-1:0][31:0] warp_ids; - wire[`NUM_THREADS-1:0][31:0] warp_idz; - wire[`NUM_THREADS-1:0][31:0] csr_vec_read_data_s2; + wire [`NUM_THREADS-1:0][31:0] thread_ids; + wire [`NUM_THREADS-1:0][31:0] warp_ids; + wire [`NUM_THREADS-1:0][31:0] warp_idz; + wire [`NUM_THREADS-1:0][31:0] csr_vec_read_data_s2; genvar cur_t; for (cur_t = 0; cur_t < `NUM_THREADS; cur_t = cur_t + 1) begin @@ -102,10 +97,10 @@ module VX_csr_pipe warp_id_select ? warp_idz : csr_vec_read_data_s2; - assign VX_csr_wb.valid = valid_s2; - assign VX_csr_wb.warp_num = warp_num_s2; - assign VX_csr_wb.rd = rd_s2; - assign VX_csr_wb.wb = wb_s2; - assign VX_csr_wb.csr_result = final_csr_data; + assign vx_csr_wb.valid = valid_s2; + assign vx_csr_wb.warp_num = warp_num_s2; + assign vx_csr_wb.rd = rd_s2; + assign vx_csr_wb.wb = wb_s2; + assign vx_csr_wb.csr_result = final_csr_data; endmodule diff --git a/hw/rtl/VX_csr_wrapper.v b/hw/rtl/VX_csr_wrapper.v index 4097a779..6c37fdc3 100644 --- a/hw/rtl/VX_csr_wrapper.v +++ b/hw/rtl/VX_csr_wrapper.v @@ -2,9 +2,8 @@ `include "VX_define.vh" module VX_csr_wrapper ( - VX_csr_req_inter VX_csr_req, - - VX_csr_wb_inter VX_csr_wb + VX_csr_req_inter vx_csr_req, + VX_csr_wb_inter vx_csr_wb ); @@ -18,21 +17,21 @@ module VX_csr_wrapper ( end for (cur_tw = 0; cur_tw < `NUM_THREADS; cur_tw = cur_tw + 1) begin : warp_ids_init - assign warp_ids[cur_tw] = {{(31-`NW_BITS-1){1'b0}}, VX_csr_req.warp_num}; + assign warp_ids[cur_tw] = {{(31-`NW_BITS-1){1'b0}}, vx_csr_req.warp_num}; end endgenerate - assign VX_csr_wb.valid = VX_csr_req.valid; - assign VX_csr_wb.warp_num = VX_csr_req.warp_num; - assign VX_csr_wb.rd = VX_csr_req.rd; - assign VX_csr_wb.wb = VX_csr_req.wb; + assign vx_csr_wb.valid = vx_csr_req.valid; + assign vx_csr_wb.warp_num = vx_csr_req.warp_num; + assign vx_csr_wb.rd = vx_csr_req.rd; + assign vx_csr_wb.wb = vx_csr_req.wb; - wire thread_select = VX_csr_req.csr_address == 12'h20; - wire warp_select = VX_csr_req.csr_address == 12'h21; + wire thread_select = vx_csr_req.csr_address == 12'h20; + wire warp_select = vx_csr_req.csr_address == 12'h21; - assign VX_csr_wb.csr_result = thread_select ? thread_ids : + assign vx_csr_wb.csr_result = thread_select ? thread_ids : warp_select ? warp_ids : 0; diff --git a/hw/rtl/VX_decode.v b/hw/rtl/VX_decode.v index 1ea0ef97..3256eab1 100644 --- a/hw/rtl/VX_decode.v +++ b/hw/rtl/VX_decode.v @@ -6,349 +6,338 @@ module VX_decode( VX_inst_meta_inter fd_inst_meta_de, // Outputs - VX_frE_to_bckE_req_inter VX_frE_to_bckE_req, - VX_wstall_inter VX_wstall, - VX_join_inter VX_join, + VX_frE_to_bckE_req_inter vx_frE_to_bckE_req, + VX_wstall_inter vx_wstall, + VX_join_inter vx_join, output wire terminate_sim ); - wire[31:0] in_instruction = fd_inst_meta_de.instruction; - wire[31:0] in_curr_PC = fd_inst_meta_de.inst_pc; - wire[`NW_BITS-1:0] in_warp_num = fd_inst_meta_de.warp_num; + wire[31:0] in_instruction = fd_inst_meta_de.instruction; + wire[31:0] in_curr_PC = fd_inst_meta_de.inst_pc; + wire[`NW_BITS-1:0] in_warp_num = fd_inst_meta_de.warp_num; - assign VX_frE_to_bckE_req.curr_PC = in_curr_PC; + assign vx_frE_to_bckE_req.curr_PC = in_curr_PC; - wire[`NUM_THREADS-1:0] in_valid = fd_inst_meta_de.valid; + wire[`NUM_THREADS-1:0] in_valid = fd_inst_meta_de.valid; - wire[6:0] curr_opcode; + wire[6:0] curr_opcode; - wire is_itype; - wire is_rtype; - wire is_stype; - wire is_btype; - wire is_linst; - wire is_jal; - wire is_jalr; - wire is_lui; - wire is_auipc; - wire is_csr; - wire is_csr_immed; - wire is_e_inst; + wire is_itype; + wire is_rtype; + wire is_stype; + wire is_btype; + wire is_linst; + wire is_jal; + wire is_jalr; + wire is_lui; + wire is_auipc; + wire is_csr; + wire is_csr_immed; + wire is_e_inst; - wire is_gpgpu; - wire is_wspawn; - wire is_tmc; - wire is_split; - wire is_join; - wire is_barrier; + wire is_gpgpu; + wire is_wspawn; + wire is_tmc; + wire is_split; + wire is_join; + wire is_barrier; - wire[2:0] func3; - wire[6:0] func7; - wire[11:0] u_12; + wire[2:0] func3; + wire[6:0] func7; + wire[11:0] u_12; - wire[7:0] jal_b_19_to_12; - wire jal_b_11; - wire[9:0] jal_b_10_to_1; - wire jal_b_20; - wire jal_b_0; - wire[20:0] jal_unsigned_offset; - wire[31:0] jal_1_offset; + wire[7:0] jal_b_19_to_12; + wire jal_b_11; + wire[9:0] jal_b_10_to_1; + wire jal_b_20; + wire jal_b_0; + wire[20:0] jal_unsigned_offset; + wire[31:0] jal_1_offset; - wire[11:0] jalr_immed; - wire[31:0] jal_2_offset; + wire[11:0] jalr_immed; + wire[31:0] jal_2_offset; - wire jal_sys_cond1; - wire jal_sys_cond2; - wire jal_sys_jal; - wire[31:0] jal_sys_off; + wire jal_sys_cond1; + wire jal_sys_cond2; + wire jal_sys_jal; + wire[31:0] jal_sys_off; - wire csr_cond1; - wire csr_cond2; + wire csr_cond1; + wire csr_cond2; - wire[11:0] alu_tempp; - wire alu_shift_i; - wire[11:0] alu_shift_i_immed; + wire[11:0] alu_tempp; + wire alu_shift_i; + wire[11:0] alu_shift_i_immed; - wire[1:0] csr_type; + wire[1:0] csr_type; - reg[4:0] csr_alu; - reg[4:0] alu_op; - reg[4:0] mul_alu; - reg[19:0] temp_upper_immed; - reg temp_jal; - reg[31:0] temp_jal_offset; - reg[31:0] temp_itype_immed; - reg[2:0] temp_branch_type; - reg temp_branch_stall; + reg[4:0] csr_alu; + reg[4:0] alu_op; + reg[4:0] mul_alu; + reg[19:0] temp_upper_immed; + reg temp_jal; + reg[31:0] temp_jal_offset; + reg[31:0] temp_itype_immed; + reg[2:0] temp_branch_type; + reg temp_branch_stall; - // always @(posedge reset) begin - - // end + assign vx_frE_to_bckE_req.valid = fd_inst_meta_de.valid; - assign VX_frE_to_bckE_req.valid = fd_inst_meta_de.valid; + assign vx_frE_to_bckE_req.warp_num = in_warp_num; - assign VX_frE_to_bckE_req.warp_num = in_warp_num; + assign curr_opcode = in_instruction[6:0]; + + assign vx_frE_to_bckE_req.rd = in_instruction[11:7]; + assign vx_frE_to_bckE_req.rs1 = in_instruction[19:15]; + assign vx_frE_to_bckE_req.rs2 = in_instruction[24:20]; + assign func3 = in_instruction[14:12]; + assign func7 = in_instruction[31:25]; + assign u_12 = in_instruction[31:20]; + + assign vx_frE_to_bckE_req.PC_next = in_curr_PC + 32'h4; + + // Write Back sigal + assign is_rtype = (curr_opcode == `R_INST); + assign is_linst = (curr_opcode == `L_INST); + assign is_itype = (curr_opcode == `ALU_INST) || is_linst; + assign is_stype = (curr_opcode == `S_INST); + assign is_btype = (curr_opcode == `B_INST); + assign is_jal = (curr_opcode == `JAL_INST); + assign is_jalr = (curr_opcode == `JALR_INST); + assign is_lui = (curr_opcode == `LUI_INST); + assign is_auipc = (curr_opcode == `AUIPC_INST); + assign is_csr = (curr_opcode == `SYS_INST) && (func3 != 0); + assign is_csr_immed = (is_csr) && (func3[2] == 1); + // assign is_e_inst = (curr_opcode == `SYS_INST) && (func3 == 0); + assign is_e_inst = in_instruction == 32'h00000073; + + assign is_gpgpu = (curr_opcode == `GPGPU_INST); + + assign is_tmc = is_gpgpu && (func3 == 0); // Goes to BE + assign is_wspawn = is_gpgpu && (func3 == 1); // Goes to BE + assign is_barrier = is_gpgpu && (func3 == 4); // Goes to BE + assign is_split = is_gpgpu && (func3 == 2); // Goes to BE + assign is_join = is_gpgpu && (func3 == 3); // Doesn't go to BE - assign curr_opcode = in_instruction[6:0]; + assign vx_join.is_join = is_join; + assign vx_join.join_warp_num = in_warp_num; - assign VX_frE_to_bckE_req.rd = in_instruction[11:7]; - assign VX_frE_to_bckE_req.rs1 = in_instruction[19:15]; - assign VX_frE_to_bckE_req.rs2 = in_instruction[24:20]; - assign func3 = in_instruction[14:12]; - assign func7 = in_instruction[31:25]; - assign u_12 = in_instruction[31:20]; - - - assign VX_frE_to_bckE_req.PC_next = in_curr_PC + 32'h4; - - - // Write Back sigal - assign is_rtype = (curr_opcode == `R_INST); - assign is_linst = (curr_opcode == `L_INST); - assign is_itype = (curr_opcode == `ALU_INST) || is_linst; - assign is_stype = (curr_opcode == `S_INST); - assign is_btype = (curr_opcode == `B_INST); - assign is_jal = (curr_opcode == `JAL_INST); - assign is_jalr = (curr_opcode == `JALR_INST); - assign is_lui = (curr_opcode == `LUI_INST); - assign is_auipc = (curr_opcode == `AUIPC_INST); - assign is_csr = (curr_opcode == `SYS_INST) && (func3 != 0); - assign is_csr_immed = (is_csr) && (func3[2] == 1); - // assign is_e_inst = (curr_opcode == `SYS_INST) && (func3 == 0); - assign is_e_inst = in_instruction == 32'h00000073; - - assign is_gpgpu = (curr_opcode == `GPGPU_INST); - - assign is_tmc = is_gpgpu && (func3 == 0); // Goes to BE - assign is_wspawn = is_gpgpu && (func3 == 1); // Goes to BE - assign is_barrier = is_gpgpu && (func3 == 4); // Goes to BE - assign is_split = is_gpgpu && (func3 == 2); // Goes to BE - assign is_join = is_gpgpu && (func3 == 3); // Doesn't go to BE - - - assign VX_join.is_join = is_join; - assign VX_join.join_warp_num = in_warp_num; - - - assign VX_frE_to_bckE_req.is_wspawn = is_wspawn; - assign VX_frE_to_bckE_req.is_tmc = is_tmc; - assign VX_frE_to_bckE_req.is_split = is_split; - assign VX_frE_to_bckE_req.is_barrier = is_barrier; + assign vx_frE_to_bckE_req.is_wspawn = is_wspawn; + assign vx_frE_to_bckE_req.is_tmc = is_tmc; + assign vx_frE_to_bckE_req.is_split = is_split; + assign vx_frE_to_bckE_req.is_barrier = is_barrier; - assign VX_frE_to_bckE_req.csr_immed = is_csr_immed; - assign VX_frE_to_bckE_req.is_csr = is_csr; + assign vx_frE_to_bckE_req.csr_immed = is_csr_immed; + assign vx_frE_to_bckE_req.is_csr = is_csr; - assign VX_frE_to_bckE_req.wb = (is_jal || is_jalr || is_e_inst) ? `WB_JAL : - is_linst ? `WB_MEM : - (is_itype || is_rtype || is_lui || is_auipc || is_csr) ? `WB_ALU : - `NO_WB; + assign vx_frE_to_bckE_req.wb = (is_jal || is_jalr || is_e_inst) ? `WB_JAL : + is_linst ? `WB_MEM : + (is_itype || is_rtype || is_lui || is_auipc || is_csr) ? `WB_ALU : + `NO_WB; - assign VX_frE_to_bckE_req.rs2_src = (is_itype || is_stype) ? `RS2_IMMED : `RS2_REG; + assign vx_frE_to_bckE_req.rs2_src = (is_itype || is_stype) ? `RS2_IMMED : `RS2_REG; - // MEM signals - assign VX_frE_to_bckE_req.mem_read = (is_linst) ? func3 : `NO_MEM_READ; - assign VX_frE_to_bckE_req.mem_write = (is_stype) ? func3 : `NO_MEM_WRITE; + // MEM signals + assign vx_frE_to_bckE_req.mem_read = (is_linst) ? func3 : `NO_MEM_READ; + assign vx_frE_to_bckE_req.mem_write = (is_stype) ? func3 : `NO_MEM_WRITE; - // UPPER IMMEDIATE - always @(*) begin - case(curr_opcode) - `LUI_INST: temp_upper_immed = {func7, VX_frE_to_bckE_req.rs2, VX_frE_to_bckE_req.rs1, func3}; - `AUIPC_INST: temp_upper_immed = {func7, VX_frE_to_bckE_req.rs2, VX_frE_to_bckE_req.rs1, func3}; - default: temp_upper_immed = 20'h0; - endcase // curr_opcode - end + // UPPER IMMEDIATE + always @(*) begin + case(curr_opcode) + `LUI_INST: temp_upper_immed = {func7, vx_frE_to_bckE_req.rs2, vx_frE_to_bckE_req.rs1, func3}; + `AUIPC_INST: temp_upper_immed = {func7, vx_frE_to_bckE_req.rs2, vx_frE_to_bckE_req.rs1, func3}; + default: temp_upper_immed = 20'h0; + endcase // curr_opcode + end - assign VX_frE_to_bckE_req.upper_immed = temp_upper_immed; + assign vx_frE_to_bckE_req.upper_immed = temp_upper_immed; - assign jal_b_19_to_12 = in_instruction[19:12]; - assign jal_b_11 = in_instruction[20]; - assign jal_b_10_to_1 = in_instruction[30:21]; - assign jal_b_20 = in_instruction[31]; - assign jal_b_0 = 1'b0; - assign jal_unsigned_offset = {jal_b_20, jal_b_19_to_12, jal_b_11, jal_b_10_to_1, jal_b_0}; - assign jal_1_offset = {{11{jal_b_20}}, jal_unsigned_offset}; + assign jal_b_19_to_12 = in_instruction[19:12]; + assign jal_b_11 = in_instruction[20]; + assign jal_b_10_to_1 = in_instruction[30:21]; + assign jal_b_20 = in_instruction[31]; + assign jal_b_0 = 1'b0; + assign jal_unsigned_offset = {jal_b_20, jal_b_19_to_12, jal_b_11, jal_b_10_to_1, jal_b_0}; + assign jal_1_offset = {{11{jal_b_20}}, jal_unsigned_offset}; - assign jalr_immed = {func7, VX_frE_to_bckE_req.rs2}; - assign jal_2_offset = {{20{jalr_immed[11]}}, jalr_immed}; + assign jalr_immed = {func7, vx_frE_to_bckE_req.rs2}; + assign jal_2_offset = {{20{jalr_immed[11]}}, jalr_immed}; - assign jal_sys_cond1 = func3 == 3'h0; - assign jal_sys_cond2 = u_12 < 12'h2; + assign jal_sys_cond1 = func3 == 3'h0; + assign jal_sys_cond2 = u_12 < 12'h2; - assign jal_sys_jal = (jal_sys_cond1 && jal_sys_cond2) ? 1'b1 : 1'b0; - assign jal_sys_off = (jal_sys_cond1 && jal_sys_cond2) ? 32'hb0000000 : 32'hdeadbeef; + assign jal_sys_jal = (jal_sys_cond1 && jal_sys_cond2) ? 1'b1 : 1'b0; + assign jal_sys_off = (jal_sys_cond1 && jal_sys_cond2) ? 32'hb0000000 : 32'hdeadbeef; - // JAL - always @(*) begin - case(curr_opcode) - `JAL_INST: - begin - temp_jal = 1'b1 && (|in_valid); - temp_jal_offset = jal_1_offset; - end - `JALR_INST: - begin - temp_jal = 1'b1 && (|in_valid); - temp_jal_offset = jal_2_offset; - end - `SYS_INST: - begin - // $display("SYS EBREAK %h", (jal_sys_jal && (|in_valid)) ); - temp_jal = jal_sys_jal && (|in_valid); - temp_jal_offset = jal_sys_off; - end - default: - begin - temp_jal = 1'b0 && (|in_valid); - temp_jal_offset = 32'hdeadbeef; - end + // JAL + always @(*) begin + case(curr_opcode) + `JAL_INST: + begin + temp_jal = 1'b1 && (|in_valid); + temp_jal_offset = jal_1_offset; + end + `JALR_INST: + begin + temp_jal = 1'b1 && (|in_valid); + temp_jal_offset = jal_2_offset; + end + `SYS_INST: + begin + // $display("SYS EBREAK %h", (jal_sys_jal && (|in_valid)) ); + temp_jal = jal_sys_jal && (|in_valid); + temp_jal_offset = jal_sys_off; + end + default: + begin + temp_jal = 1'b0 && (|in_valid); + temp_jal_offset = 32'hdeadbeef; + end + endcase + end + + assign vx_frE_to_bckE_req.jalQual = is_jal; + assign vx_frE_to_bckE_req.jal = temp_jal; + assign vx_frE_to_bckE_req.jal_offset = temp_jal_offset; + + // wire is_ebreak; + + + // assign is_ebreak = is_e_inst; + wire ebreak = (curr_opcode == `SYS_INST) && (jal_sys_jal && (|in_valid)); + assign vx_frE_to_bckE_req.ebreak = ebreak; + assign terminate_sim = is_e_inst; + + + // CSR + + assign csr_cond1 = func3 != 3'h0; + assign csr_cond2 = u_12 >= 12'h2; + + assign vx_frE_to_bckE_req.csr_address = (csr_cond1 && csr_cond2) ? u_12 : 12'h55; + + + // ITYPE IMEED + assign alu_shift_i = (func3 == 3'h1) || (func3 == 3'h5); + assign alu_shift_i_immed = {{7{1'b0}}, vx_frE_to_bckE_req.rs2}; + assign alu_tempp = alu_shift_i ? alu_shift_i_immed : u_12; + + + always @(*) begin + case(curr_opcode) + `ALU_INST: temp_itype_immed = {{20{alu_tempp[11]}}, alu_tempp}; + `S_INST: temp_itype_immed = {{20{func7[6]}}, func7, vx_frE_to_bckE_req.rd}; + `L_INST: temp_itype_immed = {{20{u_12[11]}}, u_12}; + `B_INST: temp_itype_immed = {{20{in_instruction[31]}}, in_instruction[31], in_instruction[7], in_instruction[30:25], in_instruction[11:8]}; + default: temp_itype_immed = 32'hdeadbeef; endcase - end + end - assign VX_frE_to_bckE_req.jalQual = is_jal; - assign VX_frE_to_bckE_req.jal = temp_jal; - assign VX_frE_to_bckE_req.jal_offset = temp_jal_offset; + assign vx_frE_to_bckE_req.itype_immed = temp_itype_immed; - // wire is_ebreak; + always @(*) begin + case(curr_opcode) + `B_INST: + begin + // $display("BRANCH IN DECODE"); + temp_branch_stall = 1'b1 && (|in_valid); + case(func3) + 3'h0: temp_branch_type = `BEQ; + 3'h1: temp_branch_type = `BNE; + 3'h4: temp_branch_type = `BLT; + 3'h5: temp_branch_type = `BGT; + 3'h6: temp_branch_type = `BLTU; + 3'h7: temp_branch_type = `BGTU; + default: temp_branch_type = `NO_BRANCH; + endcase + end + `JAL_INST: + begin + temp_branch_type = `NO_BRANCH; + temp_branch_stall = 1'b1 && (|in_valid); + end + `JALR_INST: + begin + temp_branch_type = `NO_BRANCH; + temp_branch_stall = 1'b1 && (|in_valid); + end + default: + begin + temp_branch_type = `NO_BRANCH; + temp_branch_stall = 1'b0 && (|in_valid); + end + endcase + end - // assign is_ebreak = is_e_inst; - wire ebreak = (curr_opcode == `SYS_INST) && (jal_sys_jal && (|in_valid)); - assign VX_frE_to_bckE_req.ebreak = ebreak; - wire out_ebreak = ebreak; - assign terminate_sim = is_e_inst; + assign vx_frE_to_bckE_req.branch_type = temp_branch_type; + assign vx_wstall.wstall = (temp_branch_stall || is_tmc || is_split || is_barrier) && (|in_valid); + assign vx_wstall.warp_num = in_warp_num; - // CSR + always @(*) begin + // ALU OP + case(func3) + 3'h0: alu_op = (curr_opcode == `ALU_INST) ? `ADD : (func7 == 7'h0 ? `ADD : `SUB); + 3'h1: alu_op = `SLLA; + 3'h2: alu_op = `SLT; + 3'h3: alu_op = `SLTU; + 3'h4: alu_op = `XOR; + 3'h5: alu_op = (func7 == 7'h0) ? `SRL : `SRA; + 3'h6: alu_op = `OR; + 3'h7: alu_op = `AND; + default: alu_op = `NO_ALU; + endcase + end - assign csr_cond1 = func3 != 3'h0; - assign csr_cond2 = u_12 >= 12'h2; + always @(*) begin + // ALU OP + case(func3) + 3'h0: mul_alu = `MUL; + 3'h1: mul_alu = `MULH; + 3'h2: mul_alu = `MULHSU; + 3'h3: mul_alu = `MULHU; + 3'h4: mul_alu = `DIV; + 3'h5: mul_alu = `DIVU; + 3'h6: mul_alu = `REM; + 3'h7: mul_alu = `REMU; + default: mul_alu = `NO_ALU; + endcase + end - assign VX_frE_to_bckE_req.csr_address = (csr_cond1 && csr_cond2) ? u_12 : 12'h55; + assign csr_type = func3[1:0]; + always @(*) begin + case(csr_type) + 2'h1: csr_alu = `CSR_ALU_RW; + 2'h2: csr_alu = `CSR_ALU_RS; + 2'h3: csr_alu = `CSR_ALU_RC; + default: csr_alu = `NO_ALU; + endcase + end - // ITYPE IMEED - assign alu_shift_i = (func3 == 3'h1) || (func3 == 3'h5); - assign alu_shift_i_immed = {{7{1'b0}}, VX_frE_to_bckE_req.rs2}; - assign alu_tempp = alu_shift_i ? alu_shift_i_immed : u_12; + wire[4:0] temp_final_alu; + assign temp_final_alu = is_btype ? ((vx_frE_to_bckE_req.branch_type < `BLTU) ? `SUB : `SUBU) : + is_lui ? `LUI_ALU : + is_auipc ? `AUIPC_ALU : + is_csr ? csr_alu : + (is_stype || is_linst) ? `ADD : + alu_op; - always @(*) begin - case(curr_opcode) - `ALU_INST: temp_itype_immed = {{20{alu_tempp[11]}}, alu_tempp}; - `S_INST: temp_itype_immed = {{20{func7[6]}}, func7, VX_frE_to_bckE_req.rd}; - `L_INST: temp_itype_immed = {{20{u_12[11]}}, u_12}; - `B_INST: temp_itype_immed = {{20{in_instruction[31]}}, in_instruction[31], in_instruction[7], in_instruction[30:25], in_instruction[11:8]}; - default: temp_itype_immed = 32'hdeadbeef; - endcase - end - - assign VX_frE_to_bckE_req.itype_immed = temp_itype_immed; - - - - always @(*) begin - case(curr_opcode) - `B_INST: - begin - // $display("BRANCH IN DECODE"); - temp_branch_stall = 1'b1 && (|in_valid); - case(func3) - 3'h0: temp_branch_type = `BEQ; - 3'h1: temp_branch_type = `BNE; - 3'h4: temp_branch_type = `BLT; - 3'h5: temp_branch_type = `BGT; - 3'h6: temp_branch_type = `BLTU; - 3'h7: temp_branch_type = `BGTU; - default: temp_branch_type = `NO_BRANCH; - endcase - end - - `JAL_INST: - begin - temp_branch_type = `NO_BRANCH; - temp_branch_stall = 1'b1 && (|in_valid); - end - `JALR_INST: - begin - temp_branch_type = `NO_BRANCH; - temp_branch_stall = 1'b1 && (|in_valid); - end - default: - begin - temp_branch_type = `NO_BRANCH; - temp_branch_stall = 1'b0 && (|in_valid); - end - endcase - end - - assign VX_frE_to_bckE_req.branch_type = temp_branch_type; - - assign VX_wstall.wstall = (temp_branch_stall || is_tmc || is_split || is_barrier) && (|in_valid); - assign VX_wstall.warp_num = in_warp_num; - - always @(*) begin - // ALU OP - case(func3) - 3'h0: alu_op = (curr_opcode == `ALU_INST) ? `ADD : (func7 == 7'h0 ? `ADD : `SUB); - 3'h1: alu_op = `SLLA; - 3'h2: alu_op = `SLT; - 3'h3: alu_op = `SLTU; - 3'h4: alu_op = `XOR; - 3'h5: alu_op = (func7 == 7'h0) ? `SRL : `SRA; - 3'h6: alu_op = `OR; - 3'h7: alu_op = `AND; - default: alu_op = `NO_ALU; - endcase - end - - always @(*) begin - // ALU OP - case(func3) - 3'h0: mul_alu = `MUL; - 3'h1: mul_alu = `MULH; - 3'h2: mul_alu = `MULHSU; - 3'h3: mul_alu = `MULHU; - 3'h4: mul_alu = `DIV; - 3'h5: mul_alu = `DIVU; - 3'h6: mul_alu = `REM; - 3'h7: mul_alu = `REMU; - default: mul_alu = `NO_ALU; - endcase - end - - assign csr_type = func3[1:0]; - - always @(*) begin - case(csr_type) - 2'h1: csr_alu = `CSR_ALU_RW; - 2'h2: csr_alu = `CSR_ALU_RS; - 2'h3: csr_alu = `CSR_ALU_RC; - default: csr_alu = `NO_ALU; - endcase - end - - wire[4:0] temp_final_alu; - - assign temp_final_alu = is_btype ? ((VX_frE_to_bckE_req.branch_type < `BLTU) ? `SUB : `SUBU) : - is_lui ? `LUI_ALU : - is_auipc ? `AUIPC_ALU : - is_csr ? csr_alu : - (is_stype || is_linst) ? `ADD : - alu_op; - - assign VX_frE_to_bckE_req.alu_op = ((func7[0] == 1'b1) && is_rtype) ? mul_alu : temp_final_alu; + assign vx_frE_to_bckE_req.alu_op = ((func7[0] == 1'b1) && is_rtype) ? mul_alu : temp_final_alu; endmodule diff --git a/hw/rtl/VX_define.vh b/hw/rtl/VX_define.vh index 9985edc1..719ded6e 100644 --- a/hw/rtl/VX_define.vh +++ b/hw/rtl/VX_define.vh @@ -9,15 +9,35 @@ // `define ASIC 1 // `define SYN_FUNC 1 +`define STRINGIFY(x) `"x`" + +`define STATIC_ASSERT(cond, msg) \ + generate \ + if (!(cond)) $error(msg); \ + endgenerate + `define LOG2UP(x) ((x > 1) ? $clog2(x) : 1) `define NUM_CORES_PER_CLUSTER (`NUM_CORES / `NUM_CLUSTERS) -`define NW_BITS `LOG2UP(`NUM_WARPS) +`define NW_BITS (`LOG2UP(`NUM_WARPS)) -`define NT_BITS `LOG2UP(`NUM_THREADS) +`define NT_BITS (`LOG2UP(`NUM_THREADS)) -`define NC_BITS `LOG2UP(`NUM_CORES) +`define NC_BITS (`LOG2UP(`NUM_CORES)) + +`define NUM_GPRS 32 + +`define CSR_ADDR_SIZE 12 + +`define NUM_CSRS 1024 + +`define CSR_WIDTH 12 + +`define CSR_CYCL_L 12'hC00; +`define CSR_CYCL_H 12'hC80; +`define CSR_INST_L 12'hC02; +`define CSR_INST_H 12'hC82; `define R_INST 7'd51 `define L_INST 7'd3 @@ -115,6 +135,9 @@ // Bank Number of words in a line `define DBANK_LINE_WORDS (`DBANK_LINE_SIZE_BYTES / `DWORD_SIZE_BYTES) +// Word size in bits +`define DWORD_SIZE_BITS (`DWORD_SIZE_BYTES * 8) + // ======================= Icache Configurable Knobs ========================== // Function ID diff --git a/hw/rtl/VX_dmem_controller.v b/hw/rtl/VX_dmem_controller.v index 8e8c4adf..9da1fbf7 100644 --- a/hw/rtl/VX_dmem_controller.v +++ b/hw/rtl/VX_dmem_controller.v @@ -5,78 +5,69 @@ module VX_dmem_controller ( input wire reset, // Dram <-> Dcache - VX_gpu_dcache_dram_req_inter VX_gpu_dcache_dram_req, - VX_gpu_dcache_dram_res_inter VX_gpu_dcache_dram_res, - VX_gpu_snp_req_rsp VX_gpu_dcache_snp_req, + VX_gpu_dcache_dram_req_inter vx_gpu_dcache_dram_req, + VX_gpu_dcache_dram_rsp_inter vx_gpu_dcache_dram_res, + VX_gpu_snp_req_rsp vx_gpu_dcache_snp_req, // Dram <-> Icache - VX_gpu_dcache_dram_req_inter VX_gpu_icache_dram_req, - VX_gpu_dcache_dram_res_inter VX_gpu_icache_dram_res, - VX_gpu_snp_req_rsp VX_gpu_icache_snp_req, + VX_gpu_dcache_dram_req_inter vx_gpu_icache_dram_req, + VX_gpu_dcache_dram_rsp_inter vx_gpu_icache_dram_res, + VX_gpu_snp_req_rsp vx_gpu_icache_snp_req, // Core <-> Dcache - VX_gpu_dcache_res_inter VX_dcache_rsp, - VX_gpu_dcache_req_inter VX_dcache_req, + VX_gpu_dcache_rsp_inter vx_dcache_rsp, + VX_gpu_dcache_req_inter vx_dcache_req, // Core <-> Icache - VX_gpu_dcache_res_inter VX_icache_rsp, - VX_gpu_dcache_req_inter VX_icache_req + VX_gpu_dcache_rsp_inter vx_icache_rsp, + VX_gpu_dcache_req_inter vx_icache_req ); + VX_gpu_dcache_rsp_inter #(.NUM_REQUESTS(`DNUM_REQUESTS)) vx_dcache_rsp_smem(); + VX_gpu_dcache_req_inter #(.NUM_REQUESTS(`DNUM_REQUESTS)) vx_dcache_req_smem(); - VX_gpu_dcache_res_inter #(.NUM_REQUESTS(`DNUM_REQUESTS)) VX_dcache_rsp_smem(); - VX_gpu_dcache_req_inter #(.NUM_REQUESTS(`DNUM_REQUESTS)) VX_dcache_req_smem(); + VX_gpu_dcache_rsp_inter #(.NUM_REQUESTS(`DNUM_REQUESTS)) vx_dcache_rsp_dcache(); + VX_gpu_dcache_req_inter #(.NUM_REQUESTS(`DNUM_REQUESTS)) vx_dcache_req_dcache(); - - VX_gpu_dcache_res_inter #(.NUM_REQUESTS(`DNUM_REQUESTS)) VX_dcache_rsp_dcache(); - VX_gpu_dcache_req_inter #(.NUM_REQUESTS(`DNUM_REQUESTS)) VX_dcache_req_dcache(); - - - wire to_shm = VX_dcache_req.core_req_addr[0][31:24] == 8'hFF; - wire dcache_wants_wb = (|VX_dcache_rsp_dcache.core_wb_valid); + wire to_shm = vx_dcache_req.core_req_addr[0][31:24] == 8'hFF; + wire dcache_wants_wb = (|vx_dcache_rsp_dcache.core_wb_valid); // Dcache Request - assign VX_dcache_req_dcache.core_req_valid = VX_dcache_req.core_req_valid & {`NUM_THREADS{~to_shm}}; - assign VX_dcache_req_dcache.core_req_addr = VX_dcache_req.core_req_addr; - assign VX_dcache_req_dcache.core_req_writedata = VX_dcache_req.core_req_writedata; - assign VX_dcache_req_dcache.core_req_mem_read = VX_dcache_req.core_req_mem_read; - assign VX_dcache_req_dcache.core_req_mem_write = VX_dcache_req.core_req_mem_write; - assign VX_dcache_req_dcache.core_req_rd = VX_dcache_req.core_req_rd; - assign VX_dcache_req_dcache.core_req_wb = VX_dcache_req.core_req_wb; - assign VX_dcache_req_dcache.core_req_warp_num = VX_dcache_req.core_req_warp_num; - assign VX_dcache_req_dcache.core_req_pc = VX_dcache_req.core_req_pc; - assign VX_dcache_req_dcache.core_no_wb_slot = VX_dcache_req.core_no_wb_slot; - + assign vx_dcache_req_dcache.core_req_valid = vx_dcache_req.core_req_valid & {`NUM_THREADS{~to_shm}}; + assign vx_dcache_req_dcache.core_req_addr = vx_dcache_req.core_req_addr; + assign vx_dcache_req_dcache.core_req_writedata = vx_dcache_req.core_req_writedata; + assign vx_dcache_req_dcache.core_req_mem_read = vx_dcache_req.core_req_mem_read; + assign vx_dcache_req_dcache.core_req_mem_write = vx_dcache_req.core_req_mem_write; + assign vx_dcache_req_dcache.core_req_rd = vx_dcache_req.core_req_rd; + assign vx_dcache_req_dcache.core_req_wb = vx_dcache_req.core_req_wb; + assign vx_dcache_req_dcache.core_req_warp_num = vx_dcache_req.core_req_warp_num; + assign vx_dcache_req_dcache.core_req_pc = vx_dcache_req.core_req_pc; + assign vx_dcache_req_dcache.core_no_wb_slot = vx_dcache_req.core_no_wb_slot; // Shred Memory Request - assign VX_dcache_req_smem.core_req_valid = VX_dcache_req.core_req_valid & {`NUM_THREADS{to_shm}}; - assign VX_dcache_req_smem.core_req_addr = VX_dcache_req.core_req_addr; - assign VX_dcache_req_smem.core_req_writedata = VX_dcache_req.core_req_writedata; - assign VX_dcache_req_smem.core_req_mem_read = VX_dcache_req.core_req_mem_read; - assign VX_dcache_req_smem.core_req_mem_write = VX_dcache_req.core_req_mem_write; - assign VX_dcache_req_smem.core_req_rd = VX_dcache_req.core_req_rd; - assign VX_dcache_req_smem.core_req_wb = VX_dcache_req.core_req_wb; - assign VX_dcache_req_smem.core_req_warp_num = VX_dcache_req.core_req_warp_num; - assign VX_dcache_req_smem.core_req_pc = VX_dcache_req.core_req_pc; - assign VX_dcache_req_smem.core_no_wb_slot = VX_dcache_req.core_no_wb_slot || dcache_wants_wb; - + assign vx_dcache_req_smem.core_req_valid = vx_dcache_req.core_req_valid & {`NUM_THREADS{to_shm}}; + assign vx_dcache_req_smem.core_req_addr = vx_dcache_req.core_req_addr; + assign vx_dcache_req_smem.core_req_writedata = vx_dcache_req.core_req_writedata; + assign vx_dcache_req_smem.core_req_mem_read = vx_dcache_req.core_req_mem_read; + assign vx_dcache_req_smem.core_req_mem_write = vx_dcache_req.core_req_mem_write; + assign vx_dcache_req_smem.core_req_rd = vx_dcache_req.core_req_rd; + assign vx_dcache_req_smem.core_req_wb = vx_dcache_req.core_req_wb; + assign vx_dcache_req_smem.core_req_warp_num = vx_dcache_req.core_req_warp_num; + assign vx_dcache_req_smem.core_req_pc = vx_dcache_req.core_req_pc; + assign vx_dcache_req_smem.core_no_wb_slot = vx_dcache_req.core_no_wb_slot || dcache_wants_wb; // Dcache Response - assign VX_dcache_rsp.core_wb_valid = dcache_wants_wb ? VX_dcache_rsp_dcache.core_wb_valid : VX_dcache_rsp_smem.core_wb_valid; - assign VX_dcache_rsp.core_wb_req_rd = dcache_wants_wb ? VX_dcache_rsp_dcache.core_wb_req_rd : VX_dcache_rsp_smem.core_wb_req_rd; - assign VX_dcache_rsp.core_wb_req_wb = dcache_wants_wb ? VX_dcache_rsp_dcache.core_wb_req_wb : VX_dcache_rsp_smem.core_wb_req_wb; - assign VX_dcache_rsp.core_wb_warp_num = dcache_wants_wb ? VX_dcache_rsp_dcache.core_wb_warp_num : VX_dcache_rsp_smem.core_wb_warp_num; - assign VX_dcache_rsp.core_wb_readdata = dcache_wants_wb ? VX_dcache_rsp_dcache.core_wb_readdata : VX_dcache_rsp_smem.core_wb_readdata; - assign VX_dcache_rsp.core_wb_pc = dcache_wants_wb ? VX_dcache_rsp_dcache.core_wb_pc : VX_dcache_rsp_smem.core_wb_pc; - - assign VX_dcache_rsp.delay_req = to_shm ? VX_dcache_rsp_smem.delay_req : VX_dcache_rsp_dcache.delay_req; - - - - VX_gpu_dcache_dram_req_inter #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) VX_gpu_smem_dram_req(); - VX_gpu_dcache_dram_res_inter #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) VX_gpu_smem_dram_res(); + assign vx_dcache_rsp.core_wb_valid = dcache_wants_wb ? vx_dcache_rsp_dcache.core_wb_valid : vx_dcache_rsp_smem.core_wb_valid; + assign vx_dcache_rsp.core_wb_req_rd = dcache_wants_wb ? vx_dcache_rsp_dcache.core_wb_req_rd : vx_dcache_rsp_smem.core_wb_req_rd; + assign vx_dcache_rsp.core_wb_req_wb = dcache_wants_wb ? vx_dcache_rsp_dcache.core_wb_req_wb : vx_dcache_rsp_smem.core_wb_req_wb; + assign vx_dcache_rsp.core_wb_warp_num = dcache_wants_wb ? vx_dcache_rsp_dcache.core_wb_warp_num : vx_dcache_rsp_smem.core_wb_warp_num; + assign vx_dcache_rsp.core_wb_readdata = dcache_wants_wb ? vx_dcache_rsp_dcache.core_wb_readdata : vx_dcache_rsp_smem.core_wb_readdata; + assign vx_dcache_rsp.core_wb_pc = dcache_wants_wb ? vx_dcache_rsp_dcache.core_wb_pc : vx_dcache_rsp_smem.core_wb_pc; + assign vx_dcache_rsp.delay_req = to_shm ? vx_dcache_rsp_smem.delay_req : vx_dcache_rsp_dcache.delay_req; + VX_gpu_dcache_dram_req_inter #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) vx_gpu_smem_dram_req(); + VX_gpu_dcache_dram_rsp_inter #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) vx_gpu_smem_dram_res(); VX_cache #( .CACHE_SIZE_BYTES (`SCACHE_SIZE_BYTES), @@ -99,69 +90,67 @@ module VX_dmem_controller ( .PRFQ_STRIDE (`SPRFQ_STRIDE), .FILL_INVALIDAOR_SIZE (`SFILL_INVALIDAOR_SIZE), .SIMULATED_DRAM_LATENCY_CYCLES(`SSIMULATED_DRAM_LATENCY_CYCLES) - ) - gpu_smem - ( + ) gpu_smem ( .clk (clk), .reset (reset), // Core req - .core_req_valid (VX_dcache_req_smem.core_req_valid), - .core_req_addr (VX_dcache_req_smem.core_req_addr), - .core_req_writedata(VX_dcache_req_smem.core_req_writedata), - .core_req_mem_read (VX_dcache_req_smem.core_req_mem_read), - .core_req_mem_write(VX_dcache_req_smem.core_req_mem_write), - .core_req_rd (VX_dcache_req_smem.core_req_rd), - .core_req_wb (VX_dcache_req_smem.core_req_wb), - .core_req_warp_num (VX_dcache_req_smem.core_req_warp_num), - .core_req_pc (VX_dcache_req_smem.core_req_pc), + .core_req_valid (vx_dcache_req_smem.core_req_valid), + .core_req_mem_read (vx_dcache_req_smem.core_req_mem_read), + .core_req_mem_write(vx_dcache_req_smem.core_req_mem_write), + .core_req_addr (vx_dcache_req_smem.core_req_addr), + .core_req_writedata(vx_dcache_req_smem.core_req_writedata), + .core_req_rd (vx_dcache_req_smem.core_req_rd), + .core_req_wb (vx_dcache_req_smem.core_req_wb), + .core_req_warp_num (vx_dcache_req_smem.core_req_warp_num), + .core_req_pc (vx_dcache_req_smem.core_req_pc), // Delay Core Req - .delay_req (VX_dcache_rsp_smem.delay_req), + .delay_req (vx_dcache_rsp_smem.delay_req), // Core Cache Can't WB - .core_no_wb_slot (VX_dcache_req_smem.core_no_wb_slot), + .core_no_wb_slot (vx_dcache_req_smem.core_no_wb_slot), // Cache CWB - .core_wb_valid (VX_dcache_rsp_smem.core_wb_valid), - .core_wb_req_rd (VX_dcache_rsp_smem.core_wb_req_rd), - .core_wb_req_wb (VX_dcache_rsp_smem.core_wb_req_wb), - .core_wb_warp_num (VX_dcache_rsp_smem.core_wb_warp_num), - .core_wb_readdata (VX_dcache_rsp_smem.core_wb_readdata), - .core_wb_pc (VX_dcache_rsp_smem.core_wb_pc), - .core_wb_address (), + .core_wb_valid (vx_dcache_rsp_smem.core_wb_valid), + .core_wb_req_rd (vx_dcache_rsp_smem.core_wb_req_rd), + .core_wb_req_wb (vx_dcache_rsp_smem.core_wb_req_wb), + .core_wb_warp_num (vx_dcache_rsp_smem.core_wb_warp_num), + .core_wb_readdata (vx_dcache_rsp_smem.core_wb_readdata), + .core_wb_pc (vx_dcache_rsp_smem.core_wb_pc), + /* verilator lint_off PINCONNECTEMPTY */ + .core_wb_address (), + /* verilator lint_on PINCONNECTEMPTY */ // DRAM response - .dram_fill_rsp (VX_gpu_smem_dram_res.dram_fill_rsp), - .dram_fill_rsp_addr(VX_gpu_smem_dram_res.dram_fill_rsp_addr), - .dram_fill_rsp_data(VX_gpu_smem_dram_res.dram_fill_rsp_data), + .dram_rsp_valid (vx_gpu_smem_dram_res.dram_rsp_valid), + .dram_rsp_addr (vx_gpu_smem_dram_res.dram_rsp_addr), + .dram_rsp_data (vx_gpu_smem_dram_res.dram_rsp_data), // DRAM accept response - .dram_fill_accept (VX_gpu_smem_dram_req.dram_fill_accept), + .dram_rsp_ready (vx_gpu_smem_dram_req.dram_rsp_ready), // DRAM Req - .dram_req (VX_gpu_smem_dram_req.dram_req), - .dram_req_write (VX_gpu_smem_dram_req.dram_req_write), - .dram_req_read (VX_gpu_smem_dram_req.dram_req_read), - .dram_req_addr (VX_gpu_smem_dram_req.dram_req_addr), - .dram_req_size (VX_gpu_smem_dram_req.dram_req_size), - .dram_req_data (VX_gpu_smem_dram_req.dram_req_data), - .dram_req_delay (1), - - // Snoop Response - .dram_req_because_of_wb(VX_gpu_smem_dram_req.dram_because_of_snp), - .dram_snp_full (VX_gpu_smem_dram_req.dram_snp_full), + .dram_req_read (vx_gpu_smem_dram_req.dram_req_read), + .dram_req_write (vx_gpu_smem_dram_req.dram_req_write), + .dram_req_addr (vx_gpu_smem_dram_req.dram_req_addr), + .dram_req_data (vx_gpu_smem_dram_req.dram_req_data), + .dram_req_full (1), // Snoop Request - .snp_req (0), - .snp_req_addr (0), - .snp_req_delay (), + .snp_req_valid (0), + .snp_req_addr (0), + /* verilator lint_off PINCONNECTEMPTY */ + .snp_req_full (), + /* verilator lint_on PINCONNECTEMPTY */ // Snoop Forward - .snp_fwd (), - .snp_fwd_addr (), - .snp_fwd_delay (0) - ); + /* verilator lint_off PINCONNECTEMPTY */ + .snp_fwd_valid (), + .snp_fwd_addr (), + /* verilator lint_on PINCONNECTEMPTY */ + .snp_fwd_full (0) + ); VX_cache #( .CACHE_SIZE_BYTES (`DCACHE_SIZE_BYTES), @@ -184,72 +173,65 @@ module VX_dmem_controller ( .PRFQ_STRIDE (`DPRFQ_STRIDE), .FILL_INVALIDAOR_SIZE (`DFILL_INVALIDAOR_SIZE), .SIMULATED_DRAM_LATENCY_CYCLES(`DSIMULATED_DRAM_LATENCY_CYCLES) - ) - gpu_dcache - ( + ) gpu_dcache ( .clk (clk), .reset (reset), // Core req - .core_req_valid (VX_dcache_req_dcache.core_req_valid), - .core_req_addr (VX_dcache_req_dcache.core_req_addr), - .core_req_writedata(VX_dcache_req_dcache.core_req_writedata), - .core_req_mem_read (VX_dcache_req_dcache.core_req_mem_read), - .core_req_mem_write(VX_dcache_req_dcache.core_req_mem_write), - .core_req_rd (VX_dcache_req_dcache.core_req_rd), - .core_req_wb (VX_dcache_req_dcache.core_req_wb), - .core_req_warp_num (VX_dcache_req_dcache.core_req_warp_num), - .core_req_pc (VX_dcache_req_dcache.core_req_pc), + .core_req_valid (vx_dcache_req_dcache.core_req_valid), + .core_req_mem_read (vx_dcache_req_dcache.core_req_mem_read), + .core_req_mem_write(vx_dcache_req_dcache.core_req_mem_write), + .core_req_addr (vx_dcache_req_dcache.core_req_addr), + .core_req_writedata(vx_dcache_req_dcache.core_req_writedata), + .core_req_rd (vx_dcache_req_dcache.core_req_rd), + .core_req_wb (vx_dcache_req_dcache.core_req_wb), + .core_req_warp_num (vx_dcache_req_dcache.core_req_warp_num), + .core_req_pc (vx_dcache_req_dcache.core_req_pc), // Delay Core Req - .delay_req (VX_dcache_rsp_dcache.delay_req), + .delay_req (vx_dcache_rsp_dcache.delay_req), // Core Cache Can't WB - .core_no_wb_slot (VX_dcache_req_dcache.core_no_wb_slot), + .core_no_wb_slot (vx_dcache_req_dcache.core_no_wb_slot), // Cache CWB - .core_wb_valid (VX_dcache_rsp_dcache.core_wb_valid), - .core_wb_req_rd (VX_dcache_rsp_dcache.core_wb_req_rd), - .core_wb_req_wb (VX_dcache_rsp_dcache.core_wb_req_wb), - .core_wb_warp_num (VX_dcache_rsp_dcache.core_wb_warp_num), - .core_wb_readdata (VX_dcache_rsp_dcache.core_wb_readdata), - .core_wb_pc (VX_dcache_rsp_dcache.core_wb_pc), + .core_wb_valid (vx_dcache_rsp_dcache.core_wb_valid), + .core_wb_req_rd (vx_dcache_rsp_dcache.core_wb_req_rd), + .core_wb_req_wb (vx_dcache_rsp_dcache.core_wb_req_wb), + .core_wb_warp_num (vx_dcache_rsp_dcache.core_wb_warp_num), + .core_wb_readdata (vx_dcache_rsp_dcache.core_wb_readdata), + .core_wb_pc (vx_dcache_rsp_dcache.core_wb_pc), + /* verilator lint_off PINCONNECTEMPTY */ .core_wb_address (), + /* verilator lint_on PINCONNECTEMPTY */ // DRAM response - .dram_fill_rsp (VX_gpu_dcache_dram_res.dram_fill_rsp), - .dram_fill_rsp_addr(VX_gpu_dcache_dram_res.dram_fill_rsp_addr), - .dram_fill_rsp_data(VX_gpu_dcache_dram_res.dram_fill_rsp_data), + .dram_rsp_valid (vx_gpu_dcache_dram_res.dram_rsp_valid), + .dram_rsp_addr (vx_gpu_dcache_dram_res.dram_rsp_addr), + .dram_rsp_data (vx_gpu_dcache_dram_res.dram_rsp_data), // DRAM accept response - .dram_fill_accept (VX_gpu_dcache_dram_req.dram_fill_accept), + .dram_rsp_ready (vx_gpu_dcache_dram_req.dram_rsp_ready), // DRAM Req - .dram_req (VX_gpu_dcache_dram_req.dram_req), - .dram_req_write (VX_gpu_dcache_dram_req.dram_req_write), - .dram_req_read (VX_gpu_dcache_dram_req.dram_req_read), - .dram_req_addr (VX_gpu_dcache_dram_req.dram_req_addr), - .dram_req_size (VX_gpu_dcache_dram_req.dram_req_size), - .dram_req_data (VX_gpu_dcache_dram_req.dram_req_data), - .dram_req_delay (VX_gpu_dcache_dram_req.dram_req_delay), - - // Snoop Response - .dram_req_because_of_wb(VX_gpu_dcache_dram_req.dram_because_of_snp), - .dram_snp_full (VX_gpu_dcache_dram_req.dram_snp_full), + .dram_req_read (vx_gpu_dcache_dram_req.dram_req_read), + .dram_req_write (vx_gpu_dcache_dram_req.dram_req_write), + .dram_req_addr (vx_gpu_dcache_dram_req.dram_req_addr), + .dram_req_data (vx_gpu_dcache_dram_req.dram_req_data), + .dram_req_full (vx_gpu_dcache_dram_req.dram_req_full), // Snoop Request - .snp_req (VX_gpu_dcache_snp_req.snp_req), - .snp_req_addr (VX_gpu_dcache_snp_req.snp_req_addr), - .snp_req_delay (VX_gpu_dcache_snp_req.snp_delay), - + .snp_req_valid (vx_gpu_dcache_snp_req.snp_req_valid), + .snp_req_addr (vx_gpu_dcache_snp_req.snp_req_addr), + .snp_req_full (vx_gpu_dcache_snp_req.snp_req_full), // Snoop Forward - .snp_fwd (), - .snp_fwd_addr (), - .snp_fwd_delay (0) - ); - - + /* verilator lint_off PINCONNECTEMPTY */ + .snp_fwd_valid (), + .snp_fwd_addr (), + /* verilator lint_on PINCONNECTEMPTY */ + .snp_fwd_full (0) + ); VX_cache #( .CACHE_SIZE_BYTES (`ICACHE_SIZE_BYTES), @@ -272,71 +254,64 @@ module VX_dmem_controller ( .PRFQ_STRIDE (`IPRFQ_STRIDE), .FILL_INVALIDAOR_SIZE (`IFILL_INVALIDAOR_SIZE), .SIMULATED_DRAM_LATENCY_CYCLES(`ISIMULATED_DRAM_LATENCY_CYCLES) - ) - gpu_icache - ( - .clk (clk), - .reset (reset), + ) gpu_icache ( + .clk (clk), + .reset (reset), // Core req - .core_req_valid (VX_icache_req.core_req_valid), - .core_req_addr (VX_icache_req.core_req_addr), - .core_req_writedata(VX_icache_req.core_req_writedata), - .core_req_mem_read (VX_icache_req.core_req_mem_read), - .core_req_mem_write(VX_icache_req.core_req_mem_write), - .core_req_rd (VX_icache_req.core_req_rd), - .core_req_wb (VX_icache_req.core_req_wb), - .core_req_warp_num (VX_icache_req.core_req_warp_num), - .core_req_pc (VX_icache_req.core_req_pc), + .core_req_valid (vx_icache_req.core_req_valid), + .core_req_mem_read (vx_icache_req.core_req_mem_read), + .core_req_mem_write (vx_icache_req.core_req_mem_write), + .core_req_addr (vx_icache_req.core_req_addr), + .core_req_writedata (vx_icache_req.core_req_writedata), + .core_req_rd (vx_icache_req.core_req_rd), + .core_req_wb (vx_icache_req.core_req_wb), + .core_req_warp_num (vx_icache_req.core_req_warp_num), + .core_req_pc (vx_icache_req.core_req_pc), // Delay Core Req - .delay_req (VX_icache_rsp.delay_req), + .delay_req (vx_icache_rsp.delay_req), // Core Cache Can't WB - .core_no_wb_slot (VX_icache_req.core_no_wb_slot), + .core_no_wb_slot (vx_icache_req.core_no_wb_slot), // Cache CWB - .core_wb_valid (VX_icache_rsp.core_wb_valid), - .core_wb_req_rd (VX_icache_rsp.core_wb_req_rd), - .core_wb_req_wb (VX_icache_rsp.core_wb_req_wb), - .core_wb_warp_num (VX_icache_rsp.core_wb_warp_num), - .core_wb_readdata (VX_icache_rsp.core_wb_readdata), - .core_wb_pc (VX_icache_rsp.core_wb_pc), - .core_wb_address (), + .core_wb_valid (vx_icache_rsp.core_wb_valid), + .core_wb_req_rd (vx_icache_rsp.core_wb_req_rd), + .core_wb_req_wb (vx_icache_rsp.core_wb_req_wb), + .core_wb_warp_num (vx_icache_rsp.core_wb_warp_num), + .core_wb_readdata (vx_icache_rsp.core_wb_readdata), + .core_wb_pc (vx_icache_rsp.core_wb_pc), + /* verilator lint_off PINCONNECTEMPTY */ + .core_wb_address (), + /* verilator lint_on PINCONNECTEMPTY */ // DRAM response - .dram_fill_rsp (VX_gpu_icache_dram_res.dram_fill_rsp), - .dram_fill_rsp_addr(VX_gpu_icache_dram_res.dram_fill_rsp_addr), - .dram_fill_rsp_data(VX_gpu_icache_dram_res.dram_fill_rsp_data), + .dram_rsp_valid (vx_gpu_icache_dram_res.dram_rsp_valid), + .dram_rsp_addr (vx_gpu_icache_dram_res.dram_rsp_addr), + .dram_rsp_data (vx_gpu_icache_dram_res.dram_rsp_data), // DRAM accept response - .dram_fill_accept (VX_gpu_icache_dram_req.dram_fill_accept), + .dram_rsp_ready (vx_gpu_icache_dram_req.dram_rsp_ready), // DRAM Req - .dram_req (VX_gpu_icache_dram_req.dram_req), - .dram_req_write (VX_gpu_icache_dram_req.dram_req_write), - .dram_req_read (VX_gpu_icache_dram_req.dram_req_read), - .dram_req_addr (VX_gpu_icache_dram_req.dram_req_addr), - .dram_req_size (VX_gpu_icache_dram_req.dram_req_size), - .dram_req_data (VX_gpu_icache_dram_req.dram_req_data), - .dram_req_delay (VX_gpu_icache_dram_req.dram_req_delay), - - // Snoop Response - .dram_req_because_of_wb(VX_gpu_icache_dram_req.dram_because_of_snp), - .dram_snp_full (VX_gpu_icache_dram_req.dram_snp_full), - + .dram_req_read (vx_gpu_icache_dram_req.dram_req_read), + .dram_req_write (vx_gpu_icache_dram_req.dram_req_write), + .dram_req_addr (vx_gpu_icache_dram_req.dram_req_addr), + .dram_req_data (vx_gpu_icache_dram_req.dram_req_data), + .dram_req_full (vx_gpu_icache_dram_req.dram_req_full), // Snoop Request - .snp_req (VX_gpu_icache_snp_req.snp_req), - .snp_req_addr (VX_gpu_icache_snp_req.snp_req_addr), - .snp_req_delay (VX_gpu_icache_snp_req.snp_delay), + .snp_req_valid (vx_gpu_icache_snp_req.snp_req_valid), + .snp_req_addr (vx_gpu_icache_snp_req.snp_req_addr), + .snp_req_full (vx_gpu_icache_snp_req.snp_req_full), // Snoop Forward - .snp_fwd (), - .snp_fwd_addr (), - .snp_fwd_delay (0) - ); - - + /* verilator lint_off PINCONNECTEMPTY */ + .snp_fwd_valid (), + .snp_fwd_addr (), + /* verilator lint_on PINCONNECTEMPTY */ + .snp_fwd_full (0) + ); endmodule diff --git a/hw/rtl/VX_execute_unit.v b/hw/rtl/VX_execute_unit.v index 65442639..85f86a37 100644 --- a/hw/rtl/VX_execute_unit.v +++ b/hw/rtl/VX_execute_unit.v @@ -4,15 +4,15 @@ module VX_execute_unit ( input wire clk, input wire reset, // Request - VX_exec_unit_req_inter VX_exec_unit_req, + VX_exec_unit_req_inter vx_exec_unit_req, // Output // Writeback - VX_inst_exec_wb_inter VX_inst_exec_wb, + VX_inst_exec_wb_inter vx_inst_exec_wb, // JAL Response - VX_jal_response_inter VX_jal_rsp, + VX_jal_response_inter vx_jal_rsp, // Branch Response - VX_branch_response_inter VX_branch_rsp, + VX_branch_response_inter vx_branch_rsp, input wire no_slot_exec, output wire out_delay @@ -23,23 +23,24 @@ module VX_execute_unit ( wire[4:0] in_alu_op; wire in_rs2_src; wire[31:0] in_itype_immed; +/* verilator lint_off UNUSED */ wire[2:0] in_branch_type; +/* verilator lint_on UNUSED */ wire[19:0] in_upper_immed; wire in_jal; wire[31:0] in_jal_offset; wire[31:0] in_curr_PC; - assign in_a_reg_data = VX_exec_unit_req.a_reg_data; - assign in_b_reg_data = VX_exec_unit_req.b_reg_data; - assign in_alu_op = VX_exec_unit_req.alu_op; - assign in_rs2_src = VX_exec_unit_req.rs2_src; - assign in_itype_immed = VX_exec_unit_req.itype_immed; - assign in_branch_type = VX_exec_unit_req.branch_type; - assign in_upper_immed = VX_exec_unit_req.upper_immed; - assign in_jal = VX_exec_unit_req.jal; - assign in_jal_offset = VX_exec_unit_req.jal_offset; - assign in_curr_PC = VX_exec_unit_req.curr_PC; - + assign in_a_reg_data = vx_exec_unit_req.a_reg_data; + assign in_b_reg_data = vx_exec_unit_req.b_reg_data; + assign in_alu_op = vx_exec_unit_req.alu_op; + assign in_rs2_src = vx_exec_unit_req.rs2_src; + assign in_itype_immed = vx_exec_unit_req.itype_immed; + assign in_branch_type = vx_exec_unit_req.branch_type; + assign in_upper_immed = vx_exec_unit_req.upper_immed; + assign in_jal = vx_exec_unit_req.jal; + assign in_jal_offset = vx_exec_unit_req.jal_offset; + assign in_curr_PC = vx_exec_unit_req.curr_PC; wire[`NUM_THREADS-1:0][31:0] alu_result; wire[`NUM_THREADS-1:0] alu_stall; @@ -68,11 +69,15 @@ module VX_execute_unit ( assign out_delay = no_slot_exec || internal_stall; - +/* verilator lint_off UNUSED */ wire [$clog2(`NUM_THREADS)-1:0] jal_branch_use_index; - wire jal_branch_found_valid; - VX_generic_priority_encoder #(.N(`NUM_THREADS)) choose_alu_result( - .valids(VX_exec_unit_req.valid), + wire jal_branch_found_valid; +/* verilator lint_on UNUSED */ + + VX_generic_priority_encoder #( + .N(`NUM_THREADS) + ) choose_alu_result ( + .valids(vx_exec_unit_req.valid), .index (jal_branch_use_index), .found (jal_branch_found_valid) ); @@ -82,7 +87,7 @@ module VX_execute_unit ( reg temp_branch_dir; always @(*) begin - case(VX_exec_unit_req.branch_type) + case (vx_exec_unit_req.branch_type) `BEQ: temp_branch_dir = (branch_use_alu_result == 0) ? `TAKEN : `NOT_TAKEN; `BNE: temp_branch_dir = (branch_use_alu_result == 0) ? `NOT_TAKEN : `TAKEN; `BLT: temp_branch_dir = (branch_use_alu_result[31] == 0) ? `NOT_TAKEN : `TAKEN; @@ -99,35 +104,35 @@ module VX_execute_unit ( genvar i; generate for (i = 0; i < `NUM_THREADS; i=i+1) begin : pc_data_setup - assign duplicate_PC_data[i] = VX_exec_unit_req.PC_next; + assign duplicate_PC_data[i] = vx_exec_unit_req.PC_next; end endgenerate - // VX_inst_exec_wb_inter VX_inst_exec_wb_temp(); + // VX_inst_exec_wb_inter vx_inst_exec_wb_temp(); // JAL Response - VX_jal_response_inter VX_jal_rsp_temp(); + VX_jal_response_inter vx_jal_rsp_temp(); // Branch Response - VX_branch_response_inter VX_branch_rsp_temp(); + VX_branch_response_inter vx_branch_rsp_temp(); // Actual Writeback - assign VX_inst_exec_wb.rd = VX_exec_unit_req.rd; - assign VX_inst_exec_wb.wb = VX_exec_unit_req.wb; - assign VX_inst_exec_wb.wb_valid = VX_exec_unit_req.valid & {`NUM_THREADS{!internal_stall}}; - assign VX_inst_exec_wb.wb_warp_num = VX_exec_unit_req.warp_num; - assign VX_inst_exec_wb.alu_result = VX_exec_unit_req.jal ? duplicate_PC_data : alu_result; + assign vx_inst_exec_wb.rd = vx_exec_unit_req.rd; + assign vx_inst_exec_wb.wb = vx_exec_unit_req.wb; + assign vx_inst_exec_wb.wb_valid = vx_exec_unit_req.valid & {`NUM_THREADS{!internal_stall}}; + assign vx_inst_exec_wb.wb_warp_num = vx_exec_unit_req.warp_num; + assign vx_inst_exec_wb.alu_result = vx_exec_unit_req.jal ? duplicate_PC_data : alu_result; - assign VX_inst_exec_wb.exec_wb_pc = in_curr_PC; + assign vx_inst_exec_wb.exec_wb_pc = in_curr_PC; // Jal rsp - assign VX_jal_rsp_temp.jal = in_jal; - assign VX_jal_rsp_temp.jal_dest = $signed(in_a_reg_data[jal_branch_use_index]) + $signed(in_jal_offset); - assign VX_jal_rsp_temp.jal_warp_num = VX_exec_unit_req.warp_num; + assign vx_jal_rsp_temp.jal = in_jal; + assign vx_jal_rsp_temp.jal_dest = $signed(in_a_reg_data[jal_branch_use_index]) + $signed(in_jal_offset); + assign vx_jal_rsp_temp.jal_warp_num = vx_exec_unit_req.warp_num; // Branch rsp - assign VX_branch_rsp_temp.valid_branch = (VX_exec_unit_req.branch_type != `NO_BRANCH) && (|VX_exec_unit_req.valid); - assign VX_branch_rsp_temp.branch_dir = temp_branch_dir; - assign VX_branch_rsp_temp.branch_warp_num = VX_exec_unit_req.warp_num; - assign VX_branch_rsp_temp.branch_dest = $signed(VX_exec_unit_req.curr_PC) + ($signed(VX_exec_unit_req.itype_immed) << 1); // itype_immed = branch_offset + assign vx_branch_rsp_temp.valid_branch = (vx_exec_unit_req.branch_type != `NO_BRANCH) && (|vx_exec_unit_req.valid); + assign vx_branch_rsp_temp.branch_dir = temp_branch_dir; + assign vx_branch_rsp_temp.branch_warp_num = vx_exec_unit_req.warp_num; + assign vx_branch_rsp_temp.branch_dest = $signed(vx_exec_unit_req.curr_PC) + ($signed(vx_exec_unit_req.itype_immed) << 1); // itype_immed = branch_offset wire zero = 0; @@ -137,27 +142,31 @@ module VX_execute_unit ( // .reset(reset), // .stall(zero), // .flush(zero), - // .in ({VX_inst_exec_wb_temp.rd, VX_inst_exec_wb_temp.wb, VX_inst_exec_wb_temp.wb_valid, VX_inst_exec_wb_temp.wb_warp_num, VX_inst_exec_wb_temp.alu_result, VX_inst_exec_wb_temp.exec_wb_pc}), - // .out ({VX_inst_exec_wb.rd , VX_inst_exec_wb.wb , VX_inst_exec_wb.wb_valid , VX_inst_exec_wb.wb_warp_num , VX_inst_exec_wb.alu_result , VX_inst_exec_wb.exec_wb_pc }) + // .in ({vx_inst_exec_wb_temp.rd, vx_inst_exec_wb_temp.wb, vx_inst_exec_wb_temp.wb_valid, vx_inst_exec_wb_temp.wb_warp_num, vx_inst_exec_wb_temp.alu_result, vx_inst_exec_wb_temp.exec_wb_pc}), + // .out ({vx_inst_exec_wb.rd , vx_inst_exec_wb.wb , vx_inst_exec_wb.wb_valid , vx_inst_exec_wb.wb_warp_num , vx_inst_exec_wb.alu_result , vx_inst_exec_wb.exec_wb_pc }) // ); - VX_generic_register #(.N(33 + `NW_BITS-1 + 1)) jal_reg( + VX_generic_register #( + .N(33 + `NW_BITS-1 + 1) + ) jal_reg ( .clk (clk), .reset(reset), .stall(zero), .flush(zero), - .in ({VX_jal_rsp_temp.jal, VX_jal_rsp_temp.jal_dest, VX_jal_rsp_temp.jal_warp_num}), - .out ({VX_jal_rsp.jal , VX_jal_rsp.jal_dest , VX_jal_rsp.jal_warp_num}) - ); + .in ({vx_jal_rsp_temp.jal, vx_jal_rsp_temp.jal_dest, vx_jal_rsp_temp.jal_warp_num}), + .out ({vx_jal_rsp.jal , vx_jal_rsp.jal_dest , vx_jal_rsp.jal_warp_num}) + ); - VX_generic_register #(.N(34 + `NW_BITS-1 + 1)) branch_reg( + VX_generic_register #( + .N(34 + `NW_BITS-1 + 1) + ) branch_reg ( .clk (clk), .reset(reset), .stall(zero), .flush(zero), - .in ({VX_branch_rsp_temp.valid_branch, VX_branch_rsp_temp.branch_dir, VX_branch_rsp_temp.branch_warp_num, VX_branch_rsp_temp.branch_dest}), - .out ({VX_branch_rsp.valid_branch , VX_branch_rsp.branch_dir , VX_branch_rsp.branch_warp_num , VX_branch_rsp.branch_dest }) - ); + .in ({vx_branch_rsp_temp.valid_branch, vx_branch_rsp_temp.branch_dir, vx_branch_rsp_temp.branch_warp_num, vx_branch_rsp_temp.branch_dest}), + .out ({vx_branch_rsp.valid_branch , vx_branch_rsp.branch_dir , vx_branch_rsp.branch_warp_num , vx_branch_rsp.branch_dest }) + ); // always @(*) begin // case(in_alu_op) @@ -169,8 +178,7 @@ module VX_execute_unit ( // end - - // assign out_is_csr = VX_exec_unit_req.is_csr; - // assign out_csr_address = VX_exec_unit_req.csr_address; + // assign out_is_csr = vx_exec_unit_req.is_csr; + // assign out_csr_address = vx_exec_unit_req.csr_address; endmodule : VX_execute_unit \ No newline at end of file diff --git a/hw/rtl/VX_fetch.v b/hw/rtl/VX_fetch.v index d3134351..54a4f7ed 100644 --- a/hw/rtl/VX_fetch.v +++ b/hw/rtl/VX_fetch.v @@ -3,103 +3,103 @@ module VX_fetch ( input wire clk, input wire reset, - VX_wstall_inter VX_wstall, - VX_join_inter VX_join, + VX_wstall_inter vx_wstall, + VX_join_inter vx_join, input wire schedule_delay, input wire icache_stage_delay, input wire[`NW_BITS-1:0] icache_stage_wid, input wire[`NUM_THREADS-1:0] icache_stage_valids, output wire out_ebreak, - VX_jal_response_inter VX_jal_rsp, - VX_branch_response_inter VX_branch_rsp, + VX_jal_response_inter vx_jal_rsp, + VX_branch_response_inter vx_branch_rsp, VX_inst_meta_inter fe_inst_meta_fi, - VX_warp_ctl_inter VX_warp_ctl + VX_warp_ctl_inter vx_warp_ctl ); - wire[`NUM_THREADS-1:0] thread_mask; - wire[`NW_BITS-1:0] warp_num; - wire[31:0] warp_pc; - wire scheduled_warp; + wire[`NUM_THREADS-1:0] thread_mask; + wire[`NW_BITS-1:0] warp_num; + wire[31:0] warp_pc; + wire scheduled_warp; - wire pipe_stall; + wire pipe_stall; - // Only reason this is there is because there is a hidden assumption that decode is exactly after fetch + // Only reason this is there is because there is a hidden assumption that decode is exactly after fetch - // Locals + // Locals - assign pipe_stall = schedule_delay || icache_stage_delay; + assign pipe_stall = schedule_delay || icache_stage_delay; - VX_warp_scheduler warp_scheduler( - .clk (clk), - .reset (reset), - .stall (pipe_stall), + VX_warp_scheduler warp_scheduler( + .clk (clk), + .reset (reset), + .stall (pipe_stall), - .is_barrier (VX_warp_ctl.is_barrier), - .barrier_id (VX_warp_ctl.barrier_id), - .num_warps (VX_warp_ctl.num_warps), - .barrier_warp_num (VX_warp_ctl.warp_num), + .is_barrier (vx_warp_ctl.is_barrier), + .barrier_id (vx_warp_ctl.barrier_id), + .num_warps (vx_warp_ctl.num_warps), + .barrier_warp_num (vx_warp_ctl.warp_num), - // Wspawn - .wspawn (VX_warp_ctl.wspawn), - .wsapwn_pc (VX_warp_ctl.wspawn_pc), - .wspawn_new_active(VX_warp_ctl.wspawn_new_active), - // CTM - .ctm (VX_warp_ctl.change_mask), - .ctm_mask (VX_warp_ctl.thread_mask), - .ctm_warp_num (VX_warp_ctl.warp_num), - // WHALT - .whalt (VX_warp_ctl.ebreak), - .whalt_warp_num (VX_warp_ctl.warp_num), - // Wstall - .wstall (VX_wstall.wstall), - .wstall_warp_num (VX_wstall.warp_num), + // Wspawn + .wspawn (vx_warp_ctl.wspawn), + .wsapwn_pc (vx_warp_ctl.wspawn_pc), + .wspawn_new_active(vx_warp_ctl.wspawn_new_active), + // CTM + .ctm (vx_warp_ctl.change_mask), + .ctm_mask (vx_warp_ctl.thread_mask), + .ctm_warp_num (vx_warp_ctl.warp_num), + // WHALT + .whalt (vx_warp_ctl.ebreak), + .whalt_warp_num (vx_warp_ctl.warp_num), + // Wstall + .wstall (vx_wstall.wstall), + .wstall_warp_num (vx_wstall.warp_num), - // Lock/release Stuff - .icache_stage_valids(icache_stage_valids), - .icache_stage_wid (icache_stage_wid), + // Lock/release Stuff + .icache_stage_valids(icache_stage_valids), + .icache_stage_wid (icache_stage_wid), - // Join - .is_join (VX_join.is_join), - .join_warp_num (VX_join.join_warp_num), + // Join + .is_join (vx_join.is_join), + .join_warp_num (vx_join.join_warp_num), - // Split - .is_split (VX_warp_ctl.is_split), - .dont_split (VX_warp_ctl.dont_split), - .split_new_mask (VX_warp_ctl.split_new_mask), - .split_later_mask (VX_warp_ctl.split_later_mask), - .split_save_pc (VX_warp_ctl.split_save_pc), - .split_warp_num (VX_warp_ctl.warp_num), + // Split + .is_split (vx_warp_ctl.is_split), + .dont_split (vx_warp_ctl.dont_split), + .split_new_mask (vx_warp_ctl.split_new_mask), + .split_later_mask (vx_warp_ctl.split_later_mask), + .split_save_pc (vx_warp_ctl.split_save_pc), + .split_warp_num (vx_warp_ctl.warp_num), - // JAL - .jal (VX_jal_rsp.jal), - .jal_dest (VX_jal_rsp.jal_dest), - .jal_warp_num (VX_jal_rsp.jal_warp_num), + // JAL + .jal (vx_jal_rsp.jal), + .jal_dest (vx_jal_rsp.jal_dest), + .jal_warp_num (vx_jal_rsp.jal_warp_num), - // Branch - .branch_valid (VX_branch_rsp.valid_branch), - .branch_dir (VX_branch_rsp.branch_dir), - .branch_dest (VX_branch_rsp.branch_dest), - .branch_warp_num (VX_branch_rsp.branch_warp_num), + // Branch + .branch_valid (vx_branch_rsp.valid_branch), + .branch_dir (vx_branch_rsp.branch_dir), + .branch_dest (vx_branch_rsp.branch_dest), + .branch_warp_num (vx_branch_rsp.branch_warp_num), - // Outputs - .thread_mask (thread_mask), - .warp_num (warp_num), - .warp_pc (warp_pc), - .out_ebreak (out_ebreak), - .scheduled_warp (scheduled_warp) - ); - - assign fe_inst_meta_fi.warp_num = warp_num; - assign fe_inst_meta_fi.valid = thread_mask; - assign fe_inst_meta_fi.instruction = 32'h0; - assign fe_inst_meta_fi.inst_pc = warp_pc; - - wire start_mat_add = scheduled_warp && (warp_pc == 32'h80000ed8) && (warp_num == 0); - wire end_mat_add = scheduled_warp && (warp_pc == 32'h80000fbc) && (warp_num == 0); + // Outputs + .thread_mask (thread_mask), + .warp_num (warp_num), + .warp_pc (warp_pc), + .out_ebreak (out_ebreak), + .scheduled_warp (scheduled_warp) + ); + assign fe_inst_meta_fi.warp_num = warp_num; + assign fe_inst_meta_fi.valid = thread_mask; + assign fe_inst_meta_fi.instruction = 32'h0; + assign fe_inst_meta_fi.inst_pc = warp_pc; +/* verilator lint_off UNUSED */ + wire start_mat_add = scheduled_warp && (warp_pc == 32'h80000ed8) && (warp_num == 0); + wire end_mat_add = scheduled_warp && (warp_pc == 32'h80000fbc) && (warp_num == 0); +/* verilator lint_on UNUSED */ endmodule \ No newline at end of file diff --git a/hw/rtl/VX_front_end.v b/hw/rtl/VX_front_end.v index 61a40ef4..2fed2e3b 100644 --- a/hw/rtl/VX_front_end.v +++ b/hw/rtl/VX_front_end.v @@ -6,15 +6,15 @@ module VX_front_end ( input wire schedule_delay, - VX_warp_ctl_inter VX_warp_ctl, + VX_warp_ctl_inter vx_warp_ctl, - VX_gpu_dcache_res_inter VX_icache_rsp, - VX_gpu_dcache_req_inter VX_icache_req, + VX_gpu_dcache_rsp_inter vx_icache_rsp, + VX_gpu_dcache_req_inter vx_icache_req, - VX_jal_response_inter VX_jal_rsp, - VX_branch_response_inter VX_branch_rsp, + VX_jal_response_inter vx_jal_rsp, + VX_branch_response_inter vx_branch_rsp, - VX_frE_to_bckE_req_inter VX_bckE_req, + VX_frE_to_bckE_req_inter vx_bckE_req, output wire fetch_ebreak ); @@ -24,8 +24,8 @@ VX_inst_meta_inter fe_inst_meta_fi(); VX_inst_meta_inter fe_inst_meta_fi2(); VX_inst_meta_inter fe_inst_meta_id(); -VX_frE_to_bckE_req_inter VX_frE_to_bckE_req(); -VX_inst_meta_inter fd_inst_meta_de(); +VX_frE_to_bckE_req_inter vx_frE_to_bckE_req(); +VX_inst_meta_inter fd_inst_meta_de(); wire total_freeze = schedule_delay; wire icache_stage_delay; @@ -52,21 +52,21 @@ end assign fetch_ebreak = vortex_ebreak || terminate_sim || old_ebreak; -VX_wstall_inter VX_wstall(); -VX_join_inter VX_join(); +VX_wstall_inter vx_wstall(); +VX_join_inter vx_join(); VX_fetch vx_fetch( .clk (clk), .reset (reset), .icache_stage_wid (icache_stage_wid), .icache_stage_valids(icache_stage_valids), - .VX_wstall (VX_wstall), - .VX_join (VX_join), + .vx_wstall (vx_wstall), + .vx_join (vx_join), .schedule_delay (schedule_delay), - .VX_jal_rsp (VX_jal_rsp), - .VX_warp_ctl (VX_warp_ctl), + .vx_jal_rsp (vx_jal_rsp), + .vx_warp_ctl (vx_warp_ctl), .icache_stage_delay (icache_stage_delay), - .VX_branch_rsp (VX_branch_rsp), + .vx_branch_rsp (vx_branch_rsp), .out_ebreak (vortex_ebreak), // fetch_ebreak .fe_inst_meta_fi (fe_inst_meta_fi) ); @@ -84,7 +84,7 @@ VX_f_d_reg vx_f_i_reg( .fd_inst_meta_de(fe_inst_meta_fi2) ); -VX_icache_stage VX_icache_stage( +VX_icache_stage vx_icache_stage( .clk (clk), .reset (reset), .total_freeze (total_freeze), @@ -93,8 +93,8 @@ VX_icache_stage VX_icache_stage( .icache_stage_wid (icache_stage_wid), .fe_inst_meta_fi (fe_inst_meta_fi2), .fe_inst_meta_id (fe_inst_meta_id), - .VX_icache_rsp (VX_icache_rsp), - .VX_icache_req (VX_icache_req) + .vx_icache_rsp (vx_icache_rsp), + .vx_icache_req (vx_icache_req) ); @@ -109,9 +109,9 @@ VX_i_d_reg vx_i_d_reg( VX_decode vx_decode( .fd_inst_meta_de (fd_inst_meta_de), - .VX_frE_to_bckE_req(VX_frE_to_bckE_req), - .VX_wstall (VX_wstall), - .VX_join (VX_join), + .vx_frE_to_bckE_req(vx_frE_to_bckE_req), + .vx_wstall (vx_wstall), + .vx_join (vx_join), .terminate_sim (terminate_sim) ); @@ -122,8 +122,8 @@ VX_d_e_reg vx_d_e_reg( .reset (reset), .in_branch_stall(no_br_stall), .in_freeze (total_freeze), - .VX_frE_to_bckE_req(VX_frE_to_bckE_req), - .VX_bckE_req (VX_bckE_req) + .vx_frE_to_bckE_req(vx_frE_to_bckE_req), + .vx_bckE_req (vx_bckE_req) ); endmodule diff --git a/hw/rtl/VX_generic_queue.v b/hw/rtl/VX_generic_queue.v index dd312dbb..4b386543 100644 --- a/hw/rtl/VX_generic_queue.v +++ b/hw/rtl/VX_generic_queue.v @@ -1,10 +1,7 @@ - -module VX_generic_queue - #( - parameter DATAW = 4, - parameter SIZE = 277 - ) - ( +module VX_generic_queue #( + parameter DATAW = 4, + parameter SIZE = 277 +) ( input wire clk, input wire reset, input wire push, @@ -16,31 +13,26 @@ module VX_generic_queue output wire full ); - reg[DATAW-1:0] data[SIZE-1:0]; - reg[$clog2(SIZE)-1:0] head; - reg[$clog2(SIZE)-1:0] tail; + reg [DATAW-1:0] data [SIZE-1:0]; + reg [`LOG2UP(SIZE)-1:0] head; + reg [`LOG2UP(SIZE)-1:0] tail; - assign empty = head == tail; - assign full = head == (tail+1); + assign empty = (head == tail); + assign full = (head == (tail+1)); integer i; always @(posedge clk) begin if (reset) begin head <= 0; tail <= 0; - for (i = 0; i < SIZE; i=i+1) begin - data[i] <= 0; - end end else begin if (push && !full) begin data[tail] <= in_data; tail <= tail+1; end - if (pop && !empty) begin head <= head + 1; end - end end diff --git a/hw/rtl/VX_generic_queue_ll.v b/hw/rtl/VX_generic_queue_ll.v index e0c8a1b1..1091c8e8 100644 --- a/hw/rtl/VX_generic_queue_ll.v +++ b/hw/rtl/VX_generic_queue_ll.v @@ -1,40 +1,36 @@ -module VX_generic_queue_ll - #( - parameter DATAW = 4, - parameter SIZE = 277 - ) - ( +module VX_generic_queue_ll #( + parameter DATAW, + parameter SIZE = 16 +) ( +/* verilator lint_off UNUSED */ input wire clk, input wire reset, input wire push, - input wire [DATAW-1:0] in_data, - - input wire pop, - output wire [DATAW-1:0] out_data, + input wire pop, output wire empty, - output wire full + output wire full, +/* verilator lint_on UNUSED */ + input wire [DATAW-1:0] in_data, + output wire [DATAW-1:0] out_data ); - - /* verilator lint_off WIDTH */ - if (SIZE == 0) begin assign empty = 1; - assign out_data = 0; + assign out_data = in_data; assign full = 0; end else begin // (SIZE > 0) - + `ifdef QUEUE_FORCE_MLAB - (* syn_ramstyle = "mlab" *) reg[DATAW-1:0] data[SIZE-1:0]; + (* syn_ramstyle = "mlab" *) reg [DATAW-1:0] data [SIZE-1:0]; `else - reg[ DATAW-1:0] data[SIZE-1:0]; + reg [DATAW-1:0] data [SIZE-1:0]; `endif - reg [DATAW-1:0] head_r; - reg [$clog2(SIZE+1)-1:0] size_r; - wire reading; - wire writing; + reg [DATAW-1:0] head_r; + reg [`LOG2UP(SIZE+1)-1:0] size_r; + wire reading; + wire writing; assign reading = pop && !empty; assign writing = push && !full; @@ -65,9 +61,9 @@ module VX_generic_queue_ll end else begin // (SIZE > 1) reg [DATAW-1:0] curr_r; - reg [$clog2(SIZE)-1:0] wr_ctr_r; - reg [$clog2(SIZE)-1:0] rd_ptr_r; - reg [$clog2(SIZE)-1:0] rd_next_ptr_r; + reg [`LOG2UP(SIZE)-1:0] wr_ctr_r; + reg [`LOG2UP(SIZE)-1:0] rd_ptr_r; + reg [`LOG2UP(SIZE)-1:0] rd_next_ptr_r; reg empty_r; reg full_r; reg bypass_r; @@ -106,7 +102,7 @@ module VX_generic_queue_ll data[wr_ctr_r] <= in_data; end end - + always @(posedge clk) begin if (reset) begin curr_r <= 0; @@ -135,7 +131,5 @@ module VX_generic_queue_ll assign full = full_r; end end - - /* verilator lint_on WIDTH */ - + endmodule \ No newline at end of file diff --git a/hw/rtl/VX_generic_register.v b/hw/rtl/VX_generic_register.v index b960fa8c..a5b2b6af 100644 --- a/hw/rtl/VX_generic_register.v +++ b/hw/rtl/VX_generic_register.v @@ -1,24 +1,24 @@ +module VX_generic_register #( + parameter N, + parameter PassThru = 0 +) ( +/* verilator lint_off UNUSED */ + input wire clk, + input wire reset, + input wire stall, + input wire flush, +/* verilator lint_on UNUSED */ + input wire[N-1:0] in, + output wire[N-1:0] out +); -module VX_generic_register - #( parameter N = 1, parameter Valid = 1) - ( - input wire clk, - input wire reset, - input wire stall, - input wire flush, - input wire[(N-1):0] in, - output wire[(N-1):0] out - ); - - if (Valid == 0) begin - + if (PassThru) begin assign out = in; - end else begin - reg[(N-1):0] value; + reg [(N-1):0] value; - always @(posedge clk or posedge reset) begin + always @(posedge clk) begin if (reset) begin value <= 0; end else if (flush) begin @@ -29,7 +29,6 @@ module VX_generic_register end assign out = value; - end endmodule \ No newline at end of file diff --git a/hw/rtl/VX_gpgpu_inst.v b/hw/rtl/VX_gpgpu_inst.v index 721932bf..5de423c9 100644 --- a/hw/rtl/VX_gpgpu_inst.v +++ b/hw/rtl/VX_gpgpu_inst.v @@ -2,56 +2,57 @@ module VX_gpgpu_inst ( // Input - VX_gpu_inst_req_inter VX_gpu_inst_req, + VX_gpu_inst_req_inter vx_gpu_inst_req, // Output - VX_warp_ctl_inter VX_warp_ctl + VX_warp_ctl_inter vx_warp_ctl ); - - - wire[`NUM_THREADS-1:0] curr_valids = VX_gpu_inst_req.valid; - wire is_split = (VX_gpu_inst_req.is_split); + wire[`NUM_THREADS-1:0] curr_valids = vx_gpu_inst_req.valid; + wire is_split = (vx_gpu_inst_req.is_split); wire[`NUM_THREADS-1:0] tmc_new_mask; - wire all_threads = `NUM_THREADS < VX_gpu_inst_req.a_reg_data[0]; + wire all_threads = `NUM_THREADS < vx_gpu_inst_req.a_reg_data[0]; + genvar curr_t; generate for (curr_t = 0; curr_t < `NUM_THREADS; curr_t=curr_t+1) begin : tmc_new_mask_init - assign tmc_new_mask[curr_t] = all_threads ? 1 : curr_t < VX_gpu_inst_req.a_reg_data[0]; + assign tmc_new_mask[curr_t] = all_threads ? 1 : curr_t < vx_gpu_inst_req.a_reg_data[0]; end endgenerate wire valid_inst = (|curr_valids); - assign VX_warp_ctl.warp_num = VX_gpu_inst_req.warp_num; - assign VX_warp_ctl.change_mask = (VX_gpu_inst_req.is_tmc) && valid_inst; - assign VX_warp_ctl.thread_mask = VX_gpu_inst_req.is_tmc ? tmc_new_mask : 0; + assign vx_warp_ctl.warp_num = vx_gpu_inst_req.warp_num; + assign vx_warp_ctl.change_mask = (vx_gpu_inst_req.is_tmc) && valid_inst; + assign vx_warp_ctl.thread_mask = vx_gpu_inst_req.is_tmc ? tmc_new_mask : 0; - // assign VX_warp_ctl.ebreak = (VX_gpu_inst_req.a_reg_data[0] == 0) && valid_inst; - assign VX_warp_ctl.ebreak = VX_warp_ctl.change_mask && (VX_warp_ctl.thread_mask == 0); + // assign vx_warp_ctl.ebreak = (vx_gpu_inst_req.a_reg_data[0] == 0) && valid_inst; + assign vx_warp_ctl.ebreak = vx_warp_ctl.change_mask && (vx_warp_ctl.thread_mask == 0); - - wire wspawn = VX_gpu_inst_req.is_wspawn; - wire[31:0] wspawn_pc = VX_gpu_inst_req.rd2; - wire all_active = `NUM_WARPS < VX_gpu_inst_req.a_reg_data[0]; + wire wspawn = vx_gpu_inst_req.is_wspawn; + wire[31:0] wspawn_pc = vx_gpu_inst_req.rd2; + wire all_active = `NUM_WARPS < vx_gpu_inst_req.a_reg_data[0]; wire[`NUM_WARPS-1:0] wspawn_new_active; + genvar curr_w; generate for (curr_w = 0; curr_w < `NUM_WARPS; curr_w=curr_w+1) begin : wspawn_new_active_init - assign wspawn_new_active[curr_w] = all_active ? 1 : curr_w < VX_gpu_inst_req.a_reg_data[0]; + assign wspawn_new_active[curr_w] = all_active ? 1 : curr_w < vx_gpu_inst_req.a_reg_data[0]; end endgenerate + assign vx_warp_ctl.is_barrier = vx_gpu_inst_req.is_barrier && valid_inst; + assign vx_warp_ctl.barrier_id = vx_gpu_inst_req.a_reg_data[0]; - assign VX_warp_ctl.is_barrier = VX_gpu_inst_req.is_barrier && valid_inst; - assign VX_warp_ctl.barrier_id = VX_gpu_inst_req.a_reg_data[0]; +/* verilator lint_off UNUSED */ + wire[31:0] num_warps_m1 = vx_gpu_inst_req.rd2 - 1; +/* verilator lint_on UNUSED */ - wire[31:0] num_warps_m1 = VX_gpu_inst_req.rd2 - 1; - assign VX_warp_ctl.num_warps = num_warps_m1[$clog2(`NUM_WARPS):0]; + assign vx_warp_ctl.num_warps = num_warps_m1[$clog2(`NUM_WARPS):0]; - assign VX_warp_ctl.wspawn = wspawn; - assign VX_warp_ctl.wspawn_pc = wspawn_pc; - assign VX_warp_ctl.wspawn_new_active = wspawn_new_active; + assign vx_warp_ctl.wspawn = wspawn; + assign vx_warp_ctl.wspawn_pc = wspawn_pc; + assign vx_warp_ctl.wspawn_new_active = wspawn_new_active; wire[`NUM_THREADS-1:0] split_new_use_mask; wire[`NUM_THREADS-1:0] split_new_later_mask; @@ -60,7 +61,7 @@ module VX_gpgpu_inst ( genvar curr_s_t; generate for (curr_s_t = 0; curr_s_t < `NUM_THREADS; curr_s_t=curr_s_t+1) begin : masks_init - wire curr_bool = (VX_gpu_inst_req.a_reg_data[curr_s_t] == 32'b1); + wire curr_bool = (vx_gpu_inst_req.a_reg_data[curr_s_t] == 32'b1); assign split_new_use_mask[curr_s_t] = curr_valids[curr_s_t] & (curr_bool); assign split_new_later_mask[curr_s_t] = curr_valids[curr_s_t] & (!curr_bool); @@ -69,23 +70,24 @@ module VX_gpgpu_inst ( wire[$clog2(`NUM_THREADS):0] num_valids; - VX_countones #(.N(`NUM_THREADS)) valids_counter ( + VX_countones #( + .N(`NUM_THREADS) + ) valids_counter ( .valids(curr_valids), .count (num_valids) - ); + ); // wire[`NW_BITS-1:0] num_valids = $countones(curr_valids); - - assign VX_warp_ctl.is_split = is_split && (num_valids > 1); - assign VX_warp_ctl.dont_split = VX_warp_ctl.is_split && ((split_new_use_mask == 0) || (split_new_use_mask == {`NUM_THREADS{1'b1}})); - assign VX_warp_ctl.split_new_mask = split_new_use_mask; - assign VX_warp_ctl.split_later_mask = split_new_later_mask; - assign VX_warp_ctl.split_save_pc = VX_gpu_inst_req.pc_next; - assign VX_warp_ctl.split_warp_num = VX_gpu_inst_req.warp_num; + assign vx_warp_ctl.is_split = is_split && (num_valids > 1); + assign vx_warp_ctl.dont_split = vx_warp_ctl.is_split && ((split_new_use_mask == 0) || (split_new_use_mask == {`NUM_THREADS{1'b1}})); + assign vx_warp_ctl.split_new_mask = split_new_use_mask; + assign vx_warp_ctl.split_later_mask = split_new_later_mask; + assign vx_warp_ctl.split_save_pc = vx_gpu_inst_req.pc_next; + assign vx_warp_ctl.split_warp_num = vx_gpu_inst_req.warp_num; - // VX_gpu_inst_req.is_wspawn - // VX_gpu_inst_req.is_split - // VX_gpu_inst_req.is_barrier + // vx_gpu_inst_req.is_wspawn + // vx_gpu_inst_req.is_split + // vx_gpu_inst_req.is_barrier endmodule \ No newline at end of file diff --git a/hw/rtl/VX_gpr.v b/hw/rtl/VX_gpr.v index 23e56d35..51a26187 100644 --- a/hw/rtl/VX_gpr.v +++ b/hw/rtl/VX_gpr.v @@ -1,168 +1,150 @@ - `include "VX_define.vh" module VX_gpr ( - input wire clk, - input wire reset, - input wire valid_write_request, - VX_gpr_read_inter VX_gpr_read, - VX_wb_inter VX_writeback_inter, + input wire clk, + input wire reset, + input wire valid_write_request, + VX_gpr_read_inter vx_gpr_read, + VX_wb_inter vx_writeback_inter, - output reg[`NUM_THREADS-1:0][31:0] out_a_reg_data, - output reg[`NUM_THREADS-1:0][31:0] out_b_reg_data + output reg[`NUM_THREADS-1:0][`NUM_GPRS-1:0] out_a_reg_data, + output reg[`NUM_THREADS-1:0][`NUM_GPRS-1:0] out_b_reg_data ); - - - wire write_enable; - `ifndef ASIC - assign write_enable = valid_write_request && ((VX_writeback_inter.wb != 0)) && (VX_writeback_inter.rd != 0); + assign write_enable = valid_write_request && ((vx_writeback_inter.wb != 0)) && (vx_writeback_inter.rd != 0); byte_enabled_simple_dual_port_ram first_ram( .we (write_enable), .clk (clk), .reset (reset), - .waddr (VX_writeback_inter.rd), - .raddr1(VX_gpr_read.rs1), - .raddr2(VX_gpr_read.rs2), - .be (VX_writeback_inter.wb_valid), - .wdata (VX_writeback_inter.write_data), + .waddr (vx_writeback_inter.rd), + .raddr1(vx_gpr_read.rs1), + .raddr2(vx_gpr_read.rs2), + .be (vx_writeback_inter.wb_valid), + .wdata (vx_writeback_inter.write_data), .q1 (out_a_reg_data), .q2 (out_b_reg_data) ); - `else - - assign write_enable = valid_write_request && ((VX_writeback_inter.wb != 0)); - - - wire going_to_write = write_enable & (|VX_writeback_inter.wb_valid); - - - wire[`NUM_THREADS-1:0][31:0] write_bit_mask; + assign write_enable = valid_write_request && ((vx_writeback_inter.wb != 0)); + wire going_to_write = write_enable & (|vx_writeback_inter.wb_valid); + wire[`NUM_THREADS-1:0][`NUM_GPRS-1:0] write_bit_mask; genvar curr_t; for (curr_t = 0; curr_t < `NUM_THREADS; curr_t=curr_t+1) begin - wire local_write = write_enable & VX_writeback_inter.wb_valid[curr_t]; - assign write_bit_mask[curr_t] = {32{~local_write}}; + wire local_write = write_enable & vx_writeback_inter.wb_valid[curr_t]; + assign write_bit_mask[curr_t] = {`NUM_GPRS{~local_write}}; end - - // wire cenb = !going_to_write; wire cenb = 0; - // wire cena_1 = (VX_gpr_read.rs1 == 0); - // wire cena_2 = (VX_gpr_read.rs2 == 0); + // wire cena_1 = (vx_gpr_read.rs1 == 0); + // wire cena_2 = (vx_gpr_read.rs2 == 0); wire cena_1 = 0; wire cena_2 = 0; - wire[`NUM_THREADS-1:0][31:0] temp_a; - wire[`NUM_THREADS-1:0][31:0] temp_b; + wire[`NUM_THREADS-1:0][`NUM_GPRS-1:0] temp_a; + wire[`NUM_THREADS-1:0][`NUM_GPRS-1:0] temp_b; - - `ifndef SYN - genvar thread; - genvar curr_bit; - for (thread = 0; thread < `NUM_THREADS; thread = thread + 1) + `ifndef SYN + genvar thread; + genvar curr_bit; + for (thread = 0; thread < `NUM_THREADS; thread = thread + 1) + begin + for (curr_bit = 0; curr_bit < `NUM_GPRS; curr_bit=curr_bit+1) begin - for (curr_bit = 0; curr_bit < 32; curr_bit=curr_bit+1) - begin - assign out_a_reg_data[thread][curr_bit] = ((temp_a[thread][curr_bit] === 1'dx) || cena_1 )? 1'b0 : temp_a[thread][curr_bit]; - assign out_b_reg_data[thread][curr_bit] = ((temp_b[thread][curr_bit] === 1'dx) || cena_2) ? 1'b0 : temp_b[thread][curr_bit]; - end + assign out_a_reg_data[thread][curr_bit] = ((temp_a[thread][curr_bit] === 1'dx) || cena_1 )? 1'b0 : temp_a[thread][curr_bit]; + assign out_b_reg_data[thread][curr_bit] = ((temp_b[thread][curr_bit] === 1'dx) || cena_2) ? 1'b0 : temp_b[thread][curr_bit]; end - - `else - + end + `else assign out_a_reg_data = temp_a; assign out_b_reg_data = temp_b; + `endif - `endif - - - wire[`NUM_THREADS-1:0][31:0] to_write = (VX_writeback_inter.rd != 0) ? VX_writeback_inter.write_data : 0; + wire[`NUM_THREADS-1:0][`NUM_GPRS-1:0] to_write = (vx_writeback_inter.rd != 0) ? vx_writeback_inter.write_data : 0; genvar curr_base_thread; for (curr_base_thread = 0; curr_base_thread < 'NT; curr_base_thread=curr_base_thread+4) begin /* verilator lint_off PINCONNECTEMPTY */ rf2_32x128_wm1 first_ram ( - .CENYA(), - .AYA(), - .CENYB(), - .WENYB(), - .AYB(), - .QA(temp_a[(curr_base_thread+3):(curr_base_thread)]), - .SOA(), - .SOB(), - .CLKA(clk), - .CENA(cena_1), - .AA(VX_gpr_read.rs1[(curr_base_thread+3):(curr_base_thread)]), - .CLKB(clk), - .CENB(cenb), - .WENB(write_bit_mask[(curr_base_thread+3):(curr_base_thread)]), - .AB(VX_writeback_inter.rd[(curr_base_thread+3):(curr_base_thread)]), - .DB(to_write[(curr_base_thread+3):(curr_base_thread)]), - .EMAA(3'b011), - .EMASA(1'b0), - .EMAB(3'b011), - .TENA(1'b1), - .TCENA(1'b0), - .TAA(5'b0), - .TENB(1'b1), - .TCENB(1'b0), - .TWENB(128'b0), - .TAB(5'b0), - .TDB(128'b0), - .RET1N(1'b1), - .SIA(2'b0), - .SEA(1'b0), - .DFTRAMBYP(1'b0), - .SIB(2'b0), - .SEB(1'b0), - .COLLDISN(1'b1) + .CENYA(), + .AYA(), + .CENYB(), + .WENYB(), + .AYB(), + .QA(temp_a[(curr_base_thread+3):(curr_base_thread)]), + .SOA(), + .SOB(), + .CLKA(clk), + .CENA(cena_1), + .AA(vx_gpr_read.rs1[(curr_base_thread+3):(curr_base_thread)]), + .CLKB(clk), + .CENB(cenb), + .WENB(write_bit_mask[(curr_base_thread+3):(curr_base_thread)]), + .AB(vx_writeback_inter.rd[(curr_base_thread+3):(curr_base_thread)]), + .DB(to_write[(curr_base_thread+3):(curr_base_thread)]), + .EMAA(3'b011), + .EMASA(1'b0), + .EMAB(3'b011), + .TENA(1'b1), + .TCENA(1'b0), + .TAA(5'b0), + .TENB(1'b1), + .TCENB(1'b0), + .TWENB(128'b0), + .TAB(5'b0), + .TDB(128'b0), + .RET1N(1'b1), + .SIA(2'b0), + .SEA(1'b0), + .DFTRAMBYP(1'b0), + .SIB(2'b0), + .SEB(1'b0), + .COLLDISN(1'b1) ); /* verilator lint_on PINCONNECTEMPTY */ /* verilator lint_off PINCONNECTEMPTY */ - rf2_32x128_wm1 second_ram ( - .CENYA(), - .AYA(), - .CENYB(), - .WENYB(), - .AYB(), - .QA(temp_b[(curr_base_thread+3):(curr_base_thread)]), - .SOA(), - .SOB(), - .CLKA(clk), - .CENA(cena_2), - .AA(VX_gpr_read.rs2[(curr_base_thread+3):(curr_base_thread)]), - .CLKB(clk), - .CENB(cenb), - .WENB(write_bit_mask[(curr_base_thread+3):(curr_base_thread)]), - .AB(VX_writeback_inter.rd[(curr_base_thread+3):(curr_base_thread)]), - .DB(to_write[(curr_base_thread+3):(curr_base_thread)]), - .EMAA(3'b011), - .EMASA(1'b0), - .EMAB(3'b011), - .TENA(1'b1), - .TCENA(1'b0), - .TAA(5'b0), - .TENB(1'b1), - .TCENB(1'b0), - .TWENB(128'b0), - .TAB(5'b0), - .TDB(128'b0), - .RET1N(1'b1), - .SIA(2'b0), - .SEA(1'b0), - .DFTRAMBYP(1'b0), - .SIB(2'b0), - .SEB(1'b0), - .COLLDISN(1'b1) + rf2_`NUM_GPRSx128_wm1 second_ram ( + .CENYA(), + .AYA(), + .CENYB(), + .WENYB(), + .AYB(), + .QA(temp_b[(curr_base_thread+3):(curr_base_thread)]), + .SOA(), + .SOB(), + .CLKA(clk), + .CENA(cena_2), + .AA(vx_gpr_read.rs2[(curr_base_thread+3):(curr_base_thread)]), + .CLKB(clk), + .CENB(cenb), + .WENB(write_bit_mask[(curr_base_thread+3):(curr_base_thread)]), + .AB(vx_writeback_inter.rd[(curr_base_thread+3):(curr_base_thread)]), + .DB(to_write[(curr_base_thread+3):(curr_base_thread)]), + .EMAA(3'b011), + .EMASA(1'b0), + .EMAB(3'b011), + .TENA(1'b1), + .TCENA(1'b0), + .TAA(5'b0), + .TENB(1'b1), + .TCENB(1'b0), + .TWENB(128'b0), + .TAB(5'b0), + .TDB(128'b0), + .RET1N(1'b1), + .SIA(2'b0), + .SEA(1'b0), + .DFTRAMBYP(1'b0), + .SIB(2'b0), + .SEB(1'b0), + .COLLDISN(1'b1) ); /* verilator lint_on PINCONNECTEMPTY */ end diff --git a/hw/rtl/VX_gpr_stage.v b/hw/rtl/VX_gpr_stage.v index 71a4a3bc..d70178c7 100644 --- a/hw/rtl/VX_gpr_stage.v +++ b/hw/rtl/VX_gpr_stage.v @@ -11,108 +11,100 @@ module VX_gpr_stage ( output wire gpr_stage_delay, // inputs - // Instruction Information - VX_frE_to_bckE_req_inter VX_bckE_req, - - // WriteBack inputs - VX_wb_inter VX_writeback_inter, - - + // Instruction Information + VX_frE_to_bckE_req_inter vx_bckE_req, + // WriteBack inputs + VX_wb_inter vx_writeback_inter, // Outputs - VX_exec_unit_req_inter VX_exec_unit_req, - VX_lsu_req_inter VX_lsu_req, - VX_gpu_inst_req_inter VX_gpu_inst_req, - VX_csr_req_inter VX_csr_req + VX_exec_unit_req_inter vx_exec_unit_req, + VX_lsu_req_inter vx_lsu_req, + VX_gpu_inst_req_inter vx_gpu_inst_req, + VX_csr_req_inter vx_csr_req ); +/* verilator lint_off UNUSED */ + wire[31:0] curr_PC = vx_bckE_req.curr_PC; + wire[2:0] branchType = vx_bckE_req.branch_type; + wire is_store = (vx_bckE_req.mem_write != `NO_MEM_WRITE); + wire is_load = (vx_bckE_req.mem_read != `NO_MEM_READ); + wire jalQual = vx_bckE_req.jalQual; +/* verilator lint_on UNUSED */ + VX_gpr_read_inter vx_gpr_read(); + assign vx_gpr_read.rs1 = vx_bckE_req.rs1; + assign vx_gpr_read.rs2 = vx_bckE_req.rs2; + assign vx_gpr_read.warp_num = vx_bckE_req.warp_num; - wire[31:0] curr_PC = VX_bckE_req.curr_PC; - wire[2:0] branchType = VX_bckE_req.branch_type; +`ifndef ASIC + VX_gpr_jal_inter vx_gpr_jal(); + assign vx_gpr_jal.is_jal = vx_bckE_req.jalQual; + assign vx_gpr_jal.curr_PC = vx_bckE_req.curr_PC; +`else + VX_gpr_jal_inter vx_gpr_jal(); + assign vx_gpr_jal.is_jal = vx_exec_unit_req.jalQual; + assign vx_gpr_jal.curr_PC = vx_exec_unit_req.curr_PC; +`endif - wire is_store = (VX_bckE_req.mem_write != `NO_MEM_WRITE); - wire is_load = (VX_bckE_req.mem_read != `NO_MEM_READ); + VX_gpr_data_inter vx_gpr_datf(); + VX_gpr_wrapper vx_grp_wrapper ( + .clk (clk), + .reset (reset), + .vx_writeback_inter(vx_writeback_inter), + .vx_gpr_read (vx_gpr_read), + .vx_gpr_jal (vx_gpr_jal), - wire jalQual = VX_bckE_req.jalQual; + .out_a_reg_data (vx_gpr_datf.a_reg_data), + .out_b_reg_data (vx_gpr_datf.b_reg_data) + ); - VX_gpr_read_inter VX_gpr_read(); - assign VX_gpr_read.rs1 = VX_bckE_req.rs1; - assign VX_gpr_read.rs2 = VX_bckE_req.rs2; - assign VX_gpr_read.warp_num = VX_bckE_req.warp_num; - - `ifndef ASIC - VX_gpr_jal_inter VX_gpr_jal(); - assign VX_gpr_jal.is_jal = VX_bckE_req.jalQual; - assign VX_gpr_jal.curr_PC = VX_bckE_req.curr_PC; - `else - VX_gpr_jal_inter VX_gpr_jal(); - assign VX_gpr_jal.is_jal = VX_exec_unit_req.jalQual; - assign VX_gpr_jal.curr_PC = VX_exec_unit_req.curr_PC; - `endif - - - VX_gpr_data_inter VX_gpr_datf(); - - - VX_gpr_wrapper vx_grp_wrapper( - .clk (clk), - .reset (reset), - .VX_writeback_inter(VX_writeback_inter), - .VX_gpr_read (VX_gpr_read), - .VX_gpr_jal (VX_gpr_jal), - - .out_a_reg_data (VX_gpr_datf.a_reg_data), - .out_b_reg_data (VX_gpr_datf.b_reg_data) - ); - - // assign VX_bckE_req.is_csr = is_csr; - // assign VX_bckE_req_out.csr_mask = (VX_bckE_req.sr_immed == 1'b1) ? {27'h0, VX_bckE_req.rs1} : VX_gpr_data.a_reg_data[0]; + // assign vx_bckE_req.is_csr = is_csr; + // assign vx_bckE_req_out.csr_mask = (vx_bckE_req.sr_immed == 1'b1) ? {27'h0, vx_bckE_req.rs1} : vx_gpr_data.a_reg_data[0]; // Outputs - VX_exec_unit_req_inter VX_exec_unit_req_temp(); - VX_lsu_req_inter VX_lsu_req_temp(); - VX_gpu_inst_req_inter VX_gpu_inst_req_temp(); - VX_csr_req_inter VX_csr_req_temp(); - - VX_inst_multiplex VX_inst_mult( - .VX_bckE_req (VX_bckE_req), - .VX_gpr_data (VX_gpr_datf), - .VX_exec_unit_req(VX_exec_unit_req_temp), - .VX_lsu_req (VX_lsu_req_temp), - .VX_gpu_inst_req (VX_gpu_inst_req_temp), - .VX_csr_req (VX_csr_req_temp) - ); - - wire is_lsu = (|VX_lsu_req_temp.valid); + VX_exec_unit_req_inter vx_exec_unit_req_temp(); + VX_lsu_req_inter vx_lsu_req_temp(); + VX_gpu_inst_req_inter vx_gpu_inst_req_temp(); + VX_csr_req_inter vx_csr_req_temp(); + VX_inst_multiplex vx_inst_mult( + .vx_bckE_req (vx_bckE_req), + .vx_gpr_data (vx_gpr_datf), + .vx_exec_unit_req(vx_exec_unit_req_temp), + .vx_lsu_req (vx_lsu_req_temp), + .vx_gpu_inst_req (vx_gpu_inst_req_temp), + .vx_csr_req (vx_csr_req_temp) + ); +/* verilator lint_off UNUSED */ + wire is_lsu = (|vx_lsu_req_temp.valid); +/* verilator lint_on UNUSED */ wire stall_rest = 0; wire flush_rest = schedule_delay; - wire stall_lsu = memory_delay; wire flush_lsu = schedule_delay && !stall_lsu; wire stall_exec = exec_delay; wire flush_exec = schedule_delay && !stall_exec; - wire stall_csr = stall_gpr_csr && VX_bckE_req.is_csr && (|VX_bckE_req.valid); + wire stall_csr = stall_gpr_csr && vx_bckE_req.is_csr && (|vx_bckE_req.valid); assign gpr_stage_delay = stall_lsu || stall_exec || stall_csr; - `ifdef ASIC +`ifdef ASIC wire delayed_lsu_last_cycle; - VX_generic_register #(.N(1)) delayed_reg ( + VX_generic_register #( + .N(1) + ) delayed_reg ( .clk (clk), .reset(reset), .stall(stall_rest), .flush(stall_rest), .in (stall_lsu), .out (delayed_lsu_last_cycle) - ); - + ); wire[`NUM_THREADS-1:0][31:0] temp_store_data; wire[`NUM_THREADS-1:0][31:0] temp_base_address; // A reg data @@ -122,107 +114,120 @@ module VX_gpr_stage ( wire store_curr_real = !delayed_lsu_last_cycle && stall_lsu; - VX_generic_register #(.N(`NUM_THREADS*32*2)) lsu_data( + VX_generic_register #( + .N(`NUM_THREADS*32*2) + ) lsu_data ( .clk (clk), .reset(reset), .stall(!store_curr_real), .flush(stall_rest), .in ({real_store_data, real_base_address}), .out ({temp_store_data, temp_base_address}) - ); + ); - assign real_store_data = VX_lsu_req_temp.store_data; - assign real_base_address = VX_lsu_req_temp.base_address; + assign real_store_data = vx_lsu_req_temp.store_data; + assign real_base_address = vx_lsu_req_temp.base_address; + assign vx_lsu_req.store_data = (delayed_lsu_last_cycle) ? temp_store_data : real_store_data; + assign vx_lsu_req.base_address = (delayed_lsu_last_cycle) ? temp_base_address : real_base_address; - assign VX_lsu_req.store_data = (delayed_lsu_last_cycle) ? temp_store_data : real_store_data; - assign VX_lsu_req.base_address = (delayed_lsu_last_cycle) ? temp_base_address : real_base_address; - - - VX_generic_register #(.N(77 + `NW_BITS-1 + 1 + (`NUM_THREADS))) lsu_reg( + VX_generic_register #( + .N(77 + `NW_BITS-1 + 1 + (`NUM_THREADS)) + ) lsu_reg ( .clk (clk), .reset(reset), .stall(stall_lsu), .flush(flush_lsu), - .in ({VX_lsu_req_temp.valid, VX_lsu_req_temp.lsu_pc, VX_lsu_req_temp.warp_num, VX_lsu_req_temp.offset, VX_lsu_req_temp.mem_read, VX_lsu_req_temp.mem_write, VX_lsu_req_temp.rd, VX_lsu_req_temp.wb}), - .out ({VX_lsu_req.valid , VX_lsu_req.lsu_pc ,VX_lsu_req.warp_num , VX_lsu_req.offset , VX_lsu_req.mem_read , VX_lsu_req.mem_write , VX_lsu_req.rd , VX_lsu_req.wb }) - ); + .in ({vx_lsu_req_temp.valid, vx_lsu_req_temp.lsu_pc, vx_lsu_req_temp.warp_num, vx_lsu_req_temp.offset, vx_lsu_req_temp.mem_read, vx_lsu_req_temp.mem_write, vx_lsu_req_temp.rd, vx_lsu_req_temp.wb}), + .out ({vx_lsu_req.valid , vx_lsu_req.lsu_pc ,vx_lsu_req.warp_num , vx_lsu_req.offset , vx_lsu_req.mem_read , vx_lsu_req.mem_write , vx_lsu_req.rd , vx_lsu_req.wb }) + ); - VX_generic_register #(.N(224 + `NW_BITS-1 + 1 + (`NUM_THREADS))) exec_unit_reg( + VX_generic_register #( + .N(224 + `NW_BITS-1 + 1 + (`NUM_THREADS)) + ) exec_unit_reg ( .clk (clk), .reset(reset), .stall(stall_exec), .flush(flush_exec), - .in ({VX_exec_unit_req_temp.valid, VX_exec_unit_req_temp.warp_num, VX_exec_unit_req_temp.curr_PC, VX_exec_unit_req_temp.PC_next, VX_exec_unit_req_temp.rd, VX_exec_unit_req_temp.wb, VX_exec_unit_req_temp.alu_op, VX_exec_unit_req_temp.rs1, VX_exec_unit_req_temp.rs2, VX_exec_unit_req_temp.rs2_src, VX_exec_unit_req_temp.itype_immed, VX_exec_unit_req_temp.upper_immed, VX_exec_unit_req_temp.branch_type, VX_exec_unit_req_temp.jalQual, VX_exec_unit_req_temp.jal, VX_exec_unit_req_temp.jal_offset, VX_exec_unit_req_temp.ebreak, VX_exec_unit_req_temp.wspawn, VX_exec_unit_req_temp.is_csr, VX_exec_unit_req_temp.csr_address, VX_exec_unit_req_temp.csr_immed, VX_exec_unit_req_temp.csr_mask}), - .out ({VX_exec_unit_req.valid , VX_exec_unit_req.warp_num , VX_exec_unit_req.curr_PC , VX_exec_unit_req.PC_next , VX_exec_unit_req.rd , VX_exec_unit_req.wb , VX_exec_unit_req.alu_op , VX_exec_unit_req.rs1 , VX_exec_unit_req.rs2 , VX_exec_unit_req.rs2_src , VX_exec_unit_req.itype_immed , VX_exec_unit_req.upper_immed , VX_exec_unit_req.branch_type , VX_exec_unit_req.jalQual , VX_exec_unit_req.jal , VX_exec_unit_req.jal_offset , VX_exec_unit_req.ebreak , VX_exec_unit_req.wspawn , VX_exec_unit_req.is_csr , VX_exec_unit_req.csr_address , VX_exec_unit_req.csr_immed , VX_exec_unit_req.csr_mask }) - ); + .in ({vx_exec_unit_req_temp.valid, vx_exec_unit_req_temp.warp_num, vx_exec_unit_req_temp.curr_PC, vx_exec_unit_req_temp.PC_next, vx_exec_unit_req_temp.rd, vx_exec_unit_req_temp.wb, vx_exec_unit_req_temp.alu_op, vx_exec_unit_req_temp.rs1, vx_exec_unit_req_temp.rs2, vx_exec_unit_req_temp.rs2_src, vx_exec_unit_req_temp.itype_immed, vx_exec_unit_req_temp.upper_immed, vx_exec_unit_req_temp.branch_type, vx_exec_unit_req_temp.jalQual, vx_exec_unit_req_temp.jal, vx_exec_unit_req_temp.jal_offset, vx_exec_unit_req_temp.ebreak, vx_exec_unit_req_temp.wspawn, vx_exec_unit_req_temp.is_csr, vx_exec_unit_req_temp.csr_address, vx_exec_unit_req_temp.csr_immed, vx_exec_unit_req_temp.csr_mask}), + .out ({vx_exec_unit_req.valid , vx_exec_unit_req.warp_num , vx_exec_unit_req.curr_PC , vx_exec_unit_req.PC_next , vx_exec_unit_req.rd , vx_exec_unit_req.wb , vx_exec_unit_req.alu_op , vx_exec_unit_req.rs1 , vx_exec_unit_req.rs2 , vx_exec_unit_req.rs2_src , vx_exec_unit_req.itype_immed , vx_exec_unit_req.upper_immed , vx_exec_unit_req.branch_type , vx_exec_unit_req.jalQual , vx_exec_unit_req.jal , vx_exec_unit_req.jal_offset , vx_exec_unit_req.ebreak , vx_exec_unit_req.wspawn , vx_exec_unit_req.is_csr , vx_exec_unit_req.csr_address , vx_exec_unit_req.csr_immed , vx_exec_unit_req.csr_mask }) + ); - assign VX_exec_unit_req.a_reg_data = real_base_address; - assign VX_exec_unit_req.b_reg_data = real_store_data; + assign vx_exec_unit_req.a_reg_data = real_base_address; + assign vx_exec_unit_req.b_reg_data = real_store_data; - VX_generic_register #(.N(36 + `NW_BITS-1 + 1 + (`NUM_THREADS))) gpu_inst_reg( + VX_generic_register #( + .N(36 + `NW_BITS-1 + 1 + (`NUM_THREADS)) + ) gpu_inst_reg ( .clk (clk), .reset(reset), .stall(stall_rest), .flush(flush_rest), - .in ({VX_gpu_inst_req_temp.valid, VX_gpu_inst_req_temp.warp_num, VX_gpu_inst_req_temp.is_wspawn, VX_gpu_inst_req_temp.is_tmc, VX_gpu_inst_req_temp.is_split, VX_gpu_inst_req_temp.is_barrier, VX_gpu_inst_req_temp.pc_next}), - .out ({VX_gpu_inst_req.valid , VX_gpu_inst_req.warp_num , VX_gpu_inst_req.is_wspawn , VX_gpu_inst_req.is_tmc , VX_gpu_inst_req.is_split , VX_gpu_inst_req.is_barrier , VX_gpu_inst_req.pc_next }) - ); + .in ({vx_gpu_inst_req_temp.valid, vx_gpu_inst_req_temp.warp_num, vx_gpu_inst_req_temp.is_wspawn, vx_gpu_inst_req_temp.is_tmc, vx_gpu_inst_req_temp.is_split, vx_gpu_inst_req_temp.is_barrier, vx_gpu_inst_req_temp.pc_next}), + .out ({vx_gpu_inst_req.valid , vx_gpu_inst_req.warp_num , vx_gpu_inst_req.is_wspawn , vx_gpu_inst_req.is_tmc , vx_gpu_inst_req.is_split , vx_gpu_inst_req.is_barrier , vx_gpu_inst_req.pc_next }) + ); - assign VX_gpu_inst_req.a_reg_data = real_base_address; - assign VX_gpu_inst_req.rd2 = real_store_data; + assign vx_gpu_inst_req.a_reg_data = real_base_address; + assign vx_gpu_inst_req.rd2 = real_store_data; - VX_generic_register #(.N(`NW_BITS-1 + 1 + `NUM_THREADS + 58)) csr_reg( + VX_generic_register #( + .N(`NW_BITS-1 + 1 + `NUM_THREADS + 58) + ) csr_reg ( .clk (clk), .reset(reset), .stall(stall_gpr_csr), .flush(flush_rest), - .in ({VX_csr_req_temp.valid, VX_csr_req_temp.warp_num, VX_csr_req_temp.rd, VX_csr_req_temp.wb, VX_csr_req_temp.alu_op, VX_csr_req_temp.is_csr, VX_csr_req_temp.csr_address, VX_csr_req_temp.csr_immed, VX_csr_req_temp.csr_mask}), - .out ({VX_csr_req.valid , VX_csr_req.warp_num , VX_csr_req.rd , VX_csr_req.wb , VX_csr_req.alu_op , VX_csr_req.is_csr , VX_csr_req.csr_address , VX_csr_req.csr_immed , VX_csr_req.csr_mask }) - ); + .in ({vx_csr_req_temp.valid, vx_csr_req_temp.warp_num, vx_csr_req_temp.rd, vx_csr_req_temp.wb, vx_csr_req_temp.alu_op, vx_csr_req_temp.is_csr, vx_csr_req_temp.csr_address, vx_csr_req_temp.csr_immed, vx_csr_req_temp.csr_mask}), + .out ({vx_csr_req.valid , vx_csr_req.warp_num , vx_csr_req.rd , vx_csr_req.wb , vx_csr_req.alu_op , vx_csr_req.is_csr , vx_csr_req.csr_address , vx_csr_req.csr_immed , vx_csr_req.csr_mask }) + ); - - // assign - - `else +`else // 341 - VX_generic_register #(.N(77 + `NW_BITS-1 + 1 + 65*(`NUM_THREADS))) lsu_reg( + VX_generic_register #( + .N(77 + `NW_BITS-1 + 1 + 65*(`NUM_THREADS)) + ) lsu_reg ( .clk (clk), .reset(reset), .stall(stall_lsu), .flush(flush_lsu), - .in ({VX_lsu_req_temp.valid, VX_lsu_req_temp.lsu_pc, VX_lsu_req_temp.warp_num, VX_lsu_req_temp.store_data, VX_lsu_req_temp.base_address, VX_lsu_req_temp.offset, VX_lsu_req_temp.mem_read, VX_lsu_req_temp.mem_write, VX_lsu_req_temp.rd, VX_lsu_req_temp.wb}), - .out ({VX_lsu_req.valid , VX_lsu_req.lsu_pc , VX_lsu_req.warp_num , VX_lsu_req.store_data , VX_lsu_req.base_address , VX_lsu_req.offset , VX_lsu_req.mem_read , VX_lsu_req.mem_write , VX_lsu_req.rd , VX_lsu_req.wb }) - ); + .in ({vx_lsu_req_temp.valid, vx_lsu_req_temp.lsu_pc, vx_lsu_req_temp.warp_num, vx_lsu_req_temp.store_data, vx_lsu_req_temp.base_address, vx_lsu_req_temp.offset, vx_lsu_req_temp.mem_read, vx_lsu_req_temp.mem_write, vx_lsu_req_temp.rd, vx_lsu_req_temp.wb}), + .out ({vx_lsu_req.valid , vx_lsu_req.lsu_pc , vx_lsu_req.warp_num , vx_lsu_req.store_data , vx_lsu_req.base_address , vx_lsu_req.offset , vx_lsu_req.mem_read , vx_lsu_req.mem_write , vx_lsu_req.rd , vx_lsu_req.wb }) + ); - VX_generic_register #(.N(224 + `NW_BITS-1 + 1 + 65*(`NUM_THREADS))) exec_unit_reg( + VX_generic_register #( + .N(224 + `NW_BITS-1 + 1 + 65*(`NUM_THREADS)) + ) exec_unit_reg ( .clk (clk), .reset(reset), .stall(stall_exec), .flush(flush_exec), - .in ({VX_exec_unit_req_temp.valid, VX_exec_unit_req_temp.warp_num, VX_exec_unit_req_temp.curr_PC, VX_exec_unit_req_temp.PC_next, VX_exec_unit_req_temp.rd, VX_exec_unit_req_temp.wb, VX_exec_unit_req_temp.a_reg_data, VX_exec_unit_req_temp.b_reg_data, VX_exec_unit_req_temp.alu_op, VX_exec_unit_req_temp.rs1, VX_exec_unit_req_temp.rs2, VX_exec_unit_req_temp.rs2_src, VX_exec_unit_req_temp.itype_immed, VX_exec_unit_req_temp.upper_immed, VX_exec_unit_req_temp.branch_type, VX_exec_unit_req_temp.jalQual, VX_exec_unit_req_temp.jal, VX_exec_unit_req_temp.jal_offset, VX_exec_unit_req_temp.ebreak, VX_exec_unit_req_temp.wspawn, VX_exec_unit_req_temp.is_csr, VX_exec_unit_req_temp.csr_address, VX_exec_unit_req_temp.csr_immed, VX_exec_unit_req_temp.csr_mask}), - .out ({VX_exec_unit_req.valid , VX_exec_unit_req.warp_num , VX_exec_unit_req.curr_PC , VX_exec_unit_req.PC_next , VX_exec_unit_req.rd , VX_exec_unit_req.wb , VX_exec_unit_req.a_reg_data , VX_exec_unit_req.b_reg_data , VX_exec_unit_req.alu_op , VX_exec_unit_req.rs1 , VX_exec_unit_req.rs2 , VX_exec_unit_req.rs2_src , VX_exec_unit_req.itype_immed , VX_exec_unit_req.upper_immed , VX_exec_unit_req.branch_type , VX_exec_unit_req.jalQual , VX_exec_unit_req.jal , VX_exec_unit_req.jal_offset , VX_exec_unit_req.ebreak , VX_exec_unit_req.wspawn , VX_exec_unit_req.is_csr , VX_exec_unit_req.csr_address , VX_exec_unit_req.csr_immed , VX_exec_unit_req.csr_mask }) - ); + .in ({vx_exec_unit_req_temp.valid, vx_exec_unit_req_temp.warp_num, vx_exec_unit_req_temp.curr_PC, vx_exec_unit_req_temp.PC_next, vx_exec_unit_req_temp.rd, vx_exec_unit_req_temp.wb, vx_exec_unit_req_temp.a_reg_data, vx_exec_unit_req_temp.b_reg_data, vx_exec_unit_req_temp.alu_op, vx_exec_unit_req_temp.rs1, vx_exec_unit_req_temp.rs2, vx_exec_unit_req_temp.rs2_src, vx_exec_unit_req_temp.itype_immed, vx_exec_unit_req_temp.upper_immed, vx_exec_unit_req_temp.branch_type, vx_exec_unit_req_temp.jalQual, vx_exec_unit_req_temp.jal, vx_exec_unit_req_temp.jal_offset, vx_exec_unit_req_temp.ebreak, vx_exec_unit_req_temp.wspawn, vx_exec_unit_req_temp.is_csr, vx_exec_unit_req_temp.csr_address, vx_exec_unit_req_temp.csr_immed, vx_exec_unit_req_temp.csr_mask}), + .out ({vx_exec_unit_req.valid , vx_exec_unit_req.warp_num , vx_exec_unit_req.curr_PC , vx_exec_unit_req.PC_next , vx_exec_unit_req.rd , vx_exec_unit_req.wb , vx_exec_unit_req.a_reg_data , vx_exec_unit_req.b_reg_data , vx_exec_unit_req.alu_op , vx_exec_unit_req.rs1 , vx_exec_unit_req.rs2 , vx_exec_unit_req.rs2_src , vx_exec_unit_req.itype_immed , vx_exec_unit_req.upper_immed , vx_exec_unit_req.branch_type , vx_exec_unit_req.jalQual , vx_exec_unit_req.jal , vx_exec_unit_req.jal_offset , vx_exec_unit_req.ebreak , vx_exec_unit_req.wspawn , vx_exec_unit_req.is_csr , vx_exec_unit_req.csr_address , vx_exec_unit_req.csr_immed , vx_exec_unit_req.csr_mask }) + ); - VX_generic_register #(.N(68 + `NW_BITS-1 + 1 + 33*(`NUM_THREADS))) gpu_inst_reg( + VX_generic_register #( + .N(68 + `NW_BITS-1 + 1 + 33*(`NUM_THREADS)) + ) gpu_inst_reg ( .clk (clk), .reset(reset), .stall(stall_rest), .flush(flush_rest), - .in ({VX_gpu_inst_req_temp.valid, VX_gpu_inst_req_temp.warp_num, VX_gpu_inst_req_temp.is_wspawn, VX_gpu_inst_req_temp.is_tmc, VX_gpu_inst_req_temp.is_split, VX_gpu_inst_req_temp.is_barrier, VX_gpu_inst_req_temp.pc_next, VX_gpu_inst_req_temp.a_reg_data, VX_gpu_inst_req_temp.rd2}), - .out ({VX_gpu_inst_req.valid , VX_gpu_inst_req.warp_num , VX_gpu_inst_req.is_wspawn , VX_gpu_inst_req.is_tmc , VX_gpu_inst_req.is_split , VX_gpu_inst_req.is_barrier , VX_gpu_inst_req.pc_next , VX_gpu_inst_req.a_reg_data , VX_gpu_inst_req.rd2 }) - ); + .in ({vx_gpu_inst_req_temp.valid, vx_gpu_inst_req_temp.warp_num, vx_gpu_inst_req_temp.is_wspawn, vx_gpu_inst_req_temp.is_tmc, vx_gpu_inst_req_temp.is_split, vx_gpu_inst_req_temp.is_barrier, vx_gpu_inst_req_temp.pc_next, vx_gpu_inst_req_temp.a_reg_data, vx_gpu_inst_req_temp.rd2}), + .out ({vx_gpu_inst_req.valid , vx_gpu_inst_req.warp_num , vx_gpu_inst_req.is_wspawn , vx_gpu_inst_req.is_tmc , vx_gpu_inst_req.is_split , vx_gpu_inst_req.is_barrier , vx_gpu_inst_req.pc_next , vx_gpu_inst_req.a_reg_data , vx_gpu_inst_req.rd2 }) + ); - VX_generic_register #(.N(`NW_BITS-1 + 1 + `NUM_THREADS + 58)) csr_reg( + VX_generic_register #( + .N(`NW_BITS-1 + 1 + `NUM_THREADS + 58) + ) csr_reg ( .clk (clk), .reset(reset), .stall(stall_gpr_csr), .flush(flush_rest), - .in ({VX_csr_req_temp.valid, VX_csr_req_temp.warp_num, VX_csr_req_temp.rd, VX_csr_req_temp.wb, VX_csr_req_temp.alu_op, VX_csr_req_temp.is_csr, VX_csr_req_temp.csr_address, VX_csr_req_temp.csr_immed, VX_csr_req_temp.csr_mask}), - .out ({VX_csr_req.valid , VX_csr_req.warp_num , VX_csr_req.rd , VX_csr_req.wb , VX_csr_req.alu_op , VX_csr_req.is_csr , VX_csr_req.csr_address , VX_csr_req.csr_immed , VX_csr_req.csr_mask }) - ); + .in ({vx_csr_req_temp.valid, vx_csr_req_temp.warp_num, vx_csr_req_temp.rd, vx_csr_req_temp.wb, vx_csr_req_temp.alu_op, vx_csr_req_temp.is_csr, vx_csr_req_temp.csr_address, vx_csr_req_temp.csr_immed, vx_csr_req_temp.csr_mask}), + .out ({vx_csr_req.valid , vx_csr_req.warp_num , vx_csr_req.rd , vx_csr_req.wb , vx_csr_req.alu_op , vx_csr_req.is_csr , vx_csr_req.csr_address , vx_csr_req.csr_immed , vx_csr_req.csr_mask }) + ); - `endif +`endif endmodule : VX_gpr_stage \ No newline at end of file diff --git a/hw/rtl/VX_gpr_wrapper.v b/hw/rtl/VX_gpr_wrapper.v index a2d2a7b6..df682245 100644 --- a/hw/rtl/VX_gpr_wrapper.v +++ b/hw/rtl/VX_gpr_wrapper.v @@ -3,9 +3,9 @@ module VX_gpr_wrapper ( input wire clk, input wire reset, - VX_gpr_read_inter VX_gpr_read, - VX_wb_inter VX_writeback_inter, - VX_gpr_jal_inter VX_gpr_jal, + VX_gpr_read_inter vx_gpr_read, + VX_wb_inter vx_writeback_inter, + VX_gpr_jal_inter vx_gpr_jal, output wire[`NUM_THREADS-1:0][31:0] out_a_reg_data, output wire[`NUM_THREADS-1:0][31:0] out_b_reg_data @@ -19,28 +19,30 @@ module VX_gpr_wrapper ( genvar index; generate for (index = 0; index < `NUM_THREADS; index = index + 1) begin : jal_data_assign - assign jal_data[index] = VX_gpr_jal.curr_PC; + assign jal_data[index] = vx_gpr_jal.curr_PC; end endgenerate `ifndef ASIC - assign out_a_reg_data = (VX_gpr_jal.is_jal ? jal_data : (temp_a_reg_data[VX_gpr_read.warp_num])); - assign out_b_reg_data = (temp_b_reg_data[VX_gpr_read.warp_num]); + assign out_a_reg_data = (vx_gpr_jal.is_jal ? jal_data : (temp_a_reg_data[vx_gpr_read.warp_num])); + assign out_b_reg_data = (temp_b_reg_data[vx_gpr_read.warp_num]); `else wire zer = 0; wire[`NW_BITS-1:0] old_warp_num; - VX_generic_register #(`NW_BITS-1+1) store_wn( + VX_generic_register #( + .N(`NW_BITS-1+1) + ) store_wn ( .clk (clk), .reset(reset), .stall(zer), .flush(zer), - .in (VX_gpr_read.warp_num), + .in (vx_gpr_read.warp_num), .out (old_warp_num) - ); + ); - assign out_a_reg_data = (VX_gpr_jal.is_jal ? jal_data : (temp_a_reg_data[old_warp_num])); + assign out_a_reg_data = (vx_gpr_jal.is_jal ? jal_data : (temp_a_reg_data[old_warp_num])); assign out_b_reg_data = (temp_b_reg_data[old_warp_num]); `endif @@ -50,13 +52,13 @@ module VX_gpr_wrapper ( for (warp_index = 0; warp_index < `NUM_WARPS; warp_index = warp_index + 1) begin : warp_gprs - wire valid_write_request = warp_index == VX_writeback_inter.wb_warp_num; + wire valid_write_request = warp_index == vx_writeback_inter.wb_warp_num; VX_gpr vx_gpr( .clk (clk), .reset (reset), .valid_write_request(valid_write_request), - .VX_gpr_read (VX_gpr_read), - .VX_writeback_inter (VX_writeback_inter), + .vx_gpr_read (vx_gpr_read), + .vx_writeback_inter (vx_writeback_inter), .out_a_reg_data (temp_a_reg_data[warp_index]), .out_b_reg_data (temp_b_reg_data[warp_index]) ); @@ -65,7 +67,6 @@ module VX_gpr_wrapper ( endgenerate - endmodule diff --git a/hw/rtl/VX_icache_stage.v b/hw/rtl/VX_icache_stage.v index 555a29e7..6aa8dfa7 100644 --- a/hw/rtl/VX_icache_stage.v +++ b/hw/rtl/VX_icache_stage.v @@ -5,61 +5,56 @@ module VX_icache_stage ( input wire reset, input wire total_freeze, output wire icache_stage_delay, - output wire[`NW_BITS-1:0] icache_stage_wid, - output wire[`NUM_THREADS-1:0] icache_stage_valids, + output wire[`NW_BITS-1:0] icache_stage_wid, + output wire[`NUM_THREADS-1:0] icache_stage_valids, VX_inst_meta_inter fe_inst_meta_fi, VX_inst_meta_inter fe_inst_meta_id, - VX_gpu_dcache_res_inter VX_icache_rsp, - VX_gpu_dcache_req_inter VX_icache_req + VX_gpu_dcache_rsp_inter vx_icache_rsp, + VX_gpu_dcache_req_inter vx_icache_req ); - reg[`NUM_THREADS-1:0] threads_active[`NUM_WARPS-1:0]; + reg[`NUM_THREADS-1:0] threads_active[`NUM_WARPS-1:0]; - wire valid_inst = (|fe_inst_meta_fi.valid); + wire valid_inst = (|fe_inst_meta_fi.valid); - // Icache Request - assign VX_icache_req.core_req_valid = valid_inst && !total_freeze; - assign VX_icache_req.core_req_addr = fe_inst_meta_fi.inst_pc; - assign VX_icache_req.core_req_writedata = 32'b0; - assign VX_icache_req.core_req_mem_read = `LW_MEM_READ; - assign VX_icache_req.core_req_mem_write = `NO_MEM_WRITE; - assign VX_icache_req.core_req_rd = 5'b0; - assign VX_icache_req.core_req_wb = {1{2'b1}}; - assign VX_icache_req.core_req_warp_num = fe_inst_meta_fi.warp_num; - assign VX_icache_req.core_req_pc = fe_inst_meta_fi.inst_pc; + // Icache Request + assign vx_icache_req.core_req_valid = valid_inst && !total_freeze; + assign vx_icache_req.core_req_addr = fe_inst_meta_fi.inst_pc; + assign vx_icache_req.core_req_writedata = 32'b0; + assign vx_icache_req.core_req_mem_read = `LW_MEM_READ; + assign vx_icache_req.core_req_mem_write = `NO_MEM_WRITE; + assign vx_icache_req.core_req_rd = 5'b0; + assign vx_icache_req.core_req_wb = {1{2'b1}}; + assign vx_icache_req.core_req_warp_num = fe_inst_meta_fi.warp_num; + assign vx_icache_req.core_req_pc = fe_inst_meta_fi.inst_pc; + assign fe_inst_meta_id.instruction = vx_icache_rsp.core_wb_readdata[0][31:0]; + assign fe_inst_meta_id.inst_pc = vx_icache_rsp.core_wb_pc[0]; + assign fe_inst_meta_id.warp_num = vx_icache_rsp.core_wb_warp_num; + + assign fe_inst_meta_id.valid = vx_icache_rsp.core_wb_valid ? threads_active[vx_icache_rsp.core_wb_warp_num] : 0; - assign fe_inst_meta_id.instruction = VX_icache_rsp.core_wb_readdata[0][31:0]; - assign fe_inst_meta_id.inst_pc = VX_icache_rsp.core_wb_pc[0]; - assign fe_inst_meta_id.warp_num = VX_icache_rsp.core_wb_warp_num; - - /* verilator lint_off WIDTH */ - assign fe_inst_meta_id.valid = VX_icache_rsp.core_wb_valid ? threads_active[VX_icache_rsp.core_wb_warp_num] : 0; - /* verilator lint_off WIDTH */ + assign icache_stage_wid = fe_inst_meta_id.warp_num; + assign icache_stage_valids = fe_inst_meta_id.valid & {`NUM_THREADS{!icache_stage_delay}}; - assign icache_stage_wid = fe_inst_meta_id.warp_num; - assign icache_stage_valids = fe_inst_meta_id.valid & {`NUM_THREADS{!icache_stage_delay}}; + // Cache can't accept request + assign icache_stage_delay = vx_icache_rsp.delay_req; - // Cache can't accept request - assign icache_stage_delay = VX_icache_rsp.delay_req; + // Core can't accept response + assign vx_icache_req.core_no_wb_slot = total_freeze; - // Core can't accept response - assign VX_icache_req.core_no_wb_slot = total_freeze; - - integer curr_w; - always @(posedge clk) begin - if (reset) begin - for (curr_w = 0; curr_w < `NUM_WARPS; curr_w=curr_w+1) threads_active[curr_w] <= 0; - end else begin - if (valid_inst && !icache_stage_delay) begin - /* verilator lint_off WIDTH */ - threads_active[fe_inst_meta_fi.warp_num] <= fe_inst_meta_fi.valid; - /* verilator lint_on WIDTH */ - end + integer curr_w; + always @(posedge clk) begin + if (reset) begin + for (curr_w = 0; curr_w < `NUM_WARPS; curr_w=curr_w+1) begin + threads_active[curr_w] <= 0; + end + end else begin + if (valid_inst && !icache_stage_delay) begin + threads_active[fe_inst_meta_fi.warp_num] <= fe_inst_meta_fi.valid; end end - - + end endmodule \ No newline at end of file diff --git a/hw/rtl/VX_inst_multiplex.v b/hw/rtl/VX_inst_multiplex.v index f9bc7730..918b9a74 100644 --- a/hw/rtl/VX_inst_multiplex.v +++ b/hw/rtl/VX_inst_multiplex.v @@ -2,23 +2,23 @@ module VX_inst_multiplex ( // Inputs - VX_frE_to_bckE_req_inter VX_bckE_req, - VX_gpr_data_inter VX_gpr_data, + VX_frE_to_bckE_req_inter vx_bckE_req, + VX_gpr_data_inter vx_gpr_data, // Outputs - VX_exec_unit_req_inter VX_exec_unit_req, - VX_lsu_req_inter VX_lsu_req, - VX_gpu_inst_req_inter VX_gpu_inst_req, - VX_csr_req_inter VX_csr_req + VX_exec_unit_req_inter vx_exec_unit_req, + VX_lsu_req_inter vx_lsu_req, + VX_gpu_inst_req_inter vx_gpu_inst_req, + VX_csr_req_inter vx_csr_req ); wire[`NUM_THREADS-1:0] is_mem_mask; wire[`NUM_THREADS-1:0] is_gpu_mask; wire[`NUM_THREADS-1:0] is_csr_mask; - wire is_mem = (VX_bckE_req.mem_write != `NO_MEM_WRITE) || (VX_bckE_req.mem_read != `NO_MEM_READ); - wire is_gpu = (VX_bckE_req.is_wspawn || VX_bckE_req.is_tmc || VX_bckE_req.is_barrier || VX_bckE_req.is_split); - wire is_csr = VX_bckE_req.is_csr; + wire is_mem = (vx_bckE_req.mem_write != `NO_MEM_WRITE) || (vx_bckE_req.mem_read != `NO_MEM_READ); + wire is_gpu = (vx_bckE_req.is_wspawn || vx_bckE_req.is_tmc || vx_bckE_req.is_barrier || vx_bckE_req.is_split); + wire is_csr = vx_bckE_req.is_csr; // wire is_gpu = 0; genvar currT; @@ -31,64 +31,64 @@ module VX_inst_multiplex ( endgenerate // LSU Unit - assign VX_lsu_req.valid = VX_bckE_req.valid & is_mem_mask; - assign VX_lsu_req.warp_num = VX_bckE_req.warp_num; - assign VX_lsu_req.base_address = VX_gpr_data.a_reg_data; - assign VX_lsu_req.store_data = VX_gpr_data.b_reg_data; + assign vx_lsu_req.valid = vx_bckE_req.valid & is_mem_mask; + assign vx_lsu_req.warp_num = vx_bckE_req.warp_num; + assign vx_lsu_req.base_address = vx_gpr_data.a_reg_data; + assign vx_lsu_req.store_data = vx_gpr_data.b_reg_data; - assign VX_lsu_req.offset = VX_bckE_req.itype_immed; + assign vx_lsu_req.offset = vx_bckE_req.itype_immed; - assign VX_lsu_req.mem_read = VX_bckE_req.mem_read; - assign VX_lsu_req.mem_write = VX_bckE_req.mem_write; - assign VX_lsu_req.rd = VX_bckE_req.rd; - assign VX_lsu_req.wb = VX_bckE_req.wb; - assign VX_lsu_req.lsu_pc = VX_bckE_req.curr_PC; + assign vx_lsu_req.mem_read = vx_bckE_req.mem_read; + assign vx_lsu_req.mem_write = vx_bckE_req.mem_write; + assign vx_lsu_req.rd = vx_bckE_req.rd; + assign vx_lsu_req.wb = vx_bckE_req.wb; + assign vx_lsu_req.lsu_pc = vx_bckE_req.curr_PC; // Execute Unit - assign VX_exec_unit_req.valid = VX_bckE_req.valid & (~is_mem_mask & ~is_gpu_mask & ~is_csr_mask); - assign VX_exec_unit_req.warp_num = VX_bckE_req.warp_num; - assign VX_exec_unit_req.curr_PC = VX_bckE_req.curr_PC; - assign VX_exec_unit_req.PC_next = VX_bckE_req.PC_next; - assign VX_exec_unit_req.rd = VX_bckE_req.rd; - assign VX_exec_unit_req.wb = VX_bckE_req.wb; - assign VX_exec_unit_req.a_reg_data = VX_gpr_data.a_reg_data; - assign VX_exec_unit_req.b_reg_data = VX_gpr_data.b_reg_data; - assign VX_exec_unit_req.alu_op = VX_bckE_req.alu_op; - assign VX_exec_unit_req.rs1 = VX_bckE_req.rs1; - assign VX_exec_unit_req.rs2 = VX_bckE_req.rs2; - assign VX_exec_unit_req.rs2_src = VX_bckE_req.rs2_src; - assign VX_exec_unit_req.itype_immed = VX_bckE_req.itype_immed; - assign VX_exec_unit_req.upper_immed = VX_bckE_req.upper_immed; - assign VX_exec_unit_req.branch_type = VX_bckE_req.branch_type; - assign VX_exec_unit_req.jalQual = VX_bckE_req.jalQual; - assign VX_exec_unit_req.jal = VX_bckE_req.jal; - assign VX_exec_unit_req.jal_offset = VX_bckE_req.jal_offset; - assign VX_exec_unit_req.ebreak = VX_bckE_req.ebreak; + assign vx_exec_unit_req.valid = vx_bckE_req.valid & (~is_mem_mask & ~is_gpu_mask & ~is_csr_mask); + assign vx_exec_unit_req.warp_num = vx_bckE_req.warp_num; + assign vx_exec_unit_req.curr_PC = vx_bckE_req.curr_PC; + assign vx_exec_unit_req.PC_next = vx_bckE_req.PC_next; + assign vx_exec_unit_req.rd = vx_bckE_req.rd; + assign vx_exec_unit_req.wb = vx_bckE_req.wb; + assign vx_exec_unit_req.a_reg_data = vx_gpr_data.a_reg_data; + assign vx_exec_unit_req.b_reg_data = vx_gpr_data.b_reg_data; + assign vx_exec_unit_req.alu_op = vx_bckE_req.alu_op; + assign vx_exec_unit_req.rs1 = vx_bckE_req.rs1; + assign vx_exec_unit_req.rs2 = vx_bckE_req.rs2; + assign vx_exec_unit_req.rs2_src = vx_bckE_req.rs2_src; + assign vx_exec_unit_req.itype_immed = vx_bckE_req.itype_immed; + assign vx_exec_unit_req.upper_immed = vx_bckE_req.upper_immed; + assign vx_exec_unit_req.branch_type = vx_bckE_req.branch_type; + assign vx_exec_unit_req.jalQual = vx_bckE_req.jalQual; + assign vx_exec_unit_req.jal = vx_bckE_req.jal; + assign vx_exec_unit_req.jal_offset = vx_bckE_req.jal_offset; + assign vx_exec_unit_req.ebreak = vx_bckE_req.ebreak; // GPR Req - assign VX_gpu_inst_req.valid = VX_bckE_req.valid & is_gpu_mask; - assign VX_gpu_inst_req.warp_num = VX_bckE_req.warp_num; - assign VX_gpu_inst_req.is_wspawn = VX_bckE_req.is_wspawn; - assign VX_gpu_inst_req.is_tmc = VX_bckE_req.is_tmc; - assign VX_gpu_inst_req.is_split = VX_bckE_req.is_split; - assign VX_gpu_inst_req.is_barrier = VX_bckE_req.is_barrier; - assign VX_gpu_inst_req.a_reg_data = VX_gpr_data.a_reg_data; - assign VX_gpu_inst_req.rd2 = VX_gpr_data.b_reg_data[0]; - assign VX_gpu_inst_req.pc_next = VX_bckE_req.PC_next; + assign vx_gpu_inst_req.valid = vx_bckE_req.valid & is_gpu_mask; + assign vx_gpu_inst_req.warp_num = vx_bckE_req.warp_num; + assign vx_gpu_inst_req.is_wspawn = vx_bckE_req.is_wspawn; + assign vx_gpu_inst_req.is_tmc = vx_bckE_req.is_tmc; + assign vx_gpu_inst_req.is_split = vx_bckE_req.is_split; + assign vx_gpu_inst_req.is_barrier = vx_bckE_req.is_barrier; + assign vx_gpu_inst_req.a_reg_data = vx_gpr_data.a_reg_data; + assign vx_gpu_inst_req.rd2 = vx_gpr_data.b_reg_data[0]; + assign vx_gpu_inst_req.pc_next = vx_bckE_req.PC_next; // CSR Req - assign VX_csr_req.valid = VX_bckE_req.valid & is_csr_mask; - assign VX_csr_req.warp_num = VX_bckE_req.warp_num; - assign VX_csr_req.rd = VX_bckE_req.rd; - assign VX_csr_req.wb = VX_bckE_req.wb; - assign VX_csr_req.alu_op = VX_bckE_req.alu_op; - assign VX_csr_req.is_csr = VX_bckE_req.is_csr; - assign VX_csr_req.csr_address = VX_bckE_req.csr_address; - assign VX_csr_req.csr_immed = VX_bckE_req.csr_immed; - assign VX_csr_req.csr_mask = VX_bckE_req.csr_mask; + assign vx_csr_req.valid = vx_bckE_req.valid & is_csr_mask; + assign vx_csr_req.warp_num = vx_bckE_req.warp_num; + assign vx_csr_req.rd = vx_bckE_req.rd; + assign vx_csr_req.wb = vx_bckE_req.wb; + assign vx_csr_req.alu_op = vx_bckE_req.alu_op; + assign vx_csr_req.is_csr = vx_bckE_req.is_csr; + assign vx_csr_req.csr_address = vx_bckE_req.csr_address; + assign vx_csr_req.csr_immed = vx_bckE_req.csr_immed; + assign vx_csr_req.csr_mask = vx_bckE_req.csr_mask; endmodule diff --git a/hw/rtl/VX_lsu.v b/hw/rtl/VX_lsu.v index 7c8ec808..e6efc6f2 100644 --- a/hw/rtl/VX_lsu.v +++ b/hw/rtl/VX_lsu.v @@ -1,89 +1,87 @@ `include "VX_define.vh" module VX_lsu ( - input wire clk, - input wire reset, - input wire no_slot_mem, - VX_lsu_req_inter VX_lsu_req, + input wire clk, + input wire reset, + input wire no_slot_mem, + VX_lsu_req_inter vx_lsu_req, - // Write back to GPR - VX_inst_mem_wb_inter VX_mem_wb, - - VX_gpu_dcache_res_inter VX_dcache_rsp, - VX_gpu_dcache_req_inter VX_dcache_req, - output wire out_delay - ); + // Write back to GPR + VX_inst_mem_wb_inter vx_mem_wb, + VX_gpu_dcache_rsp_inter vx_dcache_rsp, + VX_gpu_dcache_req_inter vx_dcache_req, + output wire out_delay +); // Generate Addresses wire[`NUM_THREADS-1:0][31:0] address; - VX_lsu_addr_gen VX_lsu_addr_gen - ( - .base_address(VX_lsu_req.base_address), - .offset (VX_lsu_req.offset), - .address (address) + VX_lsu_addr_gen VX_lsu_addr_gen ( + .base_address (vx_lsu_req.base_address), + .offset (vx_lsu_req.offset), + .address (address) ); - wire[`NUM_THREADS-1:0][31:0] use_address; - wire[`NUM_THREADS-1:0][31:0] use_store_data; - wire[`NUM_THREADS-1:0] use_valid; + wire[`NUM_THREADS-1:0][31:0] use_address; + wire[`NUM_THREADS-1:0][31:0] use_store_data; + wire[`NUM_THREADS-1:0] use_valid; wire[2:0] use_mem_read; wire[2:0] use_mem_write; wire[4:0] use_rd; - wire[`NW_BITS-1:0] use_warp_num; + wire[`NW_BITS-1:0] use_warp_num; wire[1:0] use_wb; wire[31:0] use_pc; wire zero = 0; - VX_generic_register #(.N(45 + `NW_BITS-1 + 1 + `NUM_THREADS*65)) lsu_buffer( + VX_generic_register #( + .N(45 + `NW_BITS-1 + 1 + `NUM_THREADS*65) + ) lsu_buffer( .clk (clk), .reset(reset), .stall(out_delay), .flush(zero), - .in ({address , VX_lsu_req.store_data, VX_lsu_req.valid, VX_lsu_req.mem_read, VX_lsu_req.mem_write, VX_lsu_req.rd, VX_lsu_req.warp_num, VX_lsu_req.wb, VX_lsu_req.lsu_pc}), + .in ({address , vx_lsu_req.store_data, vx_lsu_req.valid, vx_lsu_req.mem_read, vx_lsu_req.mem_write, vx_lsu_req.rd, vx_lsu_req.warp_num, vx_lsu_req.wb, vx_lsu_req.lsu_pc}), .out ({use_address, use_store_data , use_valid , use_mem_read , use_mem_write , use_rd , use_warp_num , use_wb , use_pc }) - ); - + ); // Core Request - assign VX_dcache_req.core_req_valid = use_valid; - assign VX_dcache_req.core_req_addr = use_address; - assign VX_dcache_req.core_req_writedata = use_store_data; - assign VX_dcache_req.core_req_mem_read = {`NUM_THREADS{use_mem_read}}; - assign VX_dcache_req.core_req_mem_write = {`NUM_THREADS{use_mem_write}}; - assign VX_dcache_req.core_req_rd = use_rd; - assign VX_dcache_req.core_req_wb = {`NUM_THREADS{use_wb}}; - assign VX_dcache_req.core_req_warp_num = use_warp_num; - assign VX_dcache_req.core_req_pc = use_pc; + assign vx_dcache_req.core_req_valid = use_valid; + assign vx_dcache_req.core_req_addr = use_address; + assign vx_dcache_req.core_req_writedata = use_store_data; + assign vx_dcache_req.core_req_mem_read = {`NUM_THREADS{use_mem_read}}; + assign vx_dcache_req.core_req_mem_write = {`NUM_THREADS{use_mem_write}}; + assign vx_dcache_req.core_req_rd = use_rd; + assign vx_dcache_req.core_req_wb = {`NUM_THREADS{use_wb}}; + assign vx_dcache_req.core_req_warp_num = use_warp_num; + assign vx_dcache_req.core_req_pc = use_pc; // Core can't accept response - assign VX_dcache_req.core_no_wb_slot = no_slot_mem; - + assign vx_dcache_req.core_no_wb_slot = no_slot_mem; // Cache can't accept request - assign out_delay = VX_dcache_rsp.delay_req; + assign out_delay = vx_dcache_rsp.delay_req; // Core Response - assign VX_mem_wb.rd = VX_dcache_rsp.core_wb_req_rd; - assign VX_mem_wb.wb = VX_dcache_rsp.core_wb_req_wb; - assign VX_mem_wb.wb_valid = VX_dcache_rsp.core_wb_valid; - assign VX_mem_wb.wb_warp_num = VX_dcache_rsp.core_wb_warp_num; - assign VX_mem_wb.loaded_data = VX_dcache_rsp.core_wb_readdata; + assign vx_mem_wb.rd = vx_dcache_rsp.core_wb_req_rd; + assign vx_mem_wb.wb = vx_dcache_rsp.core_wb_req_wb; + assign vx_mem_wb.wb_valid = vx_dcache_rsp.core_wb_valid; + assign vx_mem_wb.wb_warp_num = vx_dcache_rsp.core_wb_warp_num; + assign vx_mem_wb.loaded_data = vx_dcache_rsp.core_wb_readdata; wire[(`LOG2UP(`NUM_THREADS))-1:0] use_pc_index; + +/* verilator lint_off UNUSED */ wire found; +/* verilator lint_on UNUSED */ + VX_generic_priority_encoder #(.N(`NUM_THREADS)) pick_first_pc( - .valids(VX_dcache_rsp.core_wb_valid), + .valids(vx_dcache_rsp.core_wb_valid), .index (use_pc_index), .found (found) ); - assign VX_mem_wb.mem_wb_pc = VX_dcache_rsp.core_wb_pc[use_pc_index]; - - - - - + assign vx_mem_wb.mem_wb_pc = vx_dcache_rsp.core_wb_pc[use_pc_index]; + endmodule // Memory diff --git a/hw/rtl/VX_scheduler.v b/hw/rtl/VX_scheduler.v index 4b50efd2..5be151f6 100644 --- a/hw/rtl/VX_scheduler.v +++ b/hw/rtl/VX_scheduler.v @@ -6,73 +6,75 @@ module VX_scheduler ( input wire memory_delay, input wire exec_delay, input wire gpr_stage_delay, - VX_frE_to_bckE_req_inter VX_bckE_req, - VX_wb_inter VX_writeback_inter, + VX_frE_to_bckE_req_inter vx_bckE_req, + VX_wb_inter vx_writeback_inter, output wire schedule_delay, output wire is_empty ); - - /* verilator lint_off WIDTH */ reg[31:0] count_valid; assign is_empty = count_valid == 0; reg[31:0][`NUM_THREADS-1:0] rename_table[`NUM_WARPS-1:0]; - wire valid_wb = (VX_writeback_inter.wb != 0) && (|VX_writeback_inter.wb_valid) && (VX_writeback_inter.rd != 0); - wire wb_inc = (VX_bckE_req.wb != 0) && (VX_bckE_req.rd != 0); + wire valid_wb = (vx_writeback_inter.wb != 0) && (|vx_writeback_inter.wb_valid) && (vx_writeback_inter.rd != 0); + wire wb_inc = (vx_bckE_req.wb != 0) && (vx_bckE_req.rd != 0); - wire rs1_rename = rename_table[VX_bckE_req.warp_num][VX_bckE_req.rs1] != 0; - wire rs2_rename = rename_table[VX_bckE_req.warp_num][VX_bckE_req.rs2] != 0; - wire rd_rename = rename_table[VX_bckE_req.warp_num][VX_bckE_req.rd ] != 0; + wire rs1_rename = rename_table[vx_bckE_req.warp_num][vx_bckE_req.rs1] != 0; + wire rs2_rename = rename_table[vx_bckE_req.warp_num][vx_bckE_req.rs2] != 0; + wire rd_rename = rename_table[vx_bckE_req.warp_num][vx_bckE_req.rd ] != 0; - wire is_store = (VX_bckE_req.mem_write != `NO_MEM_WRITE); - wire is_load = (VX_bckE_req.mem_read != `NO_MEM_READ); + wire is_store = (vx_bckE_req.mem_write != `NO_MEM_WRITE); + wire is_load = (vx_bckE_req.mem_read != `NO_MEM_READ); // classify our next instruction. wire is_mem = is_store || is_load; - wire is_gpu = (VX_bckE_req.is_wspawn || VX_bckE_req.is_tmc || VX_bckE_req.is_barrier || VX_bckE_req.is_split); - wire is_csr = VX_bckE_req.is_csr; + wire is_gpu = (vx_bckE_req.is_wspawn || vx_bckE_req.is_tmc || vx_bckE_req.is_barrier || vx_bckE_req.is_split); + wire is_csr = vx_bckE_req.is_csr; wire is_exec = !is_mem && !is_gpu && !is_csr; - // wire rs1_pass = 0; - // wire rs2_pass = 0; + wire using_rs2 = (vx_bckE_req.rs2_src == `RS2_REG) || is_store || vx_bckE_req.is_barrier || vx_bckE_req.is_wspawn; - wire using_rs2 = (VX_bckE_req.rs2_src == `RS2_REG) || is_store || VX_bckE_req.is_barrier || VX_bckE_req.is_wspawn; - - wire rs1_rename_qual = ((rs1_rename) && (VX_bckE_req.rs1 != 0)); - wire rs2_rename_qual = ((rs2_rename) && (VX_bckE_req.rs2 != 0 && using_rs2)); - wire rd_rename_qual = ((rd_rename ) && (VX_bckE_req.rd != 0)); + wire rs1_rename_qual = ((rs1_rename) && (vx_bckE_req.rs1 != 0)); + wire rs2_rename_qual = ((rs2_rename) && (vx_bckE_req.rs2 != 0 && using_rs2)); + wire rd_rename_qual = ((rd_rename ) && (vx_bckE_req.rd != 0)); wire rename_valid = rs1_rename_qual || rs2_rename_qual || rd_rename_qual; - assign schedule_delay = ((rename_valid) && (|VX_bckE_req.valid)) - || (memory_delay && is_mem) - || (gpr_stage_delay && (is_mem || is_exec)) - || (exec_delay && is_exec); + assign schedule_delay = ((rename_valid) && (|vx_bckE_req.valid)) + || (memory_delay && is_mem) + || (gpr_stage_delay && (is_mem || is_exec)) + || (exec_delay && is_exec); integer i; integer w; - always @(posedge clk or posedge reset) begin + always @(posedge clk) begin if (reset) begin - for (w = 0; w < `NUM_WARPS; w=w+1) - begin - for (i = 0; i < 32; i = i + 1) - begin - rename_table[w][i] <= 0; + for (w = 0; w < `NUM_WARPS; w=w+1) begin + for (i = 0; i < 32; i = i + 1) begin + rename_table[w][i] <= 0; end end end else begin - if (valid_wb ) rename_table[VX_writeback_inter.wb_warp_num][VX_writeback_inter.rd] <= rename_table[VX_writeback_inter.wb_warp_num][VX_writeback_inter.rd] & (~VX_writeback_inter.wb_valid); - if (!schedule_delay && wb_inc) rename_table[VX_bckE_req.warp_num ][VX_bckE_req.rd ] <= VX_bckE_req.valid; + if (valid_wb) begin + rename_table[vx_writeback_inter.wb_warp_num][vx_writeback_inter.rd] <= rename_table[vx_writeback_inter.wb_warp_num][vx_writeback_inter.rd] & (~vx_writeback_inter.wb_valid); + end + + if (!schedule_delay && wb_inc) begin + rename_table[vx_bckE_req.warp_num][vx_bckE_req.rd] <= vx_bckE_req.valid; + end - if (valid_wb && ((rename_table[VX_writeback_inter.wb_warp_num][VX_writeback_inter.rd] & (~VX_writeback_inter.wb_valid)) == 0)) count_valid = count_valid - 1; - if (!schedule_delay && wb_inc) count_valid = count_valid + 1; + if (valid_wb + && (0 == (rename_table[vx_writeback_inter.wb_warp_num][vx_writeback_inter.rd] & ~vx_writeback_inter.wb_valid))) begin + count_valid <= count_valid - 1; + end + + if (!schedule_delay && wb_inc) begin + count_valid <= count_valid + 1; + end end end - /* verilator lint_on WIDTH */ - endmodule \ No newline at end of file diff --git a/hw/rtl/VX_warp.v b/hw/rtl/VX_warp.v index 25c976ec..f04c4a8d 100644 --- a/hw/rtl/VX_warp.v +++ b/hw/rtl/VX_warp.v @@ -38,7 +38,7 @@ module VX_warp ( end - always @(posedge clk, posedge reset) begin + always @(posedge clk) begin if (remove) begin valid <= valid_zero; end else if (in_change_mask) begin @@ -69,7 +69,7 @@ module VX_warp ( assign use_PC = temp_PC; assign out_PC = temp_PC; - always @(posedge clk or posedge reset) begin + always @(posedge clk) begin if (reset) begin real_PC <= 0; end else if (in_wspawn == 1'b1) begin diff --git a/hw/rtl/VX_warp_scheduler.v b/hw/rtl/VX_warp_scheduler.v index 1a6381ea..d866c0e8 100644 --- a/hw/rtl/VX_warp_scheduler.v +++ b/hw/rtl/VX_warp_scheduler.v @@ -19,7 +19,9 @@ module VX_warp_scheduler ( input wire[`NW_BITS-1:0] whalt_warp_num, input wire is_barrier, +/* verilator lint_off UNUSED */ input wire[31:0] barrier_id, +/* verilator lint_on UNUSED */ input wire[$clog2(`NUM_WARPS):0] num_warps, input wire[`NW_BITS-1:0] barrier_warp_num, @@ -60,10 +62,7 @@ module VX_warp_scheduler ( input wire[`NUM_THREADS-1:0] icache_stage_valids ); - - /* verilator lint_off WIDTH */ wire update_use_wspawn; - wire update_visible_active; wire[(1+32+`NUM_THREADS-1):0] d[`NUM_WARPS-1:0]; @@ -72,10 +71,12 @@ module VX_warp_scheduler ( wire[31:0] join_pc; wire[`NUM_THREADS-1:0] join_tm; +/* verilator lint_off UNUSED */ wire in_wspawn = wspawn; wire in_ctm = ctm; wire in_whalt = whalt; wire in_wstall = wstall; +/* verilator lint_on UNUSED */ reg[`NUM_WARPS-1:0] warp_active; reg[`NUM_WARPS-1:0] warp_stalled; @@ -114,13 +115,12 @@ module VX_warp_scheduler ( reg didnt_split; - /* verilator lint_off UNUSED */ // wire[$clog2(`NUM_WARPS):0] num_active; /* verilator lint_on UNUSED */ integer curr_w_help; integer curr_barrier; - always @(posedge clk or posedge reset) begin + always @(posedge clk) begin if (reset) begin for (curr_barrier = 0; curr_barrier < `NUM_BARRIERS; curr_barrier=curr_barrier+1) begin barrier_stall_mask[curr_barrier] <= 0; diff --git a/hw/rtl/VX_writeback.v b/hw/rtl/VX_writeback.v index f33c8369..696cb652 100644 --- a/hw/rtl/VX_writeback.v +++ b/hw/rtl/VX_writeback.v @@ -4,61 +4,61 @@ module VX_writeback ( input wire clk, input wire reset, // Mem WB info - VX_inst_mem_wb_inter VX_mem_wb, + VX_inst_mem_wb_inter vx_mem_wb, // EXEC Unit WB info - VX_inst_exec_wb_inter VX_inst_exec_wb, + VX_inst_exec_wb_inter vx_inst_exec_wb, // CSR Unit WB info - VX_csr_wb_inter VX_csr_wb, + VX_csr_wb_inter vx_csr_wb, // Actual WB to GPR - VX_wb_inter VX_writeback_inter, + VX_wb_inter vx_writeback_inter, output wire no_slot_mem, output wire no_slot_exec, output wire no_slot_csr ); - VX_wb_inter VX_writeback_tempp(); + VX_wb_inter vx_writeback_tempp(); - wire exec_wb = (VX_inst_exec_wb.wb != 0) && (|VX_inst_exec_wb.wb_valid); - wire mem_wb = (VX_mem_wb.wb != 0) && (|VX_mem_wb.wb_valid); - wire csr_wb = (VX_csr_wb.wb != 0) && (|VX_csr_wb.valid); + wire exec_wb = (vx_inst_exec_wb.wb != 0) && (|vx_inst_exec_wb.wb_valid); + wire mem_wb = (vx_mem_wb.wb != 0) && (|vx_mem_wb.wb_valid); + wire csr_wb = (vx_csr_wb.wb != 0) && (|vx_csr_wb.valid); assign no_slot_mem = mem_wb && (exec_wb || csr_wb); assign no_slot_csr = csr_wb && (exec_wb); assign no_slot_exec = 0; - assign VX_writeback_tempp.write_data = exec_wb ? VX_inst_exec_wb.alu_result : - csr_wb ? VX_csr_wb.csr_result : - mem_wb ? VX_mem_wb.loaded_data : + assign vx_writeback_tempp.write_data = exec_wb ? vx_inst_exec_wb.alu_result : + csr_wb ? vx_csr_wb.csr_result : + mem_wb ? vx_mem_wb.loaded_data : 0; - assign VX_writeback_tempp.wb_valid = exec_wb ? VX_inst_exec_wb.wb_valid : - csr_wb ? VX_csr_wb.valid : - mem_wb ? VX_mem_wb.wb_valid : + assign vx_writeback_tempp.wb_valid = exec_wb ? vx_inst_exec_wb.wb_valid : + csr_wb ? vx_csr_wb.valid : + mem_wb ? vx_mem_wb.wb_valid : 0; - assign VX_writeback_tempp.rd = exec_wb ? VX_inst_exec_wb.rd : - csr_wb ? VX_csr_wb.rd : - mem_wb ? VX_mem_wb.rd : + assign vx_writeback_tempp.rd = exec_wb ? vx_inst_exec_wb.rd : + csr_wb ? vx_csr_wb.rd : + mem_wb ? vx_mem_wb.rd : 0; - assign VX_writeback_tempp.wb = exec_wb ? VX_inst_exec_wb.wb : - csr_wb ? VX_csr_wb.wb : - mem_wb ? VX_mem_wb.wb : + assign vx_writeback_tempp.wb = exec_wb ? vx_inst_exec_wb.wb : + csr_wb ? vx_csr_wb.wb : + mem_wb ? vx_mem_wb.wb : 0; - assign VX_writeback_tempp.wb_warp_num = exec_wb ? VX_inst_exec_wb.wb_warp_num : - csr_wb ? VX_csr_wb.warp_num : - mem_wb ? VX_mem_wb.wb_warp_num : + assign vx_writeback_tempp.wb_warp_num = exec_wb ? vx_inst_exec_wb.wb_warp_num : + csr_wb ? vx_csr_wb.warp_num : + mem_wb ? vx_mem_wb.wb_warp_num : 0; - assign VX_writeback_tempp.wb_pc = exec_wb ? VX_inst_exec_wb.exec_wb_pc : + assign vx_writeback_tempp.wb_pc = exec_wb ? vx_inst_exec_wb.exec_wb_pc : csr_wb ? 32'hdeadbeef : - mem_wb ? VX_mem_wb.mem_wb_pc : + mem_wb ? vx_mem_wb.mem_wb_pc : 32'hdeadbeef; @@ -71,19 +71,19 @@ module VX_writeback ( .reset(reset), .stall(zero), .flush(zero), - .in ({VX_writeback_tempp.write_data, VX_writeback_tempp.wb_valid, VX_writeback_tempp.rd, VX_writeback_tempp.wb, VX_writeback_tempp.wb_warp_num, VX_writeback_tempp.wb_pc}), - .out ({use_wb_data , VX_writeback_inter.wb_valid, VX_writeback_inter.rd, VX_writeback_inter.wb, VX_writeback_inter.wb_warp_num, VX_writeback_inter.wb_pc}) + .in ({vx_writeback_tempp.write_data, vx_writeback_tempp.wb_valid, vx_writeback_tempp.rd, vx_writeback_tempp.wb, vx_writeback_tempp.wb_warp_num, vx_writeback_tempp.wb_pc}), + .out ({use_wb_data , vx_writeback_inter.wb_valid, vx_writeback_inter.rd, vx_writeback_inter.wb, vx_writeback_inter.wb_warp_num, vx_writeback_inter.wb_pc}) ); reg[31:0] last_data_wb /* verilator public */ ; always @(posedge clk) begin - if ((|VX_writeback_inter.wb_valid) && (VX_writeback_inter.wb != 0) && (VX_writeback_inter.rd == 28)) begin + if ((|vx_writeback_inter.wb_valid) && (vx_writeback_inter.wb != 0) && (vx_writeback_inter.rd == 28)) begin last_data_wb <= use_wb_data[0]; end end - assign VX_writeback_inter.write_data = use_wb_data; + assign vx_writeback_inter.write_data = use_wb_data; endmodule : VX_writeback diff --git a/hw/rtl/Vortex.v b/hw/rtl/Vortex.v index d515952b..f181af14 100644 --- a/hw/rtl/Vortex.v +++ b/hw/rtl/Vortex.v @@ -16,105 +16,82 @@ module Vortex output wire [31:0] io_data, // DRAM Dcache Req - output wire dram_req, - output wire dram_req_write, output wire dram_req_read, + output wire dram_req_write, output wire [31:0] dram_req_addr, - output wire [31:0] dram_req_size, output wire [`DBANK_LINE_SIZE-1:0] dram_req_data, - output wire [31:0] dram_expected_lat, + input wire dram_req_full, - input wire dram_req_delay, - - // DRAM Dcache Res - output wire dram_fill_accept, - input wire dram_fill_rsp, - input wire [31:0] dram_fill_rsp_addr, - input wire [`DBANK_LINE_SIZE-1:0] dram_fill_rsp_data, + // DRAM Dcache Rsp + input wire dram_rsp_valid, + input wire [31:0] dram_rsp_addr, + input wire [`DBANK_LINE_SIZE-1:0] dram_rsp_data, + output wire dram_rsp_ready, // DRAM Icache Req - output wire I_dram_req, - output wire I_dram_req_write, - output wire I_dram_req_read, - output wire [31:0] I_dram_req_addr, - output wire [31:0] I_dram_req_size, - output wire [`IBANK_LINE_SIZE-1:0] I_dram_req_data, - output wire [31:0] I_dram_expected_lat, + output wire I_dram_req_read, + output wire I_dram_req_write, + output wire [31:0] I_dram_req_addr, + output wire [`IBANK_LINE_SIZE-1:0] I_dram_req_data, + input wire I_dram_req_full, - // DRAM Icache Res - output wire I_dram_fill_accept, - input wire I_dram_fill_rsp, - input wire [31:0] I_dram_fill_rsp_addr, - input wire [`IBANK_LINE_SIZE-1:0] I_dram_fill_rsp_data, + // DRAM Icache Rsp + input wire I_dram_rsp_valid, + input wire [31:0] I_dram_rsp_addr, + input wire [`IBANK_LINE_SIZE-1:0] I_dram_rsp_data, + output wire I_dram_rsp_ready, // LLC Snooping - input wire snp_req, - input wire [31:0] snp_req_addr, - output wire snp_req_delay, + input wire snp_req_valid, + input wire [31:0] snp_req_addr, + output wire snp_req_full, - input wire I_snp_req, - input wire [31:0] I_snp_req_addr, - output wire I_snp_req_delay, - - output wire out_ebreak + output wire out_ebreak `else - input wire clk, - input wire reset, + input wire clk, + input wire reset, // IO - output wire io_valid, - output wire[31:0] io_data, + output wire io_valid, + output wire[31:0] io_data, // DRAM Dcache Req - output wire dram_req, - output wire dram_req_write, - output wire dram_req_read, - output wire [31:0] dram_req_addr, - output wire [31:0] dram_req_size, - output wire [`DBANK_LINE_SIZE-1:0] dram_req_data, - output wire [31:0] dram_expected_lat, - - // DRAM Dcache Res - output wire dram_fill_accept, - input wire dram_fill_rsp, - input wire [31:0] dram_fill_rsp_addr, - input wire [`DBANK_LINE_SIZE-1:0] dram_fill_rsp_data, + output wire dram_req_read, + output wire dram_req_write, + output wire [31:0] dram_req_addr, + output wire [`DBANK_LINE_SIZE-1:0] dram_req_data, + input wire dram_req_full, + // DRAM Dcache Rsp + input wire dram_rsp_valid, + input wire [31:0] dram_rsp_addr, + input wire [`DBANK_LINE_SIZE-1:0] dram_rsp_data, + output wire dram_rsp_ready, // DRAM Icache Req - output wire I_dram_req, - output wire I_dram_req_write, - output wire I_dram_req_read, - output wire [31:0] I_dram_req_addr, - output wire [31:0] I_dram_req_size, - output wire [`IBANK_LINE_SIZE-1:0] I_dram_req_data, - output wire [31:0] I_dram_expected_lat, + output wire I_dram_req_read, + output wire I_dram_req_write, + output wire [31:0] I_dram_req_addr, + output wire [`IBANK_LINE_SIZE-1:0] I_dram_req_data, + input wire I_dram_req_full, - // DRAM Icache Res - output wire I_dram_fill_accept, - input wire I_dram_fill_rsp, - input wire [31:0] I_dram_fill_rsp_addr, - input wire [`IBANK_LINE_SIZE-1:0] I_dram_fill_rsp_data, + // DRAM Icache Rsp + output wire I_dram_rsp_ready, + input wire I_dram_rsp_valid, + input wire [31:0] I_dram_rsp_addr, + input wire [`IBANK_LINE_SIZE-1:0] I_dram_rsp_data, - input wire dram_req_delay, + input wire snp_req_valid, + input wire [31:0] snp_req_addr, + output wire snp_req_full, - input wire snp_req, - input wire [31:0] snp_req_addr, - output wire snp_req_delay, - - input wire I_snp_req, - input wire [31:0] I_snp_req_addr, - output wire I_snp_req_delay, - - output wire out_ebreak + output wire out_ebreak `endif ); +/* verilator lint_off UNUSED */ wire scheduler_empty; - wire out_ebreak_unqual; - - // assign out_ebreak = out_ebreak_unqual && (scheduler_empty && 1); - assign out_ebreak = out_ebreak_unqual; +/* verilator lint_on UNUSED */ wire memory_delay; wire exec_delay; @@ -122,184 +99,165 @@ module Vortex wire schedule_delay; // Dcache Interface - VX_gpu_dcache_res_inter #(.NUM_REQUESTS(`DNUM_REQUESTS)) VX_dcache_rsp(); - VX_gpu_dcache_req_inter #(.NUM_REQUESTS(`DNUM_REQUESTS)) VX_dcache_req(); - VX_gpu_dcache_req_inter #(.NUM_REQUESTS(`DNUM_REQUESTS)) VX_dcache_req_qual(); + VX_gpu_dcache_rsp_inter #(.NUM_REQUESTS(`DNUM_REQUESTS)) vx_dcache_rsp(); + VX_gpu_dcache_req_inter #(.NUM_REQUESTS(`DNUM_REQUESTS)) vx_dcache_req(); + VX_gpu_dcache_req_inter #(.NUM_REQUESTS(`DNUM_REQUESTS)) vx_dcache_req_qual(); - VX_gpu_dcache_dram_req_inter #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) VX_gpu_dcache_dram_req(); - VX_gpu_dcache_dram_res_inter #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) VX_gpu_dcache_dram_res(); + VX_gpu_dcache_dram_req_inter #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) vx_gpu_dcache_dram_req(); + VX_gpu_dcache_dram_rsp_inter #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) vx_gpu_dcache_dram_res(); + assign vx_gpu_dcache_dram_res.dram_rsp_valid = dram_rsp_valid; + assign vx_gpu_dcache_dram_res.dram_rsp_addr = dram_rsp_addr; - assign VX_gpu_dcache_dram_res.dram_fill_rsp = dram_fill_rsp; - assign VX_gpu_dcache_dram_res.dram_fill_rsp_addr = dram_fill_rsp_addr; + assign dram_req_write = vx_gpu_dcache_dram_req.dram_req_write; + assign dram_req_read = vx_gpu_dcache_dram_req.dram_req_read; + assign dram_req_addr = vx_gpu_dcache_dram_req.dram_req_addr; + assign dram_rsp_ready = vx_gpu_dcache_dram_req.dram_rsp_ready; - assign dram_req = VX_gpu_dcache_dram_req.dram_req; - assign dram_req_write = VX_gpu_dcache_dram_req.dram_req_write; - assign dram_req_read = VX_gpu_dcache_dram_req.dram_req_read; - assign dram_req_addr = VX_gpu_dcache_dram_req.dram_req_addr; - assign dram_req_size = VX_gpu_dcache_dram_req.dram_req_size; - assign dram_expected_lat = `DSIMULATED_DRAM_LATENCY_CYCLES; - assign dram_fill_accept = VX_gpu_dcache_dram_req.dram_fill_accept; - - assign VX_gpu_dcache_dram_req.dram_req_delay = dram_req_delay; + assign vx_gpu_dcache_dram_req.dram_req_full = dram_req_full; genvar i; generate for (i = 0; i < `DBANK_LINE_WORDS; i=i+1) begin - assign VX_gpu_dcache_dram_res.dram_fill_rsp_data[i] = dram_fill_rsp_data[i * 32 +: 32]; - assign dram_req_data[i * 32 +: 32] = VX_gpu_dcache_dram_req.dram_req_data[i]; + assign vx_gpu_dcache_dram_res.dram_rsp_data[i] = dram_rsp_data[i * 32 +: 32]; + assign dram_req_data[i * 32 +: 32] = vx_gpu_dcache_dram_req.dram_req_data[i]; end endgenerate wire temp_io_valid = (!memory_delay) - && (|VX_dcache_req.core_req_valid) - && (VX_dcache_req.core_req_mem_write[0] != `NO_MEM_WRITE) - && (VX_dcache_req.core_req_addr[0] == 32'h00010000); + && (|vx_dcache_req.core_req_valid) + && (vx_dcache_req.core_req_mem_write[0] != `NO_MEM_WRITE) + && (vx_dcache_req.core_req_addr[0] == 32'h00010000); - wire[31:0] temp_io_data = VX_dcache_req.core_req_writedata[0]; + wire[31:0] temp_io_data = vx_dcache_req.core_req_writedata[0]; assign io_valid = temp_io_valid; assign io_data = temp_io_data; - assign VX_dcache_req_qual.core_req_valid = VX_dcache_req.core_req_valid & {`NUM_THREADS{~io_valid}}; - assign VX_dcache_req_qual.core_req_addr = VX_dcache_req.core_req_addr; - assign VX_dcache_req_qual.core_req_writedata = VX_dcache_req.core_req_writedata; - assign VX_dcache_req_qual.core_req_mem_read = VX_dcache_req.core_req_mem_read; - assign VX_dcache_req_qual.core_req_mem_write = VX_dcache_req.core_req_mem_write; - assign VX_dcache_req_qual.core_req_rd = VX_dcache_req.core_req_rd; - assign VX_dcache_req_qual.core_req_wb = VX_dcache_req.core_req_wb; - assign VX_dcache_req_qual.core_req_warp_num = VX_dcache_req.core_req_warp_num; - assign VX_dcache_req_qual.core_req_pc = VX_dcache_req.core_req_pc; - assign VX_dcache_req_qual.core_no_wb_slot = VX_dcache_req.core_no_wb_slot; + assign vx_dcache_req_qual.core_req_valid = vx_dcache_req.core_req_valid & {`NUM_THREADS{~io_valid}}; + assign vx_dcache_req_qual.core_req_addr = vx_dcache_req.core_req_addr; + assign vx_dcache_req_qual.core_req_writedata = vx_dcache_req.core_req_writedata; + assign vx_dcache_req_qual.core_req_mem_read = vx_dcache_req.core_req_mem_read; + assign vx_dcache_req_qual.core_req_mem_write = vx_dcache_req.core_req_mem_write; + assign vx_dcache_req_qual.core_req_rd = vx_dcache_req.core_req_rd; + assign vx_dcache_req_qual.core_req_wb = vx_dcache_req.core_req_wb; + assign vx_dcache_req_qual.core_req_warp_num = vx_dcache_req.core_req_warp_num; + assign vx_dcache_req_qual.core_req_pc = vx_dcache_req.core_req_pc; + assign vx_dcache_req_qual.core_no_wb_slot = vx_dcache_req.core_no_wb_slot; + VX_gpu_dcache_rsp_inter #(.NUM_REQUESTS(`INUM_REQUESTS)) vx_icache_rsp(); + VX_gpu_dcache_req_inter #(.NUM_REQUESTS(`INUM_REQUESTS)) vx_icache_req(); - VX_gpu_dcache_res_inter #(.NUM_REQUESTS(`INUM_REQUESTS)) VX_icache_rsp(); - VX_gpu_dcache_req_inter #(.NUM_REQUESTS(`INUM_REQUESTS)) VX_icache_req(); + VX_gpu_dcache_dram_req_inter #(.BANK_LINE_WORDS(`IBANK_LINE_WORDS)) vx_gpu_icache_dram_req(); + VX_gpu_dcache_dram_rsp_inter #(.BANK_LINE_WORDS(`IBANK_LINE_WORDS)) vx_gpu_icache_dram_res(); - VX_gpu_dcache_dram_req_inter #(.BANK_LINE_WORDS(`IBANK_LINE_WORDS)) VX_gpu_icache_dram_req(); - VX_gpu_dcache_dram_res_inter #(.BANK_LINE_WORDS(`IBANK_LINE_WORDS)) VX_gpu_icache_dram_res(); + assign vx_gpu_icache_dram_res.dram_rsp_valid = I_dram_rsp_valid; + assign vx_gpu_icache_dram_res.dram_rsp_addr = I_dram_rsp_addr; + assign I_dram_req_write = vx_gpu_icache_dram_req.dram_req_write; + assign I_dram_req_read = vx_gpu_icache_dram_req.dram_req_read; + assign I_dram_req_addr = vx_gpu_icache_dram_req.dram_req_addr; + assign I_dram_rsp_ready = vx_gpu_icache_dram_req.dram_rsp_ready; - assign VX_gpu_icache_dram_res.dram_fill_rsp = I_dram_fill_rsp; - assign VX_gpu_icache_dram_res.dram_fill_rsp_addr = I_dram_fill_rsp_addr; - - assign I_dram_req = VX_gpu_icache_dram_req.dram_req; - assign I_dram_req_write = VX_gpu_icache_dram_req.dram_req_write; - assign I_dram_req_read = VX_gpu_icache_dram_req.dram_req_read; - assign I_dram_req_addr = VX_gpu_icache_dram_req.dram_req_addr; - assign I_dram_req_size = VX_gpu_icache_dram_req.dram_req_size; - assign I_dram_expected_lat = `ISIMULATED_DRAM_LATENCY_CYCLES; - assign I_dram_fill_accept = VX_gpu_icache_dram_req.dram_fill_accept; - - assign VX_gpu_icache_dram_req.dram_req_delay = dram_req_delay; + assign vx_gpu_icache_dram_req.dram_req_full = I_dram_req_full; genvar j; generate for (j = 0; j < `IBANK_LINE_WORDS; j = j + 1) begin - assign VX_gpu_icache_dram_res.dram_fill_rsp_data[j] = I_dram_fill_rsp_data[j * 32 +: 32]; - assign I_dram_req_data[j * 32 +: 32] = VX_gpu_icache_dram_req.dram_req_data[j]; + assign vx_gpu_icache_dram_res.dram_rsp_data[j] = I_dram_rsp_data[j * 32 +: 32]; + assign I_dram_req_data[j * 32 +: 32] = vx_gpu_icache_dram_req.dram_req_data[j]; end endgenerate - ///////////////////////////////////////////////////////////////////////// // Front-end to Back-end -VX_frE_to_bckE_req_inter VX_bckE_req(); // New instruction request to EXE/MEM +VX_frE_to_bckE_req_inter vx_bckE_req(); // New instruction request to EXE/MEM // Back-end to Front-end -VX_wb_inter VX_writeback_inter(); // Writeback to GPRs -VX_branch_response_inter VX_branch_rsp(); // Branch Resolution to Fetch -VX_jal_response_inter VX_jal_rsp(); // Jump resolution to Fetch +VX_wb_inter vx_writeback_inter(); // Writeback to GPRs +VX_branch_response_inter vx_branch_rsp(); // Branch Resolution to Fetch +VX_jal_response_inter vx_jal_rsp(); // Jump resolution to Fetch // CSR Buses -// VX_csr_write_request_inter VX_csr_w_req(); +// VX_csr_write_request_inter vx_csr_w_req(); +VX_warp_ctl_inter vx_warp_ctl(); +VX_gpu_snp_req_rsp vx_gpu_icache_snp_req(); +VX_gpu_snp_req_rsp vx_gpu_dcache_snp_req(); -VX_warp_ctl_inter VX_warp_ctl(); - - -VX_gpu_snp_req_rsp VX_gpu_icache_snp_req(); -VX_gpu_snp_req_rsp VX_gpu_dcache_snp_req(); - -assign VX_gpu_icache_snp_req.snp_req = I_snp_req; -assign VX_gpu_icache_snp_req.snp_req_addr = I_snp_req_addr; -assign I_snp_req_delay = VX_gpu_icache_snp_req.snp_delay; - -assign VX_gpu_dcache_snp_req.snp_req = snp_req; -assign VX_gpu_dcache_snp_req.snp_req_addr = snp_req_addr; -assign snp_req_delay = VX_gpu_dcache_snp_req.snp_delay; +assign vx_gpu_dcache_snp_req.snp_req_valid = snp_req_valid; +assign vx_gpu_dcache_snp_req.snp_req_addr = snp_req_addr; +assign snp_req_full = vx_gpu_dcache_snp_req.snp_req_full; VX_front_end vx_front_end( .clk (clk), .reset (reset), - .VX_warp_ctl (VX_warp_ctl), - .VX_bckE_req (VX_bckE_req), + .vx_warp_ctl (vx_warp_ctl), + .vx_bckE_req (vx_bckE_req), .schedule_delay (schedule_delay), - .VX_icache_rsp (VX_icache_rsp), - .VX_icache_req (VX_icache_req), - .VX_jal_rsp (VX_jal_rsp), - .VX_branch_rsp (VX_branch_rsp), - .fetch_ebreak (out_ebreak_unqual) + .vx_icache_rsp (vx_icache_rsp), + .vx_icache_req (vx_icache_req), + .vx_jal_rsp (vx_jal_rsp), + .vx_branch_rsp (vx_branch_rsp), + .fetch_ebreak (out_ebreak) ); VX_scheduler schedule( - .clk (clk), - .reset (reset), - .memory_delay (memory_delay), - .exec_delay (exec_delay), - .gpr_stage_delay (gpr_stage_delay), - .VX_bckE_req (VX_bckE_req), - .VX_writeback_inter(VX_writeback_inter), - .schedule_delay (schedule_delay), - .is_empty (scheduler_empty) + .clk (clk), + .reset (reset), + .memory_delay (memory_delay), + .exec_delay (exec_delay), + .gpr_stage_delay (gpr_stage_delay), + .vx_bckE_req (vx_bckE_req), + .vx_writeback_inter (vx_writeback_inter), + .schedule_delay (schedule_delay), + .is_empty (scheduler_empty) ); VX_back_end #(.CORE_ID(CORE_ID)) vx_back_end( .clk (clk), .reset (reset), .schedule_delay (schedule_delay), - .VX_warp_ctl (VX_warp_ctl), - .VX_bckE_req (VX_bckE_req), - .VX_jal_rsp (VX_jal_rsp), - .VX_branch_rsp (VX_branch_rsp), - .VX_dcache_rsp (VX_dcache_rsp), - .VX_dcache_req (VX_dcache_req), - .VX_writeback_inter (VX_writeback_inter), + .vx_warp_ctl (vx_warp_ctl), + .vx_bckE_req (vx_bckE_req), + .vx_jal_rsp (vx_jal_rsp), + .vx_branch_rsp (vx_branch_rsp), + .vx_dcache_rsp (vx_dcache_rsp), + .vx_dcache_req (vx_dcache_req), + .vx_writeback_inter (vx_writeback_inter), .out_mem_delay (memory_delay), .out_exec_delay (exec_delay), .gpr_stage_delay (gpr_stage_delay) ); - -VX_dmem_controller VX_dmem_controller( +VX_dmem_controller vx_dmem_controller( .clk (clk), .reset (reset), // Dram <-> Dcache - .VX_gpu_dcache_dram_req (VX_gpu_dcache_dram_req), - .VX_gpu_dcache_dram_res (VX_gpu_dcache_dram_res), - .VX_gpu_dcache_snp_req (VX_gpu_dcache_snp_req), + .vx_gpu_dcache_dram_req (vx_gpu_dcache_dram_req), + .vx_gpu_dcache_dram_res (vx_gpu_dcache_dram_res), + .vx_gpu_dcache_snp_req (vx_gpu_dcache_snp_req), // Dram <-> Icache - .VX_gpu_icache_dram_req (VX_gpu_icache_dram_req), - .VX_gpu_icache_dram_res (VX_gpu_icache_dram_res), - .VX_gpu_icache_snp_req (VX_gpu_icache_snp_req), + .vx_gpu_icache_dram_req (vx_gpu_icache_dram_req), + .vx_gpu_icache_dram_res (vx_gpu_icache_dram_res), + .vx_gpu_icache_snp_req (vx_gpu_icache_snp_req), // Core <-> Icache - .VX_icache_req (VX_icache_req), - .VX_icache_rsp (VX_icache_rsp), + .vx_icache_req (vx_icache_req), + .vx_icache_rsp (vx_icache_rsp), // Core <-> Dcache - .VX_dcache_req (VX_dcache_req_qual), - .VX_dcache_rsp (VX_dcache_rsp) + .vx_dcache_req (vx_dcache_req_qual), + .vx_dcache_rsp (vx_dcache_rsp) ); // VX_csr_handler vx_csr_handler( // .clk (clk), // .in_decode_csr_address(decode_csr_address), -// .VX_csr_w_req (VX_csr_w_req), -// .in_wb_valid (VX_writeback_inter.wb_valid[0]), - +// .vx_csr_w_req (vx_csr_w_req), +// .in_wb_valid (vx_writeback_inter.wb_valid[0]), // .out_decode_csr_data (csr_decode_csr_data) // ); diff --git a/hw/rtl/Vortex_Cluster.v b/hw/rtl/Vortex_Cluster.v index afaae66b..77f252b1 100644 --- a/hw/rtl/Vortex_Cluster.v +++ b/hw/rtl/Vortex_Cluster.v @@ -15,57 +15,48 @@ module Vortex_Cluster output wire[`NUM_CORES_PER_CLUSTER-1:0][31:0] io_data, // DRAM Req - output wire out_dram_req, - output wire out_dram_req_write, - output wire out_dram_req_read, - output wire [31:0] out_dram_req_addr, - output wire [31:0] out_dram_req_size, - output wire [31:0] out_dram_req_data[`DBANK_LINE_WORDS-1:0], - output wire [31:0] out_dram_expected_lat, - input wire out_dram_req_delay, + output wire dram_req_read, + output wire dram_req_write, + output wire [31:0] dram_req_addr, + output wire [`DBANK_LINE_SIZE-1:0] dram_req_data, + input wire dram_req_full, - // DRAM Res - output wire out_dram_fill_accept, - input wire out_dram_fill_rsp, - input wire [31:0] out_dram_fill_rsp_addr, - input wire [31:0] out_dram_fill_rsp_data[`DBANK_LINE_WORDS-1:0], + // DRAM Rsp + input wire dram_rsp_valid, + input wire [31:0] dram_rsp_addr, + input wire [`DBANK_LINE_SIZE-1:0] dram_rsp_data, + output wire dram_rsp_ready, // LLC Snooping - input wire llc_snp_req, + input wire llc_snp_req_valid, input wire[31:0] llc_snp_req_addr, - output wire llc_snp_req_delay, + output wire llc_snp_req_full, output wire out_ebreak ); // DRAM Dcache Req - wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_dram_req; - wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_dram_req_write; wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_dram_req_read; + wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_dram_req_write; wire[`NUM_CORES_PER_CLUSTER-1:0] [31:0] per_core_dram_req_addr; - wire[`NUM_CORES_PER_CLUSTER-1:0] [31:0] per_core_dram_req_size; wire[`NUM_CORES_PER_CLUSTER-1:0][`DBANK_LINE_WORDS-1:0][31:0] per_core_dram_req_data; - wire[`NUM_CORES_PER_CLUSTER-1:0] [31:0] per_core_dram_expected_lat; - // DRAM Dcache Res - wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_dram_fill_accept; - wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_dram_fill_rsp; - wire[`NUM_CORES_PER_CLUSTER-1:0] [31:0] per_core_dram_fill_rsp_addr; - wire[`NUM_CORES_PER_CLUSTER-1:0][`DBANK_LINE_WORDS-1:0][31:0] per_core_dram_fill_rsp_data; + // DRAM Dcache Rsp + wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_dram_rsp_valid; + wire[`NUM_CORES_PER_CLUSTER-1:0] [31:0] per_core_dram_rsp_addr; + wire[`NUM_CORES_PER_CLUSTER-1:0][`DBANK_LINE_WORDS-1:0][31:0] per_core_dram_rsp_data; + wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_dram_rsp_ready; // DRAM Icache Req - wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_I_dram_req; - wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_I_dram_req_write; wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_I_dram_req_read; + wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_I_dram_req_write; wire[`NUM_CORES_PER_CLUSTER-1:0] [31:0] per_core_I_dram_req_addr; - wire[`NUM_CORES_PER_CLUSTER-1:0] [31:0] per_core_I_dram_req_size; wire[`NUM_CORES_PER_CLUSTER-1:0][`IBANK_LINE_WORDS-1:0][31:0] per_core_I_dram_req_data; - wire[`NUM_CORES_PER_CLUSTER-1:0] [31:0] per_core_I_dram_expected_lat; - // DRAM Icache Res - wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_I_dram_fill_accept; - wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_I_dram_fill_rsp; - wire[`NUM_CORES_PER_CLUSTER-1:0] [31:0] per_core_I_dram_fill_rsp_addr; - wire[`NUM_CORES_PER_CLUSTER-1:0][`IBANK_LINE_WORDS-1:0][31:0] per_core_I_dram_fill_rsp_data; + // DRAM Icache Rsp + wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_I_dram_rsp_valid; + wire[`NUM_CORES_PER_CLUSTER-1:0] [31:0] per_core_I_dram_rsp_addr; + wire[`NUM_CORES_PER_CLUSTER-1:0][`IBANK_LINE_WORDS-1:0][31:0] per_core_I_dram_rsp_data; + wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_I_dram_rsp_ready; // Out ebreak wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_out_ebreak; @@ -75,9 +66,9 @@ module Vortex_Cluster wire l2c_core_accept; - wire snp_fwd; + wire snp_fwd_valid; wire[31:0] snp_fwd_addr; - wire[`NUM_CORES_PER_CLUSTER-1:0] snp_fwd_delay; + wire[`NUM_CORES_PER_CLUSTER-1:0] snp_fwd_full; assign out_ebreak = (&per_core_out_ebreak); @@ -99,36 +90,28 @@ module Vortex_Cluster .reset (reset), .io_valid (per_core_io_valid [curr_core]), .io_data (per_core_io_data [curr_core]), - .dram_req (per_core_dram_req [curr_core]), - .dram_req_write (per_core_dram_req_write [curr_core]), .dram_req_read (per_core_dram_req_read [curr_core]), + .dram_req_write (per_core_dram_req_write [curr_core]), .dram_req_addr (per_core_dram_req_addr [curr_core]), - .dram_req_size (per_core_dram_req_size [curr_core]), .dram_req_data (curr_core_dram_req_data ), - .dram_expected_lat (per_core_dram_expected_lat [curr_core]), - .dram_fill_accept (per_core_dram_fill_accept [curr_core]), - .dram_fill_rsp (per_core_dram_fill_rsp [curr_core]), - .dram_fill_rsp_addr (per_core_dram_fill_rsp_addr [curr_core]), - .dram_fill_rsp_data (per_core_dram_fill_rsp_data [curr_core]), - .I_dram_req (per_core_I_dram_req [curr_core]), - .I_dram_req_write (per_core_I_dram_req_write [curr_core]), + .dram_req_full (l2c_core_accept ), + .dram_rsp_valid (per_core_dram_rsp_valid [curr_core]), + .dram_rsp_addr (per_core_dram_rsp_addr [curr_core]), + .dram_rsp_data (per_core_dram_rsp_data [curr_core]), + .dram_rsp_ready (per_core_dram_rsp_ready [curr_core]), .I_dram_req_read (per_core_I_dram_req_read [curr_core]), - .I_dram_req_addr (per_core_I_dram_req_addr [curr_core]), - .I_dram_req_size (per_core_I_dram_req_size [curr_core]), + .I_dram_req_write (per_core_I_dram_req_write [curr_core]), + .I_dram_req_addr (per_core_I_dram_req_addr [curr_core]), .I_dram_req_data (curr_core_I_dram_req_data ), - .I_dram_expected_lat (per_core_I_dram_expected_lat [curr_core]), - .I_dram_fill_accept (per_core_I_dram_fill_accept [curr_core]), - .I_dram_fill_rsp (per_core_I_dram_fill_rsp [curr_core]), - .I_dram_fill_rsp_addr (per_core_I_dram_fill_rsp_addr[curr_core]), - .I_dram_fill_rsp_data (per_core_I_dram_fill_rsp_data[curr_core]), - .dram_req_delay (l2c_core_accept ), - .out_ebreak (per_core_out_ebreak [curr_core]), - .snp_req (snp_fwd), + .I_dram_req_full (l2c_core_accept ), + .I_dram_rsp_valid (per_core_I_dram_rsp_valid [curr_core]), + .I_dram_rsp_addr (per_core_I_dram_rsp_addr [curr_core]), + .I_dram_rsp_data (per_core_I_dram_rsp_data [curr_core]), + .I_dram_rsp_ready (per_core_I_dram_rsp_ready [curr_core]), + .snp_req_valid (snp_fwd_valid), .snp_req_addr (snp_fwd_addr), - .snp_req_delay (snp_fwd_delay[curr_core]), - .I_snp_req (0), - .I_snp_req_addr (), - .I_snp_req_delay () + .snp_req_full (snp_fwd_full [curr_core]), + .out_ebreak (per_core_out_ebreak [curr_core]) ); assign per_core_dram_req_data [curr_core] = curr_core_dram_req_data; @@ -137,27 +120,28 @@ module Vortex_Cluster endgenerate //////////////////// L2 Cache //////////////////// - wire[`L2NUM_REQUESTS-1:0] l2c_core_req; - wire[`L2NUM_REQUESTS-1:0][2:0] l2c_core_req_mem_write; - wire[`L2NUM_REQUESTS-1:0][2:0] l2c_core_req_mem_read; - wire[`L2NUM_REQUESTS-1:0][31:0] l2c_core_req_addr; - wire[`L2NUM_REQUESTS-1:0][`IBANK_LINE_WORDS-1:0][31:0] l2c_core_req_data; - wire[`L2NUM_REQUESTS-1:0][1:0] l2c_core_req_wb; + + wire[`L2NUM_REQUESTS-1:0] l2c_core_req_valid; + wire[`L2NUM_REQUESTS-1:0][2:0] l2c_core_req_mem_write; + wire[`L2NUM_REQUESTS-1:0][2:0] l2c_core_req_mem_read; + wire[`L2NUM_REQUESTS-1:0][31:0] l2c_core_req_addr; + wire[`L2NUM_REQUESTS-1:0][`IBANK_LINE_WORDS-1:0][31:0] l2c_core_req_data; + wire[`L2NUM_REQUESTS-1:0][1:0] l2c_core_req_wb; - wire[`L2NUM_REQUESTS-1:0] l2c_core_no_wb_slot; + wire[`L2NUM_REQUESTS-1:0] l2c_core_no_wb_slot; - wire[`L2NUM_REQUESTS-1:0] l2c_wb; - wire[`L2NUM_REQUESTS-1:0] [31:0] l2c_wb_addr; - wire[`L2NUM_REQUESTS-1:0][`IBANK_LINE_WORDS-1:0][31:0] l2c_wb_data; + wire[`L2NUM_REQUESTS-1:0] l2c_wb; + wire[`L2NUM_REQUESTS-1:0] [31:0] l2c_wb_addr; + wire[`L2NUM_REQUESTS-1:0][`IBANK_LINE_WORDS-1:0][31:0] l2c_wb_data; - wire[`DBANK_LINE_WORDS-1:0][31:0] dram_req_data_port; - wire[`DBANK_LINE_WORDS-1:0][31:0] dram_fill_rsp_data_port; + wire[`DBANK_LINE_WORDS-1:0][31:0] dram_req_data_port; + wire[`DBANK_LINE_WORDS-1:0][31:0] dram_rsp_data_port; genvar llb_index; generate for (llb_index = 0; llb_index < `DBANK_LINE_WORDS; llb_index=llb_index+1) begin - assign out_dram_req_data [llb_index] = dram_req_data_port[llb_index]; - assign dram_fill_rsp_data_port[llb_index] = out_dram_fill_rsp_data[llb_index]; + assign dram_req_data [llb_index * `DWORD_SIZE_BITS +: `DWORD_SIZE_BITS] = dram_req_data_port[llb_index]; + assign dram_rsp_data_port [llb_index] = dram_rsp_data[llb_index * `DWORD_SIZE_BITS +: `DWORD_SIZE_BITS]; end endgenerate @@ -165,9 +149,9 @@ module Vortex_Cluster generate for (l2c_curr_core = 0; l2c_curr_core < `L2NUM_REQUESTS; l2c_curr_core=l2c_curr_core+2) begin // Core Request - assign l2c_core_req [l2c_curr_core] = per_core_dram_req [(l2c_curr_core/2)]; - assign l2c_core_req [l2c_curr_core+1] = per_core_I_dram_req[(l2c_curr_core/2)]; - + assign l2c_core_req_valid [l2c_curr_core] = (per_core_dram_req_read[(l2c_curr_core/2)] | per_core_dram_req_write[(l2c_curr_core/2)]); + assign l2c_core_req_valid [l2c_curr_core+1] = (per_core_I_dram_req_read[(l2c_curr_core/2)] | per_core_I_dram_req_write[(l2c_curr_core/2)]); + assign l2c_core_req_mem_write [l2c_curr_core] = per_core_dram_req_write[(l2c_curr_core/2)] ? `SW_MEM_WRITE : `NO_MEM_WRITE; assign l2c_core_req_mem_write [l2c_curr_core+1] = `NO_MEM_WRITE; // I caches don't write @@ -184,23 +168,21 @@ module Vortex_Cluster assign l2c_core_req_data [l2c_curr_core+1] = per_core_I_dram_req_data[(l2c_curr_core/2)]; // Core can't accept Response - assign l2c_core_no_wb_slot [l2c_curr_core] = ~per_core_dram_fill_accept [(l2c_curr_core/2)]; - assign l2c_core_no_wb_slot [l2c_curr_core+1] = ~per_core_I_dram_fill_accept[(l2c_curr_core/2)]; + assign l2c_core_no_wb_slot [l2c_curr_core] = ~per_core_dram_rsp_ready [(l2c_curr_core/2)]; + assign l2c_core_no_wb_slot [l2c_curr_core+1] = ~per_core_I_dram_rsp_ready[(l2c_curr_core/2)]; // Cache Fill Response - assign per_core_dram_fill_rsp [(l2c_curr_core/2)] = l2c_wb[l2c_curr_core]; - assign per_core_I_dram_fill_rsp [(l2c_curr_core/2)] = l2c_wb[l2c_curr_core+1]; + assign per_core_dram_rsp_valid [(l2c_curr_core/2)] = l2c_wb[l2c_curr_core]; + assign per_core_I_dram_rsp_valid [(l2c_curr_core/2)] = l2c_wb[l2c_curr_core+1]; - assign per_core_dram_fill_rsp_data[(l2c_curr_core/2)] = l2c_wb_data[l2c_curr_core]; - assign per_core_I_dram_fill_rsp_data[(l2c_curr_core/2)] = l2c_wb_data[l2c_curr_core+1]; + assign per_core_dram_rsp_data [(l2c_curr_core/2)] = l2c_wb_data[l2c_curr_core]; + assign per_core_I_dram_rsp_data [(l2c_curr_core/2)] = l2c_wb_data[l2c_curr_core+1]; - assign per_core_dram_fill_rsp_addr[(l2c_curr_core/2)] = l2c_wb_addr[l2c_curr_core]; - assign per_core_I_dram_fill_rsp_addr[(l2c_curr_core/2)] = l2c_wb_addr[l2c_curr_core+1]; + assign per_core_dram_rsp_addr [(l2c_curr_core/2)] = l2c_wb_addr[l2c_curr_core]; + assign per_core_I_dram_rsp_addr [(l2c_curr_core/2)] = l2c_wb_addr[l2c_curr_core+1]; end endgenerate - wire dram_snp_full; - wire dram_req_because_of_wb; VX_cache #( .CACHE_SIZE_BYTES (`L2CACHE_SIZE_BYTES), .BANK_LINE_SIZE_BYTES (`L2BANK_LINE_SIZE_BYTES), @@ -223,64 +205,60 @@ module Vortex_Cluster .FILL_INVALIDAOR_SIZE (`L2FILL_INVALIDAOR_SIZE), .SIMULATED_DRAM_LATENCY_CYCLES(`L2SIMULATED_DRAM_LATENCY_CYCLES) ) gpu_l2cache ( - .clk (clk), - .reset (reset), + .clk (clk), + .reset (reset), // Core Req (DRAM Fills/WB) To L2 Request - .core_req_valid (l2c_core_req), - .core_req_addr (l2c_core_req_addr), - .core_req_writedata({l2c_core_req_data}), - .core_req_mem_read (l2c_core_req_mem_read), - .core_req_mem_write(l2c_core_req_mem_write), - .core_req_rd (0), - .core_req_wb (l2c_core_req_wb), - .core_req_warp_num (0), - .core_req_pc (0), + .core_req_valid (l2c_core_req_valid), + .core_req_mem_read (l2c_core_req_mem_read), + .core_req_mem_write (l2c_core_req_mem_write), + .core_req_addr (l2c_core_req_addr), + .core_req_writedata ({l2c_core_req_data}), + .core_req_rd (0), + .core_req_wb (l2c_core_req_wb), + .core_req_warp_num (0), + .core_req_pc (0), // L2 can't accept Core Request - .delay_req (l2c_core_accept), + .delay_req (l2c_core_accept), // Core can't accept L2 Request - .core_no_wb_slot (|l2c_core_no_wb_slot), + .core_no_wb_slot (|l2c_core_no_wb_slot), // Core Writeback - .core_wb_valid (l2c_wb), - .core_wb_req_rd (), - .core_wb_req_wb (), - .core_wb_warp_num (), - .core_wb_readdata ({l2c_wb_data}), - .core_wb_address (l2c_wb_addr), - .core_wb_pc (), - + .core_wb_valid (l2c_wb), + /* verilator lint_off PINCONNECTEMPTY */ + .core_wb_req_rd (), + .core_wb_req_wb (), + .core_wb_warp_num (), + .core_wb_pc (), + /* verilator lint_on PINCONNECTEMPTY */ + .core_wb_readdata ({l2c_wb_data}), + .core_wb_address (l2c_wb_addr), + // L2 Cache DRAM Fill response - .dram_fill_rsp (out_dram_fill_rsp), - .dram_fill_rsp_addr(out_dram_fill_rsp_addr), - .dram_fill_rsp_data({dram_fill_rsp_data_port}), + .dram_rsp_valid (dram_rsp_valid), + .dram_rsp_addr (dram_rsp_addr), + .dram_rsp_data ({dram_rsp_data_port}), // L2 Cache can't accept Fill Response - .dram_fill_accept (out_dram_fill_accept), + .dram_rsp_ready (dram_rsp_ready), // L2 Cache DRAM Fill Request - .dram_req (out_dram_req), - .dram_req_write (out_dram_req_write), - .dram_req_read (out_dram_req_read), - .dram_req_addr (out_dram_req_addr), - .dram_req_size (out_dram_req_size), - .dram_req_data ({dram_req_data_port}), - .dram_req_delay (out_dram_req_delay), - - // Snoop Response - .dram_req_because_of_wb(dram_req_because_of_wb), - .dram_snp_full (dram_snp_full), + .dram_req_read (dram_req_read), + .dram_req_write (dram_req_write), + .dram_req_addr (dram_req_addr), + .dram_req_data ({dram_req_data_port}), + .dram_req_full (dram_req_full), // Snoop Request - .snp_req (llc_snp_req), - .snp_req_addr (llc_snp_req_addr), - .snp_req_delay (llc_snp_req_delay), + .snp_req_valid (llc_snp_req_valid), + .snp_req_addr (llc_snp_req_addr), + .snp_req_full (llc_snp_req_full), - .snp_fwd (snp_fwd), - .snp_fwd_addr (snp_fwd_addr), - .snp_fwd_delay (|snp_fwd_delay) + .snp_fwd_valid (snp_fwd_valid), + .snp_fwd_addr (snp_fwd_addr), + .snp_fwd_full (|snp_fwd_full) ); endmodule \ No newline at end of file diff --git a/hw/rtl/Vortex_Socket.v b/hw/rtl/Vortex_Socket.v index 5cfec2ac..237e518b 100644 --- a/hw/rtl/Vortex_Socket.v +++ b/hw/rtl/Vortex_Socket.v @@ -11,33 +11,26 @@ module Vortex_Socket ( output wire io_valid[`NUM_CORES-1:0], output wire[31:0] io_data [`NUM_CORES-1:0], - output wire[31:0] number_cores, - // DRAM Req - output wire out_dram_req, - output wire out_dram_req_write, - output wire out_dram_req_read, - output wire [31:0] out_dram_req_addr, - output wire [31:0] out_dram_req_size, - output wire [31:0] out_dram_req_data[`DBANK_LINE_WORDS-1:0], - output wire [31:0] out_dram_expected_lat, - input wire out_dram_req_delay, + output wire dram_req_read, + output wire dram_req_write, + output wire [31:0] dram_req_addr, + output wire [`DBANK_LINE_SIZE-1:0] dram_req_data, + input wire dram_req_full, - // DRAM Res - output wire out_dram_fill_accept, - input wire out_dram_fill_rsp, - input wire [31:0] out_dram_fill_rsp_addr, - input wire [31:0] out_dram_fill_rsp_data[`DBANK_LINE_WORDS-1:0], + // DRAM Rsp + input wire dram_rsp_valid, + input wire [31:0] dram_rsp_addr, + input wire [`DBANK_LINE_SIZE-1:0] dram_rsp_data, + output wire dram_rsp_ready, // LLC Snooping - input wire llc_snp_req, + input wire llc_snp_req_valid, input wire[31:0] llc_snp_req_addr, - output wire llc_snp_req_delay, + output wire llc_snp_req_full, output wire out_ebreak ); - assign number_cores = `NUM_CORES; - if (`NUM_CLUSTERS == 1) begin wire[`NUM_CORES-1:0] cluster_io_valid; @@ -51,59 +44,55 @@ module Vortex_Socket ( end Vortex_Cluster #(.CLUSTER_ID(0)) Vortex_Cluster( - .clk (clk), - .reset (reset), - .io_valid (cluster_io_valid), - .io_data (cluster_io_data), + .clk (clk), + .reset (reset), + .io_valid (cluster_io_valid), + .io_data (cluster_io_data), - .out_dram_req (out_dram_req), - .out_dram_req_write (out_dram_req_write), - .out_dram_req_read (out_dram_req_read), - .out_dram_req_addr (out_dram_req_addr), - .out_dram_req_size (out_dram_req_size), - .out_dram_req_data (out_dram_req_data), - .out_dram_expected_lat (out_dram_expected_lat), - .out_dram_req_delay (out_dram_req_delay), + .dram_req_read (dram_req_read), + .dram_req_write (dram_req_write), + .dram_req_addr (dram_req_addr), + .dram_req_data (dram_req_data), + .dram_req_full (dram_req_full), - .out_dram_fill_accept (out_dram_fill_accept), - .out_dram_fill_rsp (out_dram_fill_rsp), - .out_dram_fill_rsp_addr(out_dram_fill_rsp_addr), - .out_dram_fill_rsp_data(out_dram_fill_rsp_data), + .dram_rsp_valid (dram_rsp_valid), + .dram_rsp_addr (dram_rsp_addr), + .dram_rsp_data (dram_rsp_data), + .dram_rsp_ready (dram_rsp_ready), - .llc_snp_req (llc_snp_req), - .llc_snp_req_addr (llc_snp_req_addr), - .llc_snp_req_delay (llc_snp_req_delay), - .out_ebreak (out_ebreak) + .llc_snp_req_valid (llc_snp_req_valid), + .llc_snp_req_addr (llc_snp_req_addr), + .llc_snp_req_full (llc_snp_req_full), + + .out_ebreak (out_ebreak) ); end else begin - wire snp_fwd; - wire[31:0] snp_fwd_addr; - wire[`NUM_CLUSTERS-1:0] snp_fwd_delay; + wire snp_fwd_valid; + wire[31:0] snp_fwd_addr; + wire[`NUM_CLUSTERS-1:0] snp_fwd_full; wire[`NUM_CLUSTERS-1:0] per_cluster_out_ebreak; assign out_ebreak = (&per_cluster_out_ebreak); // // DRAM Dcache Req - wire[`NUM_CLUSTERS-1:0] per_cluster_dram_req; + wire[`NUM_CLUSTERS-1:0] per_cluster_dram_req_valid; wire[`NUM_CLUSTERS-1:0] per_cluster_dram_req_write; wire[`NUM_CLUSTERS-1:0] per_cluster_dram_req_read; wire[`NUM_CLUSTERS-1:0] [31:0] per_cluster_dram_req_addr; - wire[`NUM_CLUSTERS-1:0] [31:0] per_cluster_dram_req_size; - wire[`NUM_CLUSTERS-1:0] [31:0] per_cluster_dram_expected_lat; wire[`NUM_CLUSTERS-1:0][`DBANK_LINE_WORDS-1:0][31:0] per_cluster_dram_req_data; wire[31:0] per_cluster_dram_req_data_up[`NUM_CLUSTERS-1:0][`DBANK_LINE_WORDS-1:0]; - wire l3c_core_accept; + wire l3c_core_req_full; - // // DRAM Dcache Res - wire[`NUM_CLUSTERS-1:0] per_cluster_dram_fill_accept; - wire[`NUM_CLUSTERS-1:0] per_cluster_dram_fill_rsp; - wire[`NUM_CLUSTERS-1:0] [31:0] per_cluster_dram_fill_rsp_addr; - wire[`NUM_CLUSTERS-1:0][`DBANK_LINE_WORDS-1:0][31:0] per_cluster_dram_fill_rsp_data; - wire[31:0] per_cluster_dram_fill_rsp_data_up[`NUM_CLUSTERS-1:0][`DBANK_LINE_WORDS-1:0]; + // // DRAM Dcache Rsp + wire[`NUM_CLUSTERS-1:0] per_cluster_dram_rsp_ready; + wire[`NUM_CLUSTERS-1:0] per_cluster_dram_rsp_valid; + wire[`NUM_CLUSTERS-1:0] [31:0] per_cluster_dram_rsp_addr; + wire[`NUM_CLUSTERS-1:0][`DBANK_LINE_WORDS-1:0][31:0] per_cluster_dram_rsp_data; + wire[31:0] per_cluster_dram_rsp_data_up[`NUM_CLUSTERS-1:0][`DBANK_LINE_WORDS-1:0]; wire[`NUM_CLUSTERS-1:0][`NUM_CORES_PER_CLUSTER-1:0] per_cluster_io_valid; wire[`NUM_CLUSTERS-1:0][`NUM_CORES_PER_CLUSTER-1:0][31:0] per_cluster_io_data; @@ -115,96 +104,83 @@ module Vortex_Socket ( assign io_data [curr_cc+(curr_c*`NUM_CORES_PER_CLUSTER)] = per_cluster_io_data [curr_c][curr_cc]; end - for (curr_word = 0; curr_word < `DBANK_LINE_WORDS; curr_word = curr_word+1) begin assign per_cluster_dram_req_data [curr_c][curr_word] = per_cluster_dram_req_data_up [curr_c][curr_word]; - assign per_cluster_dram_fill_rsp_data_up[curr_c][curr_word] = per_cluster_dram_fill_rsp_data[curr_c][curr_word]; + assign per_cluster_dram_rsp_data_up[curr_c][curr_word] = per_cluster_dram_rsp_data[curr_c][curr_word]; end - end genvar curr_cluster; for (curr_cluster = 0; curr_cluster < `NUM_CLUSTERS; curr_cluster=curr_cluster+1) begin Vortex_Cluster #(.CLUSTER_ID(curr_cluster)) Vortex_Cluster( - .clk (clk), - .reset (reset), - .io_valid (per_cluster_io_valid [curr_cluster]), - .io_data (per_cluster_io_data [curr_cluster]), + .clk (clk), + .reset (reset), + .io_valid (per_cluster_io_valid [curr_cluster]), + .io_data (per_cluster_io_data [curr_cluster]), - .out_dram_req (per_cluster_dram_req [curr_cluster]), - .out_dram_req_write (per_cluster_dram_req_write [curr_cluster]), - .out_dram_req_read (per_cluster_dram_req_read [curr_cluster]), - .out_dram_req_addr (per_cluster_dram_req_addr [curr_cluster]), - .out_dram_req_size (per_cluster_dram_req_size [curr_cluster]), - .out_dram_req_data (per_cluster_dram_req_data_up [curr_cluster]), - .out_dram_expected_lat (per_cluster_dram_expected_lat [curr_cluster]), - .out_dram_req_delay (l3c_core_accept), + .dram_req_write (per_cluster_dram_req_write [curr_cluster]), + .dram_req_read (per_cluster_dram_req_read [curr_cluster]), + .dram_req_addr (per_cluster_dram_req_addr [curr_cluster]), + .dram_req_data (per_cluster_dram_req_data_up [curr_cluster]), + .dram_req_full (l3c_core_req_full), - .out_dram_fill_accept (per_cluster_dram_fill_accept [curr_cluster]), - .out_dram_fill_rsp (per_cluster_dram_fill_rsp [curr_cluster]), - .out_dram_fill_rsp_addr(per_cluster_dram_fill_rsp_addr [curr_cluster]), - .out_dram_fill_rsp_data(per_cluster_dram_fill_rsp_data_up[curr_cluster]), + .dram_rsp_valid (per_cluster_dram_rsp_valid [curr_cluster]), + .dram_rsp_addr (per_cluster_dram_rsp_addr [curr_cluster]), + .dram_rsp_data (per_cluster_dram_rsp_data_up [curr_cluster]), + .dram_rsp_ready (per_cluster_dram_rsp_ready [curr_cluster]), - .llc_snp_req (snp_fwd), - .llc_snp_req_addr (snp_fwd_addr), - .llc_snp_req_delay (snp_fwd_delay[curr_cluster]), + .llc_snp_req_valid (snp_fwd_valid), + .llc_snp_req_addr (snp_fwd_addr), + .llc_snp_req_full (snp_fwd_full[curr_cluster]), - .out_ebreak (per_cluster_out_ebreak [curr_cluster]) + .out_ebreak (per_cluster_out_ebreak [curr_cluster]) ); end //////////////////// L3 Cache //////////////////// - wire[`L3NUM_REQUESTS-1:0] l3c_core_req; - wire[`L3NUM_REQUESTS-1:0][2:0] l3c_core_req_mem_write; - wire[`L3NUM_REQUESTS-1:0][2:0] l3c_core_req_mem_read; - wire[`L3NUM_REQUESTS-1:0][31:0] l3c_core_req_addr; - wire[`L3NUM_REQUESTS-1:0][`IBANK_LINE_WORDS-1:0][31:0] l3c_core_req_data; - wire[`L3NUM_REQUESTS-1:0][1:0] l3c_core_req_wb; + wire[`L3NUM_REQUESTS-1:0] l3c_core_req_valid; + wire[`L3NUM_REQUESTS-1:0][2:0] l3c_core_req_mem_write; + wire[`L3NUM_REQUESTS-1:0][2:0] l3c_core_req_mem_read; + wire[`L3NUM_REQUESTS-1:0][31:0] l3c_core_req_addr; + wire[`L3NUM_REQUESTS-1:0][`IBANK_LINE_WORDS-1:0][31:0] l3c_core_req_data; + wire[`L3NUM_REQUESTS-1:0][1:0] l3c_core_req_wb; - wire[`L3NUM_REQUESTS-1:0] l3c_core_no_wb_slot; + wire[`L3NUM_REQUESTS-1:0] l3c_core_no_wb_slot; - wire[`L3NUM_REQUESTS-1:0] l3c_wb; - wire[`L3NUM_REQUESTS-1:0] [31:0] l3c_wb_addr; - wire[`L3NUM_REQUESTS-1:0][`IBANK_LINE_WORDS-1:0][31:0] l3c_wb_data; + wire[`L3NUM_REQUESTS-1:0] l3c_wb; + wire[`L3NUM_REQUESTS-1:0] [31:0] l3c_wb_addr; + wire[`L3NUM_REQUESTS-1:0][`IBANK_LINE_WORDS-1:0][31:0] l3c_wb_data; - - wire[`DBANK_LINE_WORDS-1:0][31:0] dram_req_data_port; - wire[`DBANK_LINE_WORDS-1:0][31:0] dram_fill_rsp_data_port; + wire[`DBANK_LINE_WORDS-1:0][31:0] dram_req_data_port; + wire[`DBANK_LINE_WORDS-1:0][31:0] dram_rsp_data_port; genvar llb_index; - for (llb_index = 0; llb_index < `DBANK_LINE_WORDS; llb_index=llb_index+1) begin - assign out_dram_req_data [llb_index] = dram_req_data_port[llb_index]; - assign dram_fill_rsp_data_port[llb_index] = out_dram_fill_rsp_data[llb_index]; - end + for (llb_index = 0; llb_index < `DBANK_LINE_WORDS; llb_index=llb_index+1) begin + assign dram_req_data [llb_index] = dram_req_data_port[llb_index]; + assign dram_rsp_data_port[llb_index] = dram_rsp_data[llb_index]; + end // genvar l3c_curr_cluster; for (l3c_curr_cluster = 0; l3c_curr_cluster < `L3NUM_REQUESTS; l3c_curr_cluster=l3c_curr_cluster+1) begin // Core Request - assign l3c_core_req [l3c_curr_cluster] = per_cluster_dram_req [l3c_curr_cluster]; - - assign l3c_core_req_mem_write [l3c_curr_cluster] = per_cluster_dram_req_write[l3c_curr_cluster] ? `SW_MEM_WRITE : `NO_MEM_WRITE; - + assign l3c_core_req_valid [l3c_curr_cluster] = per_cluster_dram_req_valid[l3c_curr_cluster]; assign l3c_core_req_mem_read [l3c_curr_cluster] = per_cluster_dram_req_read [l3c_curr_cluster] ? `LW_MEM_READ : `NO_MEM_READ; - + assign l3c_core_req_mem_write [l3c_curr_cluster] = per_cluster_dram_req_write[l3c_curr_cluster] ? `SW_MEM_WRITE : `NO_MEM_WRITE; assign l3c_core_req_wb [l3c_curr_cluster] = per_cluster_dram_req_read [l3c_curr_cluster] ? 1 : 0; - assign l3c_core_req_addr [l3c_curr_cluster] = per_cluster_dram_req_addr [l3c_curr_cluster]; - assign l3c_core_req_data [l3c_curr_cluster] = per_cluster_dram_req_data [l3c_curr_cluster]; // Core can't accept Response - assign l3c_core_no_wb_slot [l3c_curr_cluster] = ~per_cluster_dram_fill_accept[l3c_curr_cluster]; + assign l3c_core_no_wb_slot [l3c_curr_cluster] = ~per_cluster_dram_rsp_ready[l3c_curr_cluster]; // Cache Fill Response - assign per_cluster_dram_fill_rsp [l3c_curr_cluster] = l3c_wb [l3c_curr_cluster]; - assign per_cluster_dram_fill_rsp_data[l3c_curr_cluster] = l3c_wb_data[l3c_curr_cluster]; - assign per_cluster_dram_fill_rsp_addr[l3c_curr_cluster] = l3c_wb_addr[l3c_curr_cluster]; + assign per_cluster_dram_rsp_valid [l3c_curr_cluster] = l3c_wb [l3c_curr_cluster]; + assign per_cluster_dram_rsp_data [l3c_curr_cluster] = l3c_wb_data [l3c_curr_cluster]; + assign per_cluster_dram_rsp_addr [l3c_curr_cluster] = l3c_wb_addr [l3c_curr_cluster]; end - wire dram_snp_full; - wire dram_req_because_of_wb; VX_cache #( .CACHE_SIZE_BYTES (`L3CACHE_SIZE_BYTES), .BANK_LINE_SIZE_BYTES (`L3BANK_LINE_SIZE_BYTES), @@ -230,62 +206,58 @@ module Vortex_Socket ( .clk (clk), .reset (reset), - // Core Req (DRAM Fills/WB) To L2 Request - .core_req_valid (l3c_core_req), - .core_req_addr (l3c_core_req_addr), - .core_req_writedata({l3c_core_req_data}), - .core_req_mem_read (l3c_core_req_mem_read), - .core_req_mem_write(l3c_core_req_mem_write), - .core_req_rd (0), - .core_req_wb (l3c_core_req_wb), - .core_req_warp_num (0), - .core_req_pc (0), + // Core Req (DRAM Fills/WB) To L2 Request + .core_req_valid (l3c_core_req_valid), + .core_req_mem_read (l3c_core_req_mem_read), + .core_req_mem_write (l3c_core_req_mem_write), + .core_req_addr (l3c_core_req_addr), + .core_req_writedata ({l3c_core_req_data}), + .core_req_rd (0), + .core_req_wb (l3c_core_req_wb), + .core_req_warp_num (0), + .core_req_pc (0), // L2 can't accept Core Request - .delay_req (l3c_core_accept), + .delay_req (l3c_core_req_full), // Core can't accept L2 Request - .core_no_wb_slot (|l3c_core_no_wb_slot), + .core_no_wb_slot (|l3c_core_no_wb_slot), // Core Writeback - .core_wb_valid (l3c_wb), - .core_wb_req_rd (), - .core_wb_req_wb (), - .core_wb_warp_num (), - .core_wb_readdata ({l3c_wb_data}), - .core_wb_address (l3c_wb_addr), - .core_wb_pc (), + .core_wb_valid (l3c_wb), + /* verilator lint_off PINCONNECTEMPTY */ + .core_wb_req_rd (), + .core_wb_req_wb (), + .core_wb_warp_num (), + .core_wb_pc (), + /* verilator lint_on PINCONNECTEMPTY */ + .core_wb_readdata ({l3c_wb_data}), + .core_wb_address (l3c_wb_addr), // L2 Cache DRAM Fill response - .dram_fill_rsp (out_dram_fill_rsp), - .dram_fill_rsp_addr(out_dram_fill_rsp_addr), - .dram_fill_rsp_data({dram_fill_rsp_data_port}), + .dram_rsp_valid (dram_rsp_valid), + .dram_rsp_addr (dram_rsp_addr), + .dram_rsp_data ({dram_rsp_data_port}), // L2 Cache can't accept Fill Response - .dram_fill_accept (out_dram_fill_accept), + .dram_rsp_ready (dram_rsp_ready), // L2 Cache DRAM Fill Request - .dram_req (out_dram_req), - .dram_req_write (out_dram_req_write), - .dram_req_read (out_dram_req_read), - .dram_req_addr (out_dram_req_addr), - .dram_req_size (out_dram_req_size), - .dram_req_data ({dram_req_data_port}), - .dram_req_delay (out_dram_req_delay), - - // Snoop Response - .dram_req_because_of_wb(dram_req_because_of_wb), - .dram_snp_full (dram_snp_full), + .dram_req_write (dram_req_write), + .dram_req_read (dram_req_read), + .dram_req_addr (dram_req_addr), + .dram_req_data ({dram_req_data_port}), + .dram_req_full (dram_req_full), // Snoop Request - .snp_req (llc_snp_req), - .snp_req_addr (llc_snp_req_addr), - .snp_req_delay (llc_snp_req_delay), + .snp_req_valid (llc_snp_req_valid), + .snp_req_addr (llc_snp_req_addr), + .snp_req_full (llc_snp_req_full), // Snoop Forward - .snp_fwd (snp_fwd), - .snp_fwd_addr (snp_fwd_addr), - .snp_fwd_delay (|snp_fwd_delay) + .snp_fwd_valid (snp_fwd_valid), + .snp_fwd_addr (snp_fwd_addr), + .snp_fwd_full (|snp_fwd_full) ); end diff --git a/hw/rtl/byte_enabled_simple_dual_port_ram.v b/hw/rtl/byte_enabled_simple_dual_port_ram.v index 2eb4cdee..657501d8 100644 --- a/hw/rtl/byte_enabled_simple_dual_port_ram.v +++ b/hw/rtl/byte_enabled_simple_dual_port_ram.v @@ -17,29 +17,28 @@ module byte_enabled_simple_dual_port_ram // Thread Byte Bit logic [`NUM_THREADS-1:0][3:0][7:0] GPR[31:0]; - // initial begin - // for (ini = 0; ini < 32; ini = ini + 1) GPR[ini] = 0; - // end - - integer ini; always @(posedge clk) begin - if (we) begin - integer thread_ind; - for (thread_ind = 0; thread_ind < `NUM_THREADS; thread_ind = thread_ind + 1) begin - if (be[thread_ind]) begin - GPR[waddr][thread_ind][0] <= wdata[thread_ind][7:0]; - GPR[waddr][thread_ind][1] <= wdata[thread_ind][15:8]; - GPR[waddr][thread_ind][2] <= wdata[thread_ind][23:16]; - GPR[waddr][thread_ind][3] <= wdata[thread_ind][31:24]; + if (reset) begin + //-- + end else begin + if (we) begin + integer thread_ind; + for (thread_ind = 0; thread_ind < `NUM_THREADS; thread_ind = thread_ind + 1) begin + if (be[thread_ind]) begin + GPR[waddr][thread_ind][0] <= wdata[thread_ind][7:0]; + GPR[waddr][thread_ind][1] <= wdata[thread_ind][15:8]; + GPR[waddr][thread_ind][2] <= wdata[thread_ind][23:16]; + GPR[waddr][thread_ind][3] <= wdata[thread_ind][31:24]; + end end - end - end - // $display("^^^^^^^^^^^^^^^^^^^^^^^"); - // for (regi = 0; regi <= 31; regi = regi + 1) begin - // for (threadi = 0; threadi < `NUM_THREADS; threadi = threadi + 1) begin - // if (GPR[regi][threadi] != 0) $display("$%d: %h",regi, GPR[regi][threadi]); - // end - // end + end + // $display("^^^^^^^^^^^^^^^^^^^^^^^"); + // for (regi = 0; regi <= 31; regi = regi + 1) begin + // for (threadi = 0; threadi < `NUM_THREADS; threadi = threadi + 1) begin + // if (GPR[regi][threadi] != 0) $display("$%d: %h",regi, GPR[regi][threadi]); + // end + // end + end end assign q1 = GPR[raddr1]; diff --git a/hw/rtl/cache/VX_cache_data.v b/hw/rtl/cache/VX_cache_data.v index 0046070c..241791d8 100644 --- a/hw/rtl/cache/VX_cache_data.v +++ b/hw/rtl/cache/VX_cache_data.v @@ -1,51 +1,46 @@ `include "VX_define.vh" -module VX_cache_data - #( - parameter NUM_IND = 8, - parameter NUM_WORDS_PER_BLOCK = 4, - parameter TAG_SIZE_START = 0, - parameter TAG_SIZE_END = 16, - parameter IND_SIZE_START = 0, - parameter IND_SIZE_END = 7 - ) - ( +module VX_cache_data #( + parameter NUM_IND = 8, + parameter NUM_WORDS_PER_BLOCK = 4, + parameter TAG_SIZE_START = 0, + parameter TAG_SIZE_END = 16, + parameter IND_SIZE_START = 0, + parameter IND_SIZE_END = 7 +) ( input wire clk, rst, // Clock - // `ifdef PARAM - // Addr - input wire[IND_SIZE_END:IND_SIZE_START] addr, - // WE - input wire[NUM_WORDS_PER_BLOCK-1:0][3:0] we, - input wire evict, - // Data - input wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_write, - input wire[TAG_SIZE_END:TAG_SIZE_START] tag_write, +// `ifdef PARAM + // Addr + input wire[IND_SIZE_END:IND_SIZE_START] addr, + // WE + input wire[NUM_WORDS_PER_BLOCK-1:0][3:0] we, + input wire evict, + // Data + input wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_write, + input wire[TAG_SIZE_END:TAG_SIZE_START] tag_write, + + output wire[TAG_SIZE_END:TAG_SIZE_START] tag_use, + output wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_use, + output wire valid_use, + output wire dirty_use +// `else +// // Addr +// input wire[7:0] addr, +// // WE +// input wire[NUM_WORDS_PER_BLOCK-1:0][3:0] we, +// input wire evict, +// // Data +// input wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_write, // Update Data +// input wire[16:0] tag_write, - output wire[TAG_SIZE_END:TAG_SIZE_START] tag_use, - output wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_use, - output wire valid_use, - output wire dirty_use - // `else - // // Addr - // input wire[7:0] addr, - // // WE - // input wire[NUM_WORDS_PER_BLOCK-1:0][3:0] we, - // input wire evict, - // // Data - // input wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_write, // Update Data - // input wire[16:0] tag_write, - - - // output wire[16:0] tag_use, - // output wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_use, - // output wire valid_use, - // output wire dirty_use - // `endif - +// output wire[16:0] tag_use, +// output wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_use, +// output wire valid_use, +// output wire dirty_use +// `endif ); - //localparam NUM_BANKS = CACHE_BANKS; //localparam CACHE_BLOCK_PER_BANK = (CACHE_BLOCK / CACHE_BANKS); // localparam NUM_WORDS_PER_BLOCK = CACHE_BLOCK / (CACHE_BANKS*4); @@ -53,179 +48,165 @@ module VX_cache_data wire currently_writing = (|we); wire update_dirty = ((!dirty_use) && currently_writing) || (evict); - wire dirt_new = evict ? 0 : (|we); +`ifndef SYN + // (3:0) 4 bytes + reg[NUM_WORDS_PER_BLOCK-1:0][3:0][7:0] data[NUM_IND-1:0]; // Actual Data + reg[TAG_SIZE_END:TAG_SIZE_START] tag[NUM_IND-1:0]; + reg valid[NUM_IND-1:0]; + reg dirty[NUM_IND-1:0]; - `ifndef SYN + // 16 bytes + assign data_use = data[addr]; // Read Port + assign tag_use = tag[addr]; + assign valid_use = valid[addr]; + assign dirty_use = dirty[addr]; - // (3:0) 4 bytes - reg[NUM_WORDS_PER_BLOCK-1:0][3:0][7:0] data[NUM_IND-1:0]; // Actual Data - reg[TAG_SIZE_END:TAG_SIZE_START] tag[NUM_IND-1:0]; - reg valid[NUM_IND-1:0]; - reg dirty[NUM_IND-1:0]; + integer f; + integer ini_ind; + always @(posedge clk, posedge rst) begin : update_all + if (rst) begin + for (ini_ind = 0; ini_ind < NUM_IND; ini_ind=ini_ind+1) begin + //data[ini_ind] <= 0; + //tag[ini_ind] <= 0; + valid[ini_ind] <= 0; + //dirty[ini_ind] <= 0; + end + end else begin + if (update_dirty) dirty[addr] <= dirt_new; // WRite Port + if (evict) tag[addr] <= tag_write; + if (evict) valid[addr] <= 1; - - // 16 bytes - assign data_use = data[addr]; // Read Port - assign tag_use = tag[addr]; - assign valid_use = valid[addr]; - assign dirty_use = dirty[addr]; - - integer f; - integer ini_ind; - always @(posedge clk, posedge rst) begin : update_all - if (rst) begin - for (ini_ind = 0; ini_ind < NUM_IND; ini_ind=ini_ind+1) begin - //data[ini_ind] <= 0; - //tag[ini_ind] <= 0; - valid[ini_ind] <= 0; - //dirty[ini_ind] <= 0; + for (f = 0; f < NUM_WORDS_PER_BLOCK; f = f + 1) begin + if (we[f][0]) data[addr][f][0] <= data_write[f][7 :0 ]; + if (we[f][1]) data[addr][f][1] <= data_write[f][15:8 ]; + if (we[f][2]) data[addr][f][2] <= data_write[f][23:16]; + if (we[f][3]) data[addr][f][3] <= data_write[f][31:24]; end - end else begin - if (update_dirty) dirty[addr] <= dirt_new; // WRite Port - if (evict) tag[addr] <= tag_write; - if (evict) valid[addr] <= 1; - - for (f = 0; f < NUM_WORDS_PER_BLOCK; f = f + 1) begin - if (we[f][0]) data[addr][f][0] <= data_write[f][7 :0 ]; - if (we[f][1]) data[addr][f][1] <= data_write[f][15:8 ]; - if (we[f][2]) data[addr][f][2] <= data_write[f][23:16]; - if (we[f][3]) data[addr][f][3] <= data_write[f][31:24]; - end - end end + end - `else +`else - wire[IND_SIZE_END:IND_SIZE_START] use_addr = addr; + wire[IND_SIZE_END:IND_SIZE_START] use_addr = addr; - wire cena = 1; + wire cena = 1; - wire cenb_d = (|we); - wire[NUM_WORDS_PER_BLOCK-1:0][31:0] wdata_d = data_write; - wire[NUM_WORDS_PER_BLOCK-1:0][31:0] write_bit_mask_d; - wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_out_d; - genvar cur_b; - for (cur_b = 0; cur_b < NUM_WORDS_PER_BLOCK; cur_b=cur_b+1) begin - assign write_bit_mask_d[cur_b] = {32{~we[cur_b]}}; - end - assign data_use = data_out_d; + wire cenb_d = (|we); + wire[NUM_WORDS_PER_BLOCK-1:0][31:0] wdata_d = data_write; + wire[NUM_WORDS_PER_BLOCK-1:0][31:0] write_bit_mask_d; + wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_out_d; + genvar cur_b; + for (cur_b = 0; cur_b < NUM_WORDS_PER_BLOCK; cur_b=cur_b+1) begin + assign write_bit_mask_d[cur_b] = {32{~we[cur_b]}}; + end + assign data_use = data_out_d; + + // Using ASIC MEM + /* verilator lint_off PINCONNECTEMPTY */ + rf2_32x128_wm1 data ( + .CENYA(), + .AYA(), + .CENYB(), + .WENYB(), + .AYB(), + .QA(data_out_d), + .SOA(), + .SOB(), + .CLKA(clk), + .CENA(cena), + .AA(use_addr), + .CLKB(clk), + .CENB(cenb_d), + .WENB(write_bit_mask_d), + .AB(use_addr), + .DB(wdata_d), + .EMAA(3'b011), + .EMASA(1'b0), + .EMAB(3'b011), + .TENA(1'b1), + .TCENA(1'b0), + .TAA(5'b0), + .TENB(1'b1), + .TCENB(1'b0), + .TWENB(128'b0), + .TAB(5'b0), + .TDB(128'b0), + .RET1N(1'b1), + .SIA(2'b0), + .SEA(1'b0), + .DFTRAMBYP(1'b0), + .SIB(2'b0), + .SEB(1'b0), + .COLLDISN(1'b1) + ); + /* verilator lint_on PINCONNECTEMPTY */ + + wire[16:0] old_tag; + wire old_valid; + wire old_dirty; + + wire[16:0] new_tag = evict ? tag_write : old_tag; + wire new_valid = evict ? 1 : old_valid; + wire new_dirty = update_dirty ? dirt_new : old_dirty; + + wire cenb_m = (evict || update_dirty); + wire[19-1:0][31:0] write_bit_mask_m = cenb_m ? 19'b0 : 19'b1; + + // Try to fix the error in memory conneciton, modified by Lingjun Zhu on Oct. 28 2019 + // wire[NUM_WORDS_PER_BLOCK-1:0][31:0] wdata_m = {new_tag, new_dirty, new_valid}; + // wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_out_m; + + wire[19-1:0] wdata_m = {new_tag, new_dirty, new_valid}; + + wire[19-1:0] data_out_m; + + assign {old_tag, old_dirty, old_valid} = data_out_m; - // Using ASIC MEM - /* verilator lint_off PINCONNECTEMPTY */ - rf2_32x128_wm1 data ( - .CENYA(), - .AYA(), - .CENYB(), - .WENYB(), - .AYB(), - .QA(data_out_d), - .SOA(), - .SOB(), - .CLKA(clk), - .CENA(cena), - .AA(use_addr), - .CLKB(clk), - .CENB(cenb_d), - .WENB(write_bit_mask_d), - .AB(use_addr), - .DB(wdata_d), - .EMAA(3'b011), - .EMASA(1'b0), - .EMAB(3'b011), - .TENA(1'b1), - .TCENA(1'b0), - .TAA(5'b0), - .TENB(1'b1), - .TCENB(1'b0), - .TWENB(128'b0), - .TAB(5'b0), - .TDB(128'b0), - .RET1N(1'b1), - .SIA(2'b0), - .SEA(1'b0), - .DFTRAMBYP(1'b0), - .SIB(2'b0), - .SEB(1'b0), - .COLLDISN(1'b1) - ); - /* verilator lint_on PINCONNECTEMPTY */ + assign dirty_use = old_dirty; + assign valid_use = old_valid; + assign tag_use = old_tag; - - - - - wire[16:0] old_tag; - wire old_valid; - wire old_dirty; - - wire[16:0] new_tag = evict ? tag_write : old_tag; - wire new_valid = evict ? 1 : old_valid; - wire new_dirty = update_dirty ? dirt_new : old_dirty; - - - wire cenb_m = (evict || update_dirty); - wire[19-1:0][31:0] write_bit_mask_m = cenb_m ? 19'b0 : 19'b1; - - - - // Try to fix the error in memory conneciton, modified by Lingjun Zhu on Oct. 28 2019 - // wire[NUM_WORDS_PER_BLOCK-1:0][31:0] wdata_m = {new_tag, new_dirty, new_valid}; - // wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_out_m; - - wire[19-1:0] wdata_m = {new_tag, new_dirty, new_valid}; - - wire[19-1:0] data_out_m; - - assign {old_tag, old_dirty, old_valid} = data_out_m; - - - assign dirty_use = old_dirty; - assign valid_use = old_valid; - assign tag_use = old_tag; - - /* verilator lint_off PINCONNECTEMPTY */ - rf2_32x19_wm0 meta ( - .CENYA(), - .AYA(), - .CENYB(), - // .WENYB(), - .AYB(), - .QA(data_out_m), - .SOA(), - .SOB(), - .CLKA(clk), - .CENA(cena), - .AA(use_addr), - .CLKB(clk), - .CENB(cenb_m), - // .WENB(write_bit_mask_m), - .AB(use_addr), - .DB(wdata_m), - .EMAA(3'b011), - .EMASA(1'b0), - .EMAB(3'b011), - .TENA(1'b1), - .TCENA(1'b0), - .TAA(5'b0), - .TENB(1'b1), - .TCENB(1'b0), - // .TWENB(128'b0), - .TAB(5'b0), - .TDB(19'b0), - .RET1N(1'b1), - .SIA(2'b0), - .SEA(1'b0), - .DFTRAMBYP(1'b0), - .SIB(2'b0), - .SEB(1'b0), - .COLLDISN(1'b1) - ); - /* verilator lint_on PINCONNECTEMPTY */ - - - `endif + /* verilator lint_off PINCONNECTEMPTY */ + rf2_32x19_wm0 meta ( + .CENYA(), + .AYA(), + .CENYB(), + // .WENYB(), + .AYB(), + .QA(data_out_m), + .SOA(), + .SOB(), + .CLKA(clk), + .CENA(cena), + .AA(use_addr), + .CLKB(clk), + .CENB(cenb_m), + // .WENB(write_bit_mask_m), + .AB(use_addr), + .DB(wdata_m), + .EMAA(3'b011), + .EMASA(1'b0), + .EMAB(3'b011), + .TENA(1'b1), + .TCENA(1'b0), + .TAA(5'b0), + .TENB(1'b1), + .TCENB(1'b0), + // .TWENB(128'b0), + .TAB(5'b0), + .TDB(19'b0), + .RET1N(1'b1), + .SIA(2'b0), + .SEA(1'b0), + .DFTRAMBYP(1'b0), + .SIB(2'b0), + .SEB(1'b0), + .COLLDISN(1'b1) + ); + /* verilator lint_on PINCONNECTEMPTY */ +`endif endmodule diff --git a/hw/rtl/compat/VX_divide.v b/hw/rtl/compat/VX_divide.v index 554f8a3f..65b1ab8f 100644 --- a/hw/rtl/compat/VX_divide.v +++ b/hw/rtl/compat/VX_divide.v @@ -1,21 +1,19 @@ -module VX_divide - #( - parameter WIDTHN=1, - parameter WIDTHD=1, - parameter NREP="UNSIGNED", - parameter DREP="UNSIGNED", - parameter SPEED="MIXED", // "MIXED" or "HIGHEST" - parameter PIPELINE=0 - ) - ( - input clock, aclr, clken, +module VX_divide #( + parameter WIDTHN=1, + parameter WIDTHD=1, + parameter NREP="UNSIGNED", + parameter DREP="UNSIGNED", + parameter SPEED="MIXED", // "MIXED" or "HIGHEST" + parameter PIPELINE=0 +) ( + input clock, aclr, clken, - input [WIDTHN-1:0] numer, - input [WIDTHD-1:0] denom, + input [WIDTHN-1:0] numer, + input [WIDTHD-1:0] denom, - output reg [WIDTHN-1:0] quotient, - output reg [WIDTHD-1:0] remainder - ); + output reg [WIDTHN-1:0] quotient, + output reg [WIDTHD-1:0] remainder +); // synthesis read_comments_as_HDL on // localparam IMPL = "quartus"; @@ -27,14 +25,16 @@ module VX_divide generate if (NREP != DREP) begin + /* verilator lint_off DECLFILENAME */ different_nrep_drep_not_yet_supported non_existing_module(); + /* verilator lint_on DECLFILENAME */ end if (IMPL == "quartus") begin localparam lpm_speed=SPEED == "HIGHEST" ? 9:5; - lpm_divide#( + lpm_divide #( .LPM_WIDTHN(WIDTHN), .LPM_WIDTHD(WIDTHD), .LPM_NREPRESENTATION(NREP), @@ -42,7 +42,7 @@ module VX_divide .LPM_PIPELINE(PIPELINE), .LPM_REMAINDERPOSITIVE("FALSE"), // emulate verilog % operator .MAXIMIZE_SPEED(lpm_speed) - ) quartus_divider( + ) quartus_divider ( .clock(clock), .aclr(aclr), .clken(clken), @@ -51,7 +51,6 @@ module VX_divide .quotient(quotient), .remain(remainder) ); - end else begin diff --git a/hw/rtl/compat/VX_mult.v b/hw/rtl/compat/VX_mult.v index f9a07543..720da1b1 100644 --- a/hw/rtl/compat/VX_mult.v +++ b/hw/rtl/compat/VX_mult.v @@ -1,21 +1,19 @@ -module VX_mult - #( - parameter WIDTHA=1, - parameter WIDTHB=1, - parameter WIDTHP=1, - parameter REP="UNSIGNED", - parameter SPEED="MIXED", // "MIXED" or "HIGHEST" - parameter PIPELINE=0, - parameter FORCE_LE="NO" - ) - ( - input clock, aclr, clken, +module VX_mult #( + parameter WIDTHA=1, + parameter WIDTHB=1, + parameter WIDTHP=1, + parameter REP="UNSIGNED", + parameter SPEED="MIXED", // "MIXED" or "HIGHEST" + parameter PIPELINE=0, + parameter FORCE_LE="NO" +) ( + input clock, aclr, clken, - input [WIDTHA-1:0] dataa, - input [WIDTHB-1:0] datab, + input [WIDTHA-1:0] dataa, + input [WIDTHB-1:0] datab, - output reg [WIDTHP-1:0] result - ); + output reg [WIDTHP-1:0] result +); // synthesis read_comments_as_HDL on // localparam IMPL = "quartus"; @@ -29,10 +27,11 @@ module VX_mult if (IMPL == "quartus") begin - localparam lpm_speed=SPEED == "HIGHEST" ? 10:5; + localparam lpm_speed = (SPEED == "HIGHEST") ? 10 : 5; if (FORCE_LE == "YES") begin - lpm_mult#( + /* verilator lint_off DECLFILENAME */ + lpm_mult #( .LPM_WIDTHA(WIDTHA), .LPM_WIDTHB(WIDTHB), .LPM_WIDTHP(WIDTHP), @@ -40,7 +39,7 @@ module VX_mult .LPM_PIPELINE(PIPELINE), .DSP_BLOCK_BALANCING("LOGIC ELEMENTS"), .MAXIMIZE_SPEED(lpm_speed) - ) quartus_mult( + ) quartus_mult ( .clock(clock), .aclr(aclr), .clken(clken), @@ -48,6 +47,7 @@ module VX_mult .datab(datab), .result(result) ); + /* verilator lint_on DECLFILENAME */ end else begin lpm_mult#( diff --git a/hw/rtl/generic_cache/VX_bank.v b/hw/rtl/generic_cache/VX_bank.v index d20c9b0d..b9ec08b9 100644 --- a/hw/rtl/generic_cache/VX_bank.v +++ b/hw/rtl/generic_cache/VX_bank.v @@ -1,7 +1,6 @@ `include "VX_cache_config.vh" `include "VX_define.vh" -module VX_bank - #( +module VX_bank #( // Size of cache in bytes parameter CACHE_SIZE_BYTES = 1024, // Size of line inside a bank in bytes @@ -17,8 +16,7 @@ module VX_bank // Function ID, {Dcache=0, Icache=1, Sharedmemory=2} parameter FUNC_ID = 0, -// Queues feeding into banks Knobs {1, 2, 4, 8, ...} - + // Queues feeding into banks Knobs {1, 2, 4, 8, ...} // Core Request Queue Size parameter REQQ_SIZE = 8, // Miss Reserv Queue Knob @@ -28,7 +26,7 @@ module VX_bank // Snoop Req Queue parameter SNRQ_SIZE = 8, -// Queues for writebacks Knobs {1, 2, 4, 8, ...} + // Queues for writebacks Knobs {1, 2, 4, 8, ...} // Core Writeback Queue Size parameter CWBQ_SIZE = 8, // Dram Writeback Queue Size @@ -43,12 +41,9 @@ module VX_bank // Fill Invalidator Size {Fill invalidator must be active} parameter FILL_INVALIDAOR_SIZE = 16, -// Dram knobs + // Dram knobs parameter SIMULATED_DRAM_LATENCY_CYCLES = 10 - - - ) - ( +) ( input wire clk, input wire reset, @@ -77,30 +72,29 @@ module VX_bank output wire [31:0] bank_wb_address, // Dram Fill Requests - output wire dram_fill_req, + output wire dram_fill_req_valid, output wire[31:0] dram_fill_req_addr, - output wire dram_because_of_snp, - output wire dram_snp_full, + output wire dram_fill_req_is_snp, input wire dram_fill_req_queue_full, // Dram Fill Response - input wire dram_fill_rsp, - input wire [31:0] dram_fill_addr, - input wire[`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] dram_fill_rsp_data, - output wire dram_fill_accept, + input wire dram_rsp_valid, + input wire [31:0] dram_rsp_addr, + input wire[`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] dram_rsp_data, + output wire dram_rsp_ready, // Dram WB Requests input wire dram_wb_queue_pop, - output wire dram_wb_req, + output wire dram_wb_req_valid, output wire[31:0] dram_wb_req_addr, output wire[`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] dram_wb_req_data, // Snp Request - input wire snp_req, + input wire snp_req_valid, input wire[31:0] snp_req_addr, - output wire snrq_full, + output wire snp_req_full, - output wire snp_fwd, + output wire snp_fwd_valid, output wire[31:0] snp_fwd_addr, input wire snp_fwd_pop ); @@ -111,7 +105,7 @@ module VX_bank if (reset) begin snoop_state <= 0; end else begin - snoop_state <= (snoop_state | snp_req) && ((FUNC_ID == `L2FUNC_ID) || (FUNC_ID == `L3FUNC_ID)); + snoop_state <= (snoop_state | snp_req_valid) && ((FUNC_ID == `L2FUNC_ID) || (FUNC_ID == `L3FUNC_ID)); end end @@ -123,16 +117,20 @@ module VX_bank wire[31:0] snrq_addr_st0; assign snrq_valid_st0 = !snrq_empty; - VX_generic_queue_ll #(.DATAW(32), .SIZE(SNRQ_SIZE)) snr_queue( + + VX_generic_queue_ll #( + .DATAW(32), + .SIZE(SNRQ_SIZE) + ) snr_queue ( .clk (clk), .reset (reset), - .push (snp_req), + .push (snp_req_valid), .in_data (snp_req_addr), .pop (snrq_pop), .out_data(snrq_addr_st0), .empty (snrq_empty), - .full (snrq_full) - ); + .full (snp_req_full) + ); wire dfpq_pop; wire dfpq_empty; @@ -140,13 +138,16 @@ module VX_bank wire[31:0] dfpq_addr_st0; wire[`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] dfpq_filldata_st0; - assign dram_fill_accept = !dfpq_full; + assign dram_rsp_ready = !dfpq_full; - VX_generic_queue_ll #(.DATAW(32+(`BANK_LINE_WORDS*`WORD_SIZE)), .SIZE(DFPQ_SIZE)) dfp_queue( + VX_generic_queue_ll #( + .DATAW(32+(`BANK_LINE_WORDS*`WORD_SIZE)), + .SIZE(DFPQ_SIZE) + ) dfp_queue ( .clk (clk), .reset (reset), - .push (dram_fill_rsp), - .in_data ({dram_fill_addr, dram_fill_rsp_data}), + .push (dram_rsp_valid), + .in_data ({dram_rsp_addr, dram_rsp_data}), .pop (dfpq_pop), .out_data({dfpq_addr_st0, dfpq_filldata_st0}), .empty (dfpq_empty), @@ -186,9 +187,7 @@ module VX_bank .LLVQ_SIZE (LLVQ_SIZE), .FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE), .SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES) - ) - req_queue - ( + ) req_queue ( .clk (clk), .reset (reset), // Enqueue @@ -217,7 +216,7 @@ module VX_bank .reqq_req_pc_st0 (reqq_req_pc_st0), .reqq_empty (reqq_empty), .reqq_full (reqq_full) - ); + ); wire mrvq_pop; wire mrvq_full; @@ -265,9 +264,7 @@ module VX_bank .LLVQ_SIZE (LLVQ_SIZE), .FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE), .SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES) - ) - mrvq_queue - ( + ) mrvq_queue ( .clk (clk), .reset (reset), // Enqueue @@ -300,35 +297,39 @@ module VX_bank .miss_resrv_warp_num_st0 (mrvq_warp_num_st0), .miss_resrv_mem_read_st0 (mrvq_mem_read_st0), .miss_resrv_mem_write_st0(mrvq_mem_write_st0) - ); + ); wire stall_bank_pipe; reg is_fill_in_pipe; wire valid_st1 [STAGE_1_CYCLES-1:0]; wire is_fill_st1 [STAGE_1_CYCLES-1:0]; +/* verilator lint_off UNUSED */ wire going_to_write_st1[STAGE_1_CYCLES-1:0]; +/* verilator lint_on UNUSED */ wire [31:0] addr_st1 [STAGE_1_CYCLES-1:0]; integer p_stage; always @(*) begin is_fill_in_pipe = 0; for (p_stage = 0; p_stage < STAGE_1_CYCLES; p_stage=p_stage+1) begin - if (is_fill_st1[p_stage]) is_fill_in_pipe = 1; + if (is_fill_st1[p_stage]) begin + is_fill_in_pipe = 1; + end end - if (is_fill_st2) is_fill_in_pipe = 1; + if (is_fill_st2) begin + is_fill_in_pipe = 1; + end end -// assign is_fill_in_pipe = (|is_fill_st1) || is_fill_st2; + // assign is_fill_in_pipe = (|is_fill_st1) || is_fill_st2; assign mrvq_pop = mrvq_valid_st0 && !stall_bank_pipe; assign dfpq_pop = !mrvq_pop && !dfpq_empty && !stall_bank_pipe; assign reqq_pop = !mrvq_stop && !mrvq_pop && !dfpq_pop && !reqq_empty && reqq_req_st0 && !stall_bank_pipe && !is_fill_st1[0] && !is_fill_in_pipe; assign snrq_pop = !reqq_pop && !reqq_pop && !mrvq_pop && !dfpq_pop && snrq_valid_st0 && !stall_bank_pipe; - integer st1_cycle; - wire qual_is_fill_st0; wire qual_valid_st0; wire [31:0] qual_addr_st0; @@ -384,13 +385,15 @@ module VX_bank reqq_pop ? reqq_req_writeword_st0 : 0; - VX_generic_register #(.N( 1 + 1 + 1 + `WORD_SIZE + 32 + `REQ_INST_META_SIZE + (`BANK_LINE_WORDS*`WORD_SIZE) + 1 + 32)) s0_1_c0 ( - .clk (clk), - .reset(reset), - .stall(stall_bank_pipe), - .flush(0), - .in ({qual_is_snp , qual_going_to_write_st0, qual_valid_st0, qual_addr_st0, qual_writeword_st0, qual_inst_meta_st0, qual_is_fill_st0, qual_writedata_st0, qual_pc_st0 }), - .out ({is_snp_st1[0], going_to_write_st1[0] , valid_st1[0] , addr_st1[0] , writeword_st1[0] , inst_meta_st1[0] , is_fill_st1[0] , writedata_st1[0] , pc_st1[0]}) + VX_generic_register #( + .N( 1 + 1 + 1 + `WORD_SIZE + 32 + `REQ_INST_META_SIZE + (`BANK_LINE_WORDS*`WORD_SIZE) + 1 + 32) + ) s0_1_c0 ( + .clk (clk), + .reset (reset), + .stall (stall_bank_pipe), + .flush (0), + .in ({qual_is_snp , qual_going_to_write_st0, qual_valid_st0, qual_addr_st0, qual_writeword_st0, qual_inst_meta_st0, qual_is_fill_st0, qual_writedata_st0, qual_pc_st0 }), + .out ({is_snp_st1[0], going_to_write_st1[0] , valid_st1[0] , addr_st1[0] , writeword_st1[0] , inst_meta_st1[0] , is_fill_st1[0] , writedata_st1[0] , pc_st1[0]}) ); genvar curr_stage; @@ -414,14 +417,14 @@ module VX_bank wire miss_st1e; wire dirty_st1e; wire[31:0] pc_st1e; - - +/* verilator lint_off UNUSED */ wire [4:0] rd_st1e; wire [1:0] wb_st1e; wire [`NW_BITS-1:0] warp_num_st1e; - wire [2:0] mem_read_st1e; - wire [2:0] mem_write_st1e; wire [`LOG2UP(NUM_REQUESTS)-1:0] tid_st1e; +/* verilator lint_on UNUSED */ + wire [2:0] mem_read_st1e; + wire [2:0] mem_write_st1e; wire fill_saw_dirty_st1e; wire is_snp_st1e; @@ -429,7 +432,6 @@ module VX_bank assign pc_st1e = pc_st1[STAGE_1_CYCLES-1]; assign {rd_st1e, wb_st1e, warp_num_st1e, mem_read_st1e, mem_write_st1e, tid_st1e} = inst_meta_st1[STAGE_1_CYCLES-1]; - VX_tag_data_access #( .CACHE_SIZE_BYTES (CACHE_SIZE_BYTES), .BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES), @@ -448,9 +450,7 @@ module VX_bank .LLVQ_SIZE (LLVQ_SIZE), .FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE), .SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES) - ) - VX_tag_data_access - ( + ) vx_tag_data_access ( .clk (clk), .reset (reset), .stall (stall_bank_pipe), @@ -494,16 +494,16 @@ module VX_bank wire is_snp_st2; wire [31:0] pc_st2; - - VX_generic_register #(.N( 1+1+1+1+32+`WORD_SIZE+`WORD_SIZE+(`BANK_LINE_WORDS * `WORD_SIZE) + `REQ_INST_META_SIZE + `TAG_SELECT_NUM_BITS + 32 + 2)) st_1e_2 ( + VX_generic_register #( + .N( 1+1+1+1+32+`WORD_SIZE+`WORD_SIZE+(`BANK_LINE_WORDS * `WORD_SIZE) + `REQ_INST_META_SIZE + `TAG_SELECT_NUM_BITS + 32 + 2) + ) st_1e_2 ( .clk (clk), .reset(reset), .stall(stall_bank_pipe), .flush(0), .in ({is_snp_st1e, fill_saw_dirty_st1e, is_fill_st1[STAGE_1_CYCLES-1] , qual_valid_st1e_2, addr_st1[STAGE_1_CYCLES-1], writeword_st1[STAGE_1_CYCLES-1], readword_st1e, readdata_st1e, readtag_st1e, miss_st1e, dirty_st1e, pc_st1e, inst_meta_st1[STAGE_1_CYCLES-1]}), .out ({is_snp_st2 , fill_saw_dirty_st2 , is_fill_st2 , valid_st2 , addr_st2 , writeword_st2 , readword_st2 , readdata_st2 , readtag_st2 , miss_st2 , dirty_st2 , pc_st2 , inst_meta_st2 }) - ); - + ); wire should_flush; wire dwbq_push; @@ -520,7 +520,6 @@ module VX_bank assign miss_add_data = writeword_st2; assign {miss_add_rd, miss_add_wb, miss_add_warp_num, miss_add_mem_read, miss_add_mem_write, miss_add_tid} = inst_meta_st2; - // Enqueue to CWB Queue wire cwbq_push = (valid_st2 && !miss_st2) && !cwbq_full && !((FUNC_ID == `L2FUNC_ID) && (miss_add_wb == 0)) && !((is_snp_st2 && valid_st2 && ffsq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_queue_full)); wire [`WORD_SIZE_RNG] cwbq_data = readword_st2; @@ -532,7 +531,10 @@ module VX_bank wire cwbq_empty; assign bank_wb_valid = !cwbq_empty; - VX_generic_queue_ll #(.DATAW( `LOG2UP(NUM_REQUESTS) + 5 + 2 + (`NW_BITS-1+1) + `WORD_SIZE + 32 + 32), .SIZE(CWBQ_SIZE)) cwb_queue( + VX_generic_queue_ll #( + .DATAW( `LOG2UP(NUM_REQUESTS) + 5 + 2 + (`NW_BITS-1+1) + `WORD_SIZE + 32 + 32), + .SIZE(CWBQ_SIZE) + ) cwb_queue( .clk (clk), .reset (reset), @@ -543,13 +545,13 @@ module VX_bank .out_data({bank_wb_tid, bank_wb_rd, bank_wb_wb, bank_wb_warp_num, bank_wb_data, bank_wb_pc, bank_wb_address}), .empty (cwbq_empty), .full (cwbq_full) - ); + ); assign should_flush = snoop_state && valid_st2 && (miss_add_mem_write != `NO_MEM_WRITE) && !is_snp_st2 && !is_fill_st2; // Enqueue to DWB Queue - assign dwbq_push = ((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2 || should_flush) && !dwbq_full && !((is_snp_st2 && valid_st2 && ffsq_full) ||((valid_st2 && !miss_st2) && cwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_queue_full)); - wire[31:0] dwbq_req_addr; - wire dwbq_empty; + assign dwbq_push = ((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2 || should_flush) && !dwbq_full && !((is_snp_st2 && valid_st2 && ffsq_full) ||((valid_st2 && !miss_st2) && cwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_queue_full)); + wire[31:0] dwbq_req_addr; + wire dwbq_empty; wire[`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] dwbq_req_data; if ((FUNC_ID == `L2FUNC_ID) || (FUNC_ID == `L3FUNC_ID)) begin @@ -560,10 +562,9 @@ module VX_bank assign dwbq_req_addr = {readtag_st2, addr_st2[`LINE_SELECT_ADDR_END:0]} & `BASE_ADDR_MASK; end - - wire possible_fill = valid_st2 && miss_st2 && !dram_fill_req_queue_full && !is_snp_st2; wire[31:0] fill_invalidator_addr = addr_st2 & `BASE_ADDR_MASK; + VX_fill_invalidator #( .CACHE_SIZE_BYTES (CACHE_SIZE_BYTES), .BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES), @@ -581,9 +582,7 @@ module VX_bank .LLVQ_SIZE (LLVQ_SIZE), .FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE), .SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES) - ) - VX_fill_invalidator - ( + ) vx_fill_invalidator ( .clk (clk), .reset (reset), .possible_fill (possible_fill), @@ -591,16 +590,19 @@ module VX_bank .fill_addr (fill_invalidator_addr), .invalidate_fill (invalidate_fill) - ); + ); - // Enqueu in dram_fill_req - assign dram_fill_req = possible_fill && !invalidate_fill; - assign dram_because_of_snp = is_snp_st2 && valid_st2 && miss_st2; - assign dram_snp_full = snrq_full && snp_req; - assign dram_fill_req_addr = addr_st2 & `BASE_ADDR_MASK; + // Enqueue in dram_fill_req + assign dram_fill_req_valid = possible_fill && !invalidate_fill; + assign dram_fill_req_is_snp = is_snp_st2 && valid_st2 && miss_st2; + assign dram_fill_req_addr = addr_st2 & `BASE_ADDR_MASK; - assign dram_wb_req = !dwbq_empty; - VX_generic_queue_ll #(.DATAW( 32 + (`BANK_LINE_WORDS * `WORD_SIZE)), .SIZE(DWBQ_SIZE)) dwb_queue( + assign dram_wb_req_valid = !dwbq_empty; + + VX_generic_queue_ll #( + .DATAW( 32 + (`BANK_LINE_WORDS * `WORD_SIZE)), + .SIZE(DWBQ_SIZE) + ) dwb_queue ( .clk (clk), .reset (reset), @@ -611,14 +613,18 @@ module VX_bank .out_data({dram_wb_req_addr, dram_wb_req_data}), .empty (dwbq_empty), .full (dwbq_full) - ); + ); wire snp_fwd_push; wire ffsq_empty; - assign snp_fwd_push = is_snp_st2 && valid_st2 && !ffsq_full && !(((valid_st2 && !miss_st2) && cwbq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_queue_full)); - assign snp_fwd = !ffsq_empty; - VX_generic_queue_ll #(.DATAW(32), .SIZE(FFSQ_SIZE)) ffs_queue( + assign snp_fwd_push = is_snp_st2 && valid_st2 && !ffsq_full && !(((valid_st2 && !miss_st2) && cwbq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_queue_full)); + assign snp_fwd_valid = !ffsq_empty; + + VX_generic_queue_ll #( + .DATAW(32), + .SIZE(FFSQ_SIZE) + ) ffs_queue ( .clk (clk), .reset (reset), .push (snp_fwd_push), @@ -627,7 +633,7 @@ module VX_bank .out_data({snp_fwd_addr}), .empty (ffsq_empty), .full (ffsq_full) - ); + ); assign stall_bank_pipe = (is_snp_st2 && valid_st2 && ffsq_full) || ((valid_st2 && !miss_st2) && cwbq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_queue_full); diff --git a/hw/rtl/generic_cache/VX_cache.v b/hw/rtl/generic_cache/VX_cache.v index d8211a70..8af42dc1 100644 --- a/hw/rtl/generic_cache/VX_cache.v +++ b/hw/rtl/generic_cache/VX_cache.v @@ -1,7 +1,6 @@ `include "VX_cache_config.vh" -module VX_cache - #( +module VX_cache #( // Size of cache in bytes parameter CACHE_SIZE_BYTES = 1024, // Size of line inside a bank in bytes @@ -17,7 +16,7 @@ module VX_cache // Function ID, {Dcache=0, Icache=1, Sharedmemory=2} parameter FUNC_ID = 3, -// Queues feeding into banks Knobs {1, 2, 4, 8, ...} + // Queues feeding into banks Knobs {1, 2, 4, 8, ...} // Core Request Queue Size parameter REQQ_SIZE = 8, @@ -28,7 +27,7 @@ module VX_cache // Snoop Req Queue parameter SNRQ_SIZE = 8, -// Queues for writebacks Knobs {1, 2, 4, 8, ...} + // Queues for writebacks Knobs {1, 2, 4, 8, ...} // Core Writeback Queue Size parameter CWBQ_SIZE = 8, // Dram Writeback Queue Size @@ -47,21 +46,18 @@ module VX_cache parameter PRFQ_SIZE = 64, parameter PRFQ_STRIDE = 0, -// Dram knobs + // Dram knobs parameter SIMULATED_DRAM_LATENCY_CYCLES = 10 - - - ) - ( + ) ( input wire clk, input wire reset, - // Req Info + // Req Info input wire [NUM_REQUESTS-1:0] core_req_valid, input wire [NUM_REQUESTS-1:0][31:0] core_req_addr, input wire [NUM_REQUESTS-1:0][`WORD_SIZE_RNG] core_req_writedata, - input wire[NUM_REQUESTS-1:0][2:0] core_req_mem_read, - input wire[NUM_REQUESTS-1:0][2:0] core_req_mem_write, + input wire [NUM_REQUESTS-1:0][2:0] core_req_mem_read, + input wire [NUM_REQUESTS-1:0][2:0] core_req_mem_write, // Req meta input wire [4:0] core_req_rd, @@ -80,39 +76,31 @@ module VX_cache output wire [NUM_REQUESTS-1:0][31:0] core_wb_pc, output wire [NUM_REQUESTS-1:0][31:0] core_wb_address, - // Dram Fill Response - input wire dram_fill_rsp, - input wire [31:0] dram_fill_rsp_addr, - input wire [`IBANK_LINE_WORDS-1:0][31:0] dram_fill_rsp_data, - output wire dram_fill_accept, + input wire dram_rsp_valid, + input wire [31:0] dram_rsp_addr, + input wire [`IBANK_LINE_WORDS-1:0][31:0] dram_rsp_data, + output wire dram_rsp_ready, // Dram request - output wire dram_req, - output wire dram_req_write, output wire dram_req_read, + output wire dram_req_write, output wire [31:0] dram_req_addr, - output wire [31:0] dram_req_size, output wire [`IBANK_LINE_WORDS-1:0][31:0] dram_req_data, - output wire dram_req_because_of_wb, - input wire dram_req_delay, - - output wire dram_snp_full, - + input wire dram_req_full, + // Snoop Req - input wire snp_req, - input wire[31:0] snp_req_addr, - output wire snp_req_delay, + input wire snp_req_valid, + input wire [31:0] snp_req_addr, + output wire snp_req_full, // Snoop Forward - output wire snp_fwd, - output wire[31:0] snp_fwd_addr, - input wire snp_fwd_delay - + output wire snp_fwd_valid, + output wire [31:0] snp_fwd_addr, + input wire snp_fwd_full ); - wire [NUM_BANKS-1:0][NUM_REQUESTS-1:0] per_bank_valids; wire [NUM_BANKS-1:0] per_bank_wb_pop; wire [NUM_BANKS-1:0] per_bank_wb_valid; @@ -124,104 +112,90 @@ module VX_cache wire [NUM_BANKS-1:0][31:0] per_bank_wb_pc; wire [NUM_BANKS-1:0][31:0] per_bank_wb_address; - wire dfqq_full; - wire[NUM_BANKS-1:0] per_bank_dram_fill_req; - wire[NUM_BANKS-1:0][31:0] per_bank_dram_fill_req_addr; - wire[NUM_BANKS-1:0] per_bank_dram_fill_accept; + wire [NUM_BANKS-1:0] per_bank_dram_fill_req_valid; + wire [NUM_BANKS-1:0][31:0] per_bank_dram_fill_req_addr; + /* verilator lint_off UNUSED */ + wire [NUM_BANKS-1:0] per_bank_dram_fill_req_is_snp; +/* verilator lint_on UNUSED */ + wire [NUM_BANKS-1:0] per_bank_dram_rsp_ready; - wire[NUM_BANKS-1:0] per_bank_dram_wb_queue_pop; - wire[NUM_BANKS-1:0] per_bank_dram_wb_req; - wire[NUM_BANKS-1:0] per_bank_dram_because_of_snp; - wire[NUM_BANKS-1:0][31:0] per_bank_dram_wb_req_addr; - wire[NUM_BANKS-1:0][`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] per_bank_dram_wb_req_data; + wire [NUM_BANKS-1:0] per_bank_dram_wb_queue_pop; + wire [NUM_BANKS-1:0] per_bank_dram_wb_req_valid; + wire [NUM_BANKS-1:0][31:0] per_bank_dram_wb_req_addr; + wire [NUM_BANKS-1:0][`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] per_bank_dram_wb_req_data; - wire[NUM_BANKS-1:0] per_bank_reqq_full; - - wire[NUM_BANKS-1:0] per_bank_snrq_full; - - wire[NUM_BANKS-1:0] per_bank_snp_fwd; - wire[NUM_BANKS-1:0][31:0] per_bank_snp_fwd_addr; - wire[NUM_BANKS-1:0] per_bank_snp_fwd_pop; + wire [NUM_BANKS-1:0] per_bank_reqq_full; + wire [NUM_BANKS-1:0] per_bank_snrq_full; + wire [NUM_BANKS-1:0] per_bank_snp_fwd; + wire [NUM_BANKS-1:0][31:0] per_bank_snp_fwd_addr; + wire [NUM_BANKS-1:0] per_bank_snp_fwd_pop; assign delay_req = (|per_bank_reqq_full); + assign snp_req_full = (|per_bank_snrq_full); - - assign snp_req_delay = (|per_bank_snrq_full); - - - // assign dram_fill_accept = (NUM_BANKS == 1) ? per_bank_dram_fill_accept[0] : per_bank_dram_fill_accept[dram_fill_rsp_addr[`BANK_SELECT_ADDR_RNG]]; - assign dram_fill_accept = (|per_bank_dram_fill_accept); + // assign dram_rsp_ready = (NUM_BANKS == 1) ? per_bank_dram_rsp_ready[0] : per_bank_dram_rsp_ready[dram_rsp_addr[`BANK_SELECT_ADDR_RNG]]; + assign dram_rsp_ready = (|per_bank_dram_rsp_ready); VX_cache_dram_req_arb #( - .CACHE_SIZE_BYTES (CACHE_SIZE_BYTES), - .BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES), - .NUM_BANKS (NUM_BANKS), - .WORD_SIZE_BYTES (WORD_SIZE_BYTES), - .NUM_REQUESTS (NUM_REQUESTS), - .STAGE_1_CYCLES (STAGE_1_CYCLES), - .REQQ_SIZE (REQQ_SIZE), - .MRVQ_SIZE (MRVQ_SIZE), - .DFPQ_SIZE (DFPQ_SIZE), - .SNRQ_SIZE (SNRQ_SIZE), - .CWBQ_SIZE (CWBQ_SIZE), - .DWBQ_SIZE (DWBQ_SIZE), - .DFQQ_SIZE (DFQQ_SIZE), - .LLVQ_SIZE (LLVQ_SIZE), - .FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE), - .PRFQ_SIZE (PRFQ_SIZE), - .PRFQ_STRIDE (PRFQ_STRIDE), - .SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES) - ) - VX_cache_dram_req_arb - ( - .clk (clk), - .reset (reset), - .dfqq_full (dfqq_full), - .per_bank_dram_fill_req (per_bank_dram_fill_req), - .per_bank_dram_fill_req_addr(per_bank_dram_fill_req_addr), - .per_bank_dram_wb_queue_pop (per_bank_dram_wb_queue_pop), - .per_bank_dram_wb_req (per_bank_dram_wb_req), - .per_bank_dram_because_of_snp(per_bank_dram_because_of_snp), - .per_bank_dram_wb_req_addr (per_bank_dram_wb_req_addr), - .per_bank_dram_wb_req_data (per_bank_dram_wb_req_data), - .dram_req (dram_req), - .dram_req_write (dram_req_write), - .dram_req_read (dram_req_read), - .dram_req_addr (dram_req_addr), - .dram_req_size (dram_req_size), - .dram_req_data (dram_req_data), - .dram_req_because_of_wb (dram_req_because_of_wb), - .dram_req_delay (dram_req_delay) - ); - + .CACHE_SIZE_BYTES (CACHE_SIZE_BYTES), + .BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES), + .NUM_BANKS (NUM_BANKS), + .WORD_SIZE_BYTES (WORD_SIZE_BYTES), + .NUM_REQUESTS (NUM_REQUESTS), + .STAGE_1_CYCLES (STAGE_1_CYCLES), + .REQQ_SIZE (REQQ_SIZE), + .MRVQ_SIZE (MRVQ_SIZE), + .DFPQ_SIZE (DFPQ_SIZE), + .SNRQ_SIZE (SNRQ_SIZE), + .CWBQ_SIZE (CWBQ_SIZE), + .DWBQ_SIZE (DWBQ_SIZE), + .DFQQ_SIZE (DFQQ_SIZE), + .LLVQ_SIZE (LLVQ_SIZE), + .FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE), + .PRFQ_SIZE (PRFQ_SIZE), + .PRFQ_STRIDE (PRFQ_STRIDE), + .SIMULATED_DRAM_LATENCY_CYCLES (SIMULATED_DRAM_LATENCY_CYCLES) + ) vx_cache_dram_req_arb ( + .clk (clk), + .reset (reset), + .dfqq_full (dfqq_full), + .per_bank_dram_fill_req_valid(per_bank_dram_fill_req_valid), + .per_bank_dram_fill_req_addr (per_bank_dram_fill_req_addr), + .per_bank_dram_wb_queue_pop (per_bank_dram_wb_queue_pop), + .per_bank_dram_wb_req_valid (per_bank_dram_wb_req_valid), + .per_bank_dram_wb_req_addr (per_bank_dram_wb_req_addr), + .per_bank_dram_wb_req_data (per_bank_dram_wb_req_data), + .dram_req_read (dram_req_read), + .dram_req_write (dram_req_write), + .dram_req_addr (dram_req_addr), + .dram_req_data (dram_req_data), + .dram_req_full (dram_req_full) + ); VX_cache_core_req_bank_sel #( - .CACHE_SIZE_BYTES (CACHE_SIZE_BYTES), - .BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES), - .NUM_BANKS (NUM_BANKS), - .WORD_SIZE_BYTES (WORD_SIZE_BYTES), - .NUM_REQUESTS (NUM_REQUESTS), - .STAGE_1_CYCLES (STAGE_1_CYCLES), - .REQQ_SIZE (REQQ_SIZE), - .MRVQ_SIZE (MRVQ_SIZE), - .DFPQ_SIZE (DFPQ_SIZE), - .SNRQ_SIZE (SNRQ_SIZE), - .CWBQ_SIZE (CWBQ_SIZE), - .DWBQ_SIZE (DWBQ_SIZE), - .DFQQ_SIZE (DFQQ_SIZE), - .LLVQ_SIZE (LLVQ_SIZE), - .FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE), - .SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES) - ) - VX_cache_core_req_bank_sell - ( - .core_req_valid (core_req_valid), - .core_req_addr (core_req_addr), - .per_bank_valids(per_bank_valids) - ); - + .CACHE_SIZE_BYTES (CACHE_SIZE_BYTES), + .BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES), + .NUM_BANKS (NUM_BANKS), + .WORD_SIZE_BYTES (WORD_SIZE_BYTES), + .NUM_REQUESTS (NUM_REQUESTS), + .STAGE_1_CYCLES (STAGE_1_CYCLES), + .REQQ_SIZE (REQQ_SIZE), + .MRVQ_SIZE (MRVQ_SIZE), + .DFPQ_SIZE (DFPQ_SIZE), + .SNRQ_SIZE (SNRQ_SIZE), + .CWBQ_SIZE (CWBQ_SIZE), + .DWBQ_SIZE (DWBQ_SIZE), + .DFQQ_SIZE (DFQQ_SIZE), + .LLVQ_SIZE (LLVQ_SIZE), + .FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE), + .SIMULATED_DRAM_LATENCY_CYCLES (SIMULATED_DRAM_LATENCY_CYCLES) + ) vx_cache_core_req_bank_sell ( + .core_req_valid (core_req_valid), + .core_req_addr (core_req_addr), + .per_bank_valids (per_bank_valids) + ); VX_cache_wb_sel_merge #( .CACHE_SIZE_BYTES (CACHE_SIZE_BYTES), @@ -241,9 +215,7 @@ module VX_cache .LLVQ_SIZE (LLVQ_SIZE), .FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE), .SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES) - ) - VX_cache_core_wb_sel_merge - ( + ) vx_cache_core_wb_sel_merge ( .per_bank_wb_valid (per_bank_wb_valid), .per_bank_wb_tid (per_bank_wb_tid), .per_bank_wb_rd (per_bank_wb_rd), @@ -262,28 +234,27 @@ module VX_cache .core_wb_readdata (core_wb_readdata), .core_wb_address (core_wb_address), .core_wb_pc (core_wb_pc) - ); - - - + ); // Snoop Forward Logic - VX_snp_fwd_arb #(.NUM_BANKS(NUM_BANKS)) VX_snp_fwd_arb( + VX_snp_fwd_arb #( + .NUM_BANKS(NUM_BANKS) + ) vx_snp_fwd_arb( .per_bank_snp_fwd (per_bank_snp_fwd), .per_bank_snp_fwd_addr(per_bank_snp_fwd_addr), .per_bank_snp_fwd_pop (per_bank_snp_fwd_pop), - .snp_fwd (snp_fwd), + .snp_fwd_valid (snp_fwd_valid), .snp_fwd_addr (snp_fwd_addr), - .snp_fwd_delay (snp_fwd_delay) - ); + .snp_fwd_full (snp_fwd_full) + ); // Snoop Forward Logic genvar curr_bank; generate for (curr_bank = 0; curr_bank < NUM_BANKS; curr_bank=curr_bank+1) begin - wire [NUM_REQUESTS-1:0] curr_bank_valids; - wire [NUM_REQUESTS-1:0][31:0] curr_bank_addr; + wire [NUM_REQUESTS-1:0] curr_bank_valids; + wire [NUM_REQUESTS-1:0][31:0] curr_bank_addr; wire [NUM_REQUESTS-1:0][`WORD_SIZE_RNG] curr_bank_writedata; wire [4:0] curr_bank_rd; wire [NUM_REQUESTS-1:0][1:0] curr_bank_wb; @@ -294,7 +265,7 @@ module VX_cache wire curr_bank_wb_pop; wire curr_bank_wb_valid; - wire [`LOG2UP(NUM_REQUESTS)-1:0] curr_bank_wb_tid; + wire [`LOG2UP(NUM_REQUESTS)-1:0] curr_bank_wb_tid; wire [31:0] curr_bank_wb_pc; wire [4:0] curr_bank_wb_rd; wire [1:0] curr_bank_wb_wb; @@ -302,19 +273,18 @@ module VX_cache wire [`WORD_SIZE_RNG] curr_bank_wb_data; wire [31:0] curr_bank_wb_address; - wire curr_bank_dram_fill_rsp; - wire [31:0] curr_bank_dram_fill_rsp_addr; - wire [`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] curr_bank_dram_fill_rsp_data; - wire curr_bank_dram_fill_accept; + wire curr_bank_dram_rsp_valid; + wire [31:0] curr_bank_dram_rsp_addr; + wire [`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] curr_bank_dram_rsp_data; + wire curr_bank_dram_rsp_ready; wire curr_bank_dfqq_full; - wire curr_bank_dram_fill_req; - wire curr_bank_dram_because_of_snp; - wire curr_bank_dram_snp_full; + wire curr_bank_dram_fill_req_valid; + wire curr_bank_dram_fill_req_is_snp; wire[31:0] curr_bank_dram_fill_req_addr; wire curr_bank_dram_wb_queue_pop; - wire curr_bank_dram_wb_req; + wire curr_bank_dram_wb_req_valid; wire[31:0] curr_bank_dram_wb_req_addr; wire[`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] curr_bank_dram_wb_req_data; @@ -326,9 +296,7 @@ module VX_cache wire curr_bank_snp_fwd; wire[31:0] curr_bank_snp_fwd_addr; wire curr_bank_snp_fwd_pop; - wire curr_bank_snrq_full; - - + wire curr_bank_snp_req_full; // Core Req assign curr_bank_valids = per_bank_valids[curr_bank]; @@ -354,56 +322,53 @@ module VX_cache assign per_bank_wb_address [curr_bank] = curr_bank_wb_address; // Dram fill request - assign curr_bank_dfqq_full = dfqq_full; - assign per_bank_dram_fill_req[curr_bank] = curr_bank_dram_fill_req; - assign per_bank_dram_fill_req_addr[curr_bank] = curr_bank_dram_fill_req_addr; + assign curr_bank_dfqq_full = dfqq_full; + assign per_bank_dram_fill_req_valid[curr_bank] = curr_bank_dram_fill_req_valid; + assign per_bank_dram_fill_req_addr[curr_bank] = curr_bank_dram_fill_req_addr; + assign per_bank_dram_fill_req_is_snp[curr_bank] = curr_bank_dram_fill_req_is_snp; // Dram fill response - assign curr_bank_dram_fill_rsp = (NUM_BANKS == 1) || (dram_fill_rsp && (curr_bank_dram_fill_rsp_addr[`BANK_SELECT_ADDR_RNG] == curr_bank)); - assign curr_bank_dram_fill_rsp_addr = dram_fill_rsp_addr; - assign curr_bank_dram_fill_rsp_data = dram_fill_rsp_data; - assign per_bank_dram_fill_accept[curr_bank] = curr_bank_dram_fill_accept; + assign curr_bank_dram_rsp_valid = (NUM_BANKS == 1) || (dram_rsp_valid && (curr_bank_dram_rsp_addr[`BANK_SELECT_ADDR_RNG] == curr_bank)); + assign curr_bank_dram_rsp_addr = dram_rsp_addr; + assign curr_bank_dram_rsp_data = dram_rsp_data; + assign per_bank_dram_rsp_ready[curr_bank] = curr_bank_dram_rsp_ready; // Dram writeback request assign curr_bank_dram_wb_queue_pop = per_bank_dram_wb_queue_pop[curr_bank]; - assign per_bank_dram_wb_req[curr_bank] = curr_bank_dram_wb_req; - assign per_bank_dram_because_of_snp[curr_bank] = curr_bank_dram_because_of_snp; + assign per_bank_dram_wb_req_valid[curr_bank] = curr_bank_dram_wb_req_valid; assign per_bank_dram_wb_req_addr[curr_bank] = curr_bank_dram_wb_req_addr; assign per_bank_dram_wb_req_data[curr_bank] = curr_bank_dram_wb_req_data; // Snoop Request - assign curr_bank_snp_req = snp_req && (snp_req_addr[`BANK_SELECT_ADDR_RNG] == curr_bank); - assign curr_bank_snp_req_addr = snp_req_addr; - assign per_bank_snrq_full[curr_bank] = curr_bank_snrq_full; + assign curr_bank_snp_req = snp_req_valid && (snp_req_addr[`BANK_SELECT_ADDR_RNG] == curr_bank); + assign curr_bank_snp_req_addr = snp_req_addr; + assign per_bank_snrq_full[curr_bank] = curr_bank_snp_req_full; // Snoop Fwd assign curr_bank_snp_fwd_pop = per_bank_snp_fwd_pop[curr_bank]; assign per_bank_snp_fwd[curr_bank] = curr_bank_snp_fwd; assign per_bank_snp_fwd_addr[curr_bank] = curr_bank_snp_fwd_addr; - VX_bank #( - .CACHE_SIZE_BYTES (CACHE_SIZE_BYTES), - .BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES), - .NUM_BANKS (NUM_BANKS), - .WORD_SIZE_BYTES (WORD_SIZE_BYTES), - .NUM_REQUESTS (NUM_REQUESTS), - .STAGE_1_CYCLES (STAGE_1_CYCLES), - .FUNC_ID (FUNC_ID), - .REQQ_SIZE (REQQ_SIZE), - .MRVQ_SIZE (MRVQ_SIZE), - .DFPQ_SIZE (DFPQ_SIZE), - .SNRQ_SIZE (SNRQ_SIZE), - .CWBQ_SIZE (CWBQ_SIZE), - .DWBQ_SIZE (DWBQ_SIZE), - .DFQQ_SIZE (DFQQ_SIZE), - .LLVQ_SIZE (LLVQ_SIZE), - .FFSQ_SIZE (FFSQ_SIZE), - .FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE), - .SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES) - ) - bank - ( + .CACHE_SIZE_BYTES (CACHE_SIZE_BYTES), + .BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES), + .NUM_BANKS (NUM_BANKS), + .WORD_SIZE_BYTES (WORD_SIZE_BYTES), + .NUM_REQUESTS (NUM_REQUESTS), + .STAGE_1_CYCLES (STAGE_1_CYCLES), + .FUNC_ID (FUNC_ID), + .REQQ_SIZE (REQQ_SIZE), + .MRVQ_SIZE (MRVQ_SIZE), + .DFPQ_SIZE (DFPQ_SIZE), + .SNRQ_SIZE (SNRQ_SIZE), + .CWBQ_SIZE (CWBQ_SIZE), + .DWBQ_SIZE (DWBQ_SIZE), + .DFQQ_SIZE (DFQQ_SIZE), + .LLVQ_SIZE (LLVQ_SIZE), + .FFSQ_SIZE (FFSQ_SIZE), + .FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE), + .SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES) + ) bank ( .clk (clk), .reset (reset), // Core req @@ -431,39 +396,35 @@ module VX_cache .bank_wb_address (curr_bank_wb_address), // Dram fill req - .dram_fill_req (curr_bank_dram_fill_req), + .dram_fill_req_valid (curr_bank_dram_fill_req_valid), .dram_fill_req_addr (curr_bank_dram_fill_req_addr), + .dram_fill_req_is_snp (curr_bank_dram_fill_req_is_snp), .dram_fill_req_queue_full(curr_bank_dfqq_full), // Dram fill rsp - .dram_fill_rsp (curr_bank_dram_fill_rsp), - .dram_fill_addr (curr_bank_dram_fill_rsp_addr), - .dram_fill_rsp_data (curr_bank_dram_fill_rsp_data), - .dram_fill_accept (curr_bank_dram_fill_accept), + .dram_rsp_valid (curr_bank_dram_rsp_valid), + .dram_rsp_addr (curr_bank_dram_rsp_addr), + .dram_rsp_data (curr_bank_dram_rsp_data), + .dram_rsp_ready (curr_bank_dram_rsp_ready), // Dram writeback .dram_wb_queue_pop (curr_bank_dram_wb_queue_pop), - .dram_wb_req (curr_bank_dram_wb_req), + .dram_wb_req_valid (curr_bank_dram_wb_req_valid), .dram_wb_req_addr (curr_bank_dram_wb_req_addr), - .dram_wb_req_data (curr_bank_dram_wb_req_data), - .dram_because_of_snp (curr_bank_dram_because_of_snp), - .dram_snp_full (curr_bank_dram_snp_full), + .dram_wb_req_data (curr_bank_dram_wb_req_data), // Snoop Request - .snp_req (curr_bank_snp_req), + .snp_req_valid (curr_bank_snp_req), .snp_req_addr (curr_bank_snp_req_addr), - .snrq_full (curr_bank_snrq_full), + .snp_req_full (curr_bank_snp_req_full), // Snoop Fwd - .snp_fwd (curr_bank_snp_fwd), + .snp_fwd_valid (curr_bank_snp_fwd), .snp_fwd_addr (curr_bank_snp_fwd_addr), .snp_fwd_pop (curr_bank_snp_fwd_pop) - - ); - + ); end + endgenerate - - - + endmodule \ No newline at end of file diff --git a/hw/rtl/generic_cache/VX_cache_config.vh b/hw/rtl/generic_cache/VX_cache_config.vh index ef88a195..4500a5f6 100644 --- a/hw/rtl/generic_cache/VX_cache_config.vh +++ b/hw/rtl/generic_cache/VX_cache_config.vh @@ -9,24 +9,24 @@ // 5 + 2 + 4 + 3 + 3 + 1 `define REQ_INST_META_SIZE (5 + 2 + (`NW_BITS-1+1) + 3 + 3 + `LOG2UP(NUM_REQUESTS)) -`define WORD_SIZE (8*WORD_SIZE_BYTES) +`define WORD_SIZE (8 * WORD_SIZE_BYTES) `define WORD_SIZE_RNG (`WORD_SIZE)-1:0 // 128 -`define BANK_SIZE_BYTES CACHE_SIZE_BYTES/NUM_BANKS +`define BANK_SIZE_BYTES (CACHE_SIZE_BYTES / NUM_BANKS) // 8 -`define BANK_LINE_COUNT (`BANK_SIZE_BYTES/BANK_LINE_SIZE_BYTES) +`define BANK_LINE_COUNT (`BANK_SIZE_BYTES / BANK_LINE_SIZE_BYTES) // 4 `define BANK_LINE_WORDS (BANK_LINE_SIZE_BYTES / WORD_SIZE_BYTES) // Offset is fixed -`define OFFSET_ADDR_NUM_BITS 2 -`define OFFSET_SIZE_END 1 -`define OFFSET_ADDR_START 0 -`define OFFSET_ADDR_END 1 -`define OFFSET_ADDR_RNG `OFFSET_ADDR_END:`OFFSET_ADDR_START -`define OFFSET_SIZE_RNG `OFFSET_SIZE_END:0 +`define OFFSET_ADDR_NUM_BITS 2 +`define OFFSET_SIZE_END 1 +`define OFFSET_ADDR_START 0 +`define OFFSET_ADDR_END 1 +`define OFFSET_ADDR_RNG `OFFSET_ADDR_END:`OFFSET_ADDR_START +`define OFFSET_SIZE_RNG `OFFSET_SIZE_END:0 // 2 `define WORD_SELECT_NUM_BITS (`LOG2UP(`BANK_LINE_WORDS)) @@ -55,17 +55,14 @@ // 3 `define LINE_SELECT_NUM_BITS (`LOG2UP(`BANK_LINE_COUNT)) -// 3 -`define LINE_SELECT_SIZE_END (`LINE_SELECT_NUM_BITS) // 7 `define LINE_SELECT_ADDR_START (1+`BANK_SELECT_ADDR_END) // 9 -`define LINE_SELECT_ADDR_END (`LINE_SELECT_SIZE_END+`LINE_SELECT_ADDR_START-1) +`define LINE_SELECT_ADDR_END (`LINE_SELECT_NUM_BITS+`LINE_SELECT_ADDR_START-1) // 9:7 `define LINE_SELECT_ADDR_RNG `LINE_SELECT_ADDR_END:`LINE_SELECT_ADDR_START // 2:0 -`define LINE_SELECT_SIZE_RNG `LINE_SELECT_SIZE_END-1:0 - +`define LINE_SELECT_SIZE_RNG `LINE_SELECT_NUM_BITS-1:0 // 10 `define TAG_SELECT_ADDR_START (1+`LINE_SELECT_ADDR_END) @@ -76,9 +73,10 @@ // 22 `define TAG_SELECT_SIZE_END (`TAG_SELECT_NUM_BITS) // 21:0 -`define TAG_SELECT_SIZE_RNG `TAG_SELECT_SIZE_END-1:0 +`define TAG_SELECT_SIZE_RNG `TAG_SELECT_NUM_BITS-1:0 + +`define TAG_LINE_SELECT_BITS (`TAG_SELECT_NUM_BITS+`LINE_SELECT_NUM_BITS) `define BASE_ADDR_MASK (~((1<<(`WORD_SELECT_ADDR_END+1))-1)) `endif - diff --git a/hw/rtl/generic_cache/VX_cache_core_req_bank_sel.v b/hw/rtl/generic_cache/VX_cache_core_req_bank_sel.v index 428f729f..850fe19f 100644 --- a/hw/rtl/generic_cache/VX_cache_core_req_bank_sel.v +++ b/hw/rtl/generic_cache/VX_cache_core_req_bank_sel.v @@ -54,8 +54,6 @@ module VX_cache_core_req_bank_sel output reg [NUM_BANKS-1:0][NUM_REQUESTS-1:0] per_bank_valids ); - wire[31:0] req_address; - generate integer curr_req; always @(*) begin diff --git a/hw/rtl/generic_cache/VX_cache_dfq_queue.v b/hw/rtl/generic_cache/VX_cache_dfq_queue.v index 09ec7cc6..a8e9e181 100644 --- a/hw/rtl/generic_cache/VX_cache_dfq_queue.v +++ b/hw/rtl/generic_cache/VX_cache_dfq_queue.v @@ -1,7 +1,6 @@ `include "VX_cache_config.vh" -module VX_cache_dfq_queue - #( +module VX_cache_dfq_queue #( // Size of cache in bytes parameter CACHE_SIZE_BYTES = 1024, // Size of line inside a bank in bytes @@ -15,8 +14,7 @@ module VX_cache_dfq_queue // Number of cycles to complete stage 1 (read from memory) parameter STAGE_1_CYCLES = 2, -// Queues feeding into banks Knobs {1, 2, 4, 8, ...} - + // Queues feeding into banks Knobs {1, 2, 4, 8, ...} // Core Request Queue Size parameter REQQ_SIZE = 8, // Miss Reserv Queue Knob @@ -26,7 +24,7 @@ module VX_cache_dfq_queue // Snoop Req Queue parameter SNRQ_SIZE = 8, -// Queues for writebacks Knobs {1, 2, 4, 8, ...} + // Queues for writebacks Knobs {1, 2, 4, 8, ...} // Core Writeback Queue Size parameter CWBQ_SIZE = 8, // Dram Writeback Queue Size @@ -39,16 +37,13 @@ module VX_cache_dfq_queue // Fill Invalidator Size {Fill invalidator must be active} parameter FILL_INVALIDAOR_SIZE = 16, -// Dram knobs + // Dram knobs parameter SIMULATED_DRAM_LATENCY_CYCLES = 10 - - - ) - ( +) ( input wire clk, input wire reset, input wire dfqq_push, - input wire[NUM_BANKS-1:0] per_bank_dram_fill_req, + input wire[NUM_BANKS-1:0] per_bank_dram_fill_req_valid, input wire[NUM_BANKS-1:0][31:0] per_bank_dram_fill_req_addr, input wire dfqq_pop, @@ -61,17 +56,14 @@ module VX_cache_dfq_queue wire[NUM_BANKS-1:0] out_per_bank_dram_fill_req; wire[NUM_BANKS-1:0][31:0] out_per_bank_dram_fill_req_addr; - reg [NUM_BANKS-1:0] use_per_bank_dram_fill_req; reg [NUM_BANKS-1:0][31:0] use_per_bank_dram_fill_req_addr; - wire[NUM_BANKS-1:0] qual_bank_dram_fill_req; wire[NUM_BANKS-1:0][31:0] qual_bank_dram_fill_req_addr; wire[NUM_BANKS-1:0] updated_bank_dram_fill_req; - wire o_empty; wire use_empty = !(|use_per_bank_dram_fill_req); @@ -79,27 +71,34 @@ module VX_cache_dfq_queue wire push_qual = dfqq_push && !dfqq_full; wire pop_qual = dfqq_pop && use_empty && !out_empty; - VX_generic_queue_ll #(.DATAW(NUM_BANKS * (1+32)), .SIZE(DFQQ_SIZE)) dfqq_queue( + + VX_generic_queue_ll #( + .DATAW(NUM_BANKS * (1+32)), + .SIZE(DFQQ_SIZE) + ) dfqq_queue ( .clk (clk), .reset (reset), .push (push_qual), - .in_data ({per_bank_dram_fill_req, per_bank_dram_fill_req_addr}), + .in_data ({per_bank_dram_fill_req_valid, per_bank_dram_fill_req_addr}), .pop (pop_qual), .out_data({out_per_bank_dram_fill_req, out_per_bank_dram_fill_req_addr}), .empty (o_empty), .full (dfqq_full) - ); + ); assign qual_bank_dram_fill_req = use_empty ? (out_per_bank_dram_fill_req & {NUM_BANKS{!o_empty}}) : (use_per_bank_dram_fill_req & {NUM_BANKS{!use_empty}}); assign qual_bank_dram_fill_req_addr = use_empty ? out_per_bank_dram_fill_req_addr : use_per_bank_dram_fill_req_addr; wire[`LOG2UP(NUM_BANKS)-1:0] qual_request_index; - wire qual_has_request; - VX_generic_priority_encoder #(.N(NUM_BANKS)) VX_sel_bank( + wire qual_has_request; + + VX_generic_priority_encoder #( + .N(NUM_BANKS) + ) vx_sel_bank ( .valids(qual_bank_dram_fill_req), .index (qual_request_index), .found (qual_has_request) - ); + ); assign dfqq_empty = !qual_has_request; assign dfqq_req = qual_bank_dram_fill_req [qual_request_index]; @@ -119,5 +118,4 @@ module VX_cache_dfq_queue end end - endmodule \ No newline at end of file diff --git a/hw/rtl/generic_cache/VX_cache_dram_req_arb.v b/hw/rtl/generic_cache/VX_cache_dram_req_arb.v index 7a19db32..b3e8e046 100644 --- a/hw/rtl/generic_cache/VX_cache_dram_req_arb.v +++ b/hw/rtl/generic_cache/VX_cache_dram_req_arb.v @@ -1,7 +1,6 @@ `include "VX_cache_config.vh" -module VX_cache_dram_req_arb - #( +module VX_cache_dram_req_arb #( // Size of cache in bytes parameter CACHE_SIZE_BYTES = 1024, // Size of line inside a bank in bytes @@ -15,7 +14,7 @@ module VX_cache_dram_req_arb // Number of cycles to complete stage 1 (read from memory) parameter STAGE_1_CYCLES = 2, -// Queues feeding into banks Knobs {1, 2, 4, 8, ...} + // Queues feeding into banks Knobs {1, 2, 4, 8, ...} // Core Request Queue Size parameter REQQ_SIZE = 8, @@ -26,7 +25,7 @@ module VX_cache_dram_req_arb // Snoop Req Queue parameter SNRQ_SIZE = 8, -// Queues for writebacks Knobs {1, 2, 4, 8, ...} + // Queues for writebacks Knobs {1, 2, 4, 8, ...} // Core Writeback Queue Size parameter CWBQ_SIZE = 8, // Dram Writeback Queue Size @@ -45,39 +44,29 @@ module VX_cache_dram_req_arb // Dram knobs parameter SIMULATED_DRAM_LATENCY_CYCLES = 10 - - - ) - ( +) ( input wire clk, input wire reset, - // Fill Request - output wire dfqq_full, - input wire[NUM_BANKS-1:0] per_bank_dram_fill_req, - input wire[NUM_BANKS-1:0][31:0] per_bank_dram_fill_req_addr, - - // DFQ Request - output wire[NUM_BANKS-1:0] per_bank_dram_wb_queue_pop, - input wire[NUM_BANKS-1:0] per_bank_dram_wb_req, - input wire[NUM_BANKS-1:0][31:0] per_bank_dram_wb_req_addr, - input wire[NUM_BANKS-1:0][`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] per_bank_dram_wb_req_data, - input wire[NUM_BANKS-1:0] per_bank_dram_because_of_snp, - - // real Dram request - output wire dram_req, - output wire dram_req_write, - output wire dram_req_read, - output wire [31:0] dram_req_addr, - output wire [31:0] dram_req_size, - output wire [`IBANK_LINE_WORDS-1:0][31:0] dram_req_data, - output wire dram_req_because_of_wb, - - input wire dram_req_delay + output wire dfqq_full, + input wire[NUM_BANKS-1:0] per_bank_dram_fill_req_valid, + input wire[NUM_BANKS-1:0][31:0] per_bank_dram_fill_req_addr, -); + // DFQ Request + output wire[NUM_BANKS-1:0] per_bank_dram_wb_queue_pop, + input wire[NUM_BANKS-1:0] per_bank_dram_wb_req_valid, + input wire[NUM_BANKS-1:0][31:0] per_bank_dram_wb_req_addr, + input wire[NUM_BANKS-1:0][`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] per_bank_dram_wb_req_data, + + // real Dram request + output wire dram_req_read, + output wire dram_req_write, + output wire [31:0] dram_req_addr, + output wire [`IBANK_LINE_WORDS-1:0][31:0] dram_req_data, + input wire dram_req_full +); wire pref_pop; wire pref_valid; @@ -86,66 +75,62 @@ module VX_cache_dram_req_arb wire dwb_valid; wire dfqq_req; - assign pref_pop = !dwb_valid && !dfqq_req && !dram_req_delay && pref_valid; + assign pref_pop = !dwb_valid && !dfqq_req && !dram_req_full && pref_valid; VX_prefetcher #( .PRFQ_SIZE (PRFQ_SIZE), .PRFQ_STRIDE (PRFQ_STRIDE), .BANK_LINE_SIZE_BYTES(BANK_LINE_SIZE_BYTES), .WORD_SIZE_BYTES (WORD_SIZE_BYTES) - ) - prfqq - ( + ) prfqq ( .clk (clk), .reset (reset), - .dram_req (dram_req && dram_req_read), + .dram_req (dram_req_read), .dram_req_addr(dram_req_addr), .pref_pop (pref_pop), .pref_valid (pref_valid), .pref_addr (pref_addr) - - - ); + ); wire[31:0] dfqq_req_addr; +/* verilator lint_off UNUSED */ wire dfqq_empty; - wire dfqq_pop = !dwb_valid && dfqq_req && !dram_req_delay; // If no dwb, and dfqq has valids, then pop - wire dfqq_push = (|per_bank_dram_fill_req); +/* verilator lint_on UNUSED */ + wire dfqq_pop = !dwb_valid && dfqq_req && !dram_req_full; // If no dwb, and dfqq has valids, then pop + wire dfqq_push = (|per_bank_dram_fill_req_valid); - VX_cache_dfq_queue VX_cache_dfq_queue( - .clk (clk), - .reset (reset), - .dfqq_push (dfqq_push), - .per_bank_dram_fill_req (per_bank_dram_fill_req), - .per_bank_dram_fill_req_addr(per_bank_dram_fill_req_addr), - .dfqq_pop (dfqq_pop), - .dfqq_req (dfqq_req), - .dfqq_req_addr (dfqq_req_addr), - .dfqq_empty (dfqq_empty), - .dfqq_full (dfqq_full) - ); + VX_cache_dfq_queue vx_cache_dfq_queue( + .clk (clk), + .reset (reset), + .dfqq_push (dfqq_push), + .per_bank_dram_fill_req_valid (per_bank_dram_fill_req_valid), + .per_bank_dram_fill_req_addr (per_bank_dram_fill_req_addr), + .dfqq_pop (dfqq_pop), + .dfqq_req (dfqq_req), + .dfqq_req_addr (dfqq_req_addr), + .dfqq_empty (dfqq_empty), + .dfqq_full (dfqq_full) + ); wire[`LOG2UP(NUM_BANKS)-1:0] dwb_bank; - // wire[NUM_BANKS-1:0] use_wb_valid = per_bank_dram_wb_req | per_bank_dram_because_of_snp; - wire[NUM_BANKS-1:0] use_wb_valid = per_bank_dram_wb_req; - VX_generic_priority_encoder #(.N(NUM_BANKS)) VX_sel_dwb( + + wire[NUM_BANKS-1:0] use_wb_valid = per_bank_dram_wb_req_valid; + + VX_generic_priority_encoder #( + .N(NUM_BANKS) + ) vx_sel_dwb ( .valids(use_wb_valid), .index (dwb_bank), .found (dwb_valid) - ); + ); + assign per_bank_dram_wb_queue_pop = dram_req_full ? 0 : use_wb_valid & ((1 << dwb_bank)); - assign per_bank_dram_wb_queue_pop = dram_req_delay ? 0 : use_wb_valid & ((1 << dwb_bank)); - - - assign dram_req = dwb_valid || dfqq_req || pref_pop; - assign dram_req_write = dwb_valid && dram_req; - assign dram_req_read = ((dfqq_req && !dwb_valid) || pref_pop) && dram_req; - assign dram_req_addr = (dwb_valid ? per_bank_dram_wb_req_addr[dwb_bank] : (dfqq_req ? dfqq_req_addr : pref_addr)) & `BASE_ADDR_MASK; - assign dram_req_size = BANK_LINE_SIZE_BYTES; - assign {dram_req_data} = dwb_valid ? {per_bank_dram_wb_req_data[dwb_bank] }: 0; - // assign dram_req_because_of_wb = dwb_valid ? per_bank_dram_because_of_snp[dwb_bank] : 0; - assign dram_req_because_of_wb = 0; + wire dram_req = dwb_valid || dfqq_req || pref_pop; + assign dram_req_read = ((dfqq_req && !dwb_valid) || pref_pop) && dram_req; + assign dram_req_write = dwb_valid && dram_req; + assign dram_req_addr = (dwb_valid ? per_bank_dram_wb_req_addr[dwb_bank] : (dfqq_req ? dfqq_req_addr : pref_addr)) & `BASE_ADDR_MASK; + assign {dram_req_data} = dwb_valid ? {per_bank_dram_wb_req_data[dwb_bank] }: 0; endmodule \ No newline at end of file diff --git a/hw/rtl/generic_cache/VX_cache_miss_resrv.v b/hw/rtl/generic_cache/VX_cache_miss_resrv.v index c68dbb77..68c3210f 100644 --- a/hw/rtl/generic_cache/VX_cache_miss_resrv.v +++ b/hw/rtl/generic_cache/VX_cache_miss_resrv.v @@ -1,8 +1,7 @@ `include "VX_cache_config.vh" -module VX_cache_miss_resrv - #( +module VX_cache_miss_resrv #( // Size of cache in bytes parameter CACHE_SIZE_BYTES = 1024, // Size of line inside a bank in bytes @@ -16,8 +15,7 @@ module VX_cache_miss_resrv // Number of cycles to complete stage 1 (read from memory) parameter STAGE_1_CYCLES = 2, -// Queues feeding into banks Knobs {1, 2, 4, 8, ...} - + // Queues feeding into banks Knobs {1, 2, 4, 8, ...} // Core Request Queue Size parameter REQQ_SIZE = 8, // Miss Reserv Queue Knob @@ -27,7 +25,7 @@ module VX_cache_miss_resrv // Snoop Req Queue parameter SNRQ_SIZE = 8, -// Queues for writebacks Knobs {1, 2, 4, 8, ...} + // Queues for writebacks Knobs {1, 2, 4, 8, ...} // Core Writeback Queue Size parameter CWBQ_SIZE = 8, // Dram Writeback Queue Size @@ -40,12 +38,9 @@ module VX_cache_miss_resrv // Fill Invalidator Size {Fill invalidator must be active} parameter FILL_INVALIDAOR_SIZE = 16, -// Dram knobs + // Dram knobs parameter SIMULATED_DRAM_LATENCY_CYCLES = 10 - - - ) - ( +) ( input wire clk, input wire reset, @@ -65,7 +60,11 @@ module VX_cache_miss_resrv // Broadcast Fill input wire is_fill_st1, + +/* verilator lint_off UNUSED */ + // TODO: should fix this input wire[31:0] fill_addr_st1, +/* verilator lint_on UNUSED */ // Miss dequeue input wire miss_resrv_pop, @@ -81,96 +80,91 @@ module VX_cache_miss_resrv output wire[2:0] miss_resrv_mem_write_st0 ); + // Size of metadata = 32 + `LOG2UP(NUM_REQUESTS) + 5 + 2 + (`NW_BITS-1 + 1) + reg [`MRVQ_METADATA_SIZE-1:0] metadata_table[MRVQ_SIZE-1:0]; + reg [MRVQ_SIZE-1:0][31:0] addr_table; + reg [MRVQ_SIZE-1:0][31:0] pc_table; + reg [MRVQ_SIZE-1:0] valid_table; + reg [MRVQ_SIZE-1:0] ready_table; + reg [`LOG2UP(MRVQ_SIZE)-1:0] head_ptr; + reg [`LOG2UP(MRVQ_SIZE)-1:0] tail_ptr; - // Size of metadata = 32 + `LOG2UP(NUM_REQUESTS) + 5 + 2 + (`NW_BITS-1 + 1) - reg[`MRVQ_METADATA_SIZE-1:0] metadata_table[MRVQ_SIZE-1:0]; - reg[MRVQ_SIZE-1:0][31:0] addr_table; - reg[MRVQ_SIZE-1:0][31:0] pc_table; - reg[MRVQ_SIZE-1:0] valid_table; - reg[MRVQ_SIZE-1:0] ready_table; - reg[`LOG2UP(MRVQ_SIZE)-1:0] head_ptr; - reg[`LOG2UP(MRVQ_SIZE)-1:0] tail_ptr; + reg [31:0] size; - reg[31:0] size; + // assign miss_resrv_full = (MRVQ_SIZE != 2) && (tail_ptr+1) == head_ptr; + assign miss_resrv_full = (MRVQ_SIZE != 2) && (size == MRVQ_SIZE ); + assign miss_resrv_stop = (MRVQ_SIZE != 2) && (size > (MRVQ_SIZE-5)); + wire enqueue_possible = !miss_resrv_full; + wire [`LOG2UP(MRVQ_SIZE)-1:0] enqueue_index = tail_ptr; - // assign miss_resrv_full = (MRVQ_SIZE != 2) && (tail_ptr+1) == head_ptr; - assign miss_resrv_full = (MRVQ_SIZE != 2) && (size == MRVQ_SIZE ); - assign miss_resrv_stop = (MRVQ_SIZE != 2) && (size > (MRVQ_SIZE-5)); + reg [MRVQ_SIZE-1:0] make_ready; + genvar curr_e; + generate + for (curr_e = 0; curr_e < MRVQ_SIZE; curr_e=curr_e+1) begin + assign make_ready[curr_e] = is_fill_st1 && valid_table[curr_e] + && addr_table[curr_e][31:`LINE_SELECT_ADDR_START] == fill_addr_st1[31:`LINE_SELECT_ADDR_START]; + end + endgenerate - wire enqueue_possible = !miss_resrv_full; - wire[`LOG2UP(MRVQ_SIZE)-1:0] enqueue_index = tail_ptr; + wire dequeue_possible = valid_table[head_ptr] && ready_table[head_ptr]; + wire [`LOG2UP(MRVQ_SIZE)-1:0] dequeue_index = head_ptr; - reg[MRVQ_SIZE-1:0] make_ready; - genvar curr_e; - generate - for (curr_e = 0; curr_e < MRVQ_SIZE; curr_e=curr_e+1) begin - assign make_ready[curr_e] = is_fill_st1 && valid_table[curr_e] - && addr_table[curr_e][31:`LINE_SELECT_ADDR_START] == fill_addr_st1[31:`LINE_SELECT_ADDR_START]; + assign miss_resrv_valid_st0 = (MRVQ_SIZE != 2) && dequeue_possible; + assign miss_resrv_pc_st0 = pc_table[dequeue_index]; + assign miss_resrv_addr_st0 = addr_table[dequeue_index]; + assign {miss_resrv_data_st0, miss_resrv_tid_st0, miss_resrv_rd_st0, miss_resrv_wb_st0, miss_resrv_warp_num_st0, miss_resrv_mem_read_st0, miss_resrv_mem_write_st0} = metadata_table[dequeue_index]; + + wire mrvq_push = miss_add && enqueue_possible && (MRVQ_SIZE != 2); + wire mrvq_pop = miss_resrv_pop && dequeue_possible; + + wire update_ready = (|make_ready); + integer i; + always @(posedge clk) begin + if (reset) begin + for (i = 0; i < MRVQ_SIZE; i=i+1) begin + metadata_table[i] <= 0; + end + valid_table <= 0; + ready_table <= 0; + addr_table <= 0; + pc_table <= 0; + size <= 0; + head_ptr <= 0; + tail_ptr <= 0; + end else begin + if (mrvq_push) begin + valid_table[enqueue_index] <= 1; + ready_table[enqueue_index] <= 0; + pc_table[enqueue_index] <= miss_add_pc; + addr_table[enqueue_index] <= miss_add_addr; + metadata_table[enqueue_index] <= {miss_add_data, miss_add_tid, miss_add_rd, miss_add_wb, miss_add_warp_num, miss_add_mem_read, miss_add_mem_write}; + tail_ptr <= tail_ptr + 1; end - endgenerate + if (update_ready) begin + ready_table <= ready_table | make_ready; + end - wire dequeue_possible = valid_table[head_ptr] && ready_table[head_ptr]; - wire[`LOG2UP(MRVQ_SIZE)-1:0] dequeue_index = head_ptr; + if (mrvq_pop) begin + valid_table[dequeue_index] <= 0; + ready_table[dequeue_index] <= 0; + addr_table[dequeue_index] <= 0; + metadata_table[dequeue_index] <= 0; + pc_table[dequeue_index] <= 0; + head_ptr <= head_ptr + 1; + end - assign miss_resrv_valid_st0 = (MRVQ_SIZE != 2) && dequeue_possible; - assign miss_resrv_pc_st0 = pc_table[dequeue_index]; - assign miss_resrv_addr_st0 = addr_table[dequeue_index]; - assign {miss_resrv_data_st0, miss_resrv_tid_st0, miss_resrv_rd_st0, miss_resrv_wb_st0, miss_resrv_warp_num_st0, miss_resrv_mem_read_st0, miss_resrv_mem_write_st0} = metadata_table[dequeue_index]; - - - wire mrvq_push = miss_add && enqueue_possible && (MRVQ_SIZE != 2); - wire mrvq_pop = miss_resrv_pop && dequeue_possible; - - wire update_ready = (|make_ready); - integer i; - always @(posedge clk) begin - if (reset) begin - for (i = 0; i < MRVQ_SIZE; i=i+1) metadata_table[i] <= 0; - valid_table <= 0; - ready_table <= 0; - addr_table <= 0; - pc_table <= 0; - size <= 0; - head_ptr <= 0; - tail_ptr <= 0; - end else begin + if (!(mrvq_push && mrvq_pop)) begin if (mrvq_push) begin - valid_table[enqueue_index] <= 1; - ready_table[enqueue_index] <= 0; - pc_table[enqueue_index] <= miss_add_pc; - addr_table[enqueue_index] <= miss_add_addr; - metadata_table[enqueue_index] <= {miss_add_data, miss_add_tid, miss_add_rd, miss_add_wb, miss_add_warp_num, miss_add_mem_read, miss_add_mem_write}; - tail_ptr <= tail_ptr + 1; - end - - if (update_ready) begin - ready_table <= ready_table | make_ready; + size <= size + 1; end if (mrvq_pop) begin - valid_table[dequeue_index] <= 0; - ready_table[dequeue_index] <= 0; - addr_table[dequeue_index] <= 0; - metadata_table[dequeue_index] <= 0; - pc_table[dequeue_index] <= 0; - head_ptr <= head_ptr + 1; + size <= size - 1; end - - if (!(mrvq_push && mrvq_pop)) begin - if (mrvq_push) begin - size <= size + 1; - end - - if (mrvq_pop) begin - size <= size - 1; - end - end - end end - - + end endmodule \ No newline at end of file diff --git a/hw/rtl/generic_cache/VX_cache_req_queue.v b/hw/rtl/generic_cache/VX_cache_req_queue.v index 65581783..9fe7e33f 100644 --- a/hw/rtl/generic_cache/VX_cache_req_queue.v +++ b/hw/rtl/generic_cache/VX_cache_req_queue.v @@ -1,7 +1,6 @@ `include "VX_cache_config.vh" -module VX_cache_req_queue - #( +module VX_cache_req_queue #( // Size of cache in bytes parameter CACHE_SIZE_BYTES = 1024, // Size of line inside a bank in bytes @@ -15,8 +14,7 @@ module VX_cache_req_queue // Number of cycles to complete stage 1 (read from memory) parameter STAGE_1_CYCLES = 2, -// Queues feeding into banks Knobs {1, 2, 4, 8, ...} - + // Queues feeding into banks Knobs {1, 2, 4, 8, ...} // Core Request Queue Size parameter REQQ_SIZE = 8, // Miss Reserv Queue Knob @@ -26,7 +24,7 @@ module VX_cache_req_queue // Snoop Req Queue parameter SNRQ_SIZE = 8, -// Queues for writebacks Knobs {1, 2, 4, 8, ...} + // Queues for writebacks Knobs {1, 2, 4, 8, ...} // Core Writeback Queue Size parameter CWBQ_SIZE = 8, // Dram Writeback Queue Size @@ -39,12 +37,9 @@ module VX_cache_req_queue // Fill Invalidator Size {Fill invalidator must be active} parameter FILL_INVALIDAOR_SIZE = 16, -// Dram knobs + // Dram knobs parameter SIMULATED_DRAM_LATENCY_CYCLES = 10 - - - ) - ( +) ( input wire clk, input wire reset, @@ -88,7 +83,6 @@ module VX_cache_req_queue wire [NUM_REQUESTS-1:0][2:0] out_per_mem_write; wire [31:0] out_per_pc; - reg [NUM_REQUESTS-1:0] use_per_valids; reg [NUM_REQUESTS-1:0][31:0] use_per_addr; reg [NUM_REQUESTS-1:0][`WORD_SIZE_RNG] use_per_writedata; @@ -99,7 +93,6 @@ module VX_cache_req_queue reg [NUM_REQUESTS-1:0][2:0] use_per_mem_read; reg [NUM_REQUESTS-1:0][2:0] use_per_mem_write; - wire [NUM_REQUESTS-1:0] qual_valids; wire [NUM_REQUESTS-1:0][31:0] qual_addr; wire [NUM_REQUESTS-1:0][`WORD_SIZE_RNG] qual_writedata; @@ -110,7 +103,9 @@ module VX_cache_req_queue wire [NUM_REQUESTS-1:0][2:0] qual_mem_write; wire [31:0] qual_pc; +/* verilator lint_off UNUSED */ reg [NUM_REQUESTS-1:0] updated_valids; +/* verilator lint_on UNUSED */ wire o_empty; @@ -120,17 +115,19 @@ module VX_cache_req_queue wire push_qual = reqq_push && !reqq_full; wire pop_qual = !out_empty && use_empty; - VX_generic_queue_ll #(.DATAW( (NUM_REQUESTS * (1+32+`WORD_SIZE)) + 5 + (NUM_REQUESTS*2) + (`NW_BITS-1+1) + (NUM_REQUESTS * (3 + 3)) + 32 ), .SIZE(REQQ_SIZE)) reqq_queue( - .clk (clk), - .reset (reset), - .push (push_qual), - .in_data ({bank_valids , bank_addr , bank_writedata , bank_rd , bank_wb , bank_warp_num , bank_mem_read , bank_mem_write , bank_pc}), - .pop (pop_qual), - .out_data({out_per_valids, out_per_addr, out_per_writedata, out_per_rd, out_per_wb, out_per_warp_num, out_per_mem_read, out_per_mem_write, out_per_pc}), - .empty (o_empty), - .full (reqq_full) - ); - + VX_generic_queue_ll #( + .DATAW( (NUM_REQUESTS * (1+32+`WORD_SIZE)) + 5 + (NUM_REQUESTS*2) + (`NW_BITS-1+1) + (NUM_REQUESTS * (3 + 3)) + 32 ), + .SIZE(REQQ_SIZE) + ) reqq_queue ( + .clk (clk), + .reset (reset), + .push (push_qual), + .in_data ({bank_valids , bank_addr , bank_writedata , bank_rd , bank_wb , bank_warp_num , bank_mem_read , bank_mem_write , bank_pc}), + .pop (pop_qual), + .out_data ({out_per_valids, out_per_addr, out_per_writedata, out_per_rd, out_per_wb, out_per_warp_num, out_per_mem_read, out_per_mem_write, out_per_pc}), + .empty (o_empty), + .full (reqq_full) + ); wire[NUM_REQUESTS-1:0] real_out_per_valids = out_per_valids & {NUM_REQUESTS{~out_empty}}; @@ -146,11 +143,13 @@ module VX_cache_req_queue wire[`LOG2UP(NUM_REQUESTS)-1:0] qual_request_index; wire qual_has_request; - VX_generic_priority_encoder #(.N(NUM_REQUESTS)) VX_sel_bank( + VX_generic_priority_encoder #( + .N(NUM_REQUESTS) + ) vx_sel_bank ( .valids(qual_valids), .index (qual_request_index), .found (qual_has_request) - ); + ); assign reqq_empty = !qual_has_request; assign reqq_req_st0 = qual_has_request; @@ -164,7 +163,6 @@ module VX_cache_req_queue assign reqq_req_mem_write_st0 = qual_mem_write[qual_request_index]; assign reqq_req_pc_st0 = qual_pc; - always @(*) begin updated_valids = qual_valids; if (qual_has_request) begin @@ -172,7 +170,6 @@ module VX_cache_req_queue end end - always @(posedge clk) begin if (reset) begin use_per_valids <= 0; @@ -204,5 +201,4 @@ module VX_cache_req_queue end end - endmodule \ No newline at end of file diff --git a/hw/rtl/generic_cache/VX_cache_wb_sel_merge.v b/hw/rtl/generic_cache/VX_cache_wb_sel_merge.v index 148365e1..cb5676d1 100644 --- a/hw/rtl/generic_cache/VX_cache_wb_sel_merge.v +++ b/hw/rtl/generic_cache/VX_cache_wb_sel_merge.v @@ -1,7 +1,6 @@ `include "VX_cache_config.vh" -module VX_cache_wb_sel_merge - #( +module VX_cache_wb_sel_merge #( // Size of cache in bytes parameter CACHE_SIZE_BYTES = 1024, // Size of line inside a bank in bytes @@ -17,8 +16,7 @@ module VX_cache_wb_sel_merge // Function ID, {Dcache=0, Icache=1, Sharedmemory=2} parameter FUNC_ID = 0, -// Queues feeding into banks Knobs {1, 2, 4, 8, ...} - + // Queues feeding into banks Knobs {1, 2, 4, 8, ...} // Core Request Queue Size parameter REQQ_SIZE = 8, // Miss Reserv Queue Knob @@ -28,7 +26,7 @@ module VX_cache_wb_sel_merge // Snoop Req Queue parameter SNRQ_SIZE = 8, -// Queues for writebacks Knobs {1, 2, 4, 8, ...} + // Queues for writebacks Knobs {1, 2, 4, 8, ...} // Core Writeback Queue Size parameter CWBQ_SIZE = 8, // Dram Writeback Queue Size @@ -41,35 +39,29 @@ module VX_cache_wb_sel_merge // Fill Invalidator Size {Fill invalidator must be active} parameter FILL_INVALIDAOR_SIZE = 16, -// Dram knobs + // Dram knobs parameter SIMULATED_DRAM_LATENCY_CYCLES = 10 - - - ) - ( - +) ( // Per Bank WB - input wire [NUM_BANKS-1:0] per_bank_wb_valid, - input wire [NUM_BANKS-1:0][`LOG2UP(NUM_REQUESTS)-1:0] per_bank_wb_tid, - input wire [NUM_BANKS-1:0][4:0] per_bank_wb_rd, - input wire [NUM_BANKS-1:0][1:0] per_bank_wb_wb, - input wire [NUM_BANKS-1:0][`NW_BITS-1:0] per_bank_wb_warp_num, - input wire [NUM_BANKS-1:0][`WORD_SIZE_RNG] per_bank_wb_data, - input wire [NUM_BANKS-1:0][31:0] per_bank_wb_pc, - input wire [NUM_BANKS-1:0][31:0] per_bank_wb_address, - output wire [NUM_BANKS-1:0] per_bank_wb_pop, - + input wire [NUM_BANKS-1:0] per_bank_wb_valid, + input wire [NUM_BANKS-1:0][`LOG2UP(NUM_REQUESTS)-1:0] per_bank_wb_tid, + input wire [NUM_BANKS-1:0][4:0] per_bank_wb_rd, + input wire [NUM_BANKS-1:0][1:0] per_bank_wb_wb, + input wire [NUM_BANKS-1:0][`NW_BITS-1:0] per_bank_wb_warp_num, + input wire [NUM_BANKS-1:0][`WORD_SIZE_RNG] per_bank_wb_data, + input wire [NUM_BANKS-1:0][31:0] per_bank_wb_pc, + input wire [NUM_BANKS-1:0][31:0] per_bank_wb_address, + output wire [NUM_BANKS-1:0] per_bank_wb_pop, // Core Writeback - input wire core_no_wb_slot, - output reg [NUM_REQUESTS-1:0] core_wb_valid, - output reg [NUM_REQUESTS-1:0][`WORD_SIZE_RNG] core_wb_readdata, - output reg [NUM_REQUESTS-1:0][31:0] core_wb_pc, - output wire [4:0] core_wb_req_rd, - output wire [1:0] core_wb_req_wb, - output wire [`NW_BITS-1:0] core_wb_warp_num, - output reg [NUM_REQUESTS-1:0][31:0] core_wb_address - + input wire core_no_wb_slot, + output reg [NUM_REQUESTS-1:0] core_wb_valid, + output reg [NUM_REQUESTS-1:0][`WORD_SIZE_RNG] core_wb_readdata, + output reg [NUM_REQUESTS-1:0][31:0] core_wb_pc, + output wire [4:0] core_wb_req_rd, + output wire [1:0] core_wb_req_wb, + output wire [`NW_BITS-1:0] core_wb_warp_num, + output reg [NUM_REQUESTS-1:0][31:0] core_wb_address ); reg [NUM_BANKS-1:0] per_bank_wb_pop_unqual; @@ -83,15 +75,16 @@ module VX_cache_wb_sel_merge // end // endgenerate - wire [`LOG2UP(NUM_BANKS)-1:0] main_bank_index; - wire found_bank; + wire found_bank; - VX_generic_priority_encoder #(.N(NUM_BANKS)) VX_sel_bank( + VX_generic_priority_encoder #( + .N(NUM_BANKS) + ) vx_sel_bank ( .valids(per_bank_wb_valid), .index (main_bank_index), .found (found_bank) - ); + ); assign core_wb_req_rd = per_bank_wb_rd[main_bank_index]; assign core_wb_req_wb = per_bank_wb_wb[main_bank_index]; @@ -106,42 +99,36 @@ module VX_cache_wb_sel_merge core_wb_address = 0; for (this_bank = 0; this_bank < NUM_BANKS; this_bank = this_bank + 1) begin if ((FUNC_ID == `L2FUNC_ID) || (FUNC_ID == `L3FUNC_ID)) begin - - if (found_bank - && !core_wb_valid[per_bank_wb_tid[this_bank]] - && per_bank_wb_valid[this_bank] - && ((main_bank_index == `LOG2UP(NUM_BANKS)'(this_bank)) - || (per_bank_wb_tid[this_bank] != per_bank_wb_tid[main_bank_index]))) begin - core_wb_valid[per_bank_wb_tid[this_bank]] = 1; - core_wb_readdata[per_bank_wb_tid[this_bank]] = per_bank_wb_data[this_bank]; - core_wb_pc[per_bank_wb_tid[this_bank]] = per_bank_wb_pc[this_bank]; - core_wb_address[per_bank_wb_tid[this_bank]] = per_bank_wb_address[this_bank]; - per_bank_wb_pop_unqual[this_bank] = 1; - end else begin - per_bank_wb_pop_unqual[this_bank] = 0; - end - + if (found_bank + && !core_wb_valid[per_bank_wb_tid[this_bank]] + && per_bank_wb_valid[this_bank] + && ((main_bank_index == `LOG2UP(NUM_BANKS)'(this_bank)) + || (per_bank_wb_tid[this_bank] != per_bank_wb_tid[main_bank_index]))) begin + core_wb_valid[per_bank_wb_tid[this_bank]] = 1; + core_wb_readdata[per_bank_wb_tid[this_bank]] = per_bank_wb_data[this_bank]; + core_wb_pc[per_bank_wb_tid[this_bank]] = per_bank_wb_pc[this_bank]; + core_wb_address[per_bank_wb_tid[this_bank]] = per_bank_wb_address[this_bank]; + per_bank_wb_pop_unqual[this_bank] = 1; + end else begin + per_bank_wb_pop_unqual[this_bank] = 0; + end end else begin - - if (((main_bank_index == `LOG2UP(NUM_BANKS)'(this_bank)) - || (per_bank_wb_tid[this_bank] != per_bank_wb_tid[main_bank_index])) - && found_bank - && !core_wb_valid[per_bank_wb_tid[this_bank]] - && (per_bank_wb_valid[this_bank]) - && (per_bank_wb_rd[this_bank] == per_bank_wb_rd[main_bank_index]) - && (per_bank_wb_warp_num[this_bank] == per_bank_wb_warp_num[main_bank_index])) begin - core_wb_valid[per_bank_wb_tid[this_bank]] = 1; - core_wb_readdata[per_bank_wb_tid[this_bank]] = per_bank_wb_data[this_bank]; - core_wb_pc[per_bank_wb_tid[this_bank]] = per_bank_wb_pc[this_bank]; - core_wb_address[per_bank_wb_tid[this_bank]] = per_bank_wb_address[this_bank]; - per_bank_wb_pop_unqual[this_bank] = 1; - end else begin - per_bank_wb_pop_unqual[this_bank] = 0; - - end - + if (((main_bank_index == `LOG2UP(NUM_BANKS)'(this_bank)) + || (per_bank_wb_tid[this_bank] != per_bank_wb_tid[main_bank_index])) + && found_bank + && !core_wb_valid[per_bank_wb_tid[this_bank]] + && (per_bank_wb_valid[this_bank]) + && (per_bank_wb_rd[this_bank] == per_bank_wb_rd[main_bank_index]) + && (per_bank_wb_warp_num[this_bank] == per_bank_wb_warp_num[main_bank_index])) begin + core_wb_valid[per_bank_wb_tid[this_bank]] = 1; + core_wb_readdata[per_bank_wb_tid[this_bank]] = per_bank_wb_data[this_bank]; + core_wb_pc[per_bank_wb_tid[this_bank]] = per_bank_wb_pc[this_bank]; + core_wb_address[per_bank_wb_tid[this_bank]] = per_bank_wb_address[this_bank]; + per_bank_wb_pop_unqual[this_bank] = 1; + end else begin + per_bank_wb_pop_unqual[this_bank] = 0; + end end - end end endgenerate diff --git a/hw/rtl/generic_cache/VX_dcache_llv_resp_bank_sel.v b/hw/rtl/generic_cache/VX_dcache_llv_resp_bank_sel.v index 37f79d35..fc80d1ee 100644 --- a/hw/rtl/generic_cache/VX_dcache_llv_resp_bank_sel.v +++ b/hw/rtl/generic_cache/VX_dcache_llv_resp_bank_sel.v @@ -47,14 +47,14 @@ module VX_dcache_llv_resp_bank_sel ( output reg [NUM_BANKS-1:0] per_bank_llvq_pop, input wire[NUM_BANKS-1:0] per_bank_llvq_valid, - input wire[NUM_BANKS-1:0][31:0] per_bank_llvq_res_addr, - input wire[NUM_BANKS-1:0][`BANK_LINE_WORDS-1:0][31:0] per_bank_llvq_res_data, - input wire[NUM_BANKS-1:0][`LOG2UP(NUM_REQUESTS)-1:0] per_bank_llvq_res_tid, + input wire[NUM_BANKS-1:0][31:0] per_bank_llvq_rsp_addr, + input wire[NUM_BANKS-1:0][`BANK_LINE_WORDS-1:0][31:0] per_bank_llvq_rsp_data, + input wire[NUM_BANKS-1:0][`LOG2UP(NUM_REQUESTS)-1:0] per_bank_llvq_rsp_tid, input wire llvq_pop, output reg[NUM_REQUESTS-1:0] llvq_valid, - output reg[NUM_REQUESTS-1:0][31:0] llvq_res_addr, - output reg[NUM_REQUESTS-1:0][`BANK_LINE_WORDS-1:0][31:0] llvq_res_data + output reg[NUM_REQUESTS-1:0][31:0] llvq_rsp_addr, + output reg[NUM_REQUESTS-1:0][`BANK_LINE_WORDS-1:0][31:0] llvq_rsp_data ); @@ -62,7 +62,7 @@ module VX_dcache_llv_resp_bank_sel wire [(`LOG2UP(NUM_BANKS))-1:0] main_bank_index; wire found_bank; - VX_generic_priority_encoder #(.N(NUM_BANKS)) VX_sel_bank( + VX_generic_priority_encoder #(.N(NUM_BANKS)) vx_sel_bank( .valids(per_bank_llvq_valid), .index (main_bank_index), .found (found_bank) @@ -71,13 +71,13 @@ module VX_dcache_llv_resp_bank_sel always @(*) begin llvq_valid = 0; - llvq_res_addr = 0; - llvq_res_data = 0; + llvq_rsp_addr = 0; + llvq_rsp_data = 0; per_bank_llvq_pop = 0; if (found_bank && llvq_pop) begin - llvq_valid [per_bank_llvq_res_tid[main_bank_index]] = 1'b1; - llvq_res_addr[per_bank_llvq_res_tid[main_bank_index]] = per_bank_llvq_res_addr[main_bank_index]; - llvq_res_data[per_bank_llvq_res_tid[main_bank_index]] = per_bank_llvq_res_data[main_bank_index]; + llvq_valid [per_bank_llvq_rsp_tid[main_bank_index]] = 1'b1; + llvq_rsp_addr[per_bank_llvq_rsp_tid[main_bank_index]] = per_bank_llvq_rsp_addr[main_bank_index]; + llvq_rsp_data[per_bank_llvq_rsp_tid[main_bank_index]] = per_bank_llvq_rsp_data[main_bank_index]; per_bank_llvq_pop[main_bank_index] = 1'b1; end end diff --git a/hw/rtl/generic_cache/VX_fill_invalidator.v b/hw/rtl/generic_cache/VX_fill_invalidator.v index 3b4a2a5c..678067dd 100644 --- a/hw/rtl/generic_cache/VX_fill_invalidator.v +++ b/hw/rtl/generic_cache/VX_fill_invalidator.v @@ -82,17 +82,18 @@ module VX_fill_invalidator wire [(`LOG2UP(FILL_INVALIDAOR_SIZE))-1:0] enqueue_index; - wire enqueue_found; - VX_generic_priority_encoder #(.N(FILL_INVALIDAOR_SIZE)) VX_sel_bank( + wire enqueue_found; + + VX_generic_priority_encoder #( + .N(FILL_INVALIDAOR_SIZE) + ) vx_sel_bank ( .valids(~fills_active), .index (enqueue_index), .found (enqueue_found) - ); - + ); assign invalidate_fill = possible_fill && matched; - always @(posedge clk) begin if (reset) begin fills_active <= 0; @@ -109,7 +110,6 @@ module VX_fill_invalidator end end - // reg success_found; // reg[(`LOG2UP(FILL_INVALIDAOR_SIZE))-1:0] success_index; @@ -133,21 +133,15 @@ module VX_fill_invalidator // end // end - - - // wire [(`LOG2UP(FILL_INVALIDAOR_SIZE))-1:0] enqueue_index; // wire enqueue_found; - // VX_generic_priority_encoder #(.N(FILL_INVALIDAOR_SIZE)) VX_sel_bank( + // VX_generic_priority_encoder #(.N(FILL_INVALIDAOR_SIZE)) vx_sel_bank( // .valids(~fills_active), // .index (enqueue_index), // .found (enqueue_found) // ); - - - // always @(posedge clk) begin // if (reset) begin // fills_active <= 0; @@ -165,8 +159,6 @@ module VX_fill_invalidator // end // end - end - endmodule \ No newline at end of file diff --git a/hw/rtl/generic_cache/VX_prefetcher.v b/hw/rtl/generic_cache/VX_prefetcher.v index 043606e6..a1d4cf37 100644 --- a/hw/rtl/generic_cache/VX_prefetcher.v +++ b/hw/rtl/generic_cache/VX_prefetcher.v @@ -1,15 +1,13 @@ `include "VX_cache_config.vh" -module VX_prefetcher - #( - parameter PRFQ_SIZE = 64, - parameter PRFQ_STRIDE = 2, - // Size of line inside a bank in bytes - parameter BANK_LINE_SIZE_BYTES = 16, - // Size of a word in bytes - parameter WORD_SIZE_BYTES = 4 - ) - ( +module VX_prefetcher #( + parameter PRFQ_SIZE = 64, + parameter PRFQ_STRIDE = 2, + // Size of line inside a bank in bytes + parameter BANK_LINE_SIZE_BYTES = 16, + // Size of a word in bytes + parameter WORD_SIZE_BYTES = 4 +) ( input wire clk, input wire reset, @@ -21,24 +19,23 @@ module VX_prefetcher output wire[31:0] pref_addr ); - - reg[`LOG2UP(PRFQ_STRIDE):0] use_valid; reg[31:0] use_addr; - wire current_valid; wire[31:0] current_addr; wire current_full; wire current_empty; - assign current_valid = ~current_empty; wire update_use = ((use_valid == 0) || ((use_valid-1) == 0)) && current_valid; - VX_generic_queue_ll #(.DATAW(32), .SIZE(PRFQ_SIZE)) pfq_queue( + VX_generic_queue_ll #( + .DATAW(32), + .SIZE(PRFQ_SIZE) + ) pfq_queue ( .clk (clk), .reset (reset), @@ -50,14 +47,11 @@ module VX_prefetcher .empty (current_empty), .full (current_full) - ); - - + ); assign pref_valid = use_valid != 0; assign pref_addr = use_addr; - always @(posedge clk) begin if (reset) begin use_valid <= 0; @@ -70,7 +64,6 @@ module VX_prefetcher use_valid <= use_valid - 1; use_addr <= use_addr + BANK_LINE_SIZE_BYTES; end - end end diff --git a/hw/rtl/generic_cache/VX_snp_fwd_arb.v b/hw/rtl/generic_cache/VX_snp_fwd_arb.v index e22ea69d..e57efc6f 100644 --- a/hw/rtl/generic_cache/VX_snp_fwd_arb.v +++ b/hw/rtl/generic_cache/VX_snp_fwd_arb.v @@ -5,28 +5,30 @@ module VX_snp_fwd_arb parameter NUM_BANKS = 8 ) ( - input wire[NUM_BANKS-1:0] per_bank_snp_fwd, - input wire[NUM_BANKS-1:0][31:0] per_bank_snp_fwd_addr, - output reg[NUM_BANKS-1:0] per_bank_snp_fwd_pop, + input wire [NUM_BANKS-1:0] per_bank_snp_fwd, + input wire [NUM_BANKS-1:0][31:0] per_bank_snp_fwd_addr, + output reg [NUM_BANKS-1:0] per_bank_snp_fwd_pop, - output wire snp_fwd, - output wire[31:0] snp_fwd_addr, - input wire snp_fwd_delay + output wire snp_fwd_valid, + output wire [31:0] snp_fwd_addr, + input wire snp_fwd_full ); - wire[NUM_BANKS-1:0] qual_per_bank_snp_fwd = per_bank_snp_fwd & {NUM_BANKS{!snp_fwd_delay}}; + wire[NUM_BANKS-1:0] qual_per_bank_snp_fwd = per_bank_snp_fwd & {NUM_BANKS{!snp_fwd_full}}; wire[`LOG2UP(NUM_BANKS)-1:0] fsq_bank; - wire fsq_valid; + wire fsq_valid; - VX_generic_priority_encoder #(.N(NUM_BANKS)) VX_sel_ffsq( + VX_generic_priority_encoder #( + .N(NUM_BANKS) + ) vx_sel_ffsq( .valids(qual_per_bank_snp_fwd), .index (fsq_bank), .found (fsq_valid) - ); + ); - assign snp_fwd = fsq_valid; + assign snp_fwd_valid = fsq_valid; assign snp_fwd_addr = per_bank_snp_fwd_addr[fsq_bank]; always @(*) begin diff --git a/hw/rtl/generic_cache/VX_tag_data_access.v b/hw/rtl/generic_cache/VX_tag_data_access.v index af768fb0..aa45981c 100644 --- a/hw/rtl/generic_cache/VX_tag_data_access.v +++ b/hw/rtl/generic_cache/VX_tag_data_access.v @@ -1,7 +1,6 @@ `include "VX_cache_config.vh" -module VX_tag_data_access - #( +module VX_tag_data_access #( // Size of cache in bytes parameter CACHE_SIZE_BYTES = 1024, // Size of line inside a bank in bytes @@ -17,8 +16,7 @@ module VX_tag_data_access // Function ID, {Dcache=0, Icache=1, Sharedmemory=2} parameter FUNC_ID = 0, -// Queues feeding into banks Knobs {1, 2, 4, 8, ...} - + // Queues feeding into banks Knobs {1, 2, 4, 8, ...} // Core Request Queue Size parameter REQQ_SIZE = 8, // Miss Reserv Queue Knob @@ -28,7 +26,7 @@ module VX_tag_data_access // Snoop Req Queue parameter SNRQ_SIZE = 8, -// Queues for writebacks Knobs {1, 2, 4, 8, ...} + // Queues for writebacks Knobs {1, 2, 4, 8, ...} // Core Writeback Queue Size parameter CWBQ_SIZE = 8, // Dram Writeback Queue Size @@ -41,24 +39,26 @@ module VX_tag_data_access // Fill Invalidator Size {Fill invalidator must be active} parameter FILL_INVALIDAOR_SIZE = 16, -// Dram knobs + // Dram knobs parameter SIMULATED_DRAM_LATENCY_CYCLES = 10 - - - ) - ( +) ( input wire clk, input wire reset, input wire stall, input wire is_snp_st1e, input wire stall_bank_pipe, // Initial Reading +/* verilator lint_off UNUSED */ + // TODO: input wire[31:0] readaddr_st10, - +/* verilator lint_on UNUSED */ // Write/Read Logic input wire valid_req_st1e, input wire writefill_st1e, +/* verilator lint_off UNUSED */ + // TODO: input wire[31:0] writeaddr_st1e, +/* verilator lint_on UNUSED */ input wire[`WORD_SIZE_RNG] writeword_st1e, input wire[`DBANK_LINE_WORDS-1:0][31:0] writedata_st1e, input wire[2:0] mem_write_st1e, @@ -69,19 +69,14 @@ module VX_tag_data_access output wire[`TAG_SELECT_SIZE_RNG] readtag_st1e, output wire miss_st1e, output wire dirty_st1e, - output wire fill_saw_dirty_st1e - + output wire fill_saw_dirty_st1e ); - - reg[`DBANK_LINE_WORDS-1:0][31:0] readdata_st[STAGE_1_CYCLES-1:0]; - reg read_valid_st1c[STAGE_1_CYCLES-1:0]; reg read_dirty_st1c[STAGE_1_CYCLES-1:0]; reg[`TAG_SELECT_SIZE_RNG] read_tag_st1c [STAGE_1_CYCLES-1:0]; reg[`DBANK_LINE_WORDS-1:0][31:0] read_data_st1c [STAGE_1_CYCLES-1:0]; - wire qual_read_valid_st1; wire qual_read_dirty_st1; wire[`TAG_SELECT_SIZE_RNG] qual_read_tag_st1; @@ -98,9 +93,9 @@ module VX_tag_data_access wire real_writefill = writefill_st1e && ((valid_req_st1e && !use_read_valid_st1e) || (valid_req_st1e && use_read_valid_st1e && (writeaddr_st1e[`TAG_SELECT_ADDR_RNG] != use_read_tag_st1e))); - wire fill_sent; wire invalidate_line; + VX_tag_data_structure #( .CACHE_SIZE_BYTES (CACHE_SIZE_BYTES), .BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES), @@ -119,14 +114,12 @@ module VX_tag_data_access .LLVQ_SIZE (LLVQ_SIZE), .FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE), .SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES) - ) - VX_tag_data_structure - ( + ) vx_tag_data_structure ( .clk (clk), .reset (reset), .stall_bank_pipe(stall_bank_pipe), - .read_addr (readaddr_st10), + .read_addr (readaddr_st10[`LINE_SELECT_ADDR_RNG]), .read_valid (qual_read_valid_st1), .read_dirty (qual_read_dirty_st1), .read_tag (qual_read_tag_st1), @@ -135,13 +128,17 @@ module VX_tag_data_access .invalidate (invalidate_line), .write_enable(use_write_enable), .write_fill (real_writefill), - .write_addr (writeaddr_st1e), + .write_addr (writeaddr_st1e[`LINE_SELECT_ADDR_RNG]), + .tag_index (writeaddr_st1e[`TAG_SELECT_ADDR_RNG]), .write_data (use_write_data), .fill_sent (fill_sent) - ); + ); // VX_generic_register #(.N( 1 + 1 + `TAG_SELECT_NUM_BITS + (`DBANK_LINE_WORDS*32) )) s0_1_c0 ( - VX_generic_register #(.N( 1 + 1 + `TAG_SELECT_NUM_BITS + (`DBANK_LINE_WORDS*32) ), .Valid(0)) s0_1_c0 ( + VX_generic_register #( + .N( 1 + 1 + `TAG_SELECT_NUM_BITS + (`DBANK_LINE_WORDS*32) ), + .PassThru(1) + ) s0_1_c0 ( .clk (clk), .reset(reset), .stall(stall), @@ -153,7 +150,9 @@ module VX_tag_data_access genvar curr_stage; generate for (curr_stage = 1; curr_stage < STAGE_1_CYCLES-1; curr_stage = curr_stage + 1) begin - VX_generic_register #(.N( 1 + 1 + `TAG_SELECT_NUM_BITS + (`DBANK_LINE_WORDS*32) )) s0_1_cc ( + VX_generic_register #( + .N( 1 + 1 + `TAG_SELECT_NUM_BITS + (`DBANK_LINE_WORDS*32)) + ) s0_1_cc ( .clk (clk), .reset(reset), .stall(stall), @@ -164,7 +163,6 @@ module VX_tag_data_access end endgenerate - assign use_read_valid_st1e = read_valid_st1c[STAGE_1_CYCLES-1] || (FUNC_ID == `SFUNC_ID); // If shared memory, always valid assign use_read_dirty_st1e = read_dirty_st1c[STAGE_1_CYCLES-1] && (FUNC_ID != `SFUNC_ID); // Dirty only applies in Dcache assign use_read_tag_st1e = (FUNC_ID == `SFUNC_ID) ? writeaddr_st1e[`TAG_SELECT_ADDR_RNG] : read_tag_st1c [STAGE_1_CYCLES-1]; // Tag is always the same in SM @@ -178,6 +176,7 @@ module VX_tag_data_access wire[`OFFSET_SIZE_RNG] byte_select = writeaddr_st1e[`OFFSET_ADDR_RNG]; wire[`WORD_SELECT_SIZE_RNG] block_offset = writeaddr_st1e[`WORD_SELECT_ADDR_RNG]; +/* verilator lint_off UNUSED */ wire lw = valid_req_st1e && (mem_read_st1e == `LW_MEM_READ); wire lb = valid_req_st1e && (mem_read_st1e == `LB_MEM_READ); wire lh = valid_req_st1e && (mem_read_st1e == `LH_MEM_READ); @@ -187,49 +186,15 @@ module VX_tag_data_access wire b0 = (byte_select == 0); wire b1 = (byte_select == 1); wire b2 = (byte_select == 2); - wire b3 = (byte_select == 3); + wire b3 = (byte_select == 3); +/* verilator lint_on UNUSED */ +/* verilator lint_off UNUSED */ wire[31:0] w0 = read_data_st1c[STAGE_1_CYCLES-1][0][31:0]; wire[31:0] w1 = read_data_st1c[STAGE_1_CYCLES-1][1][31:0]; wire[31:0] w2 = read_data_st1c[STAGE_1_CYCLES-1][2][31:0]; wire[31:0] w3 = read_data_st1c[STAGE_1_CYCLES-1][3][31:0]; - - wire[31:0] data_unmod = read_data_st1c[STAGE_1_CYCLES-1][block_offset][31:0]; - - wire[31:0] data_unQual = (b0 || lw) ? (data_unmod) : - b1 ? (data_unmod >> 8) : - b2 ? (data_unmod >> 16) : - (data_unmod >> 24); - - - wire[31:0] lb_data = (data_unQual[7] ) ? (data_unQual | 32'hFFFFFF00) : (data_unQual & 32'hFF); - wire[31:0] lh_data = (data_unQual[15]) ? (data_unQual | 32'hFFFF0000) : (data_unQual & 32'hFFFF); - wire[31:0] lbu_data = (data_unQual & 32'hFF); - wire[31:0] lhu_data = (data_unQual & 32'hFFFF); - wire[31:0] lw_data = (data_unQual); - - - wire[31:0] sw_data = writeword_st1e[31:0]; - - wire[31:0] sb_data = b1 ? {{16{1'b0}}, writeword_st1e[7:0], { 8{1'b0}}} : - b2 ? {{ 8{1'b0}}, writeword_st1e[7:0], {16{1'b0}}} : - b3 ? {{ 0{1'b0}}, writeword_st1e[7:0], {24{1'b0}}} : - writeword_st1e[31:0]; - - wire[31:0] sh_data = b2 ? {writeword_st1e[15:0], {16{1'b0}}} : writeword_st1e[31:0]; - - - - wire[31:0] use_write_dat = sb ? sb_data : - sh ? sh_data : - sw_data; - - - wire[31:0] data_Qual = lb ? lb_data : - lh ? lh_data : - lhu ? lhu_data : - lbu ? lbu_data : - lw_data; +/* verilator lint_on UNUSED */ /////////////////////// STORE LOGIC /////////////////// @@ -245,6 +210,7 @@ module VX_tag_data_access wire[`DBANK_LINE_WORDS-1:0][3:0] we; wire[`DBANK_LINE_WORDS-1:0][31:0] data_write; + genvar g; generate for (g = 0; g < `DBANK_LINE_WORDS; g = g + 1) begin : write_enables @@ -257,9 +223,18 @@ module VX_tag_data_access (normal_write && sh) ? sh_mask : 4'b0000; - if (!(FUNC_ID == `L2FUNC_ID)) assign data_write[g] = force_write ? writedata_st1e[g] : use_write_dat; + if (FUNC_ID != `L2FUNC_ID) begin + wire[31:0] sb_data = b1 ? {{16{1'b0}}, writeword_st1e[7:0], { 8{1'b0}}} : + b2 ? {{ 8{1'b0}}, writeword_st1e[7:0], {16{1'b0}}} : + b3 ? {{ 0{1'b0}}, writeword_st1e[7:0], {24{1'b0}}} : + writeword_st1e[31:0]; + wire[31:0] sw_data = writeword_st1e[31:0]; + wire[31:0] sh_data = b2 ? {writeword_st1e[15:0], {16{1'b0}}} : writeword_st1e[31:0]; + wire[31:0] use_write_dat = sb ? sb_data : sh ? sh_data : sw_data; + assign data_write[g] = force_write ? writedata_st1e[g] : use_write_dat; + end end - if ((FUNC_ID == `L2FUNC_ID)) begin + if (FUNC_ID == `L2FUNC_ID) begin assign data_write = force_write ? writedata_st1e : writeword_st1e; end endgenerate @@ -268,13 +243,29 @@ module VX_tag_data_access assign use_write_data = data_write; /////////////////////// + if (FUNC_ID == `L2FUNC_ID) begin assign readword_st1e = read_data_st1c[STAGE_1_CYCLES-1]; end else begin + wire[31:0] data_unmod = read_data_st1c[STAGE_1_CYCLES-1][block_offset][31:0]; + wire[31:0] data_unQual = (b0 || lw) ? (data_unmod) : + b1 ? (data_unmod >> 8) : + b2 ? (data_unmod >> 16) : + (data_unmod >> 24); + wire[31:0] lb_data = (data_unQual[7] ) ? (data_unQual | 32'hFFFFFF00) : (data_unQual & 32'hFF); + wire[31:0] lh_data = (data_unQual[15]) ? (data_unQual | 32'hFFFF0000) : (data_unQual & 32'hFFFF); + wire[31:0] lbu_data = (data_unQual & 32'hFF); + wire[31:0] lhu_data = (data_unQual & 32'hFFFF); + wire[31:0] lw_data = (data_unQual); + wire[31:0] data_Qual = lb ? lb_data : + lh ? lh_data : + lhu ? lhu_data : + lbu ? lbu_data : + lw_data; + assign readword_st1e = data_Qual; end - wire[`TAG_SELECT_ADDR_RNG] writeaddr_tag = writeaddr_st1e[`TAG_SELECT_ADDR_RNG]; wire tags_mismatch = writeaddr_tag != use_read_tag_st1e; diff --git a/hw/rtl/generic_cache/VX_tag_data_structure.v b/hw/rtl/generic_cache/VX_tag_data_structure.v index be81edd7..0fb13742 100644 --- a/hw/rtl/generic_cache/VX_tag_data_structure.v +++ b/hw/rtl/generic_cache/VX_tag_data_structure.v @@ -1,7 +1,6 @@ `include "VX_cache_config.vh" -module VX_tag_data_structure - #( +module VX_tag_data_structure #( // Size of cache in bytes parameter CACHE_SIZE_BYTES = 1024, // Size of line inside a bank in bytes @@ -17,8 +16,7 @@ module VX_tag_data_structure // Function ID, {Dcache=0, Icache=1, Sharedmemory=2} parameter FUNC_ID = 0, -// Queues feeding into banks Knobs {1, 2, 4, 8, ...} - + // Queues feeding into banks Knobs {1, 2, 4, 8, ...} // Core Request Queue Size parameter REQQ_SIZE = 8, // Miss Reserv Queue Knob @@ -28,7 +26,7 @@ module VX_tag_data_structure // Snoop Req Queue parameter SNRQ_SIZE = 8, -// Queues for writebacks Knobs {1, 2, 4, 8, ...} + // Queues for writebacks Knobs {1, 2, 4, 8, ...} // Core Writeback Queue Size parameter CWBQ_SIZE = 8, // Dram Writeback Queue Size @@ -41,44 +39,37 @@ module VX_tag_data_structure // Fill Invalidator Size {Fill invalidator must be active} parameter FILL_INVALIDAOR_SIZE = 16, -// Dram knobs + // Dram knobs parameter SIMULATED_DRAM_LATENCY_CYCLES = 10 +) ( + input wire clk, + input wire reset, + input wire stall_bank_pipe, - - ) - ( - input wire clk, - input wire reset, - input wire stall_bank_pipe, - - input wire[31:0] read_addr, - output wire read_valid, - output wire read_dirty, - output wire[`TAG_SELECT_SIZE_RNG] read_tag, + input wire[`LINE_SELECT_SIZE_RNG] read_addr, + output wire read_valid, + output wire read_dirty, + output wire[`TAG_SELECT_SIZE_RNG] read_tag, output wire[`DBANK_LINE_WORDS-1:0][31:0] read_data, - input wire invalidate, - input wire[`DBANK_LINE_WORDS-1:0][3:0] write_enable, - input wire write_fill, - input wire[31:0] write_addr, + input wire invalidate, + input wire[`DBANK_LINE_WORDS-1:0][3:0] write_enable, + input wire write_fill, + input wire[`LINE_SELECT_SIZE_RNG] write_addr, + input wire[`TAG_SELECT_SIZE_RNG] tag_index, input wire[`DBANK_LINE_WORDS-1:0][31:0] write_data, - input wire fill_sent - + input wire fill_sent ); - reg[`DBANK_LINE_WORDS-1:0][3:0][7:0] data [`BANK_LINE_COUNT-1:0]; - reg[`TAG_SELECT_SIZE_RNG] tag [`BANK_LINE_COUNT-1:0]; - reg valid[`BANK_LINE_COUNT-1:0]; - reg dirty[`BANK_LINE_COUNT-1:0]; + reg [`DBANK_LINE_WORDS-1:0][3:0][7:0] data [`BANK_LINE_COUNT-1:0]; + reg [`TAG_SELECT_SIZE_RNG] tag [`BANK_LINE_COUNT-1:0]; + reg valid [`BANK_LINE_COUNT-1:0]; + reg dirty [`BANK_LINE_COUNT-1:0]; - - wire[`TAG_SELECT_ADDR_RNG] curr_tag = write_addr[`TAG_SELECT_ADDR_RNG]; - wire[`LINE_SELECT_ADDR_RNG] curr_inx = write_addr[`LINE_SELECT_ADDR_RNG]; - - assign read_valid = valid[read_addr[`LINE_SELECT_ADDR_RNG]]; - assign read_dirty = dirty[read_addr[`LINE_SELECT_ADDR_RNG]]; - assign read_tag = tag [read_addr[`LINE_SELECT_ADDR_RNG]]; - assign read_data = data [read_addr[`LINE_SELECT_ADDR_RNG]]; + assign read_valid = valid [read_addr]; + assign read_dirty = dirty [read_addr]; + assign read_tag = tag [read_addr]; + assign read_data = data [read_addr]; wire going_to_write = (|write_enable); @@ -94,27 +85,27 @@ module VX_tag_data_structure end end else if (!stall_bank_pipe) begin if (going_to_write) begin - valid[write_addr[`LINE_SELECT_ADDR_RNG]] <= 1; - tag [write_addr[`LINE_SELECT_ADDR_RNG]] <= write_addr[`TAG_SELECT_ADDR_RNG]; + valid[write_addr] <= 1; + tag [write_addr] <= tag_index; if (write_fill) begin - dirty[write_addr[`LINE_SELECT_ADDR_RNG]] <= 0; + dirty[write_addr] <= 0; end else begin - dirty[write_addr[`LINE_SELECT_ADDR_RNG]] <= 1; + dirty[write_addr] <= 1; end end else if (fill_sent) begin - dirty[write_addr[`LINE_SELECT_ADDR_RNG]] <= 0; - // valid[write_addr[`LINE_SELECT_ADDR_RNG]] <= 0; + dirty[write_addr] <= 0; + // valid[write_addr] <= 0; end if (invalidate) begin - valid[write_addr[`LINE_SELECT_ADDR_RNG]] <= 0; + valid[write_addr] <= 0; end for (f = 0; f < `DBANK_LINE_WORDS; f = f + 1) begin - if (write_enable[f][0]) data[write_addr[`LINE_SELECT_ADDR_RNG]][f][0] <= write_data[f][7 :0 ]; - if (write_enable[f][1]) data[write_addr[`LINE_SELECT_ADDR_RNG]][f][1] <= write_data[f][15:8 ]; - if (write_enable[f][2]) data[write_addr[`LINE_SELECT_ADDR_RNG]][f][2] <= write_data[f][23:16]; - if (write_enable[f][3]) data[write_addr[`LINE_SELECT_ADDR_RNG]][f][3] <= write_data[f][31:24]; + if (write_enable[f][0]) data[write_addr][f][0] <= write_data[f][7 :0 ]; + if (write_enable[f][1]) data[write_addr][f][1] <= write_data[f][15:8 ]; + if (write_enable[f][2]) data[write_addr][f][2] <= write_data[f][23:16]; + if (write_enable[f][3]) data[write_addr][f][3] <= write_data[f][31:24]; end end end diff --git a/hw/rtl/interfaces/VX_branch_response_inter.v b/hw/rtl/interfaces/VX_branch_response_inter.v index d4be7be2..01bec227 100644 --- a/hw/rtl/interfaces/VX_branch_response_inter.v +++ b/hw/rtl/interfaces/VX_branch_response_inter.v @@ -4,10 +4,11 @@ `include "../VX_define.vh" interface VX_branch_response_inter (); - wire valid_branch; - wire branch_dir; - wire[31:0] branch_dest; - wire[`NW_BITS-1:0] branch_warp_num; + + wire valid_branch; + wire branch_dir; + wire [31:0] branch_dest; + wire [`NW_BITS-1:0] branch_warp_num; endinterface diff --git a/hw/rtl/interfaces/VX_csr_req_inter.v b/hw/rtl/interfaces/VX_csr_req_inter.v index 15b70985..bf9fbe72 100644 --- a/hw/rtl/interfaces/VX_csr_req_inter.v +++ b/hw/rtl/interfaces/VX_csr_req_inter.v @@ -5,15 +5,15 @@ interface VX_csr_req_inter (); - wire[`NUM_THREADS-1:0] valid; - wire[`NW_BITS-1:0] warp_num; - wire[4:0] rd; - wire[1:0] wb; - wire[4:0] alu_op; - wire is_csr; - wire[11:0] csr_address; - wire csr_immed; - wire[31:0] csr_mask; + wire [`NUM_THREADS-1:0] valid; + wire [`NW_BITS-1:0] warp_num; + wire [4:0] rd; + wire [1:0] wb; + wire [4:0] alu_op; + wire is_csr; + wire [11:0] csr_address; + wire csr_immed; + wire [31:0] csr_mask; endinterface diff --git a/hw/rtl/interfaces/VX_csr_wb_inter.v b/hw/rtl/interfaces/VX_csr_wb_inter.v index 11011a68..c33c6c2d 100644 --- a/hw/rtl/interfaces/VX_csr_wb_inter.v +++ b/hw/rtl/interfaces/VX_csr_wb_inter.v @@ -5,12 +5,12 @@ interface VX_csr_wb_inter (); - wire[`NUM_THREADS-1:0] valid; - wire[`NW_BITS-1:0] warp_num; - wire[4:0] rd; - wire[1:0] wb; + wire [`NUM_THREADS-1:0] valid; + wire [`NW_BITS-1:0] warp_num; + wire [4:0] rd; + wire [1:0] wb; - wire[`NUM_THREADS-1:0][31:0] csr_result; + wire [`NUM_THREADS-1:0][31:0] csr_result; endinterface diff --git a/hw/rtl/interfaces/VX_dcache_request_inter.v b/hw/rtl/interfaces/VX_dcache_request_inter.v index af5db2ce..64f8bca2 100644 --- a/hw/rtl/interfaces/VX_dcache_request_inter.v +++ b/hw/rtl/interfaces/VX_dcache_request_inter.v @@ -5,11 +5,11 @@ interface VX_dcache_request_inter (); - wire[`NUM_THREADS-1:0][31:0] out_cache_driver_in_address; - wire[2:0] out_cache_driver_in_mem_read; - wire[2:0] out_cache_driver_in_mem_write; - wire[`NUM_THREADS-1:0] out_cache_driver_in_valid; - wire[`NUM_THREADS-1:0][31:0] out_cache_driver_in_data; + wire [`NUM_THREADS-1:0][31:0] out_cache_driver_in_address; + wire [2:0] out_cache_driver_in_mem_read; + wire [2:0] out_cache_driver_in_mem_write; + wire [`NUM_THREADS-1:0] out_cache_driver_in_valid; + wire [`NUM_THREADS-1:0][31:0] out_cache_driver_in_data; endinterface diff --git a/hw/rtl/interfaces/VX_dcache_response_inter.v b/hw/rtl/interfaces/VX_dcache_response_inter.v index c48bce7b..b849786c 100644 --- a/hw/rtl/interfaces/VX_dcache_response_inter.v +++ b/hw/rtl/interfaces/VX_dcache_response_inter.v @@ -5,8 +5,8 @@ interface VX_dcache_response_inter (); - wire[`NUM_THREADS-1:0][31:0] in_cache_driver_out_data; - wire delay; + wire [`NUM_THREADS-1:0][31:0] in_cache_driver_out_data; + wire delay; endinterface diff --git a/hw/rtl/interfaces/VX_dram_req_rsp_inter.v b/hw/rtl/interfaces/VX_dram_req_rsp_inter.v index 52ce5f4f..1edc3b3d 100644 --- a/hw/rtl/interfaces/VX_dram_req_rsp_inter.v +++ b/hw/rtl/interfaces/VX_dram_req_rsp_inter.v @@ -6,18 +6,19 @@ interface VX_dram_req_rsp_inter #( parameter NUM_BANKS = 8, - parameter NUM_WORDS_PER_BLOCK = 4) (); + parameter NUM_WORDS_PER_BLOCK = 4 +) (); // Req - wire [31:0] o_m_evict_addr; - wire [31:0] o_m_read_addr; - wire o_m_valid; - wire[NUM_BANKS - 1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] o_m_writedata; - wire o_m_read_or_write; + wire [31:0] o_m_evict_addr; + wire [31:0] o_m_read_addr; + wire o_m_valid; + wire [NUM_BANKS - 1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] o_m_writedata; + wire o_m_read_or_write; // Rsp - wire[NUM_BANKS - 1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata; - wire i_m_ready; + wire [NUM_BANKS - 1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata; + wire i_m_ready; endinterface diff --git a/hw/rtl/interfaces/VX_exec_unit_req_inter.v b/hw/rtl/interfaces/VX_exec_unit_req_inter.v index eef7e745..495a0d96 100644 --- a/hw/rtl/interfaces/VX_exec_unit_req_inter.v +++ b/hw/rtl/interfaces/VX_exec_unit_req_inter.v @@ -6,43 +6,43 @@ interface VX_exec_unit_req_inter (); // Meta - wire[`NUM_THREADS-1:0] valid; - wire[`NW_BITS-1:0] warp_num; - wire[31:0] curr_PC; - wire[31:0] PC_next; + wire [`NUM_THREADS-1:0] valid; + wire [`NW_BITS-1:0] warp_num; + wire [31:0] curr_PC; + wire [31:0] PC_next; // Write Back Info - wire[4:0] rd; - wire[1:0] wb; + wire [4:0] rd; + wire [1:0] wb; // Data and alu op - wire[`NUM_THREADS-1:0][31:0] a_reg_data; - wire[`NUM_THREADS-1:0][31:0] b_reg_data; - wire[4:0] alu_op; - wire[4:0] rs1; - wire[4:0] rs2; - wire rs2_src; - wire[31:0] itype_immed; - wire[19:0] upper_immed; + wire [`NUM_THREADS-1:0][31:0] a_reg_data; + wire [`NUM_THREADS-1:0][31:0] b_reg_data; + wire [4:0] alu_op; + wire [4:0] rs1; + wire [4:0] rs2; + wire rs2_src; + wire [31:0] itype_immed; + wire [19:0] upper_immed; // Branch type - wire[2:0] branch_type; + wire [2:0] branch_type; // Jal info - wire jalQual; - wire jal; - wire[31:0] jal_offset; + wire jalQual; + wire jal; + wire [31:0] jal_offset; - /* verilator lint_off UNUSED */ - wire ebreak; - wire wspawn; - /* verilator lint_on UNUSED */ +/* verilator lint_off UNUSED */ + wire ebreak; + wire wspawn; +/* verilator lint_on UNUSED */ // CSR info - wire is_csr; - wire[11:0] csr_address; - wire csr_immed; - wire[31:0] csr_mask; + wire is_csr; + wire [11:0] csr_address; + wire csr_immed; + wire [31:0] csr_mask; endinterface diff --git a/hw/rtl/interfaces/VX_frE_to_bckE_req_inter.v b/hw/rtl/interfaces/VX_frE_to_bckE_req_inter.v index 8a30ff57..bc96b3fb 100644 --- a/hw/rtl/interfaces/VX_frE_to_bckE_req_inter.v +++ b/hw/rtl/interfaces/VX_frE_to_bckE_req_inter.v @@ -5,37 +5,37 @@ interface VX_frE_to_bckE_req_inter (); - wire[11:0] csr_address; - wire is_csr; - wire csr_immed; - wire[31:0] csr_mask; - wire[4:0] rd; - wire[4:0] rs1; - wire[4:0] rs2; - wire[4:0] alu_op; - wire[1:0] wb; - wire rs2_src; - wire[31:0] itype_immed; - wire[2:0] mem_read; - wire[2:0] mem_write; - wire[2:0] branch_type; - wire[19:0] upper_immed; - wire[31:0] curr_PC; - /* verilator lint_off UNUSED */ - wire ebreak; - /* verilator lint_on UNUSED */ - wire jalQual; - wire jal; - wire[31:0] jal_offset; - wire[31:0] PC_next; - wire[`NUM_THREADS-1:0] valid; - wire[`NW_BITS-1:0] warp_num; + wire [11:0] csr_address; + wire is_csr; + wire csr_immed; + wire [31:0] csr_mask; + wire [4:0] rd; + wire [4:0] rs1; + wire [4:0] rs2; + wire [4:0] alu_op; + wire [1:0] wb; + wire rs2_src; + wire [31:0] itype_immed; + wire [2:0] mem_read; + wire [2:0] mem_write; + wire [2:0] branch_type; + wire [19:0] upper_immed; + wire [31:0] curr_PC; +/* verilator lint_off UNUSED */ + wire ebreak; +/* verilator lint_on UNUSED */ + wire jalQual; + wire jal; + wire [31:0] jal_offset; + wire [31:0] PC_next; + wire [`NUM_THREADS-1:0] valid; + wire [`NW_BITS-1:0] warp_num; // GPGPU stuff - wire is_wspawn; - wire is_tmc; - wire is_split; - wire is_barrier; + wire is_wspawn; + wire is_tmc; + wire is_split; + wire is_barrier; endinterface diff --git a/hw/rtl/interfaces/VX_gpr_clone_inter.v b/hw/rtl/interfaces/VX_gpr_clone_inter.v index d281194e..9ffbe6ff 100644 --- a/hw/rtl/interfaces/VX_gpr_clone_inter.v +++ b/hw/rtl/interfaces/VX_gpr_clone_inter.v @@ -5,12 +5,10 @@ `include "../VX_define.vh" interface VX_gpr_clone_inter (); - /* verilator lint_off UNUSED */ - wire is_clone; - wire[`NW_BITS-1:0] warp_num; + wire is_clone; + wire[`NW_BITS-1:0] warp_num; /* verilator lint_on UNUSED */ - endinterface `endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_gpr_data_inter.v b/hw/rtl/interfaces/VX_gpr_data_inter.v index 19554bcb..7987ecda 100644 --- a/hw/rtl/interfaces/VX_gpr_data_inter.v +++ b/hw/rtl/interfaces/VX_gpr_data_inter.v @@ -6,8 +6,8 @@ interface VX_gpr_data_inter (); - wire[`NUM_THREADS-1:0][31:0] a_reg_data; - wire[`NUM_THREADS-1:0][31:0] b_reg_data; + wire [`NUM_THREADS-1:0][31:0] a_reg_data; + wire [`NUM_THREADS-1:0][31:0] b_reg_data; endinterface diff --git a/hw/rtl/interfaces/VX_gpr_read_inter.v b/hw/rtl/interfaces/VX_gpr_read_inter.v index b69e17d4..33d3abae 100644 --- a/hw/rtl/interfaces/VX_gpr_read_inter.v +++ b/hw/rtl/interfaces/VX_gpr_read_inter.v @@ -5,9 +5,9 @@ interface VX_gpr_read_inter (); - wire[4:0] rs1; - wire[4:0] rs2; - wire[`NW_BITS-1:0] warp_num; + wire [4:0] rs1; + wire [4:0] rs2; + wire [`NW_BITS-1:0] warp_num; endinterface diff --git a/hw/rtl/interfaces/VX_gpr_wspawn_inter.v b/hw/rtl/interfaces/VX_gpr_wspawn_inter.v index 1670da07..f3798f99 100644 --- a/hw/rtl/interfaces/VX_gpr_wspawn_inter.v +++ b/hw/rtl/interfaces/VX_gpr_wspawn_inter.v @@ -6,10 +6,9 @@ interface VX_gpr_wspawn_inter (); /* verilator lint_off UNUSED */ wire is_wspawn; - wire[`NW_BITS-1:0] which_wspawn; + wire [`NW_BITS-1:0] which_wspawn; // wire[`NW_BITS-1:0] warp_num; /* verilator lint_on UNUSED */ - endinterface `endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_gpu_dcache_dram_req_inter.v b/hw/rtl/interfaces/VX_gpu_dcache_dram_req_inter.v index 8fabfec4..06299c95 100644 --- a/hw/rtl/interfaces/VX_gpu_dcache_dram_req_inter.v +++ b/hw/rtl/interfaces/VX_gpu_dcache_dram_req_inter.v @@ -1,33 +1,20 @@ - - `ifndef VX_GPU_DRAM_DCACHE_REQ `define VX_GPU_DRAM_DCACHE_REQ `include "../generic_cache/VX_cache_config.vh" -interface VX_gpu_dcache_dram_req_inter - #( - parameter BANK_LINE_WORDS = 2 - ) - (); +interface VX_gpu_dcache_dram_req_inter #( + parameter BANK_LINE_WORDS = 2 +) (); // DRAM Request - wire dram_req; wire dram_req_write; wire dram_req_read; wire [31:0] dram_req_addr; - wire [31:0] dram_req_size; - wire [BANK_LINE_WORDS-1:0][31:0] dram_req_data; + wire [BANK_LINE_WORDS-1:0][31:0] dram_req_data; + wire dram_req_full; - // Snoop - wire dram_because_of_snp; - wire dram_snp_full; - - // DRAM Cache can't accept response - wire dram_fill_accept; - - // DRAM Cache can't accept request - wire dram_req_delay; + wire dram_rsp_ready; endinterface diff --git a/hw/rtl/interfaces/VX_gpu_dcache_dram_res_inter.v b/hw/rtl/interfaces/VX_gpu_dcache_dram_res_inter.v deleted file mode 100644 index e6a3bfa0..00000000 --- a/hw/rtl/interfaces/VX_gpu_dcache_dram_res_inter.v +++ /dev/null @@ -1,18 +0,0 @@ -`ifndef VX_GPU_DRAM_DCACHE_RES -`define VX_GPU_DRAM_DCACHE_RES - -`include "../generic_cache/VX_cache_config.vh" - -interface VX_gpu_dcache_dram_res_inter - #( - parameter BANK_LINE_WORDS = 2 - ) - (); - // DRAM Rsponse - wire dram_fill_rsp; - wire [31:0] dram_fill_rsp_addr; - wire [BANK_LINE_WORDS-1:0][31:0] dram_fill_rsp_data; - -endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_gpu_dcache_dram_rsp_inter.v b/hw/rtl/interfaces/VX_gpu_dcache_dram_rsp_inter.v new file mode 100644 index 00000000..e7e270ea --- /dev/null +++ b/hw/rtl/interfaces/VX_gpu_dcache_dram_rsp_inter.v @@ -0,0 +1,16 @@ +`ifndef VX_GPU_DRAM_DCACHE_RSP +`define VX_GPU_DRAM_DCACHE_RSP + +`include "../generic_cache/VX_cache_config.vh" + +interface VX_gpu_dcache_dram_rsp_inter #( + parameter BANK_LINE_WORDS = 2 +) (); + // DRAM Response + wire dram_rsp_valid; + wire [31:0] dram_rsp_addr; + wire [BANK_LINE_WORDS-1:0][31:0] dram_rsp_data; + +endinterface + +`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_gpu_dcache_req_inter.v b/hw/rtl/interfaces/VX_gpu_dcache_req_inter.v index a848261d..c70165e1 100644 --- a/hw/rtl/interfaces/VX_gpu_dcache_req_inter.v +++ b/hw/rtl/interfaces/VX_gpu_dcache_req_inter.v @@ -1,15 +1,11 @@ - - `ifndef VX_GPU_DCACHE_REQ `define VX_GPU_DCACHE_REQ `include "../generic_cache/VX_cache_config.vh" -interface VX_gpu_dcache_req_inter - #( - parameter NUM_REQUESTS = 32 - ) - (); +interface VX_gpu_dcache_req_inter #( + parameter NUM_REQUESTS = 32 +) (); // Core Request wire [NUM_REQUESTS-1:0] core_req_valid; diff --git a/hw/rtl/interfaces/VX_gpu_dcache_res_inter.v b/hw/rtl/interfaces/VX_gpu_dcache_rsp_inter.v similarity index 70% rename from hw/rtl/interfaces/VX_gpu_dcache_res_inter.v rename to hw/rtl/interfaces/VX_gpu_dcache_rsp_inter.v index 9eeed08d..d7c8717a 100644 --- a/hw/rtl/interfaces/VX_gpu_dcache_res_inter.v +++ b/hw/rtl/interfaces/VX_gpu_dcache_rsp_inter.v @@ -1,17 +1,18 @@ -`ifndef VX_GPU_DCACHE_RES -`define VX_GPU_DCACHE_RES +`ifndef VX_GPU_DCACHE_RSP +`define VX_GPU_DCACHE_RSP `include "../generic_cache/VX_cache_config.vh" -interface VX_gpu_dcache_res_inter - #( - parameter NUM_REQUESTS = 32 - ) (); +interface VX_gpu_dcache_rsp_inter #( + parameter NUM_REQUESTS = 32 +) (); // Cache WB wire [NUM_REQUESTS-1:0] core_wb_valid; +/* verilator lint_off UNUSED */ wire [4:0] core_wb_req_rd; wire [1:0] core_wb_req_wb; +/* verilator lint_off UNUSED */ wire [`NW_BITS-1:0] core_wb_warp_num; wire [NUM_REQUESTS-1:0][31:0] core_wb_readdata; wire [NUM_REQUESTS-1:0][31:0] core_wb_pc; diff --git a/hw/rtl/interfaces/VX_gpu_dcache_snp_req_inter.v b/hw/rtl/interfaces/VX_gpu_dcache_snp_req_inter.v index 89c6855f..254c652a 100644 --- a/hw/rtl/interfaces/VX_gpu_dcache_snp_req_inter.v +++ b/hw/rtl/interfaces/VX_gpu_dcache_snp_req_inter.v @@ -5,7 +5,7 @@ interface VX_gpu_dcache_snp_req_inter (); // Snoop Req - wire snp_req; + wire snp_req_valid; wire [31:0] snp_req_addr; endinterface diff --git a/hw/rtl/interfaces/VX_gpu_inst_req_inter.v b/hw/rtl/interfaces/VX_gpu_inst_req_inter.v index af3e5648..5a01813d 100644 --- a/hw/rtl/interfaces/VX_gpu_inst_req_inter.v +++ b/hw/rtl/interfaces/VX_gpu_inst_req_inter.v @@ -5,8 +5,8 @@ interface VX_gpu_inst_req_inter(); - wire[`NUM_THREADS-1:0] valid; - wire[`NW_BITS-1:0] warp_num; + wire [`NUM_THREADS-1:0] valid; + wire [`NW_BITS-1:0] warp_num; wire is_wspawn; wire is_tmc; wire is_split; @@ -15,8 +15,8 @@ interface VX_gpu_inst_req_inter(); wire[31:0] pc_next; - wire[`NUM_THREADS-1:0][31:0] a_reg_data; - wire[31:0] rd2; + wire [`NUM_THREADS-1:0][31:0] a_reg_data; + wire [31:0] rd2; endinterface diff --git a/hw/rtl/interfaces/VX_gpu_snp_req_rsp.v b/hw/rtl/interfaces/VX_gpu_snp_req_rsp.v index 6ca2541d..0b25c32b 100644 --- a/hw/rtl/interfaces/VX_gpu_snp_req_rsp.v +++ b/hw/rtl/interfaces/VX_gpu_snp_req_rsp.v @@ -6,11 +6,12 @@ interface VX_gpu_snp_req_rsp (); // Snoop request - wire snp_req; - wire[31:0] snp_req_addr; + wire snp_req_valid; + wire [31:0] snp_req_addr; + wire snp_req_full; // Snoop Response - wire snp_delay; + // TODO: endinterface diff --git a/hw/rtl/interfaces/VX_icache_request_inter.v b/hw/rtl/interfaces/VX_icache_request_inter.v index aa4ee22a..116ba841 100644 --- a/hw/rtl/interfaces/VX_icache_request_inter.v +++ b/hw/rtl/interfaces/VX_icache_request_inter.v @@ -6,11 +6,11 @@ interface VX_icache_request_inter (); - wire[31:0] pc_address; - wire[2:0] out_cache_driver_in_mem_read; - wire[2:0] out_cache_driver_in_mem_write; - wire out_cache_driver_in_valid; - wire[31:0] out_cache_driver_in_data; + wire [31:0] pc_address; + wire [2:0] out_cache_driver_in_mem_read; + wire [2:0] out_cache_driver_in_mem_write; + wire out_cache_driver_in_valid; + wire [31:0] out_cache_driver_in_data; endinterface diff --git a/hw/rtl/interfaces/VX_icache_response_inter.v b/hw/rtl/interfaces/VX_icache_response_inter.v index 3ca7a37a..0660428f 100644 --- a/hw/rtl/interfaces/VX_icache_response_inter.v +++ b/hw/rtl/interfaces/VX_icache_response_inter.v @@ -7,8 +7,8 @@ interface VX_icache_response_inter (); // wire ready; // wire stall; - wire[31:0] instruction; - wire delay; + wire [31:0] instruction; + wire delay; endinterface diff --git a/hw/rtl/interfaces/VX_inst_exec_wb_inter.v b/hw/rtl/interfaces/VX_inst_exec_wb_inter.v index 50535566..a3ffa03b 100644 --- a/hw/rtl/interfaces/VX_inst_exec_wb_inter.v +++ b/hw/rtl/interfaces/VX_inst_exec_wb_inter.v @@ -6,12 +6,12 @@ interface VX_inst_exec_wb_inter (); - wire[`NUM_THREADS-1:0][31:0] alu_result; - wire[31:0] exec_wb_pc; - wire[4:0] rd; - wire[1:0] wb; - wire[`NUM_THREADS-1:0] wb_valid; - wire[`NW_BITS-1:0] wb_warp_num; + wire [`NUM_THREADS-1:0][31:0] alu_result; + wire [31:0] exec_wb_pc; + wire [4:0] rd; + wire [1:0] wb; + wire [`NUM_THREADS-1:0] wb_valid; + wire [`NW_BITS-1:0] wb_warp_num; endinterface diff --git a/hw/rtl/interfaces/VX_inst_mem_wb_inter.v b/hw/rtl/interfaces/VX_inst_mem_wb_inter.v index 54d548cd..a5b47e9e 100644 --- a/hw/rtl/interfaces/VX_inst_mem_wb_inter.v +++ b/hw/rtl/interfaces/VX_inst_mem_wb_inter.v @@ -6,12 +6,12 @@ interface VX_inst_mem_wb_inter (); - wire[`NUM_THREADS-1:0][31:0] loaded_data; - wire[31:0] mem_wb_pc; - wire[4:0] rd; - wire[1:0] wb; - wire[`NUM_THREADS-1:0] wb_valid; - wire[`NW_BITS-1:0] wb_warp_num; + wire [`NUM_THREADS-1:0][31:0] loaded_data; + wire [31:0] mem_wb_pc; + wire [4:0] rd; + wire [1:0] wb; + wire [`NUM_THREADS-1:0] wb_valid; + wire [`NW_BITS-1:0] wb_warp_num; endinterface diff --git a/hw/rtl/interfaces/VX_inst_meta_inter.v b/hw/rtl/interfaces/VX_inst_meta_inter.v index 084d4d27..9dbfc368 100644 --- a/hw/rtl/interfaces/VX_inst_meta_inter.v +++ b/hw/rtl/interfaces/VX_inst_meta_inter.v @@ -5,10 +5,10 @@ interface VX_inst_meta_inter (); - wire[31:0] instruction; - wire[31:0] inst_pc; - wire[`NW_BITS-1:0] warp_num; - wire[`NUM_THREADS-1:0] valid; + wire [31:0] instruction; + wire [31:0] inst_pc; + wire [`NW_BITS-1:0] warp_num; + wire [`NUM_THREADS-1:0] valid; endinterface diff --git a/hw/rtl/interfaces/VX_jal_response_inter.v b/hw/rtl/interfaces/VX_jal_response_inter.v index 288fe350..85784b17 100644 --- a/hw/rtl/interfaces/VX_jal_response_inter.v +++ b/hw/rtl/interfaces/VX_jal_response_inter.v @@ -7,8 +7,8 @@ interface VX_jal_response_inter (); wire jal; - wire[31:0] jal_dest; - wire[`NW_BITS-1:0] jal_warp_num; + wire [31:0] jal_dest; + wire [`NW_BITS-1:0] jal_warp_num; endinterface diff --git a/hw/rtl/interfaces/VX_join_inter.v b/hw/rtl/interfaces/VX_join_inter.v index 89b907c4..98ff29e7 100644 --- a/hw/rtl/interfaces/VX_join_inter.v +++ b/hw/rtl/interfaces/VX_join_inter.v @@ -6,8 +6,8 @@ interface VX_join_inter (); - wire is_join; - wire[`NW_BITS-1:0] join_warp_num; + wire is_join; + wire [`NW_BITS-1:0] join_warp_num; endinterface diff --git a/hw/rtl/interfaces/VX_lsu_req_inter.v b/hw/rtl/interfaces/VX_lsu_req_inter.v index 752a689b..75c9682f 100644 --- a/hw/rtl/interfaces/VX_lsu_req_inter.v +++ b/hw/rtl/interfaces/VX_lsu_req_inter.v @@ -6,16 +6,16 @@ interface VX_lsu_req_inter (); - wire[`NUM_THREADS-1:0] valid; - wire[31:0] lsu_pc; - wire[`NW_BITS-1:0] warp_num; - wire[`NUM_THREADS-1:0][31:0] store_data; - wire[`NUM_THREADS-1:0][31:0] base_address; // A reg data - wire[31:0] offset; // itype_immed - wire[2:0] mem_read; - wire[2:0] mem_write; - wire[4:0] rd; - wire[1:0] wb; + wire [`NUM_THREADS-1:0] valid; + wire [31:0] lsu_pc; + wire [`NW_BITS-1:0] warp_num; + wire [`NUM_THREADS-1:0][31:0] store_data; + wire [`NUM_THREADS-1:0][31:0] base_address; // A reg data + wire [31:0] offset; // itype_immed + wire [2:0] mem_read; + wire [2:0] mem_write; + wire [4:0] rd; + wire [1:0] wb; endinterface diff --git a/hw/rtl/interfaces/VX_mem_req_inter.v b/hw/rtl/interfaces/VX_mem_req_inter.v index 03b4711f..0f0920cd 100644 --- a/hw/rtl/interfaces/VX_mem_req_inter.v +++ b/hw/rtl/interfaces/VX_mem_req_inter.v @@ -5,20 +5,20 @@ interface VX_mem_req_inter (); - wire[`NUM_THREADS-1:0][31:0] alu_result; - wire[2:0] mem_read; - wire[2:0] mem_write; - wire[4:0] rd; - wire[1:0] wb; - wire[4:0] rs1; - wire[4:0] rs2; - wire[`NUM_THREADS-1:0][31:0] rd2; - wire[31:0] PC_next; - wire[31:0] curr_PC; - wire[31:0] branch_offset; - wire[2:0] branch_type; - wire[`NUM_THREADS-1:0] valid; - wire[`NW_BITS-1:0] warp_num; + wire [`NUM_THREADS-1:0][31:0] alu_result; + wire [2:0] mem_read; + wire [2:0] mem_write; + wire [4:0] rd; + wire [1:0] wb; + wire [4:0] rs1; + wire [4:0] rs2; + wire [`NUM_THREADS-1:0][31:0] rd2; + wire [31:0] PC_next; + wire [31:0] curr_PC; + wire [31:0] branch_offset; + wire [2:0] branch_type; + wire [`NUM_THREADS-1:0] valid; + wire [`NW_BITS-1:0] warp_num; endinterface diff --git a/hw/rtl/interfaces/VX_mw_wb_inter.v b/hw/rtl/interfaces/VX_mw_wb_inter.v index 0dc72f45..a9bfeada 100644 --- a/hw/rtl/interfaces/VX_mw_wb_inter.v +++ b/hw/rtl/interfaces/VX_mw_wb_inter.v @@ -6,13 +6,13 @@ interface VX_mw_wb_inter (); - wire[`NUM_THREADS-1:0][31:0] alu_result; - wire[`NUM_THREADS-1:0][31:0] mem_result; - wire[4:0] rd; - wire[1:0] wb; - wire[31:0] PC_next; - wire[`NUM_THREADS-1:0] valid; - wire [`NW_BITS-1:0] warp_num; + wire [`NUM_THREADS-1:0][31:0] alu_result; + wire [`NUM_THREADS-1:0][31:0] mem_result; + wire [4:0] rd; + wire [1:0] wb; + wire [31:0] PC_next; + wire [`NUM_THREADS-1:0] valid; + wire [`NW_BITS-1:0] warp_num; endinterface diff --git a/hw/rtl/interfaces/VX_warp_ctl_inter.v b/hw/rtl/interfaces/VX_warp_ctl_inter.v index 88f1a961..5da935dd 100644 --- a/hw/rtl/interfaces/VX_warp_ctl_inter.v +++ b/hw/rtl/interfaces/VX_warp_ctl_inter.v @@ -6,27 +6,29 @@ interface VX_warp_ctl_inter (); - wire[`NW_BITS-1:0] warp_num; - wire change_mask; - wire[`NUM_THREADS-1:0] thread_mask; + wire [`NW_BITS-1:0] warp_num; + wire change_mask; + wire [`NUM_THREADS-1:0] thread_mask; - wire wspawn; - wire[31:0] wspawn_pc; - wire[`NUM_WARPS-1:0] wspawn_new_active; + wire wspawn; + wire [31:0] wspawn_pc; + wire [`NUM_WARPS-1:0] wspawn_new_active; - wire ebreak; + wire ebreak; // barrier - wire is_barrier; - wire[31:0] barrier_id; - wire[$clog2(`NUM_WARPS):0] num_warps; + wire is_barrier; + wire [31:0] barrier_id; + wire [$clog2(`NUM_WARPS):0] num_warps; - wire is_split; - wire dont_split; - wire[`NW_BITS-1:0] split_warp_num; - wire[`NUM_THREADS-1:0] split_new_mask; - wire[`NUM_THREADS-1:0] split_later_mask; - wire[31:0] split_save_pc; + wire is_split; + wire dont_split; +/* verilator lint_off UNUSED */ + wire [`NW_BITS-1:0] split_warp_num; +/* verilator lint_on UNUSED */ + wire [`NUM_THREADS-1:0] split_new_mask; + wire [`NUM_THREADS-1:0] split_later_mask; + wire [31:0] split_save_pc; endinterface diff --git a/hw/rtl/interfaces/VX_wb_inter.v b/hw/rtl/interfaces/VX_wb_inter.v index 4941e7aa..4a7f64ab 100644 --- a/hw/rtl/interfaces/VX_wb_inter.v +++ b/hw/rtl/interfaces/VX_wb_inter.v @@ -5,12 +5,12 @@ interface VX_wb_inter (); - wire[`NUM_THREADS-1:0][31:0] write_data; - wire[31:0] wb_pc; - wire[4:0] rd; - wire[1:0] wb; - wire[`NUM_THREADS-1:0] wb_valid; - wire[`NW_BITS-1:0] wb_warp_num; + wire [`NUM_THREADS-1:0][31:0] write_data; + wire [31:0] wb_pc; + wire [4:0] rd; + wire [1:0] wb; + wire [`NUM_THREADS-1:0] wb_valid; + wire [`NW_BITS-1:0] wb_warp_num; endinterface diff --git a/hw/rtl/interfaces/VX_wstall_inter.v b/hw/rtl/interfaces/VX_wstall_inter.v index 23f83196..be215d65 100644 --- a/hw/rtl/interfaces/VX_wstall_inter.v +++ b/hw/rtl/interfaces/VX_wstall_inter.v @@ -5,8 +5,8 @@ interface VX_wstall_inter(); - wire wstall; - wire[`NW_BITS-1:0] warp_num; + wire wstall; + wire [`NW_BITS-1:0] warp_num; endinterface diff --git a/hw/rtl/pipe_regs/VX_d_e_reg.v b/hw/rtl/pipe_regs/VX_d_e_reg.v index 26b3576b..8be24a3b 100644 --- a/hw/rtl/pipe_regs/VX_d_e_reg.v +++ b/hw/rtl/pipe_regs/VX_d_e_reg.v @@ -1,32 +1,28 @@ `include "../VX_define.vh" module VX_d_e_reg ( - input wire clk, - input wire reset, - input wire in_branch_stall, - input wire in_freeze, - VX_frE_to_bckE_req_inter VX_frE_to_bckE_req, + input wire clk, + input wire reset, + input wire in_branch_stall, + input wire in_freeze, + VX_frE_to_bckE_req_inter vx_frE_to_bckE_req, + VX_frE_to_bckE_req_inter vx_bckE_req +); + wire stall = in_freeze; + wire flush = (in_branch_stall == `STALL); - VX_frE_to_bckE_req_inter VX_bckE_req + VX_generic_register #( + .N(233 + `NW_BITS-1 + 1 + `NUM_THREADS) + ) d_e_reg ( + .clk (clk), + .reset (reset), + .stall (stall), + .flush (flush), + .in ({vx_frE_to_bckE_req.csr_address, vx_frE_to_bckE_req.jalQual, vx_frE_to_bckE_req.ebreak, vx_frE_to_bckE_req.is_csr, vx_frE_to_bckE_req.csr_immed, vx_frE_to_bckE_req.csr_mask, vx_frE_to_bckE_req.rd, vx_frE_to_bckE_req.rs1, vx_frE_to_bckE_req.rs2, vx_frE_to_bckE_req.alu_op, vx_frE_to_bckE_req.wb, vx_frE_to_bckE_req.rs2_src, vx_frE_to_bckE_req.itype_immed, vx_frE_to_bckE_req.mem_read, vx_frE_to_bckE_req.mem_write, vx_frE_to_bckE_req.branch_type, vx_frE_to_bckE_req.upper_immed, vx_frE_to_bckE_req.curr_PC, vx_frE_to_bckE_req.jal, vx_frE_to_bckE_req.jal_offset, vx_frE_to_bckE_req.PC_next, vx_frE_to_bckE_req.valid, vx_frE_to_bckE_req.warp_num, vx_frE_to_bckE_req.is_wspawn, vx_frE_to_bckE_req.is_tmc, vx_frE_to_bckE_req.is_split, vx_frE_to_bckE_req.is_barrier}), + .out ({vx_bckE_req.csr_address , vx_bckE_req.jalQual , vx_bckE_req.ebreak ,vx_bckE_req.is_csr , vx_bckE_req.csr_immed , vx_bckE_req.csr_mask , vx_bckE_req.rd , vx_bckE_req.rs1 , vx_bckE_req.rs2 , vx_bckE_req.alu_op , vx_bckE_req.wb , vx_bckE_req.rs2_src , vx_bckE_req.itype_immed , vx_bckE_req.mem_read , vx_bckE_req.mem_write , vx_bckE_req.branch_type , vx_bckE_req.upper_immed , vx_bckE_req.curr_PC , vx_bckE_req.jal , vx_bckE_req.jal_offset , vx_bckE_req.PC_next , vx_bckE_req.valid , vx_bckE_req.warp_num , vx_bckE_req.is_wspawn , vx_bckE_req.is_tmc , vx_bckE_req.is_split , vx_bckE_req.is_barrier }) ); - - wire stall = in_freeze; - wire flush = (in_branch_stall == `STALL); - - - VX_generic_register #(.N(233 + `NW_BITS-1 + 1 + `NUM_THREADS)) d_e_reg - ( - .clk (clk), - .reset(reset), - .stall(stall), - .flush(flush), - .in ({VX_frE_to_bckE_req.csr_address, VX_frE_to_bckE_req.jalQual, VX_frE_to_bckE_req.ebreak, VX_frE_to_bckE_req.is_csr, VX_frE_to_bckE_req.csr_immed, VX_frE_to_bckE_req.csr_mask, VX_frE_to_bckE_req.rd, VX_frE_to_bckE_req.rs1, VX_frE_to_bckE_req.rs2, VX_frE_to_bckE_req.alu_op, VX_frE_to_bckE_req.wb, VX_frE_to_bckE_req.rs2_src, VX_frE_to_bckE_req.itype_immed, VX_frE_to_bckE_req.mem_read, VX_frE_to_bckE_req.mem_write, VX_frE_to_bckE_req.branch_type, VX_frE_to_bckE_req.upper_immed, VX_frE_to_bckE_req.curr_PC, VX_frE_to_bckE_req.jal, VX_frE_to_bckE_req.jal_offset, VX_frE_to_bckE_req.PC_next, VX_frE_to_bckE_req.valid, VX_frE_to_bckE_req.warp_num, VX_frE_to_bckE_req.is_wspawn, VX_frE_to_bckE_req.is_tmc, VX_frE_to_bckE_req.is_split, VX_frE_to_bckE_req.is_barrier}), - .out ({VX_bckE_req.csr_address , VX_bckE_req.jalQual , VX_bckE_req.ebreak ,VX_bckE_req.is_csr , VX_bckE_req.csr_immed , VX_bckE_req.csr_mask , VX_bckE_req.rd , VX_bckE_req.rs1 , VX_bckE_req.rs2 , VX_bckE_req.alu_op , VX_bckE_req.wb , VX_bckE_req.rs2_src , VX_bckE_req.itype_immed , VX_bckE_req.mem_read , VX_bckE_req.mem_write , VX_bckE_req.branch_type , VX_bckE_req.upper_immed , VX_bckE_req.curr_PC , VX_bckE_req.jal , VX_bckE_req.jal_offset , VX_bckE_req.PC_next , VX_bckE_req.valid , VX_bckE_req.warp_num , VX_bckE_req.is_wspawn , VX_bckE_req.is_tmc , VX_bckE_req.is_split , VX_bckE_req.is_barrier }) - ); - - endmodule diff --git a/hw/rtl/shared_memory/VX_priority_encoder_sm.v b/hw/rtl/shared_memory/VX_priority_encoder_sm.v index d976d6da..e55ea1cb 100644 --- a/hw/rtl/shared_memory/VX_priority_encoder_sm.v +++ b/hw/rtl/shared_memory/VX_priority_encoder_sm.v @@ -102,7 +102,7 @@ module VX_priority_encoder_sm // wire[`NUM_THREADS-1:0] new_left_requests = left_requests & ~(serviced_qual); - always @(posedge clk, posedge reset) begin + always @(posedge clk) begin if (reset) begin left_requests <= 0; // serviced = 0; diff --git a/hw/rtl/shared_memory/VX_shared_memory_block.v b/hw/rtl/shared_memory/VX_shared_memory_block.v index 1452004d..c879176c 100644 --- a/hw/rtl/shared_memory/VX_shared_memory_block.v +++ b/hw/rtl/shared_memory/VX_shared_memory_block.v @@ -8,8 +8,8 @@ module VX_shared_memory_block parameter BITS_PER_BANK = 3 ) ( - input wire clk, // Clock - input wire reset, + input wire clk, // Clock + input wire reset, //input wire[6:0] addr, //input wire[3:0][31:0] wdata, //input wire[1:0] we, @@ -22,28 +22,16 @@ module VX_shared_memory_block input wire shm_write, output wire[SMB_WORDS_PER_READ-1:0][31:0] data_out - ); - - `ifndef SYN - reg[SMB_WORDS_PER_READ-1:0][3:0][7:0] shared_memory[SMB_HEIGHT-1:0]; - - wire [$clog2(SMB_HEIGHT) - 1:0]reg_addr; + reg [SMB_WORDS_PER_READ-1:0][3:0][7:0] shared_memory[SMB_HEIGHT-1:0]; + wire [$clog2(SMB_HEIGHT) - 1:0] reg_addr; - //wire need_to_write = (|we); - integer curr_ind; - // initial begin - // for (curr_ind = 0; curr_ind < SMB_HEIGHT; curr_ind = curr_ind + 1) - // begin - // shared_memory[curr_ind] = 0; - // end - // end - always @(posedge clk, posedge reset) begin + always @(posedge clk) begin if (reset) begin - //for (curr_ind = 0; curr_ind < 128; curr_ind = curr_ind + 1) - end else if(shm_write) begin + //-- + end else if (shm_write) begin if (we == 2'b00) shared_memory[reg_addr][0] <= wdata[0]; if (we == 2'b01) shared_memory[reg_addr][1] <= wdata[1]; if (we == 2'b10) shared_memory[reg_addr][2] <= wdata[2]; @@ -52,10 +40,6 @@ module VX_shared_memory_block end assign reg_addr = addr; - // always @(posedge clk) - // reg_addr <= addr; - - assign data_out = shm_write ? 0 : shared_memory[reg_addr]; `else @@ -69,6 +53,7 @@ module VX_shared_memory_block //assign write_bit_mask[1] = (we == 2'b01) ? {32{1'b1}} : {32{1'b0}}; //assign write_bit_mask[2] = (we == 2'b10) ? {32{1'b1}} : {32{1'b0}}; //assign write_bit_mask[3] = (we == 2'b11) ? {32{1'b1}} : {32{1'b0}}; + genvar curr_word; for (curr_word = 0; curr_word < SMB_WORDS_PER_READ; curr_word = curr_word + 1) begin @@ -115,7 +100,6 @@ module VX_shared_memory_block ); /* verilator lint_on PINCONNECTEMPTY */ - `endif endmodule diff --git a/hw/simulate/simulator.cpp b/hw/simulate/simulator.cpp index 4046c1ce..b8918034 100644 --- a/hw/simulate/simulator.cpp +++ b/hw/simulate/simulator.cpp @@ -51,18 +51,17 @@ void Simulator::ibus_driver() { } } - if (vortex_->I_dram_req && !I_dram_stalled_) { + if (!I_dram_stalled_) { // std::cout << "Icache Dram Request received!\n"; if (vortex_->I_dram_req_read) { // std::cout << "Icache Dram Request is read!\n"; // Need to add an element dram_req_t dram_req; dram_req.cycles_left = DRAM_LATENCY; - dram_req.data_length = vortex_->I_dram_req_size / 4; dram_req.base_addr = vortex_->I_dram_req_addr; - dram_req.data = (unsigned *)malloc(dram_req.data_length * sizeof(unsigned)); + dram_req.data = (unsigned *)malloc(GLOBAL_BLOCK_SIZE_BYTES); - for (int i = 0; i < dram_req.data_length; i++) { + for (int i = 0; i < (GLOBAL_BLOCK_SIZE_BYTES / 4); i++) { unsigned curr_addr = dram_req.base_addr + (i * 4); unsigned data_rd; ram_->getWord(curr_addr, &data_rd); @@ -74,9 +73,8 @@ void Simulator::ibus_driver() { if (vortex_->I_dram_req_write) { unsigned base_addr = vortex_->I_dram_req_addr; - unsigned data_length = vortex_->I_dram_req_size / 4; - for (int i = 0; i < data_length; i++) { + for (int i = 0; i < (GLOBAL_BLOCK_SIZE_BYTES / 4); i++) { unsigned curr_addr = base_addr + (i * 4); unsigned data_wr = vortex_->I_dram_req_data[i]; ram_->writeWord(curr_addr, &data_wr); @@ -84,22 +82,22 @@ void Simulator::ibus_driver() { } } - if (vortex_->I_dram_fill_accept && dequeue_valid) { + if (vortex_->I_dram_rsp_ready && dequeue_valid) { // std::cout << "Icache Dram Response Sending...!\n"; - vortex_->I_dram_fill_rsp = 1; - vortex_->I_dram_fill_rsp_addr = I_dram_req_vec_[dequeue_index].base_addr; + vortex_->I_dram_rsp_valid = 1; + vortex_->I_dram_rsp_addr = I_dram_req_vec_[dequeue_index].base_addr; // std::cout << "Fill Rsp -> Addr: " << std::hex << (I_dram_req_vec_[dequeue_index].base_addr) << std::dec << "\n"; - for (int i = 0; i < I_dram_req_vec_[dequeue_index].data_length; i++) { - vortex_->I_dram_fill_rsp_data[i] = I_dram_req_vec_[dequeue_index].data[i]; + for (int i = 0; i < (GLOBAL_BLOCK_SIZE_BYTES / 4); i++) { + vortex_->I_dram_rsp_data[i] = I_dram_req_vec_[dequeue_index].data[i]; } free(I_dram_req_vec_[dequeue_index].data); I_dram_req_vec_.erase(I_dram_req_vec_.begin() + dequeue_index); } else { - vortex_->I_dram_fill_rsp = 0; - vortex_->I_dram_fill_rsp_addr = 0; + vortex_->I_dram_rsp_valid = 0; + vortex_->I_dram_rsp_addr = 0; } #ifdef ENABLE_DRAM_STALLS @@ -112,7 +110,7 @@ void Simulator::ibus_driver() { } #endif - vortex_->dram_req_delay = I_dram_stalled_; + vortex_->dram_req_full = I_dram_stalled_; } #endif @@ -144,63 +142,15 @@ void Simulator::dbus_driver() { #ifdef USE_MULTICORE - if (vortex_->out_dram_req && !dram_stalled_) { - if (vortex_->out_dram_req_read) { - // Need to add an element - dram_req_t dram_req; - dram_req.cycles_left = DRAM_LATENCY; - dram_req.data_length = vortex_->out_dram_req_size / 4; - dram_req.base_addr = vortex_->out_dram_req_addr; - dram_req.data = (unsigned *)malloc(dram_req.data_length * sizeof(unsigned)); - - for (int i = 0; i < dram_req.data_length; i++) { - unsigned curr_addr = dram_req.base_addr + (i * 4); - unsigned data_rd; - ram_->getWord(curr_addr, &data_rd); - dram_req.data[i] = data_rd; - } - dram_req_vec_.push_back(dram_req); - } - - if (vortex_->out_dram_req_write) { - unsigned base_addr = vortex_->out_dram_req_addr; - unsigned data_length = vortex_->out_dram_req_size / 4; - - for (int i = 0; i < data_length; i++) { - unsigned curr_addr = base_addr + (i * 4); - unsigned data_wr = vortex_->out_dram_req_data[i]; - ram_->writeWord(curr_addr, &data_wr); - } - } - } - - if (vortex_->out_dram_fill_accept && dequeue_valid) { - vortex_->out_dram_fill_rsp = 1; - vortex_->out_dram_fill_rsp_addr = dram_req_vec_[dequeue_index].base_addr; - - for (int i = 0; i < dram_req_vec_[dequeue_index].data_length; i++) { - vortex_->out_dram_fill_rsp_data[i] = dram_req_vec_[dequeue_index].data[i]; - } - free(dram_req_vec_[dequeue_index].data); - - dram_req_vec_.erase(dram_req_vec_.begin() + dequeue_index); - } else { - vortex_->out_dram_fill_rsp = 0; - vortex_->out_dram_fill_rsp_addr = 0; - } - -#else - - if (vortex_->dram_req && !dram_stalled_) { + if (!dram_stalled_) { if (vortex_->dram_req_read) { // Need to add an element dram_req_t dram_req; dram_req.cycles_left = DRAM_LATENCY; - dram_req.data_length = vortex_->dram_req_size / 4; dram_req.base_addr = vortex_->dram_req_addr; - dram_req.data = (unsigned *)malloc(dram_req.data_length * sizeof(unsigned)); + dram_req.data = (unsigned *)malloc(GLOBAL_BLOCK_SIZE_BYTES); - for (int i = 0; i < dram_req.data_length; i++) { + for (int i = 0; i < (GLOBAL_BLOCK_SIZE_BYTES / 4); i++) { unsigned curr_addr = dram_req.base_addr + (i * 4); unsigned data_rd; ram_->getWord(curr_addr, &data_rd); @@ -211,9 +161,8 @@ void Simulator::dbus_driver() { if (vortex_->dram_req_write) { unsigned base_addr = vortex_->dram_req_addr; - unsigned data_length = vortex_->dram_req_size / 4; - for (int i = 0; i < data_length; i++) { + for (int i = 0; i < (GLOBAL_BLOCK_SIZE_BYTES / 4); i++) { unsigned curr_addr = base_addr + (i * 4); unsigned data_wr = vortex_->dram_req_data[i]; ram_->writeWord(curr_addr, &data_wr); @@ -221,34 +170,79 @@ void Simulator::dbus_driver() { } } - if (vortex_->dram_fill_accept && dequeue_valid) { - vortex_->dram_fill_rsp = 1; - vortex_->dram_fill_rsp_addr = dram_req_vec_[dequeue_index].base_addr; + if (vortex_->dram_rsp_ready && dequeue_valid) { + vortex_->dram_rsp_valid = 1; + vortex_->dram_rsp_addr = dram_req_vec_[dequeue_index].base_addr; - for (int i = 0; i < dram_req_vec_[dequeue_index].data_length; i++) { - vortex_->dram_fill_rsp_data[i] = dram_req_vec_[dequeue_index].data[i]; + for (int i = 0; i < (GLOBAL_BLOCK_SIZE_BYTES / 4); i++) { + vortex_->dram_rsp_data[i] = dram_req_vec_[dequeue_index].data[i]; } free(dram_req_vec_[dequeue_index].data); dram_req_vec_.erase(dram_req_vec_.begin() + dequeue_index); } else { - vortex_->dram_fill_rsp = 0; - vortex_->dram_fill_rsp_addr = 0; + vortex_->dram_rsp_valid = 0; + vortex_->dram_rsp_addr = 0; + } + +#else + + if (!dram_stalled_) { + if (vortex_->dram_req_read) { + // Need to add an element + dram_req_t dram_req; + dram_req.cycles_left = DRAM_LATENCY; + dram_req.base_addr = vortex_->dram_req_addr; + dram_req.data = (unsigned *)malloc(GLOBAL_BLOCK_SIZE_BYTES); + + for (int i = 0; i < (GLOBAL_BLOCK_SIZE_BYTES / 4); i++) { + unsigned curr_addr = dram_req.base_addr + (i * 4); + unsigned data_rd; + ram_->getWord(curr_addr, &data_rd); + dram_req.data[i] = data_rd; + } + dram_req_vec_.push_back(dram_req); + } + + if (vortex_->dram_req_write) { + unsigned base_addr = vortex_->dram_req_addr; + + for (int i = 0; i < (GLOBAL_BLOCK_SIZE_BYTES / 4); i++) { + unsigned curr_addr = base_addr + (i * 4); + unsigned data_wr = vortex_->dram_req_data[i]; + ram_->writeWord(curr_addr, &data_wr); + } + } + } + + if (vortex_->dram_rsp_ready && dequeue_valid) { + vortex_->dram_rsp_valid = 1; + vortex_->dram_rsp_addr = dram_req_vec_[dequeue_index].base_addr; + + for (int i = 0; i < (GLOBAL_BLOCK_SIZE_BYTES / 4); i++) { + vortex_->dram_rsp_data[i] = dram_req_vec_[dequeue_index].data[i]; + } + free(dram_req_vec_[dequeue_index].data); + + dram_req_vec_.erase(dram_req_vec_.begin() + dequeue_index); + } else { + vortex_->dram_rsp_valid = 0; + vortex_->dram_rsp_addr = 0; } #endif #ifdef USE_MULTICORE - vortex_->out_dram_req_delay = dram_stalled_; + vortex_->dram_req_full = dram_stalled_; #else - vortex_->dram_req_delay = dram_stalled_; + vortex_->dram_req_full = dram_stalled_; #endif } void Simulator::io_handler() { #ifdef USE_MULTICORE bool io_valid = false; - for (int c = 0; c < vortex_->number_cores; c++) { + for (int c = 0; c < NUM_CORES; c++) { if (vortex_->io_valid[c]) { uint32_t data_write = (uint32_t)vortex_->io_data[c]; char c = (char)data_write; @@ -318,33 +312,33 @@ void Simulator::send_snoops(uint32_t mem_addr, uint32_t size) { #ifdef USE_MULTICORE // submit snoop requests for the needed blocks vortex_->llc_snp_req_addr = aligned_addr_start; - vortex_->llc_snp_req = false; + vortex_->llc_snp_req_valid = false; for (;;) { this->step(); - if (vortex_->llc_snp_req) { - vortex_->llc_snp_req = false; + if (vortex_->llc_snp_req_valid) { + vortex_->llc_snp_req_valid = false; if (vortex_->llc_snp_req_addr >= aligned_addr_end) break; vortex_->llc_snp_req_addr += GLOBAL_BLOCK_SIZE_BYTES; } - if (!vortex_->llc_snp_req_delay) { - vortex_->llc_snp_req = true; + if (!vortex_->llc_snp_req_full) { + vortex_->llc_snp_req_valid = true; } } #else // submit snoop requests for the needed blocks vortex_->snp_req_addr = aligned_addr_start; - vortex_->snp_req = false; + vortex_->snp_req_valid = false; for (;;) { this->step(); - if (vortex_->snp_req) { - vortex_->snp_req = false; + if (vortex_->snp_req_valid) { + vortex_->snp_req_valid = false; if (vortex_->snp_req_addr >= aligned_addr_end) break; vortex_->snp_req_addr += GLOBAL_BLOCK_SIZE_BYTES; } - if (!vortex_->snp_req_delay) { - vortex_->snp_req = true; + if (!vortex_->snp_req_full) { + vortex_->snp_req_valid = true; } } #endif @@ -362,7 +356,6 @@ void Simulator::flush_caches(uint32_t mem_addr, uint32_t size) { // this->send_snoops(mem_addr, size); // this->wait(PIPELINE_FLUSH_LATENCY); // #endif - } bool Simulator::run() { @@ -381,7 +374,7 @@ bool Simulator::run() { int status = 0; #else // check riscv-tests PASSED/FAILED status - int status = (int)vortex_->Vortex->vx_back_end->VX_wb->last_data_wb & 0xf; + int status = (int)vortex_->Vortex->vx_back_end->vx_wb->last_data_wb & 0xf; #endif return (status == 1); diff --git a/hw/simulate/simulator.h b/hw/simulate/simulator.h index 80c5a930..422c41bb 100644 --- a/hw/simulate/simulator.h +++ b/hw/simulate/simulator.h @@ -27,7 +27,6 @@ typedef struct { int cycles_left; - int data_length; unsigned base_addr; unsigned *data; } dram_req_t; diff --git a/hw/simulate/testbench.cpp b/hw/simulate/testbench.cpp index 1861192d..f8e2f0b4 100644 --- a/hw/simulate/testbench.cpp +++ b/hw/simulate/testbench.cpp @@ -12,7 +12,7 @@ int main(int argc, char **argv) Verilated::commandArgs(argc, argv); -//#define ALL_TESTS +#define ALL_TESTS #ifdef ALL_TESTS bool passed = true;