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RTL code refactoring

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This commit is contained in:
Blaise Tine
2020-04-19 03:38:00 -04:00
parent 460aabf6b1
commit 9b476f1e17
97 changed files with 3127 additions and 18563 deletions
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17
hw/rtl/interfaces/VX_dram_req_rsp_inter.v
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@@ -6,18 +6,19 @@
interface VX_dram_req_rsp_inter #(
parameter NUM_BANKS = 8,
parameter NUM_WORDS_PER_BLOCK = 4) ();
parameter NUM_WORDS_PER_BLOCK = 4
) ();
// Req
wire [31:0] o_m_evict_addr;
wire [31:0] o_m_read_addr;
wire o_m_valid;
wire[NUM_BANKS - 1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] o_m_writedata;
wire o_m_read_or_write;
wire [31:0] o_m_evict_addr;
wire [31:0] o_m_read_addr;
wire o_m_valid;
wire [NUM_BANKS - 1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] o_m_writedata;
wire o_m_read_or_write;
// Rsp
wire[NUM_BANKS - 1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata;
wire i_m_ready;
wire [NUM_BANKS - 1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata;
wire i_m_ready;
endinterface