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RTL code refactoring

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This commit is contained in:
Blaise Tine
2020-04-19 03:38:00 -04:00
parent 460aabf6b1
commit 9b476f1e17
97 changed files with 3127 additions and 18563 deletions
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24
hw/rtl/generic_cache/VX_snp_fwd_arb.v
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@@ -5,28 +5,30 @@ module VX_snp_fwd_arb
parameter NUM_BANKS = 8
)
(
input wire[NUM_BANKS-1:0] per_bank_snp_fwd,
input wire[NUM_BANKS-1:0][31:0] per_bank_snp_fwd_addr,
output reg[NUM_BANKS-1:0] per_bank_snp_fwd_pop,
input wire [NUM_BANKS-1:0] per_bank_snp_fwd,
input wire [NUM_BANKS-1:0][31:0] per_bank_snp_fwd_addr,
output reg [NUM_BANKS-1:0] per_bank_snp_fwd_pop,
output wire snp_fwd,
output wire[31:0] snp_fwd_addr,
input wire snp_fwd_delay
output wire snp_fwd_valid,
output wire [31:0] snp_fwd_addr,
input wire snp_fwd_full
);
wire[NUM_BANKS-1:0] qual_per_bank_snp_fwd = per_bank_snp_fwd & {NUM_BANKS{!snp_fwd_delay}};
wire[NUM_BANKS-1:0] qual_per_bank_snp_fwd = per_bank_snp_fwd & {NUM_BANKS{!snp_fwd_full}};
wire[`LOG2UP(NUM_BANKS)-1:0] fsq_bank;
wire fsq_valid;
wire fsq_valid;
VX_generic_priority_encoder #(.N(NUM_BANKS)) VX_sel_ffsq(
VX_generic_priority_encoder #(
.N(NUM_BANKS)
) vx_sel_ffsq(
.valids(qual_per_bank_snp_fwd),
.index (fsq_bank),
.found (fsq_valid)
);
);
assign snp_fwd = fsq_valid;
assign snp_fwd_valid = fsq_valid;
assign snp_fwd_addr = per_bank_snp_fwd_addr[fsq_bank];
always @(*) begin