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RTL code refactoring

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This commit is contained in:
Blaise Tine
2020-04-19 03:38:00 -04:00
parent 460aabf6b1
commit 9b476f1e17
97 changed files with 3127 additions and 18563 deletions
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37
hw/rtl/compat/VX_divide.v
View File

@@ -1,21 +1,19 @@
module VX_divide
#(
parameter WIDTHN=1,
parameter WIDTHD=1,
parameter NREP="UNSIGNED",
parameter DREP="UNSIGNED",
parameter SPEED="MIXED", // "MIXED" or "HIGHEST"
parameter PIPELINE=0
)
(
input clock, aclr, clken,
module VX_divide #(
parameter WIDTHN=1,
parameter WIDTHD=1,
parameter NREP="UNSIGNED",
parameter DREP="UNSIGNED",
parameter SPEED="MIXED", // "MIXED" or "HIGHEST"
parameter PIPELINE=0
) (
input clock, aclr, clken,
input [WIDTHN-1:0] numer,
input [WIDTHD-1:0] denom,
input [WIDTHN-1:0] numer,
input [WIDTHD-1:0] denom,
output reg [WIDTHN-1:0] quotient,
output reg [WIDTHD-1:0] remainder
);
output reg [WIDTHN-1:0] quotient,
output reg [WIDTHD-1:0] remainder
);
// synthesis read_comments_as_HDL on
// localparam IMPL = "quartus";
@@ -27,14 +25,16 @@ module VX_divide
generate
if (NREP != DREP) begin
/* verilator lint_off DECLFILENAME */
different_nrep_drep_not_yet_supported non_existing_module();
/* verilator lint_on DECLFILENAME */
end
if (IMPL == "quartus") begin
localparam lpm_speed=SPEED == "HIGHEST" ? 9:5;
lpm_divide#(
lpm_divide #(
.LPM_WIDTHN(WIDTHN),
.LPM_WIDTHD(WIDTHD),
.LPM_NREPRESENTATION(NREP),
@@ -42,7 +42,7 @@ module VX_divide
.LPM_PIPELINE(PIPELINE),
.LPM_REMAINDERPOSITIVE("FALSE"), // emulate verilog % operator
.MAXIMIZE_SPEED(lpm_speed)
) quartus_divider(
) quartus_divider (
.clock(clock),
.aclr(aclr),
.clken(clken),
@@ -51,7 +51,6 @@ module VX_divide
.quotient(quotient),
.remain(remainder)
);
end
else begin

38
hw/rtl/compat/VX_mult.v
View File

@@ -1,21 +1,19 @@
module VX_mult
#(
parameter WIDTHA=1,
parameter WIDTHB=1,
parameter WIDTHP=1,
parameter REP="UNSIGNED",
parameter SPEED="MIXED", // "MIXED" or "HIGHEST"
parameter PIPELINE=0,
parameter FORCE_LE="NO"
)
(
input clock, aclr, clken,
module VX_mult #(
parameter WIDTHA=1,
parameter WIDTHB=1,
parameter WIDTHP=1,
parameter REP="UNSIGNED",
parameter SPEED="MIXED", // "MIXED" or "HIGHEST"
parameter PIPELINE=0,
parameter FORCE_LE="NO"
) (
input clock, aclr, clken,
input [WIDTHA-1:0] dataa,
input [WIDTHB-1:0] datab,
input [WIDTHA-1:0] dataa,
input [WIDTHB-1:0] datab,
output reg [WIDTHP-1:0] result
);
output reg [WIDTHP-1:0] result
);
// synthesis read_comments_as_HDL on
// localparam IMPL = "quartus";
@@ -29,10 +27,11 @@ module VX_mult
if (IMPL == "quartus") begin
localparam lpm_speed=SPEED == "HIGHEST" ? 10:5;
localparam lpm_speed = (SPEED == "HIGHEST") ? 10 : 5;
if (FORCE_LE == "YES") begin
lpm_mult#(
/* verilator lint_off DECLFILENAME */
lpm_mult #(
.LPM_WIDTHA(WIDTHA),
.LPM_WIDTHB(WIDTHB),
.LPM_WIDTHP(WIDTHP),
@@ -40,7 +39,7 @@ module VX_mult
.LPM_PIPELINE(PIPELINE),
.DSP_BLOCK_BALANCING("LOGIC ELEMENTS"),
.MAXIMIZE_SPEED(lpm_speed)
) quartus_mult(
) quartus_mult (
.clock(clock),
.aclr(aclr),
.clken(clken),
@@ -48,6 +47,7 @@ module VX_mult
.datab(datab),
.result(result)
);
/* verilator lint_on DECLFILENAME */
end
else begin
lpm_mult#(