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Passing all tests with 2 threads

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This commit is contained in:
felsabbagh3
2019-03-30 03:54:20 -04:00
parent d02c3d25b7
commit 99a0792a0c
30 changed files with 116803 additions and 3316 deletions
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results.txt Normal file
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2
rtl/VX_alu.v
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@@ -62,7 +62,7 @@ module VX_alu(
`CSR_ALU_RW: out_alu_result = in_csr_data; `CSR_ALU_RW: out_alu_result = in_csr_data;
`CSR_ALU_RS: out_alu_result = in_csr_data; `CSR_ALU_RS: out_alu_result = in_csr_data;
`CSR_ALU_RC: out_alu_result = in_csr_data; `CSR_ALU_RC: out_alu_result = in_csr_data;
`MUL: out_alu_result = mult_signed_result[31:0]; `MUL: begin out_alu_result = mult_signed_result[31:0]; $display("(%x) %x * %x = %x", in_curr_PC, ALU_in1, ALU_in2, out_alu_result); end
`MULH: out_alu_result = mult_signed_result[63:32]; `MULH: out_alu_result = mult_signed_result[63:32];
`MULHSU: out_alu_result = mult_signed_un_result[63:32]; `MULHSU: out_alu_result = mult_signed_un_result[63:32];
`MULHU: out_alu_result = mult_unsigned_result[63:32]; `MULHU: out_alu_result = mult_unsigned_result[63:32];

67
rtl/VX_decode.v
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@@ -132,32 +132,53 @@ module VX_decode(
always @(posedge clk) begin // always @(posedge clk) begin
$display("Decode: curr_pc: %h", in_curr_PC); // $display("Decode: curr_pc: %h", in_curr_PC);
end // end
genvar index; // genvar index;
generate // generate
for (index=0; index < `NT; index=index+1) // for (index=0; index < `NT; index=index+1)
begin: gen_code_label // begin: gen_code_label
VX_register_file vx_register_file( // VX_register_file vx_register_file(
// .clk(clk),
// .in_valid(in_wb_valid[index]),
// .in_write_register(write_register),
// .in_rd(in_rd),
// .in_data(in_write_data[index]),
// .in_src1(out_rs1),
// .in_src2(out_rs2),
// .out_src1_data(rd1_register[index]),
// .out_src2_data(rd2_register[index])
// );
// end
// endgenerate
VX_register_file vx_register_file_0(
.clk(clk), .clk(clk),
.in_valid(in_wb_valid[index]), .in_valid(in_wb_valid[0]),
.in_write_register(write_register), .in_write_register(write_register),
.in_rd(in_rd), .in_rd(in_rd),
.in_data(in_write_data[index]), .in_data(in_write_data[0]),
.in_src1(out_rs1), .in_src1(out_rs1),
.in_src2(out_rs2), .in_src2(out_rs2),
.out_src1_data(rd1_register[index]), .out_src1_data(rd1_register[0]),
.out_src2_data(rd2_register[index]) .out_src2_data(rd2_register[0])
); );
end
endgenerate
VX_register_file vx_register_file_1(
.clk(clk),
.in_valid(in_wb_valid[1]),
.in_write_register(write_register),
.in_rd(in_rd),
.in_data(in_write_data[1]),
.in_src1(out_rs1),
.in_src2(out_rs2),
.out_src1_data(rd1_register[1]),
.out_src2_data(rd2_register[1])
);
assign curr_opcode = in_instruction[6:0]; assign curr_opcode = in_instruction[6:0];
@@ -191,14 +212,22 @@ module VX_decode(
// ch_print("DECODE: PC: {0}, INSTRUCTION: {1}", in_curr_PC, in_instruction); // ch_print("DECODE: PC: {0}, INSTRUCTION: {1}", in_curr_PC, in_instruction);
genvar index_out_reg; genvar index_out_reg;
genvar index_out_reg_2;
generate generate
for (index_out_reg = 0; index_out_reg < `NT; index_out_reg = index_out_reg + 1) for (index_out_reg = 0; index_out_reg <= `NT; index_out_reg = index_out_reg + 2)
begin begin
assign out_reg_data[index_out_reg] = ( (is_jal == 1'b1) ? in_curr_PC : ((in_src1_fwd == 1'b1) ? in_src1_fwd_data[index_out_reg] : rd1_register[index_out_reg])); assign index_out_reg_2 = index_out_reg / 2;
assign out_reg_data[index_out_reg+1] = (in_src2_fwd == 1'b1) ? in_src2_fwd_data[index_out_reg] : rd2_register[index_out_reg]; assign out_reg_data[index_out_reg] = ( (is_jal == 1'b1) ? in_curr_PC : ((in_src1_fwd == 1'b1) ? in_src1_fwd_data[index_out_reg_2] : rd1_register[index_out_reg_2]));
assign out_reg_data[index_out_reg+1] = (in_src2_fwd == 1'b1) ? in_src2_fwd_data[index_out_reg_2] : rd2_register[index_out_reg_2];
end end
endgenerate endgenerate
// assign out_reg_data[0] = ( (is_jal == 1'b1) ? in_curr_PC : ((in_src1_fwd == 1'b1) ? in_src1_fwd_data[0] : rd1_register[0]));
// assign out_reg_data[1] = (in_src2_fwd == 1'b1) ? in_src2_fwd_data[0] : rd2_register[0];
// assign out_reg_data[2] = ( (is_jal == 1'b1) ? in_curr_PC : ((in_src1_fwd == 1'b1) ? in_src1_fwd_data[1] : rd1_register[1]));
// assign out_reg_data[3] = (in_src2_fwd == 1'b1) ? in_src2_fwd_data[1] : rd2_register[1];
// assign internal_rd1 = ((is_jal == 1'b1) ? in_curr_PC : ((in_src1_fwd == 1'b1) ? in_src1_fwd_data : rd1_register)); // assign internal_rd1 = ((is_jal == 1'b1) ? in_curr_PC : ((in_src1_fwd == 1'b1) ? in_src1_fwd_data : rd1_register));
// assign internal_rd2 = (in_src2_fwd == 1'b1) ? in_src2_fwd_data : rd2_register; // assign internal_rd2 = (in_src2_fwd == 1'b1) ? in_src2_fwd_data : rd2_register;

6
rtl/VX_define.h
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@@ -1,8 +1,8 @@
#define NT 1 #define NT 2
#define NT_M1 0 #define NT_M1 1
#define NT_T2_M1 1 #define NT_T2_M1 3
#define R_INST 51 #define R_INST 51
#define L_INST 3 #define L_INST 3

6
rtl/VX_define.v
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@@ -1,7 +1,7 @@
`define NT 1 `define NT 2
`define NT_M1 0 `define NT_M1 1
`define NT_T2_M1 1 `define NT_T2_M1 3
`define R_INST 7'd51 `define R_INST 7'd51

59
rtl/VX_execute.v
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@@ -56,26 +56,49 @@ module VX_execute (
// .out_alu_result(out_alu_result) // .out_alu_result(out_alu_result)
// ); // );
genvar index; // genvar index;
genvar index_2; // genvar index_2;
generate // generate
for (index=0; index <= `NT; index=index+2) // assign index_2 = 0;
begin: gen_code_label // for (index=0; index <= `NT; index=index+2)
assign index_2 = index / 2; // begin: gen_code_label
VX_alu vx_alu( // VX_alu vx_alu(
.in_reg_data (in_reg_data[index+1:index]), // .in_reg_data (in_reg_data[index+1:index]),
.in_rs2_src (in_rs2_src), // .in_rs2_src (in_rs2_src),
.in_itype_immed(in_itype_immed), // .in_itype_immed(in_itype_immed),
.in_upper_immed(in_upper_immed), // .in_upper_immed(in_upper_immed),
.in_alu_op (in_alu_op), // .in_alu_op (in_alu_op),
.in_csr_data (in_csr_data), // .in_csr_data (in_csr_data),
.in_curr_PC (in_curr_PC), // .in_curr_PC (in_curr_PC),
.out_alu_result(out_alu_result[index_2]) // .out_alu_result(out_alu_result[index_2])
); // );
end // index_2 = index_2 + 1;
endgenerate // end
// endgenerate
VX_alu vx_alu_0(
.in_reg_data (in_reg_data[1:0]),
.in_rs2_src (in_rs2_src),
.in_itype_immed(in_itype_immed),
.in_upper_immed(in_upper_immed),
.in_alu_op (in_alu_op),
.in_csr_data (in_csr_data),
.in_curr_PC (in_curr_PC),
.out_alu_result(out_alu_result[0])
);
VX_alu vx_alu_1(
.in_reg_data (in_reg_data[3:2]),
.in_rs2_src (in_rs2_src),
.in_itype_immed(in_itype_immed),
.in_upper_immed(in_upper_immed),
.in_alu_op (in_alu_op),
.in_csr_data (in_csr_data),
.in_curr_PC (in_curr_PC),
.out_alu_result(out_alu_result[1])
);
assign out_jal_dest = $signed(in_reg_data[0]) + $signed(in_jal_offset); assign out_jal_dest = $signed(in_reg_data[0]) + $signed(in_jal_offset);
assign out_jal = in_jal; assign out_jal = in_jal;

5
rtl/VX_fetch.v
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@@ -52,7 +52,7 @@ module VX_fetch (
// for (ini_cur_th = 0; ini_cur_th < `NT; ini_cur_th=ini_cur_th+1) // for (ini_cur_th = 0; ini_cur_th < `NT; ini_cur_th=ini_cur_th+1)
// valid[ini_cur_th] = 1; // Thread 1 active // valid[ini_cur_th] = 1; // Thread 1 active
valid[0] = 1; valid[0] = 1;
// valid[1] = 0; valid[1] = 0;
stall_reg = 0; stall_reg = 0;
delay_reg = 0; delay_reg = 0;
old = 0; old = 0;
@@ -107,6 +107,9 @@ module VX_fetch (
endgenerate endgenerate
// assign out_valid[0] = stall ? 1'b0 : valid[0];
// assign out_valid[1] = stall ? 1'b0 : valid[1];
always @(*) begin always @(*) begin
if ((in_jal == 1'b1) && (delay_reg == 1'b0)) begin if ((in_jal == 1'b1) && (delay_reg == 1'b0)) begin

9
rtl/VX_memory.v
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@@ -59,6 +59,15 @@ module VX_memory (
assign out_PC_next = in_PC_next; assign out_PC_next = in_PC_next;
assign out_valid = in_valid; assign out_valid = in_valid;
always @(*) begin
if (in_cache_driver_out_data[0] != 32'hbabebabe)
begin
$display("MEM: data read from cache_driver: %h", in_cache_driver_out_data[0]);
end
end
assign out_branch_dest = $signed(in_curr_PC) + ($signed(in_branch_offset) << 1); assign out_branch_dest = $signed(in_curr_PC) + ($signed(in_branch_offset) << 1);

4
rtl/VX_register_file.v
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@@ -31,11 +31,11 @@ module VX_register_file (
assign write_data = in_data; assign write_data = in_data;
assign write_register = in_rd; assign write_register = in_rd;
assign write_enable = in_write_register && (in_rd != 5'h0) && in_valid; assign write_enable = (in_write_register && (in_rd != 5'h0)) && in_valid;
always @(posedge clk) begin always @(posedge clk) begin
if(write_enable) begin if(write_enable) begin
$display("Writing %h to %d",write_data, write_register); $display("RF: Writing %h to %d",write_data, write_register);
registers[write_register] <= write_data; registers[write_register] <= write_data;
end end
end end

26
rtl/VX_writeback.v
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@@ -9,6 +9,7 @@ module VX_writeback (
input wire[4:0] in_rd, input wire[4:0] in_rd,
input wire[1:0] in_wb, input wire[1:0] in_wb,
input wire[31:0] in_PC_next, input wire[31:0] in_PC_next,
input wire in_valid[`NT_M1:0],
output wire[31:0] out_write_data[`NT_M1:0], output wire[31:0] out_write_data[`NT_M1:0],
output wire[4:0] out_rd, output wire[4:0] out_rd,
@@ -18,23 +19,18 @@ module VX_writeback (
wire is_jal; wire is_jal;
wire uses_alu; wire uses_alu;
always @(negedge clk) begin
if (in_wb != 0) begin
$display("(%h) WB Data: %h, to register: %d",in_PC_next - 4, in_mem_result[0], in_rd);
end
end
wire[31:0] out_pc_data[`NT_M1:0]; wire[31:0] out_pc_data[`NT_M1:0];
genvar index; // genvar index;
for (index=0; index < `NT; index=index+1) // for (index=0; index < `NT; index=index+1)
assign out_pc_data[index] = in_PC_next; // assign out_pc_data[index] = in_PC_next;
generate // generate
// endgenerate
endgenerate assign out_pc_data[0] = in_PC_next;
assign out_pc_data[1] = in_PC_next;
assign is_jal = in_wb == `WB_JAL; assign is_jal = in_wb == `WB_JAL;
assign uses_alu = in_wb == `WB_ALU; assign uses_alu = in_wb == `WB_ALU;
@@ -44,6 +40,12 @@ module VX_writeback (
in_mem_result; in_mem_result;
always @(negedge clk) begin
if (in_wb != 0) begin
$display("[%h] WB Data: %h {%h}, to register: %d [%d %d]",in_PC_next - 4, out_write_data[0], in_mem_result[0], in_rd, in_valid[0], in_valid[1]);
end
end
assign out_rd = in_rd; assign out_rd = in_rd;
assign out_wb = in_wb; assign out_wb = in_wb;

11
rtl/Vortex.v
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@@ -5,7 +5,8 @@ module Vortex(
input wire clk, input wire clk,
input wire reset, input wire reset,
input wire[31:0] fe_instruction, input wire[31:0] fe_instruction,
input wire[31:0] in_cache_driver_out_data[`NT_M1:0], input wire[31:0] in_cache_driver_out_data_0,
input wire[31:0] in_cache_driver_out_data_1,
output wire[31:0] curr_PC, output wire[31:0] curr_PC,
output wire[31:0] out_cache_driver_in_address[`NT_M1:0], output wire[31:0] out_cache_driver_in_address[`NT_M1:0],
output wire[2:0] out_cache_driver_in_mem_read, output wire[2:0] out_cache_driver_in_mem_read,
@@ -14,6 +15,11 @@ module Vortex(
output wire[31:0] out_cache_driver_in_data[`NT_M1:0] output wire[31:0] out_cache_driver_in_data[`NT_M1:0]
); );
wire[31:0] in_cache_driver_out_data[`NT_M1:0];
assign in_cache_driver_out_data[0] = in_cache_driver_out_data_0;
assign in_cache_driver_out_data[1] = in_cache_driver_out_data_1;
assign curr_PC = fetch_curr_PC; assign curr_PC = fetch_curr_PC;
@@ -381,7 +387,7 @@ VX_e_m_reg vx_e_m_reg(
wire[31:0] use_rd2[`NT_M1:0]; wire[31:0] use_rd2[`NT_M1:0];
assign use_rd2[0] = e_m_reg_data[1]; assign use_rd2[0] = e_m_reg_data[1];
// assign use_rd2[1] = e_m_reg_data[3]; assign use_rd2[1] = e_m_reg_data[3];
VX_memory vx_memory( VX_memory vx_memory(
.in_alu_result (e_m_alu_result), .in_alu_result (e_m_alu_result),
@@ -447,6 +453,7 @@ VX_writeback vx_writeback(
.in_rd (m_w_rd), .in_rd (m_w_rd),
.in_wb (m_w_wb), .in_wb (m_w_wb),
.in_PC_next (m_w_PC_next), .in_PC_next (m_w_PC_next),
.in_valid (m_w_valid),
.out_write_data(writeback_write_data), .out_write_data(writeback_write_data),
.out_rd (writeback_rd), .out_rd (writeback_rd),

BIN
rtl/obj_dir/VVortex
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Binary file not shown.

1936
rtl/obj_dir/VVortex.cpp
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File diff suppressed because it is too large Load Diff

226
rtl/obj_dir/VVortex.h
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@@ -26,11 +26,12 @@ VL_MODULE(VVortex) {
VL_OUT8(out_cache_driver_in_mem_read,2,0); VL_OUT8(out_cache_driver_in_mem_read,2,0);
VL_OUT8(out_cache_driver_in_mem_write,2,0); VL_OUT8(out_cache_driver_in_mem_write,2,0);
VL_IN(fe_instruction,31,0); VL_IN(fe_instruction,31,0);
VL_IN(in_cache_driver_out_data_0,31,0);
VL_IN(in_cache_driver_out_data_1,31,0);
VL_OUT(curr_PC,31,0); VL_OUT(curr_PC,31,0);
VL_IN(in_cache_driver_out_data[1],31,0); VL_OUT(out_cache_driver_in_address[2],31,0);
VL_OUT(out_cache_driver_in_address[1],31,0); VL_OUT8(out_cache_driver_in_valid[2],0,0);
VL_OUT8(out_cache_driver_in_valid[1],0,0); VL_OUT(out_cache_driver_in_data[2],31,0);
VL_OUT(out_cache_driver_in_data[1],31,0);
// LOCAL SIGNALS // LOCAL SIGNALS
// Internals; generally not touched by application code // Internals; generally not touched by application code
@@ -41,12 +42,14 @@ VL_MODULE(VVortex) {
VL_SIG8(Vortex__DOT__execute_branch_stall,0,0); VL_SIG8(Vortex__DOT__execute_branch_stall,0,0);
VL_SIG8(Vortex__DOT__memory_branch_dir,0,0); VL_SIG8(Vortex__DOT__memory_branch_dir,0,0);
VL_SIG8(Vortex__DOT__forwarding_fwd_stall,0,0); VL_SIG8(Vortex__DOT__forwarding_fwd_stall,0,0);
VL_SIG8(Vortex__DOT__forwarding_src1_fwd,0,0);
VL_SIG8(Vortex__DOT__forwarding_src2_fwd,0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT__stall_reg,0,0); VL_SIG8(Vortex__DOT__vx_fetch__DOT__stall_reg,0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT__delay_reg,0,0); VL_SIG8(Vortex__DOT__vx_fetch__DOT__delay_reg,0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT__state,4,0); VL_SIG8(Vortex__DOT__vx_fetch__DOT__state,4,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT__prev_debug,0,0); VL_SIG8(Vortex__DOT__vx_fetch__DOT__prev_debug,0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT__stall,0,0); VL_SIG8(Vortex__DOT__vx_fetch__DOT__stall,0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT__valid,0,0); VL_SIG8(Vortex__DOT__vx_fetch__DOT__valid,1,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__is_itype,0,0); VL_SIG8(Vortex__DOT__vx_decode__DOT__is_itype,0,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__is_csr,0,0); VL_SIG8(Vortex__DOT__vx_decode__DOT__is_csr,0,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__mul_alu,4,0); VL_SIG8(Vortex__DOT__vx_decode__DOT__mul_alu,4,0);
@@ -98,58 +101,62 @@ VL_MODULE(VVortex) {
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__csr_mask,31,0); VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__csr_mask,31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__curr_PC,31,0); VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__curr_PC,31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__jal_offset,31,0); VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__jal_offset,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2,31,0); VL_SIG(Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2,31,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__PC_next,31,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__csr_result,31,0);
}; };
struct { struct {
VL_SIG(Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2,31,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__PC_next,31,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__csr_result,31,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__curr_PC,31,0); VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__curr_PC,31,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__branch_offset,31,0); VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__branch_offset,31,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__jal_dest,31,0); VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__jal_dest,31,0);
VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__PC_next,31,0); VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__PC_next,31,0);
VL_SIG64(Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__mult_signed_result,63,0); VL_SIG64(Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__mult_signed_result,63,0);
VL_SIG64(Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__mult_signed_result,63,0);
VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__cycle,63,0); VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__cycle,63,0);
VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__instret,63,0); VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__instret,63,0);
VL_SIG8(Vortex__DOT__fetch_valid[1],0,0); VL_SIG(Vortex__DOT__in_cache_driver_out_data[2],31,0);
VL_SIG8(Vortex__DOT__f_d_valid[1],0,0); VL_SIG8(Vortex__DOT__fetch_valid[2],0,0);
VL_SIG(Vortex__DOT__decode_reg_data[2],31,0); VL_SIG8(Vortex__DOT__f_d_valid[2],0,0);
VL_SIG8(Vortex__DOT__decode_valid[1],0,0); VL_SIG(Vortex__DOT__decode_reg_data[4],31,0);
VL_SIG(Vortex__DOT__d_e_reg_data[2],31,0); VL_SIG8(Vortex__DOT__decode_valid[2],0,0);
VL_SIG8(Vortex__DOT__d_e_valid[1],0,0); VL_SIG(Vortex__DOT__d_e_reg_data[4],31,0);
VL_SIG(Vortex__DOT__execute_alu_result[1],31,0); VL_SIG8(Vortex__DOT__d_e_valid[2],0,0);
VL_SIG(Vortex__DOT__execute_reg_data[2],31,0); VL_SIG(Vortex__DOT__execute_alu_result[2],31,0);
VL_SIG8(Vortex__DOT__execute_valid[1],0,0); VL_SIG(Vortex__DOT__execute_reg_data[4],31,0);
VL_SIG(Vortex__DOT__e_m_alu_result[1],31,0); VL_SIG8(Vortex__DOT__execute_valid[2],0,0);
VL_SIG(Vortex__DOT__e_m_reg_data[2],31,0); VL_SIG(Vortex__DOT__e_m_alu_result[2],31,0);
VL_SIG8(Vortex__DOT__e_m_valid[1],0,0); VL_SIG(Vortex__DOT__e_m_reg_data[4],31,0);
VL_SIG(Vortex__DOT__memory_alu_result[1],31,0); VL_SIG8(Vortex__DOT__e_m_valid[2],0,0);
VL_SIG(Vortex__DOT__memory_mem_result[1],31,0); VL_SIG(Vortex__DOT__memory_alu_result[2],31,0);
VL_SIG8(Vortex__DOT__memory_valid[1],0,0); VL_SIG(Vortex__DOT__memory_mem_result[2],31,0);
VL_SIG(Vortex__DOT__m_w_alu_result[1],31,0); VL_SIG8(Vortex__DOT__memory_valid[2],0,0);
VL_SIG(Vortex__DOT__m_w_mem_result[1],31,0); VL_SIG(Vortex__DOT__m_w_alu_result[2],31,0);
VL_SIG8(Vortex__DOT__m_w_valid[1],0,0); VL_SIG(Vortex__DOT__m_w_mem_result[2],31,0);
VL_SIG(Vortex__DOT__writeback_write_data[1],31,0); VL_SIG8(Vortex__DOT__m_w_valid[2],0,0);
VL_SIG(Vortex__DOT__forwarding_src1_fwd_data[1],31,0); VL_SIG(Vortex__DOT__writeback_write_data[2],31,0);
VL_SIG(Vortex__DOT__forwarding_src2_fwd_data[1],31,0); VL_SIG(Vortex__DOT__forwarding_src1_fwd_data[2],31,0);
VL_SIG(Vortex__DOT__use_rd2[1],31,0); VL_SIG(Vortex__DOT__forwarding_src2_fwd_data[2],31,0);
VL_SIG8(Vortex__DOT__vx_f_d_reg__DOT__valid[1],0,0); VL_SIG(Vortex__DOT__use_rd2[2],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__rd1_register[1],31,0); VL_SIG8(Vortex__DOT__vx_f_d_reg__DOT__valid[2],0,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__rd2_register[1],31,0); VL_SIG(Vortex__DOT__vx_decode__DOT__rd1_register[2],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__0__KET____DOT__vx_register_file__DOT__registers[32],31,0); VL_SIG(Vortex__DOT__vx_decode__DOT__rd2_register[2],31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__reg_data[2],31,0); VL_SIG(Vortex__DOT__vx_decode__DOT__vx_register_file_0__DOT__registers[32],31,0);
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid[1],0,0); VL_SIG(Vortex__DOT__vx_decode__DOT__vx_register_file_1__DOT__registers[32],31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[2],31,0); VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__reg_data[4],31,0);
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid_z[1],0,0); VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid[2],0,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__alu_result[1],31,0); VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[4],31,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__reg_data[2],31,0); VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid_z[2],0,0);
VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__valid[1],0,0); VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__alu_result[2],31,0);
VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__alu_result[1],31,0); VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__reg_data[4],31,0);
VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__mem_result[1],31,0); VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__valid[2],0,0);
VL_SIG8(Vortex__DOT__vx_m_w_reg__DOT__valid[1],0,0); VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__alu_result[2],31,0);
VL_SIG(Vortex__DOT__vx_writeback__DOT__out_pc_data[1],31,0); VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__mem_result[2],31,0);
VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[1],31,0); VL_SIG8(Vortex__DOT__vx_m_w_reg__DOT__valid[2],0,0);
VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[1],31,0); VL_SIG(Vortex__DOT__vx_writeback__DOT__out_pc_data[2],31,0);
VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[1],31,0); VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[2],31,0);
VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[2],31,0);
VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[2],31,0);
VL_SIG16(Vortex__DOT__vx_csr_handler__DOT__csr[4096],11,0); VL_SIG16(Vortex__DOT__vx_csr_handler__DOT__csr[4096],11,0);
}; };
@@ -159,61 +166,66 @@ VL_MODULE(VVortex) {
VL_SIG8(__Vtableidx1,2,0); VL_SIG8(__Vtableidx1,2,0);
VL_SIG8(__Vclklast__TOP__clk,0,0); VL_SIG8(__Vclklast__TOP__clk,0,0);
VL_SIG8(__Vclklast__TOP__reset,0,0); VL_SIG8(__Vclklast__TOP__reset,0,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_register_file__out_src2_data,31,0); VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_0__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_register_file__out_src1_data,31,0); VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_0__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_alu__out_alu_result,31,0); VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_1__out_src2_data,31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_fetch__out_valid[1],0,0); VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_1__out_src1_data,31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[1],0,0); VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_0__out_alu_result,31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[1],0,0); VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_1__out_alu_result,31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_decode__out_valid[1],0,0); VL_SIG8(Vortex__DOT____Vcellout__vx_fetch__out_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_decode__out_reg_data[2],31,0); VL_SIG8(Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[1],31,0); VL_SIG8(Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[1],31,0); VL_SIG8(Vortex__DOT____Vcellout__vx_decode__out_valid[2],0,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[1],0,0); VL_SIG(Vortex__DOT____Vcellout__vx_decode__out_reg_data[4],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_write_data[1],31,0); VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[2],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_decode__in_valid[1],0,0); VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[2],31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[1],0,0); VL_SIG8(Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data[2],31,0); VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_write_data[2],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[1],0,0); VL_SIG8(Vortex__DOT____Vcellinp__vx_decode__in_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_d_e_reg__in_reg_data[2],31,0); VL_SIG8(Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[2],0,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_execute__out_valid[1],0,0); VL_SIG(Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data[4],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_execute__out_reg_data[2],31,0); VL_SIG8(Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_execute__out_alu_result[1],31,0); VL_SIG(Vortex__DOT____Vcellinp__vx_d_e_reg__in_reg_data[4],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_execute__in_valid[1],0,0); VL_SIG8(Vortex__DOT____Vcellout__vx_execute__out_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_execute__in_reg_data[2],31,0); VL_SIG(Vortex__DOT____Vcellout__vx_execute__out_reg_data[4],31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[1],0,0); VL_SIG(Vortex__DOT____Vcellout__vx_execute__out_alu_result[2],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data[2],31,0); VL_SIG8(Vortex__DOT____Vcellinp__vx_execute__in_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[1],31,0); VL_SIG(Vortex__DOT____Vcellinp__vx_execute__in_reg_data[4],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[1],0,0); VL_SIG8(Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data[2],31,0); VL_SIG(Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data[4],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[1],31,0); VL_SIG(Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[2],31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[1],0,0); VL_SIG8(Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[1],31,0); VL_SIG(Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data[4],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[1],31,0); VL_SIG(Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[2],31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_memory__out_valid[1],0,0); VL_SIG8(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_mem_result[1],31,0); VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_alu_result[1],31,0); VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[1],31,0); VL_SIG8(Vortex__DOT____Vcellout__vx_memory__out_valid[2],0,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_memory__in_valid[1],0,0); VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_mem_result[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_rd2[1],31,0); VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_alu_result[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_alu_result[1],31,0); VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[2],31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[1],0,0); VL_SIG8(Vortex__DOT____Vcellinp__vx_memory__in_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[1],31,0); VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_rd2[2],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[1],31,0); VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_alu_result[2],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[1],0,0); VL_SIG8(Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[1],31,0); VL_SIG(Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[1],31,0); VL_SIG(Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[2],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_writeback__out_write_data[1],31,0); VL_SIG8(Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[1],31,0); VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[1],31,0); VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[2],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[1],31,0); VL_SIG(Vortex__DOT____Vcellout__vx_writeback__out_write_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[1],31,0); VL_SIG8(Vortex__DOT____Vcellinp__vx_writeback__in_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[1],31,0); VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[1],31,0); VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[1],31,0); VL_SIG(Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[1],31,0); VL_SIG(Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[1],31,0); VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[2],31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data[2],31,0); VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[2],31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_0__in_reg_data[2],31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_1__in_reg_data[2],31,0);
static VL_ST_SIG8(__Vtable1_Vortex__DOT__vx_decode__DOT__mul_alu[8],4,0); static VL_ST_SIG8(__Vtable1_Vortex__DOT__vx_decode__DOT__mul_alu[8],4,0);
// INTERNAL VARIABLES // INTERNAL VARIABLES
@@ -248,7 +260,7 @@ VL_MODULE(VVortex) {
private: private:
static QData _change_request(VVortex__Syms* __restrict vlSymsp); static QData _change_request(VVortex__Syms* __restrict vlSymsp);
public: public:
static void _combo__TOP__3(VVortex__Syms* __restrict vlSymsp); static void _combo__TOP__4(VVortex__Syms* __restrict vlSymsp);
static void _combo__TOP__9(VVortex__Syms* __restrict vlSymsp); static void _combo__TOP__9(VVortex__Syms* __restrict vlSymsp);
private: private:
void _ctor_var_reset(); void _ctor_var_reset();
@@ -264,9 +276,9 @@ VL_MODULE(VVortex) {
static void _initial__TOP__6(VVortex__Syms* __restrict vlSymsp); static void _initial__TOP__6(VVortex__Syms* __restrict vlSymsp);
static void _sequent__TOP__1(VVortex__Syms* __restrict vlSymsp); static void _sequent__TOP__1(VVortex__Syms* __restrict vlSymsp);
static void _sequent__TOP__2(VVortex__Syms* __restrict vlSymsp); static void _sequent__TOP__2(VVortex__Syms* __restrict vlSymsp);
static void _sequent__TOP__5(VVortex__Syms* __restrict vlSymsp); static void _sequent__TOP__3(VVortex__Syms* __restrict vlSymsp);
static void _sequent__TOP__7(VVortex__Syms* __restrict vlSymsp); static void _sequent__TOP__7(VVortex__Syms* __restrict vlSymsp);
static void _settle__TOP__4(VVortex__Syms* __restrict vlSymsp); static void _settle__TOP__5(VVortex__Syms* __restrict vlSymsp);
static void _settle__TOP__8(VVortex__Syms* __restrict vlSymsp); static void _settle__TOP__8(VVortex__Syms* __restrict vlSymsp);
} VL_ATTR_ALIGNED(128); } VL_ATTR_ALIGNED(128);

2
rtl/obj_dir/VVortex.mk
View File

@@ -10,7 +10,7 @@ default: VVortex
# Perl executable (from $PERL) # Perl executable (from $PERL)
PERL = perl PERL = perl
# Path to Verilator kit (from $VERILATOR_ROOT) # Path to Verilator kit (from $VERILATOR_ROOT)
VERILATOR_ROOT = /usr/local/share/verilator VERILATOR_ROOT = /usr/local/Cellar/verilator/4.010/share/verilator
# SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE) # SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE)
SYSTEMC_INCLUDE ?= SYSTEMC_INCLUDE ?=
# SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR) # SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR)

BIN
rtl/obj_dir/VVortex__ALL.a
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7
rtl/obj_dir/VVortex__ALLcls.d
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@@ -1,4 +1,5 @@
VVortex__ALLcls.o: VVortex__ALLcls.cpp VVortex.cpp VVortex.h \ VVortex__ALLcls.o: VVortex__ALLcls.cpp VVortex.cpp VVortex.h \
/usr/local/share/verilator/include/verilated_heavy.h \ /usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_heavy.h \
/usr/local/share/verilator/include/verilated.h \ /usr/local/Cellar/verilator/4.010/share/verilator/include/verilated.h \
/usr/local/share/verilator/include/verilatedos.h VVortex__Syms.h /usr/local/Cellar/verilator/4.010/share/verilator/include/verilatedos.h \
VVortex__Syms.h

BIN
rtl/obj_dir/VVortex__ALLcls.o
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7
rtl/obj_dir/VVortex__ALLsup.d
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@@ -1,4 +1,5 @@
VVortex__ALLsup.o: VVortex__ALLsup.cpp VVortex__Syms.cpp VVortex__Syms.h \ VVortex__ALLsup.o: VVortex__ALLsup.cpp VVortex__Syms.cpp VVortex__Syms.h \
/usr/local/share/verilator/include/verilated_heavy.h \ /usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_heavy.h \
/usr/local/share/verilator/include/verilated.h \ /usr/local/Cellar/verilator/4.010/share/verilator/include/verilated.h \
/usr/local/share/verilator/include/verilatedos.h VVortex.h /usr/local/Cellar/verilator/4.010/share/verilator/include/verilatedos.h \
VVortex.h

BIN
rtl/obj_dir/VVortex__ALLsup.o
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2
rtl/obj_dir/VVortex__ver.d
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@@ -1 +1 @@
obj_dir/VVortex.cpp obj_dir/VVortex.h obj_dir/VVortex.mk obj_dir/VVortex__Syms.cpp obj_dir/VVortex__Syms.h obj_dir/VVortex__ver.d obj_dir/VVortex_classes.mk : /usr/local/bin/verilator_bin /usr/local/bin/verilator_bin VX_alu.v VX_csr_handler.v VX_d_e_reg.v VX_decode.v VX_define.v VX_e_m_reg.v VX_execute.v VX_f_d_reg.v VX_fetch.v VX_forwarding.v VX_m_w_reg.v VX_memory.v VX_register_file.v VX_writeback.v Vortex.v obj_dir/VVortex.cpp obj_dir/VVortex.h obj_dir/VVortex.mk obj_dir/VVortex__Syms.cpp obj_dir/VVortex__Syms.h obj_dir/VVortex__ver.d obj_dir/VVortex_classes.mk : /usr/local/Cellar/verilator/4.010/bin/verilator_bin /usr/local/Cellar/verilator/4.010/bin/verilator_bin VX_alu.v VX_csr_handler.v VX_d_e_reg.v VX_decode.v VX_define.v VX_e_m_reg.v VX_execute.v VX_f_d_reg.v VX_fetch.v VX_forwarding.v VX_m_w_reg.v VX_memory.v VX_register_file.v VX_writeback.v Vortex.v

48
rtl/obj_dir/VVortex__verFiles.dat
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@@ -1,26 +1,26 @@
# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will. # DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will.
C "-Wall -cc Vortex.v VX_alu.v VX_fetch.v VX_f_d_reg.v VX_decode.v VX_register_file.v VX_d_e_reg.v VX_execute.v VX_e_m_reg.v VX_memory.v VX_m_w_reg.v VX_writeback.v VX_csr_handler.v VX_forwarding.v --exe test_bench.cpp" C "-Wall -cc Vortex.v VX_alu.v VX_fetch.v VX_f_d_reg.v VX_decode.v VX_register_file.v VX_d_e_reg.v VX_execute.v VX_e_m_reg.v VX_memory.v VX_m_w_reg.v VX_writeback.v VX_csr_handler.v VX_forwarding.v --exe test_bench.cpp"
S 5163137 401094 1553636247 412576209 1553636247 412576209 "/usr/local/bin/verilator_bin" S 4608404 12889046060 1553037052 0 1548678579 0 "/usr/local/Cellar/verilator/4.010/bin/verilator_bin"
S 2782 5518365 1553641993 611294425 1553641993 611294425 "VX_alu.v" S 2869 12889318286 1553929158 0 1553929158 0 "VX_alu.v"
S 1495 5518326 1553635490 361093288 1553635490 361093288 "VX_csr_handler.v" S 1495 12889087229 1553211178 0 1553211178 0 "VX_csr_handler.v"
S 4780 5518327 1553705050 153020819 1553705050 153020819 "VX_d_e_reg.v" S 4780 12889318287 1553672988 0 1553672988 0 "VX_d_e_reg.v"
S 10711 5518328 1553706261 998510628 1553706261 998510628 "VX_decode.v" S 11922 12889419225 1553929867 0 1553929867 0 "VX_decode.v"
S 1551 5518330 1553706438 435305366 1553706438 435305366 "VX_define.v" S 1551 12889419227 1553898607 0 1553898607 0 "VX_define.v"
S 3941 5518331 1553705050 153020819 1553705050 153020819 "VX_e_m_reg.v" S 3941 12889318289 1553673060 0 1553673060 0 "VX_e_m_reg.v"
S 3370 5518332 1553705050 153020819 1553705050 153020819 "VX_execute.v" S 4044 12889318290 1553932436 0 1553932436 0 "VX_execute.v"
S 1382 5518333 1553705050 153020819 1553705050 153020819 "VX_f_d_reg.v" S 1382 12889050060 1553673124 0 1553673124 0 "VX_f_d_reg.v"
S 3944 5518334 1553706489 155533656 1553706489 155533656 "VX_fetch.v" S 4048 12889419228 1553932280 0 1553932280 0 "VX_fetch.v"
S 5632 5518335 1553705050 153020819 1553705050 153020819 "VX_forwarding.v" S 5632 12889086478 1553672336 0 1553672336 0 "VX_forwarding.v"
S 1677 5518336 1553705050 153020819 1553705050 153020819 "VX_m_w_reg.v" S 1677 12889085814 1553673165 0 1553673165 0 "VX_m_w_reg.v"
S 2790 5518337 1553705050 153020819 1553705050 153020819 "VX_memory.v" S 2973 12889084513 1553931546 0 1553931546 0 "VX_memory.v"
S 997 5518338 1553705589 591472686 1553705589 591472686 "VX_register_file.v" S 1003 12889419229 1553930745 0 1553930745 0 "VX_register_file.v"
S 986 5518339 1553706081 977698760 1553706081 977698760 "VX_writeback.v" S 1173 12889419230 1553930874 0 1553930874 0 "VX_writeback.v"
S 15638 5518364 1553706457 931393127 1553706457 931393127 "Vortex.v" S 15887 12889419231 1553932044 0 1553932044 0 "Vortex.v"
T 134893 5518343 1553706491 727545232 1553706491 727545232 "obj_dir/VVortex.cpp" T 187461 12889423037 1553932439 0 1553932439 0 "obj_dir/VVortex.cpp"
T 13928 5518342 1553706491 723545213 1553706491 723545213 "obj_dir/VVortex.h" T 14542 12889423036 1553932439 0 1553932439 0 "obj_dir/VVortex.h"
T 1777 5518345 1553706491 727545232 1553706491 727545232 "obj_dir/VVortex.mk" T 1800 12889423039 1553932439 0 1553932439 0 "obj_dir/VVortex.mk"
T 530 5518341 1553706491 723545213 1553706491 723545213 "obj_dir/VVortex__Syms.cpp" T 530 12889423035 1553932439 0 1553932439 0 "obj_dir/VVortex__Syms.cpp"
T 717 5518340 1553706491 723545213 1553706491 723545213 "obj_dir/VVortex__Syms.h" T 717 12889423034 1553932439 0 1553932439 0 "obj_dir/VVortex__Syms.h"
T 418 5518346 1553706491 727545232 1553706491 727545232 "obj_dir/VVortex__ver.d" T 464 12889423040 1553932439 0 1553932439 0 "obj_dir/VVortex__ver.d"
T 0 0 1553706491 727545232 1553706491 727545232 "obj_dir/VVortex__verFiles.dat" T 0 0 1553932439 0 1553932439 0 "obj_dir/VVortex__verFiles.dat"
T 1159 5518344 1553706491 727545232 1553706491 727545232 "obj_dir/VVortex_classes.mk" T 1159 12889423038 1553932439 0 1553932439 0 "obj_dir/VVortex_classes.mk"

117090
rtl/obj_dir/debug.txt
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8
rtl/obj_dir/test_bench.d
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@@ -1,5 +1,5 @@
test_bench.o: ../test_bench.cpp ../test_bench.h ../VX_define.h ../ram.h \ test_bench.o: ../test_bench.cpp ../test_bench.h ../VX_define.h ../ram.h \
VVortex.h /usr/local/share/verilator/include/verilated_heavy.h \ VVortex.h \
/usr/local/share/verilator/include/verilated.h \ /usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_heavy.h \
/usr/local/share/verilator/include/verilatedos.h \ /usr/local/Cellar/verilator/4.010/share/verilator/include/verilated.h \
/usr/local/share/verilator/include/verilated.h /usr/local/Cellar/verilator/4.010/share/verilator/include/verilatedos.h

BIN
rtl/obj_dir/test_bench.o
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17
rtl/obj_dir/verilated.d
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@@ -1,8 +1,9 @@
verilated.o: /usr/local/share/verilator/include/verilated.cpp \ verilated.o: \
/usr/local/share/verilator/include/verilatedos.h \ /usr/local/Cellar/verilator/4.010/share/verilator/include/verilated.cpp \
/usr/local/share/verilator/include/verilated_imp.h \ /usr/local/Cellar/verilator/4.010/share/verilator/include/verilatedos.h \
/usr/local/share/verilator/include/verilated.h \ /usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_imp.h \
/usr/local/share/verilator/include/verilated_heavy.h \ /usr/local/Cellar/verilator/4.010/share/verilator/include/verilated.h \
/usr/local/share/verilator/include/verilated_syms.h \ /usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_heavy.h \
/usr/local/share/verilator/include/verilated_sym_props.h \ /usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_syms.h \
/usr/local/share/verilator/include/verilated_config.h /usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_sym_props.h \
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_config.h

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rtl/obj_dir/verilated.o
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417
rtl/results.txt
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@@ -1,9 +1,414 @@
**************** ../../emulator/riscv_tests/rv32ui-p-sub.hex **************** **************** ../../emulator/riscv_tests/rv32ui-p-add.hex ****************
# Dynamic Instructions: 496 # Dynamic Instructions: 597
# of total cycles: 500 # of total cycles: 608
# of forwarding stalls: 0 # of forwarding stalls: 0
# of branch stalls: 0 # of branch stalls: 0
# CPI: 1.00806 # CPI: 1.01843
# time to simulate: 2.13149e-317 milliseconds # time to simulate: 6.95313e-310 milliseconds
# GRADE: Failed on test: 4294967295 # GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-addi.hex ****************
# Dynamic Instructions: 312
# of total cycles: 323
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.03526
# time to simulate: 6.95313e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-and.hex ****************
# Dynamic Instructions: 595
# of total cycles: 606
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.01849
# time to simulate: 6.95313e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-andi.hex ****************
# Dynamic Instructions: 246
# of total cycles: 257
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.04472
# time to simulate: 6.95313e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-auipc.hex ****************
# Dynamic Instructions: 65
# of total cycles: 76
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.16923
# time to simulate: 6.95313e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-beq.hex ****************
# Dynamic Instructions: 431
# of total cycles: 442
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.02552
# time to simulate: 6.95313e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-bge.hex ****************
# Dynamic Instructions: 467
# of total cycles: 478
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.02355
# time to simulate: 6.95313e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-bgeu.hex ****************
# Dynamic Instructions: 492
# of total cycles: 503
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.02236
# time to simulate: 6.95313e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-blt.hex ****************
# Dynamic Instructions: 431
# of total cycles: 442
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.02552
# time to simulate: 6.95313e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-bltu.hex ****************
# Dynamic Instructions: 456
# of total cycles: 467
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.02412
# time to simulate: 6.95313e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-bne.hex ****************
# Dynamic Instructions: 431
# of total cycles: 442
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.02552
# time to simulate: 6.95313e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-jal.hex ****************
# Dynamic Instructions: 61
# of total cycles: 72
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.18033
# time to simulate: 6.95313e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-jalr.hex ****************
# Dynamic Instructions: 138
# of total cycles: 149
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.07971
# time to simulate: 6.95313e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-lb.hex ****************
# Dynamic Instructions: 331
# of total cycles: 342
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.03323
# time to simulate: 6.95313e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-lbu.hex ****************
# Dynamic Instructions: 331
# of total cycles: 342
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.03323
# time to simulate: 6.95313e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-lh.hex ****************
# Dynamic Instructions: 339
# of total cycles: 350
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.03245
# time to simulate: 6.95313e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-lhu.hex ****************
# Dynamic Instructions: 343
# of total cycles: 354
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.03207
# time to simulate: 6.95313e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-lui.hex ****************
# Dynamic Instructions: 73
# of total cycles: 84
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.15068
# time to simulate: 6.95313e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-lw.hex ****************
# Dynamic Instructions: 346
# of total cycles: 357
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.03179
# time to simulate: 6.95313e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-or.hex ****************
# Dynamic Instructions: 598
# of total cycles: 609
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.01839
# time to simulate: 6.95313e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-ori.hex ****************
# Dynamic Instructions: 253
# of total cycles: 264
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.04348
# time to simulate: 6.95313e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-sb.hex ****************
# Dynamic Instructions: 571
# of total cycles: 582
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.01926
# time to simulate: 6.95313e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-sh.hex ****************
# Dynamic Instructions: 603
# of total cycles: 614
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.01824
# time to simulate: 6.95313e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-simple.hex ****************
# Dynamic Instructions: 37
# of total cycles: 48
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.2973
# time to simulate: 6.95313e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-sll.hex ****************
# Dynamic Instructions: 633
# of total cycles: 644
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.01738
# time to simulate: 6.95313e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-slli.hex ****************
# Dynamic Instructions: 311
# of total cycles: 322
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.03537
# time to simulate: 6.95313e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-slt.hex ****************
# Dynamic Instructions: 591
# of total cycles: 602
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.01861
# time to simulate: 6.95313e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-slti.hex ****************
# Dynamic Instructions: 307
# of total cycles: 318
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.03583
# time to simulate: 6.95313e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-sltiu.hex ****************
# Dynamic Instructions: 307
# of total cycles: 318
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.03583
# time to simulate: 6.95313e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-sltu.hex ****************
# Dynamic Instructions: 591
# of total cycles: 602
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.01861
# time to simulate: 6.95313e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-sra.hex ****************
# Dynamic Instructions: 654
# of total cycles: 665
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.01682
# time to simulate: 6.95313e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-srai.hex ****************
# Dynamic Instructions: 326
# of total cycles: 337
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.03374
# time to simulate: 6.95313e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-srl.hex ****************
# Dynamic Instructions: 648
# of total cycles: 659
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.01698
# time to simulate: 6.95313e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-srli.hex ****************
# Dynamic Instructions: 320
# of total cycles: 331
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.03438
# time to simulate: 6.95313e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-sub.hex ****************
# Dynamic Instructions: 587
# of total cycles: 598
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.01874
# time to simulate: 6.95313e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-sw.hex ****************
# Dynamic Instructions: 612
# of total cycles: 623
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.01797
# time to simulate: 6.95313e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-xor.hex ****************
# Dynamic Instructions: 597
# of total cycles: 608
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.01843
# time to simulate: 6.95313e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-xori.hex ****************
# Dynamic Instructions: 255
# of total cycles: 266
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.04314
# time to simulate: 6.95313e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32um-p-div.hex ****************
# Dynamic Instructions: 112
# of total cycles: 123
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.09821
# time to simulate: 6.95313e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32um-p-divu.hex ****************
# Dynamic Instructions: 113
# of total cycles: 124
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.09735
# time to simulate: 6.95313e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32um-p-mul.hex ****************
# Dynamic Instructions: 589
# of total cycles: 600
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.01868
# time to simulate: 6.95313e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32um-p-mulh.hex ****************
# Dynamic Instructions: 585
# of total cycles: 596
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.0188
# time to simulate: 6.95313e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32um-p-mulhsu.hex ****************
# Dynamic Instructions: 585
# of total cycles: 596
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.0188
# time to simulate: 6.95313e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32um-p-mulhu.hex ****************
# Dynamic Instructions: 585
# of total cycles: 596
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.0188
# time to simulate: 6.95313e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32um-p-rem.hex ****************
# Dynamic Instructions: 112
# of total cycles: 123
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.09821
# time to simulate: 6.95313e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32um-p-remu.hex ****************
# Dynamic Instructions: 112
# of total cycles: 123
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.09821
# time to simulate: 6.95313e-310 milliseconds
# GRADE: PASSING

128
rtl/test_bench.cpp
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@@ -12,77 +12,77 @@ int main(int argc, char **argv)
Vortex v; Vortex v;
// bool passed = true; bool passed = true;
// std::string tests[NUM_TESTS] = { std::string tests[NUM_TESTS] = {
// "../../emulator/riscv_tests/rv32ui-p-add.hex", "../../emulator/riscv_tests/rv32ui-p-add.hex",
// "../../emulator/riscv_tests/rv32ui-p-addi.hex", "../../emulator/riscv_tests/rv32ui-p-addi.hex",
// "../../emulator/riscv_tests/rv32ui-p-and.hex", "../../emulator/riscv_tests/rv32ui-p-and.hex",
// "../../emulator/riscv_tests/rv32ui-p-andi.hex", "../../emulator/riscv_tests/rv32ui-p-andi.hex",
// "../../emulator/riscv_tests/rv32ui-p-auipc.hex", "../../emulator/riscv_tests/rv32ui-p-auipc.hex",
// "../../emulator/riscv_tests/rv32ui-p-beq.hex", "../../emulator/riscv_tests/rv32ui-p-beq.hex",
// "../../emulator/riscv_tests/rv32ui-p-bge.hex", "../../emulator/riscv_tests/rv32ui-p-bge.hex",
// "../../emulator/riscv_tests/rv32ui-p-bgeu.hex", "../../emulator/riscv_tests/rv32ui-p-bgeu.hex",
// "../../emulator/riscv_tests/rv32ui-p-blt.hex", "../../emulator/riscv_tests/rv32ui-p-blt.hex",
// "../../emulator/riscv_tests/rv32ui-p-bltu.hex", "../../emulator/riscv_tests/rv32ui-p-bltu.hex",
// "../../emulator/riscv_tests/rv32ui-p-bne.hex", "../../emulator/riscv_tests/rv32ui-p-bne.hex",
// "../../emulator/riscv_tests/rv32ui-p-jal.hex", "../../emulator/riscv_tests/rv32ui-p-jal.hex",
// "../../emulator/riscv_tests/rv32ui-p-jalr.hex", "../../emulator/riscv_tests/rv32ui-p-jalr.hex",
// "../../emulator/riscv_tests/rv32ui-p-lb.hex", "../../emulator/riscv_tests/rv32ui-p-lb.hex",
// "../../emulator/riscv_tests/rv32ui-p-lbu.hex", "../../emulator/riscv_tests/rv32ui-p-lbu.hex",
// "../../emulator/riscv_tests/rv32ui-p-lh.hex", "../../emulator/riscv_tests/rv32ui-p-lh.hex",
// "../../emulator/riscv_tests/rv32ui-p-lhu.hex", "../../emulator/riscv_tests/rv32ui-p-lhu.hex",
// "../../emulator/riscv_tests/rv32ui-p-lui.hex", "../../emulator/riscv_tests/rv32ui-p-lui.hex",
// "../../emulator/riscv_tests/rv32ui-p-lw.hex", "../../emulator/riscv_tests/rv32ui-p-lw.hex",
// "../../emulator/riscv_tests/rv32ui-p-or.hex", "../../emulator/riscv_tests/rv32ui-p-or.hex",
// "../../emulator/riscv_tests/rv32ui-p-ori.hex", "../../emulator/riscv_tests/rv32ui-p-ori.hex",
// "../../emulator/riscv_tests/rv32ui-p-sb.hex", "../../emulator/riscv_tests/rv32ui-p-sb.hex",
// "../../emulator/riscv_tests/rv32ui-p-sh.hex", "../../emulator/riscv_tests/rv32ui-p-sh.hex",
// "../../emulator/riscv_tests/rv32ui-p-simple.hex", "../../emulator/riscv_tests/rv32ui-p-simple.hex",
// "../../emulator/riscv_tests/rv32ui-p-sll.hex", "../../emulator/riscv_tests/rv32ui-p-sll.hex",
// "../../emulator/riscv_tests/rv32ui-p-slli.hex", "../../emulator/riscv_tests/rv32ui-p-slli.hex",
// "../../emulator/riscv_tests/rv32ui-p-slt.hex", "../../emulator/riscv_tests/rv32ui-p-slt.hex",
// "../../emulator/riscv_tests/rv32ui-p-slti.hex", "../../emulator/riscv_tests/rv32ui-p-slti.hex",
// "../../emulator/riscv_tests/rv32ui-p-sltiu.hex", "../../emulator/riscv_tests/rv32ui-p-sltiu.hex",
// "../../emulator/riscv_tests/rv32ui-p-sltu.hex", "../../emulator/riscv_tests/rv32ui-p-sltu.hex",
// "../../emulator/riscv_tests/rv32ui-p-sra.hex", "../../emulator/riscv_tests/rv32ui-p-sra.hex",
// "../../emulator/riscv_tests/rv32ui-p-srai.hex", "../../emulator/riscv_tests/rv32ui-p-srai.hex",
// "../../emulator/riscv_tests/rv32ui-p-srl.hex", "../../emulator/riscv_tests/rv32ui-p-srl.hex",
// "../../emulator/riscv_tests/rv32ui-p-srli.hex", "../../emulator/riscv_tests/rv32ui-p-srli.hex",
// "../../emulator/riscv_tests/rv32ui-p-sub.hex", "../../emulator/riscv_tests/rv32ui-p-sub.hex",
// "../../emulator/riscv_tests/rv32ui-p-sw.hex", "../../emulator/riscv_tests/rv32ui-p-sw.hex",
// "../../emulator/riscv_tests/rv32ui-p-xor.hex", "../../emulator/riscv_tests/rv32ui-p-xor.hex",
// "../../emulator/riscv_tests/rv32ui-p-xori.hex", "../../emulator/riscv_tests/rv32ui-p-xori.hex",
// "../../emulator/riscv_tests/rv32um-p-div.hex", "../../emulator/riscv_tests/rv32um-p-div.hex",
// "../../emulator/riscv_tests/rv32um-p-divu.hex", "../../emulator/riscv_tests/rv32um-p-divu.hex",
// "../../emulator/riscv_tests/rv32um-p-mul.hex", "../../emulator/riscv_tests/rv32um-p-mul.hex",
// "../../emulator/riscv_tests/rv32um-p-mulh.hex", "../../emulator/riscv_tests/rv32um-p-mulh.hex",
// "../../emulator/riscv_tests/rv32um-p-mulhsu.hex", "../../emulator/riscv_tests/rv32um-p-mulhsu.hex",
// "../../emulator/riscv_tests/rv32um-p-mulhu.hex", "../../emulator/riscv_tests/rv32um-p-mulhu.hex",
// "../../emulator/riscv_tests/rv32um-p-rem.hex", "../../emulator/riscv_tests/rv32um-p-rem.hex",
// "../../emulator/riscv_tests/rv32um-p-remu.hex" "../../emulator/riscv_tests/rv32um-p-remu.hex"
// }; };
// for (int ii = 0; ii < NUM_TESTS; ii++) for (int ii = 0; ii < NUM_TESTS; ii++)
// // for (int ii = 0; ii < NUM_TESTS - 1; ii++) // for (int ii = 0; ii < NUM_TESTS - 1; ii++)
// { {
// bool curr = v.simulate(tests[ii]); bool curr = v.simulate(tests[ii]);
// if ( curr) std::cerr << GREEN << "Test Passed: " << tests[ii] << std::endl; if ( curr) std::cerr << GREEN << "Test Passed: " << tests[ii] << std::endl;
// if (!curr) std::cerr << RED << "Test Failed: " << tests[ii] << std::endl; if (!curr) std::cerr << RED << "Test Failed: " << tests[ii] << std::endl;
// passed = passed && curr; passed = passed && curr;
// std::cerr << DEFAULT; std::cerr << DEFAULT;
// } }
// if( passed) std::cerr << DEFAULT << "PASSED ALL TESTS\n"; if( passed) std::cerr << DEFAULT << "PASSED ALL TESTS\n";
// if(!passed) std::cerr << DEFAULT << "Failed one or more tests\n"; if(!passed) std::cerr << DEFAULT << "Failed one or more tests\n";
char testing[] = "../../emulator/riscv_tests/rv32ui-p-sub.hex"; // char testing[] = "../../emulator/riscv_tests/rv32ui-p-lw.hex";
bool curr = v.simulate(testing); // bool curr = v.simulate(testing);
if ( curr) std::cerr << GREEN << "Test Passed: " << testing << std::endl; // if ( curr) std::cerr << GREEN << "Test Passed: " << testing << std::endl;
if (!curr) std::cerr << RED << "Test Failed: " << testing << std::endl; // if (!curr) std::cerr << RED << "Test Failed: " << testing << std::endl;
return 0; return 0;

36
rtl/test_bench.h
View File

@@ -142,8 +142,8 @@ bool Vortex::ibus_driver()
ram.getWord(new_PC, &curr_inst); ram.getWord(new_PC, &curr_inst);
vortex->fe_instruction = curr_inst; vortex->fe_instruction = curr_inst;
printf("\n\n(%x) Inst: %x\n", new_PC, curr_inst); // printf("\n\n(%x) Inst: %x\n", new_PC, curr_inst);
printf("\n");
////////////////////// IBUS ////////////////////// ////////////////////// IBUS //////////////////////
@@ -151,12 +151,13 @@ bool Vortex::ibus_driver()
++stats_total_cycles; ++stats_total_cycles;
if (((((unsigned int)curr_inst) != 0) && (((unsigned int)curr_inst) != 0xffffffff)) || (this->ibus_state == 1) || (this->dbus_state == 1)) if (((((unsigned int)curr_inst) != 0) && (((unsigned int)curr_inst) != 0xffffffff)))
{ {
++stats_dynamic_inst; ++stats_dynamic_inst;
stop = false; stop = false;
} else } else
{ {
printf("Ibus requesting stop: %x\n", curr_inst);
stop = true; stop = true;
} }
@@ -192,6 +193,7 @@ bool Vortex::dbus_driver()
ram.writeHalf( addr, &data_write); ram.writeHalf( addr, &data_write);
} else if (vortex->out_cache_driver_in_mem_write == SW_MEM_WRITE) } else if (vortex->out_cache_driver_in_mem_write == SW_MEM_WRITE)
{ {
printf("STORING %x in %x \n", data_write, addr);
data_write = data_write; data_write = data_write;
ram.writeWord( addr, &data_write); ram.writeWord( addr, &data_write);
} }
@@ -201,55 +203,59 @@ bool Vortex::dbus_driver()
} }
printf("----\n");
for (unsigned curr_th = 0; curr_th < NT; curr_th++) for (unsigned curr_th = 0; curr_th < NT; curr_th++)
{ {
if ((vortex->out_cache_driver_in_mem_read != NO_MEM_READ) && vortex->out_cache_driver_in_valid[curr_th]) unsigned & in_data_use = (curr_th == 0) ? vortex->in_cache_driver_out_data_0 : vortex->in_cache_driver_out_data_1;
if ((vortex->out_cache_driver_in_mem_read != NO_MEM_READ) && vortex->out_cache_driver_in_valid[0])
{ {
addr = (uint32_t) vortex->out_cache_driver_in_address[curr_th]; addr = (uint32_t) vortex->out_cache_driver_in_address[1];
ram.getWord(addr, &data_read); ram.getWord(addr, &data_read);
if (vortex->out_cache_driver_in_mem_read == LB_MEM_READ) if (vortex->out_cache_driver_in_mem_read == LB_MEM_READ)
{ {
vortex->in_cache_driver_out_data[curr_th] = (data_read & 0x80) ? (data_read | 0xFFFFFF00) : (data_read & 0xFF); in_data_use = (data_read & 0x80) ? (data_read | 0xFFFFFF00) : (data_read & 0xFF);
} else if (vortex->out_cache_driver_in_mem_read == LH_MEM_READ) } else if (vortex->out_cache_driver_in_mem_read == LH_MEM_READ)
{ {
vortex->in_cache_driver_out_data[curr_th] = (data_read & 0x8000) ? (data_read | 0xFFFF0000) : (data_read & 0xFFFF); in_data_use = (data_read & 0x8000) ? (data_read | 0xFFFF0000) : (data_read & 0xFFFF);
} else if (vortex->out_cache_driver_in_mem_read == LW_MEM_READ) } else if (vortex->out_cache_driver_in_mem_read == LW_MEM_READ)
{ {
// printf("Reading mem - Addr: %h = %h\n", addr, data_read); // printf("Reading mem - Addr: %x = %x\n", addr, data_read);
// std::cout << "Reading mem - Addr: " << std::hex << addr << " = " << data_read << "\n"; // std::cout << "Reading mem - Addr: " << std::hex << addr << " = " << data_read << "\n";
std::cout << std::dec; std::cout << std::dec;
vortex->in_cache_driver_out_data[curr_th] = data_read; in_data_use = data_read;
} else if (vortex->out_cache_driver_in_mem_read == LBU_MEM_READ) } else if (vortex->out_cache_driver_in_mem_read == LBU_MEM_READ)
{ {
vortex->in_cache_driver_out_data[curr_th] = (data_read & 0xFF); in_data_use = (data_read & 0xFF);
} else if (vortex->out_cache_driver_in_mem_read == LHU_MEM_READ) } else if (vortex->out_cache_driver_in_mem_read == LHU_MEM_READ)
{ {
vortex->in_cache_driver_out_data[curr_th] = (data_read & 0xFFFF); in_data_use = (data_read & 0xFFFF);
} }
else else
{ {
vortex->in_cache_driver_out_data[curr_th] = 0xbabebabe; in_data_use = 0xbabebabe;
} }
} }
else else
{ {
vortex->in_cache_driver_out_data[curr_th] = 0xbabebabe; in_data_use = 0xbabebabe;
} }
} }
printf("******\n");
return false; return false;
@@ -315,7 +321,8 @@ bool Vortex::simulate(std::string file_to_simulate)
// cycle++; // cycle++;
// } // }
for (int i = 0; i < 500; i++) // for (int i = 0; i < 500; i++)
while (this->stop && (!(stop && (counter > 5))))
{ {
// std::cout << "************* Cycle: " << cycle << "\n"; // std::cout << "************* Cycle: " << cycle << "\n";
@@ -325,6 +332,7 @@ bool Vortex::simulate(std::string file_to_simulate)
vortex->clk = 1; vortex->clk = 1;
vortex->eval(); vortex->eval();
dstop = !dbus_driver();
vortex->clk = 0; vortex->clk = 0;