53 lines
1.1 KiB
Verilog
53 lines
1.1 KiB
Verilog
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`include "VX_define.v"
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module VX_writeback (
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input wire clk,
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input wire[31:0] in_alu_result[`NT_M1:0],
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input wire[31:0] in_mem_result[`NT_M1:0],
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input wire[4:0] in_rd,
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input wire[1:0] in_wb,
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input wire[31:0] in_PC_next,
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input wire in_valid[`NT_M1:0],
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output wire[31:0] out_write_data[`NT_M1:0],
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output wire[4:0] out_rd,
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output wire[1:0] out_wb
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);
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wire is_jal;
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wire uses_alu;
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wire[31:0] out_pc_data[`NT_M1:0];
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// genvar index;
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// for (index=0; index < `NT; index=index+1)
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// assign out_pc_data[index] = in_PC_next;
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// generate
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// endgenerate
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assign out_pc_data[0] = in_PC_next;
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assign out_pc_data[1] = in_PC_next;
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assign is_jal = in_wb == `WB_JAL;
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assign uses_alu = in_wb == `WB_ALU;
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assign out_write_data = is_jal ? out_pc_data :
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uses_alu ? in_alu_result :
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in_mem_result;
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always @(negedge clk) begin
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if (in_wb != 0) begin
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$display("[%h] WB Data: %h {%h}, to register: %d [%d %d]",in_PC_next - 4, out_write_data[0], in_mem_result[0], in_rd, in_valid[0], in_valid[1]);
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end
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end
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assign out_rd = in_rd;
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assign out_wb = in_wb;
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endmodule // VX_writeback
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