RTL code refactoring
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@@ -7,8 +7,8 @@ module Vortex_Socket (
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input wire reset,
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// IO
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output wire io_valid[`NUM_CORES-1:0],
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output wire[31:0] io_data [`NUM_CORES-1:0],
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output wire io_valid[(`NUM_CORES * `NUM_CLUSTERS)-1:0],
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output wire[31:0] io_data [(`NUM_CORES * `NUM_CLUSTERS)-1:0],
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// DRAM Req
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output wire dram_req_read,
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@@ -93,14 +93,14 @@ module Vortex_Socket (
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wire[`NUM_CLUSTERS-1:0][`DBANK_LINE_WORDS-1:0][31:0] per_cluster_dram_rsp_data;
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wire[31:0] per_cluster_dram_rsp_data_up[`NUM_CLUSTERS-1:0][`DBANK_LINE_WORDS-1:0];
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wire[`NUM_CLUSTERS-1:0][`NUM_CORES_PER_CLUSTER-1:0] per_cluster_io_valid;
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wire[`NUM_CLUSTERS-1:0][`NUM_CORES_PER_CLUSTER-1:0][31:0] per_cluster_io_data;
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wire[`NUM_CLUSTERS-1:0][`NUM_CORES-1:0] per_cluster_io_valid;
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wire[`NUM_CLUSTERS-1:0][`NUM_CORES-1:0][31:0] per_cluster_io_data;
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genvar curr_c, curr_cc, curr_word;
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for (curr_c = 0; curr_c < `NUM_CLUSTERS; curr_c =curr_c+1) begin
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for (curr_cc = 0; curr_cc < `NUM_CORES_PER_CLUSTER; curr_cc=curr_cc+1) begin
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assign io_valid[curr_cc+(curr_c*`NUM_CORES_PER_CLUSTER)] = per_cluster_io_valid[curr_c][curr_cc];
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assign io_data [curr_cc+(curr_c*`NUM_CORES_PER_CLUSTER)] = per_cluster_io_data [curr_c][curr_cc];
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for (curr_cc = 0; curr_cc < `NUM_CORES; curr_cc=curr_cc+1) begin
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assign io_valid[curr_cc+(curr_c*`NUM_CORES)] = per_cluster_io_valid[curr_c][curr_cc];
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assign io_data [curr_cc+(curr_c*`NUM_CORES)] = per_cluster_io_data [curr_c][curr_cc];
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end
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for (curr_word = 0; curr_word < `DBANK_LINE_WORDS; curr_word = curr_word+1) begin
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