From 94e4f056dba3780e21de75e5177f40c4d574180f Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Mon, 20 Apr 2020 13:10:56 -0400 Subject: [PATCH] RTL code refactoring --- hw/rtl/VX_config.vh | 8 +++--- hw/rtl/Vortex_Cluster.v | 54 ++++++++++++++++++++--------------------- hw/rtl/Vortex_Socket.v | 14 +++++------ 3 files changed, 38 insertions(+), 38 deletions(-) diff --git a/hw/rtl/VX_config.vh b/hw/rtl/VX_config.vh index 9e299ef7..7d4318d5 100644 --- a/hw/rtl/VX_config.vh +++ b/hw/rtl/VX_config.vh @@ -3,14 +3,14 @@ `include "VX_user_config.vh" -`ifndef NUM_CORES -`define NUM_CORES 1 -`endif - `ifndef NUM_CLUSTERS `define NUM_CLUSTERS 1 `endif +`ifndef NUM_CORES +`define NUM_CORES 1 +`endif + `ifndef NUM_WARPS `define NUM_WARPS 8 `endif diff --git a/hw/rtl/Vortex_Cluster.v b/hw/rtl/Vortex_Cluster.v index 9102f0a6..ac2c9ddd 100644 --- a/hw/rtl/Vortex_Cluster.v +++ b/hw/rtl/Vortex_Cluster.v @@ -9,8 +9,8 @@ module Vortex_Cluster #( input wire reset, // IO - output wire[`NUM_CORES_PER_CLUSTER-1:0] io_valid, - output wire[`NUM_CORES_PER_CLUSTER-1:0][31:0] io_data, + output wire[`NUM_CORES-1:0] io_valid, + output wire[`NUM_CORES-1:0][31:0] io_data, // DRAM Req output wire dram_req_read, @@ -33,47 +33,47 @@ module Vortex_Cluster #( output wire out_ebreak ); // DRAM Dcache Req - wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_dram_req_read; - wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_dram_req_write; - wire[`NUM_CORES_PER_CLUSTER-1:0] [31:0] per_core_dram_req_addr; - wire[`NUM_CORES_PER_CLUSTER-1:0][`DBANK_LINE_WORDS-1:0][31:0] per_core_dram_req_data; + wire[`NUM_CORES-1:0] per_core_dram_req_read; + wire[`NUM_CORES-1:0] per_core_dram_req_write; + wire[`NUM_CORES-1:0] [31:0] per_core_dram_req_addr; + wire[`NUM_CORES-1:0][`DBANK_LINE_WORDS-1:0][31:0] per_core_dram_req_data; // DRAM Dcache Rsp - wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_dram_rsp_valid; - wire[`NUM_CORES_PER_CLUSTER-1:0] [31:0] per_core_dram_rsp_addr; - wire[`NUM_CORES_PER_CLUSTER-1:0][`DBANK_LINE_WORDS-1:0][31:0] per_core_dram_rsp_data; - wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_dram_rsp_ready; + wire[`NUM_CORES-1:0] per_core_dram_rsp_valid; + wire[`NUM_CORES-1:0] [31:0] per_core_dram_rsp_addr; + wire[`NUM_CORES-1:0][`DBANK_LINE_WORDS-1:0][31:0] per_core_dram_rsp_data; + wire[`NUM_CORES-1:0] per_core_dram_rsp_ready; // DRAM Icache Req - wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_I_dram_req_read; - wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_I_dram_req_write; - wire[`NUM_CORES_PER_CLUSTER-1:0] [31:0] per_core_I_dram_req_addr; - wire[`NUM_CORES_PER_CLUSTER-1:0][`IBANK_LINE_WORDS-1:0][31:0] per_core_I_dram_req_data; + wire[`NUM_CORES-1:0] per_core_I_dram_req_read; + wire[`NUM_CORES-1:0] per_core_I_dram_req_write; + wire[`NUM_CORES-1:0] [31:0] per_core_I_dram_req_addr; + wire[`NUM_CORES-1:0][`IBANK_LINE_WORDS-1:0][31:0] per_core_I_dram_req_data; // DRAM Icache Rsp - wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_I_dram_rsp_valid; - wire[`NUM_CORES_PER_CLUSTER-1:0] [31:0] per_core_I_dram_rsp_addr; - wire[`NUM_CORES_PER_CLUSTER-1:0][`IBANK_LINE_WORDS-1:0][31:0] per_core_I_dram_rsp_data; - wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_I_dram_rsp_ready; + wire[`NUM_CORES-1:0] per_core_I_dram_rsp_valid; + wire[`NUM_CORES-1:0] [31:0] per_core_I_dram_rsp_addr; + wire[`NUM_CORES-1:0][`IBANK_LINE_WORDS-1:0][31:0] per_core_I_dram_rsp_data; + wire[`NUM_CORES-1:0] per_core_I_dram_rsp_ready; // Out ebreak - wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_out_ebreak; + wire[`NUM_CORES-1:0] per_core_out_ebreak; - wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_io_valid; - wire[`NUM_CORES_PER_CLUSTER-1:0][31:0] per_core_io_data; + wire[`NUM_CORES-1:0] per_core_io_valid; + wire[`NUM_CORES-1:0][31:0] per_core_io_data; - wire l2c_core_req_ready; + wire l2c_core_req_ready; - wire snp_fwd_valid; - wire[31:0] snp_fwd_addr; - wire[`NUM_CORES_PER_CLUSTER-1:0] snp_fwd_ready; + wire snp_fwd_valid; + wire[31:0] snp_fwd_addr; + wire[`NUM_CORES-1:0] snp_fwd_ready; assign out_ebreak = (&per_core_out_ebreak); genvar curr_core; generate - for (curr_core = 0; curr_core < `NUM_CORES_PER_CLUSTER; curr_core=curr_core+1) begin + for (curr_core = 0; curr_core < `NUM_CORES; curr_core=curr_core+1) begin wire [`IBANK_LINE_WORDS-1:0][31:0] curr_core_I_dram_req_data; wire [`DBANK_LINE_WORDS-1:0][31:0] curr_core_dram_req_data ; @@ -82,7 +82,7 @@ module Vortex_Cluster #( assign io_data [curr_core] = per_core_io_data [curr_core]; Vortex #( - .CORE_ID(curr_core + (CLUSTER_ID * `NUM_CORES_PER_CLUSTER)) + .CORE_ID(curr_core + (CLUSTER_ID * `NUM_CORES)) ) vortex_core ( .clk (clk), .reset (reset), diff --git a/hw/rtl/Vortex_Socket.v b/hw/rtl/Vortex_Socket.v index 9ae17953..dd972743 100644 --- a/hw/rtl/Vortex_Socket.v +++ b/hw/rtl/Vortex_Socket.v @@ -7,8 +7,8 @@ module Vortex_Socket ( input wire reset, // IO - output wire io_valid[`NUM_CORES-1:0], - output wire[31:0] io_data [`NUM_CORES-1:0], + output wire io_valid[(`NUM_CORES * `NUM_CLUSTERS)-1:0], + output wire[31:0] io_data [(`NUM_CORES * `NUM_CLUSTERS)-1:0], // DRAM Req output wire dram_req_read, @@ -93,14 +93,14 @@ module Vortex_Socket ( wire[`NUM_CLUSTERS-1:0][`DBANK_LINE_WORDS-1:0][31:0] per_cluster_dram_rsp_data; wire[31:0] per_cluster_dram_rsp_data_up[`NUM_CLUSTERS-1:0][`DBANK_LINE_WORDS-1:0]; - wire[`NUM_CLUSTERS-1:0][`NUM_CORES_PER_CLUSTER-1:0] per_cluster_io_valid; - wire[`NUM_CLUSTERS-1:0][`NUM_CORES_PER_CLUSTER-1:0][31:0] per_cluster_io_data; + wire[`NUM_CLUSTERS-1:0][`NUM_CORES-1:0] per_cluster_io_valid; + wire[`NUM_CLUSTERS-1:0][`NUM_CORES-1:0][31:0] per_cluster_io_data; genvar curr_c, curr_cc, curr_word; for (curr_c = 0; curr_c < `NUM_CLUSTERS; curr_c =curr_c+1) begin - for (curr_cc = 0; curr_cc < `NUM_CORES_PER_CLUSTER; curr_cc=curr_cc+1) begin - assign io_valid[curr_cc+(curr_c*`NUM_CORES_PER_CLUSTER)] = per_cluster_io_valid[curr_c][curr_cc]; - assign io_data [curr_cc+(curr_c*`NUM_CORES_PER_CLUSTER)] = per_cluster_io_data [curr_c][curr_cc]; + for (curr_cc = 0; curr_cc < `NUM_CORES; curr_cc=curr_cc+1) begin + assign io_valid[curr_cc+(curr_c*`NUM_CORES)] = per_cluster_io_valid[curr_c][curr_cc]; + assign io_data [curr_cc+(curr_c*`NUM_CORES)] = per_cluster_io_data [curr_c][curr_cc]; end for (curr_word = 0; curr_word < `DBANK_LINE_WORDS; curr_word = curr_word+1) begin