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sampler bug fixes

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This commit is contained in:
Krishna Yalamarthy
2021-03-22 13:39:30 -04:00
parent 79fdde3c0c
commit 938b66f232
5 changed files with 42 additions and 43 deletions
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10
hw/rtl/tex_unit/VX_tex_bilerp.v
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@@ -7,7 +7,7 @@ module VX_tex_bilerp #(
input wire [`BLEND_FRAC_64-1:0] blendV, input wire [`BLEND_FRAC_64-1:0] blendV,
input wire [3:0][63:0] texels, input wire [3:0][63:0] texels,
input wire [`TEX_FORMAT_BITS-1:0] color_enable, input wire [`NUM_COLOR_CHANNEL-1:0] color_enable,
output wire [31:0] sampled_data output wire [31:0] sampled_data
); );
@@ -40,22 +40,22 @@ module VX_tex_bilerp #(
); );
always @(*) begin always @(*) begin
if (color_enable[3]==1) //R if (color_enable[3]==1'b1) //R
sampled_r[31:24] = V_lerp[55:48]; sampled_r[31:24] = V_lerp[55:48];
else else
sampled_r[31:24] = {`TEX_COLOR_BITS{1'b0}}; sampled_r[31:24] = {`TEX_COLOR_BITS{1'b0}};
if (color_enable[2]==1) //G if (color_enable[2]==1'b1) //G
sampled_r[23:16] = V_lerp[39:32]; sampled_r[23:16] = V_lerp[39:32];
else else
sampled_r[23:16] = {`TEX_COLOR_BITS{1'b0}}; sampled_r[23:16] = {`TEX_COLOR_BITS{1'b0}};
if (color_enable[1]==1) //B if (color_enable[1]==1'b1) //B
sampled_r[15:8] = V_lerp[23:16]; sampled_r[15:8] = V_lerp[23:16];
else else
sampled_r[15:8] = {`TEX_COLOR_BITS{1'b0}}; sampled_r[15:8] = {`TEX_COLOR_BITS{1'b0}};
if (color_enable[0]==1) //A if (color_enable[0]==1'b1) //A
sampled_r[7:0] = V_lerp[7:0]; sampled_r[7:0] = V_lerp[7:0];
else else
sampled_r[7:0] = {`TEX_COLOR_BITS{1'b1}}; sampled_r[7:0] = {`TEX_COLOR_BITS{1'b1}};

7
hw/rtl/tex_unit/VX_tex_format.v
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@@ -13,7 +13,7 @@ module VX_tex_format #(
`UNUSED_PARAM (CORE_ID) `UNUSED_PARAM (CORE_ID)
reg [`NUM_COLOR_CHANNEL-1:0] color_enable_r; reg [`NUM_COLOR_CHANNEL-1:0] color_enable_r;
reg [NUM_TEXELS][63:0] formatted_texel_r; reg [NUM_TEXELS-1:0][63:0] formatted_texel_r;
always @(*) begin always @(*) begin
for (integer i = 0; i<NUM_TEXELS ;i++ ) begin for (integer i = 0; i<NUM_TEXELS ;i++ ) begin
@@ -47,6 +47,9 @@ module VX_tex_format #(
end end
assign color_enable = color_enable_r; assign color_enable = color_enable_r;
assign formatted_texel = formatted_texel_r & 64'h00ff00ff00ff00ff;
for (genvar i = 0;i<NUM_TEXELS ;i++ ) begin
assign formatted_texel[i] = formatted_texel_r[i] & 64'h00ff00ff00ff00ff;
end
endmodule endmodule

1
hw/rtl/tex_unit/VX_tex_memory.v
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@@ -1,5 +1,4 @@
`include "VX_tex_define.vh" `include "VX_tex_define.vh"
module VX_tex_memory #( module VX_tex_memory #(
parameter CORE_ID = 0, parameter CORE_ID = 0,
parameter REQ_INFO_WIDTH = 1 parameter REQ_INFO_WIDTH = 1

66
hw/rtl/tex_unit/VX_tex_sampler.v
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@@ -33,52 +33,50 @@ module VX_tex_sampler #(
`UNUSED_PARAM (CORE_ID) `UNUSED_PARAM (CORE_ID)
wire [31:0] req_data [`NUM_THREADS-1:0]; wire [`NUM_THREADS-1:0][31:0] req_data ;
wire [`NUM_THREADS-1:0][31:0] req_data_bilerp ;
if (req_filter == 0) begin // point sampling wire stall_out;
for (genvar i = 0; i<`NUM_THREADS ;i++ ) begin for (genvar i = 0; i<`NUM_THREADS ;i++ ) begin
req_data[i] = req_texels[i][0]
end
end else begin // bilinear sampling wire [3:0][63:0] formatted_data;
wire [`NUM_COLOR_CHANNEL-1:0] color_enable;
for (genvar i = 0; i<`NUM_THREADS ;i++ ) begin VX_tex_format #(
.CORE_ID (CORE_ID),
.NUM_TEXELS (4)
) tex_format_texel (
.texel_data (req_texels[i]),
.format (req_format),
// wire [3:0][63:0] formatted_data; .color_enable (color_enable),
// wire [`TEX_FORMAT_BITS-1:0] color_enable; .formatted_texel(formatted_data)
);
VX_tex_format #( //blendU/blendV calculation
.CORE_ID (CORE_ID), wire [`BLEND_FRAC_64-1:0] blendU;
.NUM_TEXELS (4) wire [`BLEND_FRAC_64-1:0] blendV;
) tex_format_texel (
.texel_data (req_texels[i]),
.format (req_format),
.color_enable (color_enable), assign blendU = req_u[i][`BLEND_FRAC_64-1:0];
.formatted_texel(formatted_data) assign blendV = req_v[i][`BLEND_FRAC_64-1:0];
);
//blendU/blendV calculation VX_tex_bilerp #(
wire [`BLEND_FRAC_64-1:0] blendU; .CORE_ID (CORE_ID)
wire [`BLEND_FRAC_64-1:0] blendV; ) tex_bilerp (
.blendU(blendU), //blendU
.blendV(blendV), //blendV
assign blendU = req_u[i][`BLEND_FRAC_64-1:0]; .color_enable(color_enable),
assign blendV = req_v[i][`BLEND_FRAC_64-1:0]; .texels(formatted_data),
VX_tex_bilerp #( .sampled_data(req_data_bilerp[i])
.CORE_ID (CORE_ID) );
) tex_bilerp (
.blendU(blendU), //blendU
.blendV(blendV), //blendV
.color_enable(color_enable), end
.texels(formatted_data),
.sampled_data(req_data[i]) for (genvar i = 0;i<`NUM_THREADS ;i++ ) begin
); assign req_data[i] = (req_filter == `TEX_FILTER_BITS'h0) ? req_texels[i][0] : req_data_bilerp[i];
end
end end
assign stall_out = ~rsp_ready; assign stall_out = ~rsp_ready;

1
hw/rtl/tex_unit/VX_tex_unit.v
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@@ -130,7 +130,6 @@ module VX_tex_unit #(
); );
// retrieve texel values from memory // retrieve texel values from memory
VX_tex_memory #( VX_tex_memory #(
.CORE_ID (CORE_ID), .CORE_ID (CORE_ID),
.REQ_INFO_WIDTH (REQ_INFO_WIDTH_M) .REQ_INFO_WIDTH (REQ_INFO_WIDTH_M)