From 938b66f2326d642f972b12f0daef8adce676410c Mon Sep 17 00:00:00 2001
From: Krishna Yalamarthy <kyalamarthy6@boson.cc.gt.atl.ga.us>
Date: Mon, 22 Mar 2021 13:39:30 -0400
Subject: [PATCH] sampler bug fixes

---
 hw/rtl/tex_unit/VX_tex_bilerp.v  | 10 ++---
 hw/rtl/tex_unit/VX_tex_format.v  |  7 +++-
 hw/rtl/tex_unit/VX_tex_memory.v  |  1 -
 hw/rtl/tex_unit/VX_tex_sampler.v | 66 ++++++++++++++++----------------
 hw/rtl/tex_unit/VX_tex_unit.v    |  1 -
 5 files changed, 42 insertions(+), 43 deletions(-)

diff --git a/hw/rtl/tex_unit/VX_tex_bilerp.v b/hw/rtl/tex_unit/VX_tex_bilerp.v
index 1c0dbb53..71a1594f 100644
--- a/hw/rtl/tex_unit/VX_tex_bilerp.v
+++ b/hw/rtl/tex_unit/VX_tex_bilerp.v
@@ -7,7 +7,7 @@ module VX_tex_bilerp #(
     input wire [`BLEND_FRAC_64-1:0]   blendV,
 
     input wire [3:0][63:0]            texels,
-    input wire [`TEX_FORMAT_BITS-1:0] color_enable,
+    input wire [`NUM_COLOR_CHANNEL-1:0] color_enable,
 
     output wire [31:0]                sampled_data
 );  
@@ -40,22 +40,22 @@ module VX_tex_bilerp #(
     );  
 
     always @(*) begin
-        if (color_enable[3]==1) //R
+        if (color_enable[3]==1'b1) //R
             sampled_r[31:24] = V_lerp[55:48];
         else
             sampled_r[31:24] = {`TEX_COLOR_BITS{1'b0}};
 
-        if (color_enable[2]==1) //G
+        if (color_enable[2]==1'b1) //G
             sampled_r[23:16] = V_lerp[39:32];
         else
             sampled_r[23:16] = {`TEX_COLOR_BITS{1'b0}};
 
-        if (color_enable[1]==1) //B
+        if (color_enable[1]==1'b1) //B
             sampled_r[15:8] = V_lerp[23:16];
         else
             sampled_r[15:8] = {`TEX_COLOR_BITS{1'b0}};
 
-        if (color_enable[0]==1) //A
+        if (color_enable[0]==1'b1) //A
             sampled_r[7:0] = V_lerp[7:0];
         else
             sampled_r[7:0] = {`TEX_COLOR_BITS{1'b1}};
diff --git a/hw/rtl/tex_unit/VX_tex_format.v b/hw/rtl/tex_unit/VX_tex_format.v
index a64a829b..68081e22 100644
--- a/hw/rtl/tex_unit/VX_tex_format.v
+++ b/hw/rtl/tex_unit/VX_tex_format.v
@@ -13,7 +13,7 @@ module VX_tex_format #(
     `UNUSED_PARAM (CORE_ID)
 
     reg [`NUM_COLOR_CHANNEL-1:0] color_enable_r;
-    reg [NUM_TEXELS][63:0]       formatted_texel_r;    
+    reg [NUM_TEXELS-1:0][63:0]       formatted_texel_r;    
 
     always @(*) begin
         for (integer i = 0; i<NUM_TEXELS ;i++ ) begin
@@ -47,6 +47,9 @@ module VX_tex_format #(
     end
 
     assign color_enable    = color_enable_r;
-    assign formatted_texel = formatted_texel_r & 64'h00ff00ff00ff00ff;
+
+    for (genvar i = 0;i<NUM_TEXELS ;i++ ) begin
+        assign formatted_texel[i] = formatted_texel_r[i] & 64'h00ff00ff00ff00ff;
+    end
 
 endmodule
diff --git a/hw/rtl/tex_unit/VX_tex_memory.v b/hw/rtl/tex_unit/VX_tex_memory.v
index 59725e80..3a9f0aaf 100644
--- a/hw/rtl/tex_unit/VX_tex_memory.v
+++ b/hw/rtl/tex_unit/VX_tex_memory.v
@@ -1,5 +1,4 @@
 `include "VX_tex_define.vh"
-
 module VX_tex_memory #(
     parameter CORE_ID        = 0,
     parameter REQ_INFO_WIDTH = 1
diff --git a/hw/rtl/tex_unit/VX_tex_sampler.v b/hw/rtl/tex_unit/VX_tex_sampler.v
index 43cd4f5f..7b623d6b 100644
--- a/hw/rtl/tex_unit/VX_tex_sampler.v
+++ b/hw/rtl/tex_unit/VX_tex_sampler.v
@@ -33,52 +33,50 @@ module VX_tex_sampler #(
     
     `UNUSED_PARAM (CORE_ID)
 
-    wire [31:0] req_data [`NUM_THREADS-1:0];
+    wire [`NUM_THREADS-1:0][31:0] req_data ;
+    wire [`NUM_THREADS-1:0][31:0] req_data_bilerp ;
 
-    if (req_filter == 0) begin // point sampling
+    wire stall_out;
 
-        for (genvar i = 0; i<`NUM_THREADS ;i++ ) begin
-            req_data[i] = req_texels[i][0]
-        end
+    for (genvar i = 0; i<`NUM_THREADS ;i++ ) begin
 
-    end else begin // bilinear sampling
+        wire [3:0][63:0]            formatted_data;
+        wire [`NUM_COLOR_CHANNEL-1:0] color_enable;
 
-        for (genvar i = 0; i<`NUM_THREADS ;i++ ) begin
+        VX_tex_format #(
+            .CORE_ID (CORE_ID),
+            .NUM_TEXELS (4)
+        ) tex_format_texel (
+            .texel_data  (req_texels[i]),
+            .format (req_format),
 
-            // wire [3:0][63:0]            formatted_data;
-            // wire [`TEX_FORMAT_BITS-1:0] color_enable;
+            .color_enable (color_enable),
+            .formatted_texel(formatted_data)
+        );  
 
-            VX_tex_format #(
-                .CORE_ID (CORE_ID),
-                .NUM_TEXELS (4)
-            ) tex_format_texel (
-                .texel_data  (req_texels[i]),
-                .format (req_format),
+        //blendU/blendV calculation
+        wire [`BLEND_FRAC_64-1:0]      blendU;
+        wire [`BLEND_FRAC_64-1:0]      blendV;
 
-                .color_enable (color_enable),
-                .formatted_texel(formatted_data)
-            );  
+        assign blendU = req_u[i][`BLEND_FRAC_64-1:0];
+        assign blendV = req_v[i][`BLEND_FRAC_64-1:0];
 
-            //blendU/blendV calculation
-            wire [`BLEND_FRAC_64-1:0]      blendU;
-            wire [`BLEND_FRAC_64-1:0]      blendV;
+        VX_tex_bilerp #(
+            .CORE_ID (CORE_ID)
+        ) tex_bilerp (
+            .blendU(blendU), //blendU
+            .blendV(blendV),  //blendV
 
-            assign blendU = req_u[i][`BLEND_FRAC_64-1:0];
-            assign blendV = req_v[i][`BLEND_FRAC_64-1:0];
+            .color_enable(color_enable),
+            .texels(formatted_data),
 
-            VX_tex_bilerp #(
-                .CORE_ID (CORE_ID)
-            ) tex_bilerp (
-                .blendU(blendU), //blendU
-                .blendV(blendV),  //blendV
+            .sampled_data(req_data_bilerp[i])
+        );    
 
-                .color_enable(color_enable),
-                .texels(formatted_data),
+    end
 
-                .sampled_data(req_data[i])
-            );    
-
-        end
+    for (genvar i = 0;i<`NUM_THREADS ;i++ ) begin
+        assign req_data[i] = (req_filter == `TEX_FILTER_BITS'h0) ? req_texels[i][0] : req_data_bilerp[i];
     end
 
     assign stall_out = ~rsp_ready;
diff --git a/hw/rtl/tex_unit/VX_tex_unit.v b/hw/rtl/tex_unit/VX_tex_unit.v
index 9694f987..92f5a61f 100644
--- a/hw/rtl/tex_unit/VX_tex_unit.v
+++ b/hw/rtl/tex_unit/VX_tex_unit.v
@@ -130,7 +130,6 @@ module VX_tex_unit #(
     );
 
     // retrieve texel values from memory
-    
     VX_tex_memory #(
         .CORE_ID        (CORE_ID),
         .REQ_INFO_WIDTH (REQ_INFO_WIDTH_M)