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lkg build rollout with 16cores optimization on arria10

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This commit is contained in:
Blaise Tine
2021-01-24 16:49:22 -08:00
parent 74a687e395
commit 8775f63ec4
55 changed files with 1021 additions and 868 deletions
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344
hw/rtl/cache/VX_bank.v vendored
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@@ -89,98 +89,65 @@ module VX_bank #(
wire [31:0] debug_pc_st0, debug_pc_st1;
wire [`NW_BITS-1:0] debug_wid_st0, debug_wid_st1;
/* verilator lint_on UNUSED */
`endif
wire drsq_pop;
wire drsq_empty, drsq_empty_next;
wire [`LINE_ADDR_WIDTH-1:0] drsq_addr_next;
wire [`CACHE_LINE_WIDTH-1:0] drsq_filldata_next;
wire drsq_flush_next;
wire drsq_push = dram_rsp_valid && dram_rsp_ready;
wire drsq_full;
assign dram_rsp_ready = !drsq_full;
VX_fifo_queue_xt #(
.DATAW (`LINE_ADDR_WIDTH + $bits(dram_rsp_data) + 1),
.SIZE (DRSQ_SIZE),
.FASTRAM (1)
) dram_rsp_queue (
.clk (clk),
.reset (reset),
.push (drsq_push),
.pop (drsq_pop),
.data_in ({dram_rsp_addr, dram_rsp_data, dram_rsp_flush}),
`UNUSED_PIN (data_out),
.empty (drsq_empty),
.data_out_next ({drsq_addr_next, drsq_filldata_next, drsq_flush_next}),
.empty_next (drsq_empty_next),
.full (drsq_full),
`UNUSED_PIN (size)
);
`endif
wire creq_pop;
wire creq_full, creq_empty;
wire creq_rw_next;
wire [WORD_SIZE-1:0] creq_byteen_next;
wire [`REQS_BITS-1:0] creq_tid_next;
wire creq_rw;
wire [WORD_SIZE-1:0] creq_byteen;
wire [`REQS_BITS-1:0] creq_tid;
`IGNORE_WARNINGS_BEGIN
wire [`WORD_ADDR_WIDTH-1:0] creq_addr_next_unqual;
wire [`WORD_ADDR_WIDTH-1:0] creq_addr_unqual;
`IGNORE_WARNINGS_END
wire [`LINE_ADDR_WIDTH-1:0] creq_addr_next;
wire [`UP(`WORD_SELECT_BITS)-1:0] creq_wsel_next;
wire [`WORD_WIDTH-1:0] creq_writeword_next;
wire [CORE_TAG_WIDTH-1:0] creq_tag_next;
wire [`LINE_ADDR_WIDTH-1:0] creq_addr;
wire [`UP(`WORD_SELECT_BITS)-1:0] creq_wsel;
wire [`WORD_WIDTH-1:0] creq_writeword;
wire [CORE_TAG_WIDTH-1:0] creq_tag;
wire creq_push = (| core_req_valid) && core_req_ready;
wire creq_push = core_req_valid && core_req_ready;
assign core_req_ready = !creq_full;
if (BANK_ADDR_OFFSET == 0) begin
assign creq_addr_next = `LINE_SELECT_ADDR0(creq_addr_next_unqual);
assign creq_addr = `LINE_SELECT_ADDR0(creq_addr_unqual);
end else begin
assign creq_addr_next = `LINE_SELECT_ADDRX(creq_addr_next_unqual);
assign creq_addr = `LINE_SELECT_ADDRX(creq_addr_unqual);
end
if (`WORD_SELECT_BITS != 0) begin
assign creq_wsel_next = creq_addr_next_unqual[`WORD_SELECT_BITS-1:0];
assign creq_wsel = creq_addr_unqual[`WORD_SELECT_BITS-1:0];
end else begin
assign creq_wsel_next = 0;
assign creq_wsel = 0;
end
VX_fifo_queue_xt #(
.DATAW (CORE_TAG_WIDTH + `REQS_BITS + 1 + WORD_SIZE + `WORD_ADDR_WIDTH + `WORD_WIDTH),
.SIZE (CREQ_SIZE),
.FASTRAM (1)
VX_fifo_queue #(
.DATAW (CORE_TAG_WIDTH + `REQS_BITS + 1 + WORD_SIZE + `WORD_ADDR_WIDTH + `WORD_WIDTH),
.SIZE (CREQ_SIZE)
) core_req_queue (
.clk (clk),
.reset (reset),
.push (creq_push),
.pop (creq_pop),
.data_in ({core_req_tag, core_req_tid, core_req_rw, core_req_byteen, core_req_addr, core_req_data}),
`UNUSED_PIN (data_out),
.empty (creq_empty),
.data_out_next({creq_tag_next, creq_tid_next, creq_rw_next, creq_byteen_next, creq_addr_next_unqual, creq_writeword_next}),
`UNUSED_PIN (empty_next),
.full (creq_full),
.clk (clk),
.reset (reset),
.push (creq_push),
.pop (creq_pop),
.data_in ({core_req_tag, core_req_tid, core_req_rw, core_req_byteen, core_req_addr, core_req_data}),
.data_out ({creq_tag, creq_tid, creq_rw, creq_byteen, creq_addr_unqual, creq_writeword}),
.empty (creq_empty),
.full (creq_full),
`UNUSED_PIN (alm_empty),
`UNUSED_PIN (alm_full),
`UNUSED_PIN (size)
);
wire crsq_alm_full;
wire dreq_alm_full;
wire mshr_alm_full;
wire mshr_pop;
wire mshr_pending_unqual_st0;
wire mshr_alm_full;
wire mshr_pop;
wire mshr_push;
wire mshr_pending;
wire mshr_valid;
wire mshr_valid_next;
wire [`REQS_BITS-1:0] mshr_tid_next;
wire [`LINE_ADDR_WIDTH-1:0] mshr_addr_next;
wire [`UP(`WORD_SELECT_BITS)-1:0] mshr_wsel_next;
wire [`WORD_WIDTH-1:0] mshr_writeword_next;
wire [`REQ_TAG_WIDTH-1:0] mshr_tag_next;
wire mshr_rw_next;
wire [WORD_SIZE-1:0] mshr_byteen_next;
wire [`REQS_BITS-1:0] mshr_tid;
wire [`LINE_ADDR_WIDTH-1:0] mshr_addr;
wire [`UP(`WORD_SELECT_BITS)-1:0] mshr_wsel;
wire [`WORD_WIDTH-1:0] mshr_writeword;
wire [`REQ_TAG_WIDTH-1:0] mshr_tag;
wire mshr_rw;
wire [WORD_SIZE-1:0] mshr_byteen;
wire [`LINE_ADDR_WIDTH-1:0] addr_st0, addr_st1;
wire [`UP(`WORD_SELECT_BITS)-1:0] wsel_st0, wsel_st1;
@@ -194,55 +161,76 @@ module VX_bank #(
wire is_mshr_st0, is_mshr_st1;
wire [`CACHE_LINE_WIDTH-1:0] readdata_st1;
wire miss_st0, miss_st1;
wire prev_miss_hazard_st0, prev_miss_hazard_st1;
wire force_miss_st0, force_miss_st1;
wire do_writeback_st0, do_writeback_st1;
wire writeen_unqual_st0, writeen_unqual_st1;
wire mshr_push_unqual_st0, mshr_push_unqual_st1;
wire dreq_push_unqual_st0, dreq_push_unqual_st1;
wire writeen_st1;
wire core_req_hit_st1;
wire incoming_fill_st0, incoming_fill_st1;
wire is_flush_st0;
wire mshr_pending_st0;
wire is_mshr_miss_st1 = valid_st1 && is_mshr_st1 && (miss_st1 || force_miss_st1);
wire crsq_alm_full, crsq_push, crsq_pop;
wire dreq_alm_full, dreq_push, dreq_pop;
wire drsq_pop;
VX_pending_size #(
.SIZE (MSHR_SIZE)
) mshr_pending_size (
.clk (clk),
.reset (reset),
.push (creq_pop && !creq_rw),
.pop (crsq_push),
.full (mshr_alm_full),
`UNUSED_PIN (empty),
`UNUSED_PIN (size)
);
// determine which queue to pop next in piority order
wire mshr_pop_unqual = mshr_valid;
wire drsq_pop_unqual = !mshr_pop_unqual && !drsq_empty;
// determine which queue to pop next in priority order
wire mshr_pop_unqual = mshr_valid
&& !dreq_alm_full; // ensure DRAM request queue not full (deadlock prevention)
wire drsq_pop_unqual = !mshr_pop_unqual && dram_rsp_valid;
wire creq_pop_unqual = !mshr_pop_unqual && !drsq_pop_unqual && !creq_empty;
wire is_miss_st1 = valid_st1 && !is_fill_st1 && (miss_st1 || force_miss_st1);
assign mshr_pop = mshr_pop_unqual
&& !crsq_alm_full // ensure core response ready
&& !is_mshr_miss_st1; // do not schedule another mshr request when the previous one missed
&& !crsq_alm_full // ensure core response ready
&& !(is_miss_st1 && is_mshr_st1); // do not schedule another mshr request if the previous one missed
assign drsq_pop = drsq_pop_unqual;
assign creq_pop = creq_pop_unqual
&& !crsq_alm_full // ensure core response ready
&& !dreq_alm_full // ensure dram request ready
&& !crsq_alm_full // ensure core response ready
&& !mshr_alm_full; // ensure mshr enqueue ready
assign valid_st0 = mshr_pop || drsq_pop || creq_pop;
assign is_mshr_st0 = mshr_pop_unqual;
assign is_fill_st0 = drsq_pop_unqual;
assign dram_rsp_ready = drsq_pop;
// we have a miss in mshr or entering it for the current address
wire mshr_pending_sel = mshr_pending
|| (is_miss_st1 && (creq_addr == addr_st1));
VX_pipe_register #(
.DATAW (`LINE_ADDR_WIDTH + `UP(`WORD_SELECT_BITS) + 1 + WORD_SIZE + `CACHE_LINE_WIDTH + `REQS_BITS + `REQ_TAG_WIDTH + 1),
.RESETW (0)
.DATAW (1 + 1 + 1 + `LINE_ADDR_WIDTH + `UP(`WORD_SELECT_BITS) + 1 + WORD_SIZE + `CACHE_LINE_WIDTH + `REQS_BITS + `REQ_TAG_WIDTH + 1 + 1),
.RESETW (1)
) pipe_reg0 (
.clk (clk),
.reset (reset),
.enable (1'b1),
.data_in ({
mshr_valid_next ? mshr_addr_next : (!drsq_empty_next ? drsq_addr_next : creq_addr_next),
mshr_valid_next ? mshr_wsel_next : creq_wsel_next,
mshr_valid_next ? mshr_rw_next : creq_rw_next,
mshr_valid_next ? mshr_byteen_next : creq_byteen_next,
mshr_valid_next ? {`WORDS_PER_LINE{mshr_writeword_next}} : (!drsq_empty_next ? drsq_filldata_next : {`WORDS_PER_LINE{creq_writeword_next}}),
mshr_valid_next ? mshr_tid_next : creq_tid_next,
mshr_valid_next ? `REQ_TAG_WIDTH'(mshr_tag_next) : `REQ_TAG_WIDTH'(creq_tag_next),
drsq_flush_next
mshr_pop || drsq_pop || creq_pop,
mshr_pop_unqual,
drsq_pop_unqual,
mshr_pop_unqual ? mshr_addr : (dram_rsp_valid ? dram_rsp_addr : creq_addr),
mshr_pop_unqual ? mshr_wsel : creq_wsel,
mshr_pop_unqual ? mshr_rw : creq_rw,
mshr_pop_unqual ? mshr_byteen : creq_byteen,
mshr_pop_unqual ? {`WORDS_PER_LINE{mshr_writeword}} : (dram_rsp_valid ? dram_rsp_data : {`WORDS_PER_LINE{creq_writeword}}),
mshr_pop_unqual ? mshr_tid : creq_tid,
mshr_pop_unqual ? `REQ_TAG_WIDTH'(mshr_tag) : `REQ_TAG_WIDTH'(creq_tag),
mshr_pending_sel,
dram_rsp_flush
}),
.data_out ({addr_st0, wsel_st0, mem_rw_st0, byteen_st0, data_st0, req_tid_st0, tag_st0, is_flush_st0})
.data_out ({valid_st0, is_mshr_st0, is_fill_st0, addr_st0, wsel_st0, mem_rw_st0, byteen_st0, data_st0, req_tid_st0, tag_st0, mshr_pending_st0, is_flush_st0})
);
`ifdef DBG_CACHE_REQ_INFO
@@ -262,7 +250,7 @@ module VX_bank #(
.NUM_BANKS (NUM_BANKS),
.WORD_SIZE (WORD_SIZE),
.BANK_ADDR_OFFSET (BANK_ADDR_OFFSET)
) tag_access (
) tag_access (
.clk (clk),
.reset (reset),
@@ -272,54 +260,56 @@ module VX_bank #(
`endif
// read/Fill
.lookup (creq_pop || mshr_pop),
.lookup (valid_st0 && !is_fill_st0),
.addr (addr_st0),
.fill (drsq_pop),
.fill (valid_st0 && is_fill_st0),
.is_flush (is_flush_st0),
.missed (miss_st0)
);
// redundant fills
wire is_redundant_fill = is_fill_st0 && !miss_st0;
wire is_redundant_fill = is_fill_st0 && !miss_st0;
// we have a miss in mshr or going to it for the current address
wire mshr_pending_st0 = mshr_pending_unqual_st0
|| (valid_st1 && (miss_st1 || force_miss_st1) && (addr_st0 == addr_st1));
// we had a miss with prior request for the current address
assign prev_miss_hazard_st0 = is_miss_st1 && (addr_st0 == addr_st1);
// force miss to ensure commit order when a new request has pending previous requests to same block
assign force_miss_st0 = !is_mshr_st0 && !is_fill_st0 && mshr_pending_st0;
// also force a miss for mshr requests when previous requests got a miss
assign force_miss_st0 = (!is_fill_st0 && !is_mshr_st0 && (mshr_pending_st0 || prev_miss_hazard_st0))
|| (is_mshr_st0 && is_miss_st1 && is_mshr_st1);
assign writeen_unqual_st0 = (!is_fill_st0 && !miss_st0 && mem_rw_st0)
|| (is_fill_st0 && !is_redundant_fill);
wire send_fill_req_st0 = !is_fill_st0 && miss_st0 && !mem_rw_st0;
assign do_writeback_st0 = !is_fill_st0 && mem_rw_st0;
assign dreq_push_unqual_st0 = send_fill_req_st0 || do_writeback_st0;
assign mshr_push_unqual_st0 = !is_fill_st0 && !mem_rw_st0;
assign incoming_fill_st0 = dram_rsp_valid && (addr_st0 == dram_rsp_addr);
VX_pipe_register #(
.DATAW (1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `UP(`WORD_SELECT_BITS) + `CACHE_LINE_WIDTH + 1 + WORD_SIZE + `REQS_BITS + `REQ_TAG_WIDTH),
.DATAW (1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `UP(`WORD_SELECT_BITS) + `CACHE_LINE_WIDTH + 1 + WORD_SIZE + `REQS_BITS + `REQ_TAG_WIDTH),
.RESETW (1)
) pipe_reg1 (
.clk (clk),
.reset (reset),
.enable (1'b1),
.data_in ({valid_st0, is_mshr_st0, is_fill_st0, writeen_unqual_st0, mshr_push_unqual_st0, dreq_push_unqual_st0, do_writeback_st0, miss_st0, force_miss_st0, addr_st0, wsel_st0, data_st0, mem_rw_st0, byteen_st0, req_tid_st0, tag_st0}),
.data_out ({valid_st1, is_mshr_st1, is_fill_st1, writeen_unqual_st1, mshr_push_unqual_st1, dreq_push_unqual_st1, do_writeback_st1, miss_st1, force_miss_st1, addr_st1, wsel_st1, data_st1, mem_rw_st1, byteen_st1, req_tid_st1, tag_st1})
.data_in ({valid_st0, is_mshr_st0, is_fill_st0, writeen_unqual_st0, prev_miss_hazard_st0, incoming_fill_st0, miss_st0, force_miss_st0, addr_st0, wsel_st0, data_st0, mem_rw_st0, byteen_st0, req_tid_st0, tag_st0}),
.data_out ({valid_st1, is_mshr_st1, is_fill_st1, writeen_unqual_st1, prev_miss_hazard_st1, incoming_fill_st1, miss_st1, force_miss_st1, addr_st1, wsel_st1, data_st1, mem_rw_st1, byteen_st1, req_tid_st1, tag_st1})
);
assign core_req_hit_st1 = !is_fill_st1 && !miss_st1 && !force_miss_st1;
assign writeen_st1 = writeen_unqual_st1 && (is_fill_st1 || !force_miss_st1);
wire writeen_st1 = writeen_unqual_st1 && (is_fill_st1 || !force_miss_st1);
wire dreq_push_st1 = dreq_push_unqual_st1 && (do_writeback_st1 || !force_miss_st1);
wire crsq_push_st1 = !is_fill_st1 && !mem_rw_st1 && !miss_st1 && !force_miss_st1;
wire mshr_push_st1 = mshr_push_unqual_st1 && (miss_st1 || force_miss_st1);
wire mshr_push_st1 = !is_fill_st1 && !mem_rw_st1 && (miss_st1 || force_miss_st1);
wire crsq_push_st1 = core_req_hit_st1 && !mem_rw_st1;
wire incoming_fill_qual_st1 = (dram_rsp_valid && (addr_st1 == dram_rsp_addr))
|| incoming_fill_st1;
wire send_fill_req_st1 = !is_fill_st1 && !mem_rw_st1 && miss_st1
&& (!force_miss_st1 || (is_mshr_st1 && !prev_miss_hazard_st1))
&& !incoming_fill_qual_st1;
wire do_writeback_st1 = !is_fill_st1 && mem_rw_st1;
wire dreq_push_st1 = send_fill_req_st1 || do_writeback_st1;
VX_data_access #(
.BANK_ID (BANK_ID),
@@ -361,14 +351,15 @@ module VX_bank #(
end
`endif
wire incoming_fill_st1 = valid_st0 && is_fill_st0 && (addr_st1 == addr_st0);
wire mshr_push = valid_st1 && mshr_push_st1;
assign mshr_push = valid_st1 && mshr_push_st1;
wire mshr_dequeue = valid_st1 && is_mshr_st1 && !mshr_push_st1;
// push a missed request as 'ready' if it was a forced miss that actually had a hit
// or the fill request for this block is comming
wire mshr_init_ready_state = !miss_st1 || incoming_fill_st1;
wire mshr_init_ready_state = !miss_st1 || incoming_fill_qual_st1;
// use dram rsp or core req address to lookup the mshr
wire [`LINE_ADDR_WIDTH-1:0] lookup_addr = dram_rsp_valid ? dram_rsp_addr : creq_addr;
VX_miss_resrv #(
.BANK_ID (BANK_ID),
@@ -379,7 +370,7 @@ module VX_bank #(
.WORD_SIZE (WORD_SIZE),
.NUM_REQS (NUM_REQS),
.MSHR_SIZE (MSHR_SIZE),
.ALM_FULL (MSHR_SIZE-1),
.ALM_FULL (MSHR_SIZE-2),
.CORE_TAG_WIDTH (CORE_TAG_WIDTH)
) miss_resrv (
.clk (clk),
@@ -397,22 +388,20 @@ module VX_bank #(
.enqueue_addr (addr_st1),
.enqueue_data ({data_st1[`WORD_WIDTH-1:0], req_tid_st1, tag_st1, mem_rw_st1, byteen_st1, wsel_st1}),
.enqueue_is_mshr (is_mshr_st1),
.enqueue_as_ready (mshr_init_ready_state),
.enqueue_almfull (mshr_alm_full),
.enqueue_as_ready (mshr_init_ready_state),
`UNUSED_PIN (enqueue_almfull),
`UNUSED_PIN (enqueue_full),
// lookup
.lookup_ready (drsq_pop && !is_flush_st0),
.lookup_addr (addr_st0),
.lookup_match (mshr_pending_unqual_st0),
.lookup_ready (drsq_pop),
.lookup_addr (lookup_addr),
.lookup_match (mshr_pending),
// schedule
.schedule (mshr_pop),
.schedule_valid (mshr_valid),
`UNUSED_PIN (schedule_addr),
`UNUSED_PIN (schedule_data),
.schedule_valid_next(mshr_valid_next),
.schedule_addr_next (mshr_addr_next),
.schedule_data_next ({mshr_writeword_next, mshr_tid_next, mshr_tag_next, mshr_rw_next, mshr_byteen_next, mshr_wsel_next}),
.schedule_addr (mshr_addr),
.schedule_data ({mshr_writeword, mshr_tid, mshr_tag, mshr_rw, mshr_byteen, mshr_wsel}),
// dequeue
.dequeue (mshr_dequeue)
@@ -422,8 +411,8 @@ module VX_bank #(
wire crsq_empty;
wire crsq_push = valid_st1 && crsq_push_st1;
wire crsq_pop = core_rsp_valid && core_rsp_ready;
assign crsq_push = valid_st1 && crsq_push_st1;
assign crsq_pop = core_rsp_valid && core_rsp_ready;
wire [`REQS_BITS-1:0] crsq_tid_st1 = req_tid_st1;
wire [CORE_TAG_WIDTH-1:0] crsq_tag_st1 = CORE_TAG_WIDTH'(tag_st1);
@@ -438,19 +427,18 @@ module VX_bank #(
VX_fifo_queue #(
.DATAW (`REQS_BITS + CORE_TAG_WIDTH + `WORD_WIDTH),
.SIZE (CRSQ_SIZE),
.ALM_FULL (CRSQ_SIZE-1),
.BUFFERED (1),
.FASTRAM (1)
.ALM_FULL (CRSQ_SIZE-2),
.BUFFERED (1)
) core_rsp_queue (
.clk (clk),
.reset (reset),
.push (crsq_push),
.pop (crsq_pop),
.data_in ({crsq_tid_st1, crsq_tag_st1, crsq_data_st1}),
.data_out({core_rsp_tid, core_rsp_tag, core_rsp_data}),
.empty (crsq_empty),
.alm_full(crsq_alm_full),
`UNUSED_PIN (full),
.clk (clk),
.reset (reset),
.push (crsq_push),
.pop (crsq_pop),
.data_in ({crsq_tid_st1, crsq_tag_st1, crsq_data_st1}),
.data_out ({core_rsp_tid, core_rsp_tag, core_rsp_data}),
.empty (crsq_empty),
.alm_full (crsq_alm_full),
`UNUSED_PIN (full),
`UNUSED_PIN (alm_empty),
`UNUSED_PIN (size)
);
@@ -461,10 +449,9 @@ module VX_bank #(
wire dreq_empty;
wire dreq_push = valid_st1 && dreq_push_st1
&& (do_writeback_st1 || !incoming_fill_st1);
assign dreq_push = valid_st1 && dreq_push_st1;
wire dreq_pop = dram_req_valid && dram_req_ready;
assign dreq_pop = dram_req_valid && dram_req_ready;
wire writeback = WRITE_ENABLE && do_writeback_st1;
@@ -487,20 +474,18 @@ module VX_bank #(
VX_fifo_queue #(
.DATAW (1 + CACHE_LINE_SIZE + `LINE_ADDR_WIDTH + `CACHE_LINE_WIDTH),
.SIZE (DREQ_SIZE),
.ALM_FULL (DREQ_SIZE-1),
.BUFFERED (NUM_BANKS == 1),
.FASTRAM (1)
.ALM_FULL (DREQ_SIZE-2)
) dram_req_queue (
.clk (clk),
.reset (reset),
.push (dreq_push),
.pop (dreq_pop),
.data_in ({writeback, dreq_byteen, dreq_addr, dreq_data}),
.data_out({dram_req_rw, dram_req_byteen, dram_req_addr, dram_req_data}),
.empty (dreq_empty),
.alm_full(dreq_alm_full),
`UNUSED_PIN (full),
`UNUSED_PIN (alm_empty),
.clk (clk),
.reset (reset),
.push (dreq_push),
.pop (dreq_pop),
.data_in ({writeback, dreq_byteen, dreq_addr, dreq_data}),
.data_out ({dram_req_rw, dram_req_byteen, dram_req_addr, dram_req_data}),
.empty (dreq_empty),
.alm_full (dreq_alm_full),
`UNUSED_PIN (full),
`UNUSED_PIN (alm_empty),
`UNUSED_PIN (size)
);
@@ -510,9 +495,9 @@ module VX_bank #(
`SCOPE_ASSIGN (valid_st1, valid_st1);
`SCOPE_ASSIGN (is_fill_st0, is_fill_st0);
`SCOPE_ASSIGN (is_mshr_st0, is_mshr_st0);
`SCOPE_ASSIGN (miss_st0, miss_st0);
`SCOPE_ASSIGN (miss_st0, miss_st0);
`SCOPE_ASSIGN (force_miss_st0, force_miss_st0);
`SCOPE_ASSIGN (mshr_push, mshr_push);
`SCOPE_ASSIGN (mshr_push, mshr_push);
`SCOPE_ASSIGN (crsq_alm_full, crsq_alm_full);
`SCOPE_ASSIGN (dreq_alm_full, dreq_alm_full);
`SCOPE_ASSIGN (mshr_alm_full, mshr_alm_full);
@@ -528,24 +513,31 @@ module VX_bank #(
`ifdef DBG_PRINT_CACHE_BANK
always @(posedge clk) begin
if (valid_st1 && !is_fill_st1 && miss_st1 && incoming_fill_st1) begin
if (valid_st1 && !is_fill_st1 && miss_st1 && incoming_fill_qual_st1) begin
$display("%t: miss with incoming fill - addr=%0h", $time, `LINE_TO_BYTE_ADDR(addr_st1, BANK_ID));
assert(!is_mshr_st1);
end
if (crsq_alm_full || dreq_alm_full || mshr_alm_full) begin
$display("%t: cache%0d:%0d pipeline-stall: cwbq=%b, dwbq=%b, mshr=%b", $time, CACHE_ID, BANK_ID, crsq_alm_full, dreq_alm_full, mshr_alm_full);
end
if (drsq_pop) begin
if (valid_st0 && is_fill_st0) begin
if (is_flush_st0)
$display("%t: cache%0d:%0d flush: addr=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st0, BANK_ID));
else
$display("%t: cache%0d:%0d fill-rsp: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st0, BANK_ID), data_st0);
end
if (creq_pop || mshr_pop) begin
if (mem_rw_st0)
$display("%t: cache%0d:%0d core-wr-req: addr=%0h, is_mshr=%b, tag=%0h, tid=%0d, byteen=%b, data=%0h, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st0, BANK_ID), is_mshr_st0, tag_st0, req_tid_st0, byteen_st0, data_st0[`WORD_WIDTH-1:0], debug_wid_st0, debug_pc_st0);
else
$display("%t: cache%0d:%0d core-rd-req: addr=%0h, is_mshr=%b, tag=%0h, tid=%0d, byteen=%b, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st0, BANK_ID), is_mshr_st0, tag_st0, req_tid_st0, byteen_st0, debug_wid_st0, debug_pc_st0);
if (valid_st0 && !is_fill_st0) begin
if (is_mshr_st0) begin
if (mem_rw_st0)
$display("%t: cache%0d:%0d mshr-wr-req: addr=%0h, tag=%0h, tid=%0d, byteen=%b, data=%0h, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st0, BANK_ID), tag_st0, req_tid_st0, byteen_st0, data_st0[`WORD_WIDTH-1:0], debug_wid_st0, debug_pc_st0);
else
$display("%t: cache%0d:%0d mshr-rd-req: addr=%0h, tag=%0h, tid=%0d, byteen=%b, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st0, BANK_ID), tag_st0, req_tid_st0, byteen_st0, debug_wid_st0, debug_pc_st0);
end else begin
if (mem_rw_st0)
$display("%t: cache%0d:%0d core-wr-req: addr=%0h, tag=%0h, tid=%0d, byteen=%b, data=%0h, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st0, BANK_ID), tag_st0, req_tid_st0, byteen_st0, data_st0[`WORD_WIDTH-1:0], debug_wid_st0, debug_pc_st0);
else
$display("%t: cache%0d:%0d core-rd-req: addr=%0h, tag=%0h, tid=%0d, byteen=%b, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st0, BANK_ID), tag_st0, req_tid_st0, byteen_st0, debug_wid_st0, debug_pc_st0);
end
end
if (crsq_push) begin
$display("%t: cache%0d:%0d core-rsp: addr=%0h, tag=%0h, tid=%0d, data=%0h, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st1, BANK_ID), crsq_tag_st1, crsq_tid_st1, crsq_data_st1, debug_wid_st1, debug_pc_st1);

90
hw/rtl/cache/VX_cache.v vendored
View File

@@ -85,7 +85,6 @@ module VX_cache #(
);
`STATIC_ASSERT(NUM_BANKS <= NUM_REQS, ("invalid value"))
`UNUSED_VAR (dram_rsp_tag)
wire [NUM_BANKS-1:0] per_bank_core_req_valid;
wire [NUM_BANKS-1:0][`REQS_BITS-1:0] per_bank_core_req_tid;
@@ -111,6 +110,11 @@ module VX_cache #(
wire [NUM_BANKS-1:0] per_bank_dram_rsp_ready;
wire [`CACHE_LINE_WIDTH-1:0] dram_rsp_data_qual;
wire [DRAM_TAG_WIDTH-1:0] dram_rsp_tag_qual;
wire [`LINE_ADDR_WIDTH-1:0] flush_addr;
wire flush_enable;
`ifdef PERF_ENABLE
wire [NUM_BANKS-1:0] perf_read_miss_per_bank;
wire [NUM_BANKS-1:0] perf_write_miss_per_bank;
@@ -118,24 +122,55 @@ module VX_cache #(
wire [NUM_BANKS-1:0] perf_pipe_stall_per_bank;
`endif
reg flush_enable;
reg [`LINE_SELECT_BITS-1:0] flush_ctr;
///////////////////////////////////////////////////////////////////////////
always @(posedge clk) begin
if (reset || flush) begin
flush_enable <= 1;
flush_ctr <= 0;
end else begin
if (flush_enable && (& per_bank_dram_rsp_ready)) begin
if (flush_addr == ((2 ** `LINE_SELECT_BITS)-1)) begin
flush_enable <= 0;
end
flush_ctr <= flush_ctr + 1;
end
end
wire drsq_full, drsq_empty;
wire drsq_push, drsq_pop;
assign drsq_push = dram_rsp_valid && dram_rsp_ready;
assign dram_rsp_ready = !drsq_full;
VX_fifo_queue #(
.DATAW (DRAM_TAG_WIDTH + `CACHE_LINE_WIDTH),
.SIZE (DRSQ_SIZE)
) dram_rsp_queue (
.clk (clk),
.reset (reset),
.push (drsq_push),
.pop (drsq_pop),
.data_in ({dram_rsp_tag, dram_rsp_data}),
.data_out ({dram_rsp_tag_qual, dram_rsp_data_qual}),
.empty (drsq_empty),
.full (drsq_full),
`UNUSED_PIN (alm_full),
`UNUSED_PIN (alm_empty),
`UNUSED_PIN (size)
);
if (NUM_BANKS == 1) begin
`UNUSED_VAR (dram_rsp_tag_qual)
assign drsq_pop = !drsq_empty && per_bank_dram_rsp_ready && !flush_enable;
end else begin
assign drsq_pop = !drsq_empty && per_bank_dram_rsp_ready[`DRAM_ADDR_BANK(dram_rsp_tag_qual)] && !flush_enable;
end
wire [`LINE_ADDR_WIDTH-1:0] flush_addr = `LINE_ADDR_WIDTH'(flush_ctr);
///////////////////////////////////////////////////////////////////////////
VX_flush_ctrl #(
.CACHE_SIZE (CACHE_SIZE),
.CACHE_LINE_SIZE (CACHE_LINE_SIZE),
.NUM_BANKS (NUM_BANKS),
.WORD_SIZE (WORD_SIZE)
) flush_ctrl (
.clk (clk),
.reset (reset),
.flush (flush),
.addr (flush_addr),
.ready_out ((& per_bank_dram_rsp_ready)),
.valid_out (flush_enable)
);
///////////////////////////////////////////////////////////////////////////
VX_cache_core_req_bank_sel #(
.CACHE_LINE_SIZE (CACHE_LINE_SIZE),
@@ -143,8 +178,7 @@ module VX_cache #(
.WORD_SIZE (WORD_SIZE),
.NUM_REQS (NUM_REQS),
.CORE_TAG_WIDTH (CORE_TAG_WIDTH),
.BANK_ADDR_OFFSET(BANK_ADDR_OFFSET),
.BUFFERED (NUM_BANKS > 1)
.BANK_ADDR_OFFSET(BANK_ADDR_OFFSET)
) core_req_bank_sel (
.clk (clk),
.reset (reset),
@@ -170,13 +204,7 @@ module VX_cache #(
.per_bank_core_req_ready (per_bank_core_req_ready)
);
assign dram_req_tag = dram_req_addr;
if (NUM_BANKS == 1) begin
`UNUSED_VAR (dram_rsp_tag)
assign dram_rsp_ready = per_bank_dram_rsp_ready && !flush_enable;
end else begin
assign dram_rsp_ready = per_bank_dram_rsp_ready[`DRAM_ADDR_BANK(dram_rsp_tag)] && !flush_enable;
end
///////////////////////////////////////////////////////////////////////////
for (genvar i = 0; i < NUM_BANKS; i++) begin
wire curr_bank_core_req_valid;
@@ -238,13 +266,13 @@ module VX_cache #(
// DRAM response
if (NUM_BANKS == 1) begin
assign curr_bank_dram_rsp_valid = dram_rsp_valid || flush_enable;
assign curr_bank_dram_rsp_addr = flush_enable ? flush_addr : dram_rsp_tag;
assign curr_bank_dram_rsp_valid = !drsq_empty || flush_enable;
assign curr_bank_dram_rsp_addr = flush_enable ? flush_addr : dram_rsp_tag_qual;
end else begin
assign curr_bank_dram_rsp_valid = (dram_rsp_valid && (`DRAM_ADDR_BANK(dram_rsp_tag) == i)) || flush_enable;
assign curr_bank_dram_rsp_addr = flush_enable ? flush_addr : `DRAM_TO_LINE_ADDR(dram_rsp_tag);
assign curr_bank_dram_rsp_valid = (!drsq_empty && (`DRAM_ADDR_BANK(dram_rsp_tag_qual) == i)) || flush_enable;
assign curr_bank_dram_rsp_addr = flush_enable ? flush_addr : `DRAM_TO_LINE_ADDR(dram_rsp_tag_qual);
end
assign curr_bank_dram_rsp_data = dram_rsp_data;
assign curr_bank_dram_rsp_data = dram_rsp_data_qual;
assign curr_bank_dram_rsp_flush = flush_enable;
assign per_bank_dram_rsp_ready[i] = curr_bank_dram_rsp_ready;
@@ -352,6 +380,8 @@ module VX_cache #(
.ready_out (dram_req_ready)
);
assign dram_req_tag = dram_req_addr;
`ifdef PERF_ENABLE
// per cycle: core_reads, core_writes
reg [($clog2(NUM_REQS+1)-1):0] perf_core_reads_per_cycle, perf_core_writes_per_cycle;

15
hw/rtl/cache/VX_cache_core_rsp_merge.v vendored
View File

@@ -37,12 +37,10 @@ module VX_cache_core_rsp_merge #(
if (CORE_TAG_ID_BITS != 0) begin
reg [CORE_TAG_WIDTH-1:0] core_rsp_tag_unqual;
reg core_rsp_valid_unaual_any;
wire core_rsp_ready_unqual;
always @(*) begin
core_rsp_valid_unqual = 0;
core_rsp_valid_unaual_any = 0;
core_rsp_tag_unqual = 'x;
core_rsp_data_unqual = 'x;
core_rsp_bank_select = 0;
@@ -55,8 +53,7 @@ module VX_cache_core_rsp_merge #(
for (integer i = 0; i < NUM_BANKS; i++) begin
if (per_bank_core_rsp_valid[i]
&& (per_bank_core_rsp_tag[i][CORE_TAG_ID_BITS-1:0] == core_rsp_tag_unqual[CORE_TAG_ID_BITS-1:0])) begin
core_rsp_valid_unaual_any = 1;
&& (per_bank_core_rsp_tag[i][CORE_TAG_ID_BITS-1:0] == core_rsp_tag_unqual[CORE_TAG_ID_BITS-1:0])) begin
core_rsp_valid_unqual[per_bank_core_rsp_tid[i]] = 1;
core_rsp_data_unqual[per_bank_core_rsp_tid[i]] = per_bank_core_rsp_data[i];
core_rsp_bank_select[i] = core_rsp_ready_unqual;
@@ -66,13 +63,16 @@ module VX_cache_core_rsp_merge #(
wire core_rsp_valid_out;
wire [NUM_REQS-1:0] core_rsp_valid_out_mask;
wire core_rsp_valid_any = (| per_bank_core_rsp_valid);
VX_skid_buffer #(
.DATAW (NUM_REQS + CORE_TAG_WIDTH + (NUM_REQS *`WORD_WIDTH))
.DATAW (NUM_REQS + CORE_TAG_WIDTH + (NUM_REQS *`WORD_WIDTH)),
.BUFFERED (1)
) pipe_reg (
.clk (clk),
.reset (reset),
.valid_in (core_rsp_valid_unaual_any),
.valid_in (core_rsp_valid_any),
.data_in ({core_rsp_valid_unqual, core_rsp_tag_unqual, core_rsp_data_unqual}),
.ready_in (core_rsp_ready_unqual),
.valid_out (core_rsp_valid_out),
@@ -106,7 +106,8 @@ module VX_cache_core_rsp_merge #(
for (genvar i = 0; i < NUM_REQS; i++) begin
VX_skid_buffer #(
.DATAW (CORE_TAG_WIDTH + `WORD_WIDTH)
.DATAW (CORE_TAG_WIDTH + `WORD_WIDTH),
.BUFFERED (1)
) pipe_reg (
.clk (clk),
.reset (reset),

125
hw/rtl/cache/VX_fifo_queue_xt.v vendored
View File

@@ -1,125 +0,0 @@
`include "VX_platform.vh"
module VX_fifo_queue_xt #(
parameter DATAW = 1,
parameter SIZE = 2,
parameter ADDRW = $clog2(SIZE),
parameter SIZEW = $clog2(SIZE+1),
parameter FASTRAM = 0
) (
input wire clk,
input wire reset,
input wire push,
input wire pop,
input wire [DATAW-1:0] data_in,
output wire [DATAW-1:0] data_out,
output wire empty,
output wire [DATAW-1:0] data_out_next,
output wire empty_next,
output wire full,
output wire [SIZEW-1:0] size
);
wire [DATAW-1:0] dout;
reg [DATAW-1:0] dout_r, dout_n_r;
reg [ADDRW-1:0] wr_ptr_r;
reg [ADDRW-1:0] rd_ptr_r, rd_ptr_n_r;
reg full_r;
reg empty_r, empty_n_r;
reg [ADDRW-1:0] used_r;
always @(posedge clk) begin
if (reset) begin
full_r <= 0;
used_r <= 0;
end else begin
assert(!push || !full);
assert(!pop || !empty_r);
if (push) begin
if (!pop) begin
if (used_r == ADDRW'(SIZE-1))
full_r <= 1;
end
end else if (pop) begin
full_r <= 0;
end
used_r <= used_r + ADDRW'($signed(2'(push) - 2'(pop)));
end
end
always @(posedge clk) begin
if (reset) begin
wr_ptr_r <= 0;
rd_ptr_r <= 0;
rd_ptr_n_r <= 1;
end else begin
if (push) begin
wr_ptr_r <= wr_ptr_r + ADDRW'(1);
end
if (pop) begin
rd_ptr_r <= rd_ptr_n_r;
if (SIZE > 2) begin
rd_ptr_n_r <= rd_ptr_r + ADDRW'(2);
end else begin // (SIZE == 2);
rd_ptr_n_r <= ~rd_ptr_n_r;
end
end
end
end
VX_dp_ram #(
.DATAW (DATAW),
.SIZE (SIZE),
.BUFFERED (0),
.RWCHECK (1),
.FASTRAM (FASTRAM)
) dp_ram (
.clk(clk),
.waddr(wr_ptr_r),
.raddr(rd_ptr_n_r),
.wren(push),
.byteen(1'b1),
.rden(1'b1),
.din(data_in),
.dout(dout)
);
always @(*) begin
empty_n_r = empty_r;
if (reset) begin
empty_n_r = 1;
end else begin
if (push) begin
if (!pop) begin
empty_n_r = 0;
end
end else if (pop) begin
if (used_r == ADDRW'(1)) begin
empty_n_r = 1;
end
end
end
end
always @(*) begin
dout_n_r = dout_r;
if (push && (empty_r || ((used_r == ADDRW'(1)) && pop))) begin
dout_n_r = data_in;
end else if (pop) begin
dout_n_r = dout;
end
end
always @(posedge clk) begin
empty_r <= empty_n_r;
dout_r <= dout_n_r;
end
assign data_out = dout_r;
assign data_out_next = dout_n_r;
assign empty = empty_r;
assign empty_next = empty_n_r;
assign full = full_r;
assign size = {full_r, used_r};
endmodule

40
hw/rtl/cache/VX_flush_ctrl.v vendored Normal file
View File

@@ -0,0 +1,40 @@
`include "VX_cache_config.vh"
module VX_flush_ctrl #(
// Size of cache in bytes
parameter CACHE_SIZE = 16384,
// Size of line inside a bank in bytes
parameter CACHE_LINE_SIZE = 1,
// Number of banks
parameter NUM_BANKS = 1,
// Size of a word in bytes
parameter WORD_SIZE = 1
) (
input wire clk,
input wire reset,
input wire flush,
output wire [`LINE_ADDR_WIDTH-1:0] addr,
input wire ready_out,
output wire valid_out
);
reg flush_enable;
reg [`LINE_SELECT_BITS-1:0] flush_ctr;
always @(posedge clk) begin
if (reset || flush) begin
flush_enable <= 1;
flush_ctr <= 0;
end else begin
if (flush_enable && ready_out) begin
if (flush_ctr == ((2 ** `LINE_SELECT_BITS)-1)) begin
flush_enable <= 0;
end
flush_ctr <= flush_ctr + 1;
end
end
end
assign addr = `LINE_ADDR_WIDTH'(flush_ctr);
assign valid_out = flush_enable;
endmodule

155
hw/rtl/cache/VX_miss_resrv.v vendored
View File

@@ -38,6 +38,7 @@ module VX_miss_resrv #(
input wire [`MSHR_DATA_WIDTH-1:0] enqueue_data,
input wire enqueue_is_mshr,
input wire enqueue_as_ready,
output wire enqueue_full,
output wire enqueue_almfull,
// lookup
@@ -50,9 +51,6 @@ module VX_miss_resrv #(
output wire schedule_valid,
output wire [`LINE_ADDR_WIDTH-1:0] schedule_addr,
output wire [`MSHR_DATA_WIDTH-1:0] schedule_data,
output wire schedule_valid_next,
output wire [`LINE_ADDR_WIDTH-1:0] schedule_addr_next,
output wire [`MSHR_DATA_WIDTH-1:0] schedule_data_next,
// dequeue
input wire dequeue
@@ -63,16 +61,10 @@ module VX_miss_resrv #(
reg [MSHR_SIZE-1:0] valid_table;
reg [MSHR_SIZE-1:0] ready_table;
reg [ADDRW-1:0] schedule_ptr, schedule_n_ptr;
reg [ADDRW-1:0] restore_ptr;
reg [ADDRW-1:0] head_ptr, tail_ptr;
reg [ADDRW-1:0] head_ptr, tail_ptr;
reg [ADDRW-1:0] schedule_ptr, restore_ptr;
reg [ADDRW-1:0] used_r;
reg full_r, almost_full_r;
reg schedule_valid_r, schedule_valid_n_r;
reg [`LINE_ADDR_WIDTH-1:0] schedule_addr_r, schedule_addr_n_r;
reg [`MSHR_DATA_WIDTH-1:0] dout_r, dout_n_r;
wire [`MSHR_DATA_WIDTH-1:0] dout;
reg alm_full_r, full_r;
wire [MSHR_SIZE-1:0] valid_address_match;
for (genvar i = 0; i < MSHR_SIZE; i++) begin
@@ -82,22 +74,22 @@ module VX_miss_resrv #(
assign lookup_match = (| valid_address_match);
wire push_new = enqueue && !enqueue_is_mshr;
wire restore = enqueue && enqueue_is_mshr;
wire [ADDRW-1:0] head_ptr_n = head_ptr + $bits(head_ptr)'(1);
wire [`LOG2UP(MSHR_SIZE)-1:0] head_ptr_n = head_ptr + $bits(head_ptr)'(1);
always @(posedge clk) begin
if (reset) begin
valid_table <= 0;
ready_table <= 0;
schedule_ptr <= 0;
schedule_n_ptr <= 1;
restore_ptr <= 0;
head_ptr <= 0;
tail_ptr <= 0;
used_r <= 0;
full_r <= 0;
almost_full_r <= 0;
valid_table <= 0;
ready_table <= 0;
head_ptr <= 0;
tail_ptr <= 0;
schedule_ptr <= 0;
restore_ptr <= 0;
used_r <= 0;
alm_full_r <= 0;
full_r <= 0;
end else begin
// WARNING: lookup should happen enqueue for ready_table's correct update
@@ -106,52 +98,46 @@ module VX_miss_resrv #(
ready_table <= ready_table | valid_address_match;
end
if (enqueue) begin
if (enqueue_is_mshr) begin
// restore schedule, returning missed msrq entry
valid_table[restore_ptr] <= 1;
ready_table[restore_ptr] <= enqueue_as_ready;
restore_ptr <= restore_ptr + $bits(restore_ptr)'(1);
schedule_ptr <= head_ptr;
schedule_n_ptr <= head_ptr_n;
end else begin
// push new entry
assert(!full_r);
valid_table[tail_ptr] <= 1;
ready_table[tail_ptr] <= enqueue_as_ready;
tail_ptr <= tail_ptr + $bits(tail_ptr)'(1);
end
if (push_new) begin
// push new entry
assert(!full_r);
valid_table[tail_ptr] <= 1;
ready_table[tail_ptr] <= enqueue_as_ready;
tail_ptr <= tail_ptr + $bits(tail_ptr)'(1);
end else if (restore) begin
assert(!schedule);
// restore schedule, returning missed mshr entry
valid_table[restore_ptr] <= 1;
ready_table[restore_ptr] <= enqueue_as_ready;
restore_ptr <= restore_ptr + $bits(restore_ptr)'(1);
schedule_ptr <= head_ptr;
end else if (dequeue) begin
// remove scheduled entry from buffer
// clear scheduled entry
assert(((head_ptr+$bits(head_ptr)'(1)) == schedule_ptr)
|| ((head_ptr+$bits(head_ptr)'(2)) == schedule_ptr)) else $error("schedule_ptr=%0d, head_ptr=%0d", schedule_ptr, head_ptr);
valid_table[head_ptr] <= 0;
head_ptr <= head_ptr_n;
restore_ptr <= head_ptr_n;
valid_table[head_ptr] <= 0;
end
if (schedule) begin
// schedule next entry
assert(schedule_valid_r);
valid_table[schedule_ptr] <= 0;
ready_table[schedule_ptr] <= 0;
schedule_ptr <= schedule_n_ptr;
if (MSHR_SIZE > 2) begin
schedule_n_ptr <= schedule_ptr + $bits(schedule_ptr)'(2);
end else begin // (MSHR_SIZE == 2);
schedule_n_ptr <= ~schedule_n_ptr;
end
// schedule next entry
assert(schedule_valid);
valid_table[schedule_ptr] <= 0;
ready_table[schedule_ptr] <= 0;
schedule_ptr <= schedule_ptr + $bits(schedule_ptr)'(1);
end
if (push_new) begin
if (!dequeue) begin
if (used_r == ADDRW'(ALM_FULL-1))
alm_full_r <= 1;
if (used_r == ADDRW'(MSHR_SIZE-1))
full_r <= 1;
if (used_r == ADDRW'(ALM_FULL-1))
almost_full_r <= 1;
end
end else if (dequeue) begin
if (used_r == ADDRW'(ALM_FULL))
almost_full_r <= 0;
alm_full_r <= 0;
full_r <= 0;
end
@@ -173,72 +159,33 @@ module VX_miss_resrv #(
) entries (
.clk(clk),
.waddr(tail_ptr),
.raddr(schedule_n_ptr),
.raddr(schedule_ptr),
.wren(push_new),
.byteen(1'b1),
.rden(1'b1),
.din(enqueue_data),
.dout(dout)
.dout(schedule_data)
);
always @(*) begin
schedule_valid_n_r = schedule_valid_r;
if (reset) begin
schedule_valid_n_r = 0;
end else begin
if (restore) begin
schedule_valid_n_r = enqueue_as_ready;
end else if (lookup_ready) begin
schedule_valid_n_r = schedule_valid_r || (schedule_addr_r == lookup_addr);
end else if (schedule) begin
schedule_valid_n_r = ready_table[schedule_n_ptr];
end
end
end
always @(*) begin
schedule_addr_n_r = schedule_addr_r;
dout_n_r = dout_r;
if (restore
|| (push_new && (used_r == 0 || (used_r == 1 && schedule)))) begin
schedule_addr_n_r = enqueue_addr;
dout_n_r = enqueue_data;
end else if (schedule) begin
schedule_addr_n_r = addr_table[schedule_n_ptr];
dout_n_r = dout;
end
end
always @(posedge clk) begin
schedule_valid_r <= schedule_valid_n_r;
schedule_addr_r <= schedule_addr_n_r;
dout_r <= dout_n_r;
end
assign schedule_valid = schedule_valid_r;
assign schedule_addr = schedule_addr_r;
assign schedule_data = dout_r;
assign schedule_valid_next = schedule_valid_n_r;
assign schedule_addr_next = schedule_addr_n_r;
assign schedule_data_next = dout_n_r;
assign enqueue_almfull = almost_full_r;
assign schedule_valid = ready_table[schedule_ptr];
assign schedule_addr = addr_table[schedule_ptr];
assign enqueue_almfull = alm_full_r;
assign enqueue_full = full_r;
`ifdef DBG_PRINT_CACHE_MSHR
always @(posedge clk) begin
if (lookup_ready || schedule || enqueue || dequeue) begin
if (schedule)
$display("%t: cache%0d:%0d msrq-schedule: addr%0d=%0h, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, schedule_ptr, `LINE_TO_BYTE_ADDR(schedule_addr, BANK_ID), deq_debug_wid, deq_debug_pc);
$display("%t: cache%0d:%0d mshr-schedule: addr%0d=%0h, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, schedule_ptr, `LINE_TO_BYTE_ADDR(schedule_addr, BANK_ID), deq_debug_wid, deq_debug_pc);
if (enqueue) begin
if (enqueue_is_mshr)
$display("%t: cache%0d:%0d msrq-restore: addr%0d=%0h, ready=%b", $time, CACHE_ID, BANK_ID, restore_ptr, `LINE_TO_BYTE_ADDR(enqueue_addr, BANK_ID), enqueue_as_ready);
$display("%t: cache%0d:%0d mshr-restore: addr%0d=%0h, ready=%b", $time, CACHE_ID, BANK_ID, restore_ptr, `LINE_TO_BYTE_ADDR(enqueue_addr, BANK_ID), enqueue_as_ready);
else
$display("%t: cache%0d:%0d msrq-enq: addr%0d=%0h, ready=%b, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, tail_ptr, `LINE_TO_BYTE_ADDR(enqueue_addr, BANK_ID), enqueue_as_ready, enq_debug_wid, enq_debug_pc);
$display("%t: cache%0d:%0d mshr-enqueue: addr%0d=%0h, ready=%b, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, tail_ptr, `LINE_TO_BYTE_ADDR(enqueue_addr, BANK_ID), enqueue_as_ready, enq_debug_wid, enq_debug_pc);
end
if (dequeue)
$display("%t: cache%0d:%0d msrq-deq addr%0d, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, head_ptr, enq_debug_wid, enq_debug_pc);
$write("%t: cache%0d:%0d msrq-table", $time, CACHE_ID, BANK_ID);
$display("%t: cache%0d:%0d mshr-dequeue addr%0d, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, head_ptr, enq_debug_wid, enq_debug_pc);
$write("%t: cache%0d:%0d mshr-table", $time, CACHE_ID, BANK_ID);
for (integer j = 0; j < MSHR_SIZE; j++) begin
if (valid_table[j]) begin
$write(" ");

6
hw/rtl/cache/VX_shared_mem.v vendored
View File

@@ -134,8 +134,7 @@ module VX_shared_mem #(
VX_fifo_queue #(
.DATAW (NUM_BANKS * (1 + `REQS_BITS + 1 + WORD_SIZE + `LINE_SELECT_BITS + `WORD_WIDTH + CORE_TAG_WIDTH)),
.SIZE (CREQ_SIZE),
.BUFFERED (1),
.FASTRAM (1)
.BUFFERED (1)
) core_req_queue (
.clk (clk),
.reset (reset),
@@ -217,8 +216,7 @@ module VX_shared_mem #(
VX_fifo_queue #(
.DATAW (NUM_BANKS * (1 + `WORD_WIDTH) + CORE_TAG_WIDTH),
.SIZE (CRSQ_SIZE),
.BUFFERED (1),
.FASTRAM (1)
.BUFFERED (1)
) core_rsp_queue (
.clk (clk),
.reset (reset),