40 lines
1.1 KiB
Verilog
40 lines
1.1 KiB
Verilog
`include "VX_cache_config.vh"
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module VX_flush_ctrl #(
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// Size of cache in bytes
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parameter CACHE_SIZE = 16384,
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// Size of line inside a bank in bytes
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parameter CACHE_LINE_SIZE = 1,
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// Number of banks
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parameter NUM_BANKS = 1,
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// Size of a word in bytes
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parameter WORD_SIZE = 1
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) (
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input wire clk,
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input wire reset,
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input wire flush,
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output wire [`LINE_ADDR_WIDTH-1:0] addr,
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input wire ready_out,
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output wire valid_out
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);
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reg flush_enable;
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reg [`LINE_SELECT_BITS-1:0] flush_ctr;
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always @(posedge clk) begin
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if (reset || flush) begin
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flush_enable <= 1;
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flush_ctr <= 0;
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end else begin
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if (flush_enable && ready_out) begin
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if (flush_ctr == ((2 ** `LINE_SELECT_BITS)-1)) begin
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flush_enable <= 0;
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end
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flush_ctr <= flush_ctr + 1;
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end
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end
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end
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assign addr = `LINE_ADDR_WIDTH'(flush_ctr);
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assign valid_out = flush_enable;
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endmodule |