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cache multi-porting optimization

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This commit is contained in:
Blaise Tine
2021-07-15 11:54:27 -07:00
parent c5aec572b5
commit 8678150ce0
4 changed files with 36 additions and 15 deletions
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5
hw/rtl/cache/VX_shared_mem.v vendored
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@@ -91,11 +91,12 @@ module VX_shared_mem #(
.per_bank_core_req_tid (per_bank_core_req_tid_unqual),
.per_bank_core_req_rw (per_bank_core_req_rw_unqual),
.per_bank_core_req_addr (per_bank_core_req_addr_unqual),
`UNUSED_PIN (per_bank_core_req_wsel),
.per_bank_core_req_byteen(per_bank_core_req_byteen_unqual),
.per_bank_core_req_tag (per_bank_core_req_tag_unqual),
.per_bank_core_req_data (per_bank_core_req_data_unqual),
.per_bank_core_req_ready (per_bank_core_req_ready_unqual)
.per_bank_core_req_ready (per_bank_core_req_ready_unqual),
`UNUSED_PIN (per_bank_core_req_pmask),
`UNUSED_PIN (per_bank_core_req_wsel)
);
wire [NUM_BANKS-1:0] per_bank_core_req_valid;