code refactoring: DRAM => MEM renaming
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22
hw/unit_tests/cache/cachesim.h
vendored
22
hw/unit_tests/cache/cachesim.h
vendored
@@ -14,17 +14,17 @@
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#include <vector>
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#include <queue>
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#define ENABLE_DRAM_STALLS
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#define DRAM_LATENCY 100
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#define DRAM_RQ_SIZE 16
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#define DRAM_STALLS_MODULO 16
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#define ENABLE_MEM_STALLS
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#define MEM_LATENCY 100
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#define MEM_RQ_SIZE 16
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#define MEM_STALLS_MODULO 16
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#define GLOBAL_BLOCK_SIZE 16
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typedef struct {
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int cycles_left;
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uint8_t *data;
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unsigned tag;
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} dram_req_t;
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} mem_req_t;
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typedef struct {
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char valid;
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@@ -52,7 +52,7 @@ public:
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//req/rsp
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void send_req(core_req_t *req);
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void clear_req();
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void stall_dram();
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void stall_mem();
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void send_snoop_req();
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void send_snp_fwd_in();
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@@ -60,12 +60,12 @@ public:
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bool assert_equal(unsigned int* data, unsigned int tag);
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//debug funcs
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void get_dram_req();
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void get_mem_req();
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void get_core_req(unsigned int (&rsp)[4]);
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void get_core_rsp();
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bool get_core_req_ready();
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bool get_core_rsp_ready();
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void get_dram_rsp();
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void get_mem_rsp();
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void display_miss();
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private:
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@@ -73,12 +73,12 @@ private:
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void eval();
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void eval_reqs();
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void eval_rsps();
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void eval_dram_bus();
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void eval_mem_bus();
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std::queue<core_req_t*> core_req_vec_;
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std::vector<dram_req_t> dram_rsp_vec_;
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std::vector<mem_req_t> mem_rsp_vec_;
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std::map<unsigned int, unsigned int*> core_rsp_vec_;
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int dram_rsp_active_;
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int mem_rsp_active_;
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uint32_t snp_req_active_;
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uint32_t snp_req_size_;
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