diff --git a/ci/regression.sh b/ci/regression.sh index 439b28ef..005e20da 100755 --- a/ci/regression.sh +++ b/ci/regression.sh @@ -16,7 +16,7 @@ make -s # Blackbox tests ./ci/travis_run.py ./ci/blackbox.sh --driver=vlsim --cores=1 --perf --app=demo --args="-n1" ./ci/travis_run.py ./ci/blackbox.sh --driver=vlsim --cores=1 --debug --app=demo --args="-n1" -./ci/travis_run.py ./ci/blackbox.sh --driver=vlsim --cores=1 --scope --app=demo --args="-n1" +./ci/travis_run.py ./ci/blackbox.sh --driver=vlsim --cores=1 --scope --app=basic --args="-t0 -n1" ./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=2 --clusters=2 --app=demo --args="-n1" ./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=2 --l2cache --app=demo --args="-n1" ./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=2 --clusters=2 --l2cache --l3cache --app=demo --args="-n1" diff --git a/driver/common/vx_utils.cpp b/driver/common/vx_utils.cpp index c265002d..4bc2017b 100644 --- a/driver/common/vx_utils.cpp +++ b/driver/common/vx_utils.cpp @@ -115,10 +115,10 @@ extern int vx_dump_perf(vx_device_h device, FILE* stream) { uint64_t smem_writes = 0; uint64_t smem_bank_stalls = 0; // PERF: memory - uint64_t dram_reads = 0; - uint64_t dram_writes = 0; - uint64_t dram_stalls = 0; - uint64_t dram_lat = 0; + uint64_t mem_reads = 0; + uint64_t mem_writes = 0; + uint64_t mem_stalls = 0; + uint64_t mem_lat = 0; #endif for (unsigned core_id = 0; core_id < num_cores; ++core_id) { @@ -255,21 +255,21 @@ extern int vx_dump_perf(vx_device_h device, FILE* stream) { if (num_cores > 1) fprintf(stream, "PERF: core%d: smem bank stalls=%ld (utilization=%d%%)\n", core_id, smem_bank_st_per_core, smem_bank_utilization); smem_bank_stalls += smem_bank_st_per_core; - // PERF: DRAM - uint64_t dram_reads_per_core, dram_writes_per_core, dram_stalls_per_core, dram_lat_per_core; - ret |= vx_csr_get_l(device, core_id, CSR_MPM_DRAM_READS, CSR_MPM_DRAM_READS_H, &dram_reads_per_core); - ret |= vx_csr_get_l(device, core_id, CSR_MPM_DRAM_WRITES, CSR_MPM_DRAM_WRITES_H, &dram_writes_per_core); - ret |= vx_csr_get_l(device, core_id, CSR_MPM_DRAM_ST, CSR_MPM_DRAM_ST_H, &dram_stalls_per_core); - ret |= vx_csr_get_l(device, core_id, CSR_MPM_DRAM_LAT, CSR_MPM_DRAM_LAT_H, &dram_lat_per_core); - int dram_utilization = (int)((double(dram_reads_per_core + dram_writes_per_core) / double(dram_reads_per_core + dram_writes_per_core + dram_stalls_per_core)) * 100); - int dram_avg_lat = (int)(double(dram_lat_per_core) / double(dram_reads_per_core)); - if (num_cores > 1) fprintf(stream, "PERF: core%d: dram requests=%ld (reads=%ld, writes=%ld)\n", core_id, (dram_reads_per_core + dram_writes_per_core), dram_reads_per_core, dram_writes_per_core); - if (num_cores > 1) fprintf(stream, "PERF: core%d: dram stalls=%ld (utilization=%d%%)\n", core_id, dram_stalls_per_core, dram_utilization); - if (num_cores > 1) fprintf(stream, "PERF: core%d: dram average latency=%d cycles\n", core_id, dram_avg_lat); - dram_reads += dram_reads_per_core; - dram_writes += dram_writes_per_core; - dram_stalls += dram_stalls_per_core; - dram_lat += dram_lat_per_core; + // PERF: memory + uint64_t mem_reads_per_core, mem_writes_per_core, mem_stalls_per_core, mem_lat_per_core; + ret |= vx_csr_get_l(device, core_id, CSR_MPM_MEM_READS, CSR_MPM_MEM_READS_H, &mem_reads_per_core); + ret |= vx_csr_get_l(device, core_id, CSR_MPM_MEM_WRITES, CSR_MPM_MEM_WRITES_H, &mem_writes_per_core); + ret |= vx_csr_get_l(device, core_id, CSR_MPM_MEM_ST, CSR_MPM_MEM_ST_H, &mem_stalls_per_core); + ret |= vx_csr_get_l(device, core_id, CSR_MPM_MEM_LAT, CSR_MPM_MEM_LAT_H, &mem_lat_per_core); + int mem_utilization = (int)((double(mem_reads_per_core + mem_writes_per_core) / double(mem_reads_per_core + mem_writes_per_core + mem_stalls_per_core)) * 100); + int mem_avg_lat = (int)(double(mem_lat_per_core) / double(mem_reads_per_core)); + if (num_cores > 1) fprintf(stream, "PERF: core%d: memory requests=%ld (reads=%ld, writes=%ld)\n", core_id, (mem_reads_per_core + mem_writes_per_core), mem_reads_per_core, mem_writes_per_core); + if (num_cores > 1) fprintf(stream, "PERF: core%d: memory stalls=%ld (utilization=%d%%)\n", core_id, mem_stalls_per_core, mem_utilization); + if (num_cores > 1) fprintf(stream, "PERF: core%d: memory average latency=%d cycles\n", core_id, mem_avg_lat); + mem_reads += mem_reads_per_core; + mem_writes += mem_writes_per_core; + mem_stalls += mem_stalls_per_core; + mem_lat += mem_lat_per_core; #endif } @@ -282,8 +282,8 @@ extern int vx_dump_perf(vx_device_h device, FILE* stream) { int dcache_write_hit_ratio = (int)((1.0 - (double(dcache_write_misses) / double(dcache_writes))) * 100); int dcache_bank_utilization = (int)((double(dcache_reads + dcache_writes) / double(dcache_reads + dcache_writes + dcache_bank_stalls)) * 100); int smem_bank_utilization = (int)((double(smem_reads + smem_writes) / double(smem_reads + smem_writes + smem_bank_stalls)) * 100); - int dram_utilization = (int)((double(dram_reads + dram_writes) / double(dram_reads + dram_writes + dram_stalls)) * 100); - int dram_avg_lat = (int)(double(dram_lat) / double(dram_reads)); + int mem_utilization = (int)((double(mem_reads + mem_writes) / double(mem_reads + mem_writes + mem_stalls)) * 100); + int mem_avg_lat = (int)(double(mem_lat) / double(mem_reads)); fprintf(stream, "PERF: ibuffer stalls=%ld\n", ibuffer_stalls); fprintf(stream, "PERF: scoreboard stalls=%ld\n", scoreboard_stalls); fprintf(stream, "PERF: alu unit stalls=%ld\n", alu_stalls); @@ -306,9 +306,9 @@ extern int vx_dump_perf(vx_device_h device, FILE* stream) { fprintf(stream, "PERF: smem reads=%ld\n", smem_reads); fprintf(stream, "PERF: smem writes=%ld\n", smem_writes); fprintf(stream, "PERF: smem bank stalls=%ld (utilization=%d%%)\n", smem_bank_stalls, smem_bank_utilization); - fprintf(stream, "PERF: dram requests=%ld (reads=%ld, writes=%ld)\n", (dram_reads + dram_writes), dram_reads, dram_writes); - fprintf(stream, "PERF: dram stalls=%ld (utilization=%d%%)\n", dram_stalls, dram_utilization); - fprintf(stream, "PERF: dram average latency=%d cycles\n", dram_avg_lat); + fprintf(stream, "PERF: memory requests=%ld (reads=%ld, writes=%ld)\n", (mem_reads + mem_writes), mem_reads, mem_writes); + fprintf(stream, "PERF: memory stalls=%ld (utilization=%d%%)\n", mem_stalls, mem_utilization); + fprintf(stream, "PERF: memory average latency=%d cycles\n", mem_avg_lat); #endif return ret; diff --git a/driver/opae/vlsim/Makefile b/driver/opae/vlsim/Makefile index 64f7691d..dcd58806 100644 --- a/driver/opae/vlsim/Makefile +++ b/driver/opae/vlsim/Makefile @@ -13,7 +13,7 @@ DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_BANK DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_MSHR DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_TAG DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_DATA -DBG_PRINT_FLAGS += -DDBG_PRINT_DRAM +DBG_PRINT_FLAGS += -DDBG_PRINT_MEM DBG_PRINT_FLAGS += -DDBG_PRINT_OPAE DBG_PRINT_FLAGS += -DDBG_PRINT_AVS DBG_PRINT_FLAGS += -DDBG_PRINT_SCOPE diff --git a/driver/opae/vlsim/opae_sim.cpp b/driver/opae/vlsim/opae_sim.cpp index e821fa52..d62319a5 100644 --- a/driver/opae/vlsim/opae_sim.cpp +++ b/driver/opae/vlsim/opae_sim.cpp @@ -10,10 +10,10 @@ #define RESET_DELAY 4 -#define ENABLE_DRAM_STALLS -#define DRAM_LATENCY 24 -#define DRAM_RQ_SIZE 16 -#define DRAM_STALLS_MODULO 16 +#define ENABLE_MEM_STALLS +#define MEM_LATENCY 24 +#define MEM_RQ_SIZE 16 +#define MEM_STALLS_MODULO 16 uint64_t timestamp = 0; @@ -138,7 +138,7 @@ void opae_sim::flush() { void opae_sim::reset() { host_buffers_.clear(); - dram_reads_.clear(); + mem_reads_.clear(); cci_reads_.clear(); cci_writes_.clear(); vortex_afu_->vcp2af_sRxPort_c0_rspValid = 0; @@ -268,87 +268,87 @@ void opae_sim::sTxPort_bus() { } void opae_sim::avs_bus() { - // update DRAM responses schedule - for (auto& rsp : dram_reads_) { + // update memory responses schedule + for (auto& rsp : mem_reads_) { if (rsp.cycles_left > 0) rsp.cycles_left -= 1; } - // schedule DRAM responses in FIFO order - std::list::iterator dram_rd_it(dram_reads_.end()); - if (!dram_reads_.empty() - && (0 == dram_reads_.begin()->cycles_left)) { - dram_rd_it = dram_reads_.begin(); + // schedule memory responses in FIFO order + std::list::iterator mem_rd_it(mem_reads_.end()); + if (!mem_reads_.empty() + && (0 == mem_reads_.begin()->cycles_left)) { + mem_rd_it = mem_reads_.begin(); } - // send DRAM response + // send memory response vortex_afu_->avs_readdatavalid = 0; - if (dram_rd_it != dram_reads_.end()) { + if (mem_rd_it != mem_reads_.end()) { vortex_afu_->avs_readdatavalid = 1; - memcpy(vortex_afu_->avs_readdata, dram_rd_it->data.data(), DRAM_BLOCK_SIZE); - uint32_t addr = dram_rd_it->addr; - dram_reads_.erase(dram_rd_it); - /*printf("%0ld: [sim] DRAM Rd Rsp: addr=%x, pending={", timestamp, addr * DRAM_BLOCK_SIZE); - for (auto& req : dram_reads_) { + memcpy(vortex_afu_->avs_readdata, mem_rd_it->data.data(), MEM_BLOCK_SIZE); + uint32_t addr = mem_rd_it->addr; + mem_reads_.erase(mem_rd_it); + /*printf("%0ld: [sim] MEM Rd Rsp: addr=%x, pending={", timestamp, addr * MEM_BLOCK_SIZE); + for (auto& req : mem_reads_) { if (req.cycles_left != 0) - printf(" !%0x", req.addr * DRAM_BLOCK_SIZE); + printf(" !%0x", req.addr * MEM_BLOCK_SIZE); else - printf(" %0x", req.addr * DRAM_BLOCK_SIZE); + printf(" %0x", req.addr * MEM_BLOCK_SIZE); } printf("}\n");*/ } - // handle DRAM stalls - bool dram_stalled = false; -#ifdef ENABLE_DRAM_STALLS - if (0 == ((timestamp/2) % DRAM_STALLS_MODULO)) { - dram_stalled = true; + // handle memory stalls + bool mem_stalled = false; +#ifdef ENABLE_MEM_STALLS + if (0 == ((timestamp/2) % MEM_STALLS_MODULO)) { + mem_stalled = true; } else - if (dram_reads_.size() >= DRAM_RQ_SIZE) { - dram_stalled = true; + if (mem_reads_.size() >= MEM_RQ_SIZE) { + mem_stalled = true; } #endif - // process DRAM requests - if (!dram_stalled) { + // process memory requests + if (!mem_stalled) { assert(!vortex_afu_->avs_read || !vortex_afu_->avs_write); if (vortex_afu_->avs_write) { uint64_t byteen = vortex_afu_->avs_byteenable; - unsigned base_addr = vortex_afu_->avs_address * DRAM_BLOCK_SIZE; + unsigned base_addr = vortex_afu_->avs_address * MEM_BLOCK_SIZE; uint8_t* data = (uint8_t*)(vortex_afu_->avs_writedata); - for (int i = 0; i < DRAM_BLOCK_SIZE; i++) { + for (int i = 0; i < MEM_BLOCK_SIZE; i++) { if ((byteen >> i) & 0x1) { ram_[base_addr + i] = data[i]; } } - /*printf("%0ld: [sim] DRAM Wr Req: addr=%x, data=", timestamp, base_addr); - for (int i = 0; i < DRAM_BLOCK_SIZE; i++) { - printf("%0x", data[(DRAM_BLOCK_SIZE-1)-i]); + /*printf("%0ld: [sim] MEM Wr Req: addr=%x, data=", timestamp, base_addr); + for (int i = 0; i < MEM_BLOCK_SIZE; i++) { + printf("%0x", data[(MEM_BLOCK_SIZE-1)-i]); } printf("\n");*/ } if (vortex_afu_->avs_read) { - dram_rd_req_t dram_req; - dram_req.addr = vortex_afu_->avs_address; - ram_.read(vortex_afu_->avs_address * DRAM_BLOCK_SIZE, DRAM_BLOCK_SIZE, dram_req.data.data()); - dram_req.cycles_left = DRAM_LATENCY; - for (auto& rsp : dram_reads_) { - if (dram_req.addr == rsp.addr) { - dram_req.cycles_left = rsp.cycles_left; + mem_rd_req_t mem_req; + mem_req.addr = vortex_afu_->avs_address; + ram_.read(vortex_afu_->avs_address * MEM_BLOCK_SIZE, MEM_BLOCK_SIZE, mem_req.data.data()); + mem_req.cycles_left = MEM_LATENCY; + for (auto& rsp : mem_reads_) { + if (mem_req.addr == rsp.addr) { + mem_req.cycles_left = rsp.cycles_left; break; } } - dram_reads_.emplace_back(dram_req); - /*printf("%0ld: [sim] DRAM Rd Req: addr=%x, pending={", timestamp, dram_req.addr * DRAM_BLOCK_SIZE); - for (auto& req : dram_reads_) { + mem_reads_.emplace_back(mem_req); + /*printf("%0ld: [sim] MEM Rd Req: addr=%x, pending={", timestamp, mem_req.addr * MEM_BLOCK_SIZE); + for (auto& req : mem_reads_) { if (req.cycles_left != 0) - printf(" !%0x", req.addr * DRAM_BLOCK_SIZE); + printf(" !%0x", req.addr * MEM_BLOCK_SIZE); else - printf(" %0x", req.addr * DRAM_BLOCK_SIZE); + printf(" %0x", req.addr * MEM_BLOCK_SIZE); } printf("}\n");*/ } } - vortex_afu_->avs_waitrequest = dram_stalled; + vortex_afu_->avs_waitrequest = mem_stalled; } \ No newline at end of file diff --git a/driver/opae/vlsim/opae_sim.h b/driver/opae/vlsim/opae_sim.h index 15689769..76e5f435 100644 --- a/driver/opae/vlsim/opae_sim.h +++ b/driver/opae/vlsim/opae_sim.h @@ -17,7 +17,7 @@ #include #include -#define DRAM_BLOCK_SIZE (PLATFORM_PARAM_LOCAL_MEMORY_DATA_WIDTH / 8) +#define MEM_BLOCK_SIZE (PLATFORM_PARAM_LOCAL_MEMORY_DATA_WIDTH / 8) #define CACHE_BLOCK_SIZE 64 @@ -43,9 +43,9 @@ private: typedef struct { int cycles_left; - std::array data; + std::array data; uint32_t addr; - } dram_rd_req_t; + } mem_rd_req_t; typedef struct { int cycles_left; @@ -80,7 +80,7 @@ private: std::unordered_map host_buffers_; - std::list dram_reads_; + std::list mem_reads_; std::list cci_reads_; diff --git a/driver/rtlsim/Makefile b/driver/rtlsim/Makefile index 5bfe5553..11ef6760 100644 --- a/driver/rtlsim/Makefile +++ b/driver/rtlsim/Makefile @@ -12,7 +12,7 @@ DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_BANK DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_MSHR DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_TAG DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_DATA -DBG_PRINT_FLAGS += -DDBG_PRINT_DRAM +DBG_PRINT_FLAGS += -DDBG_PRINT_MEM DBG_PRINT_FLAGS += -DDBG_PRINT_OPAE DBG_PRINT_FLAGS += -DDBG_PRINT_AVS DBG_PRINT_FLAGS += -DDBG_PRINT_SCOPE diff --git a/hw/rtl/VX_cluster.v b/hw/rtl/VX_cluster.v index ea9a766b..d9521b8e 100644 --- a/hw/rtl/VX_cluster.v +++ b/hw/rtl/VX_cluster.v @@ -9,20 +9,20 @@ module VX_cluster #( input wire clk, input wire reset, - // DRAM request - output wire dram_req_valid, - output wire dram_req_rw, - output wire [`L2DRAM_BYTEEN_WIDTH-1:0] dram_req_byteen, - output wire [`L2DRAM_ADDR_WIDTH-1:0] dram_req_addr, - output wire [`L2DRAM_LINE_WIDTH-1:0] dram_req_data, - output wire [`L2DRAM_TAG_WIDTH-1:0] dram_req_tag, - input wire dram_req_ready, + // Memory request + output wire mem_req_valid, + output wire mem_req_rw, + output wire [`L2MEM_BYTEEN_WIDTH-1:0] mem_req_byteen, + output wire [`L2MEM_ADDR_WIDTH-1:0] mem_req_addr, + output wire [`L2MEM_LINE_WIDTH-1:0] mem_req_data, + output wire [`L2MEM_TAG_WIDTH-1:0] mem_req_tag, + input wire mem_req_ready, - // DRAM response - input wire dram_rsp_valid, - input wire [`L2DRAM_LINE_WIDTH-1:0] dram_rsp_data, - input wire [`L2DRAM_TAG_WIDTH-1:0] dram_rsp_tag, - output wire dram_rsp_ready, + // Memory response + input wire mem_rsp_valid, + input wire [`L2MEM_LINE_WIDTH-1:0] mem_rsp_data, + input wire [`L2MEM_TAG_WIDTH-1:0] mem_rsp_tag, + output wire mem_rsp_ready, // CSR Request input wire csr_req_valid, @@ -42,31 +42,31 @@ module VX_cluster #( output wire ebreak ); - wire [`NUM_CORES-1:0] per_core_dram_req_valid; - wire [`NUM_CORES-1:0] per_core_dram_req_rw; - wire [`NUM_CORES-1:0][`DDRAM_BYTEEN_WIDTH-1:0] per_core_dram_req_byteen; - wire [`NUM_CORES-1:0][`DDRAM_ADDR_WIDTH-1:0] per_core_dram_req_addr; - wire [`NUM_CORES-1:0][`DDRAM_LINE_WIDTH-1:0] per_core_dram_req_data; - wire [`NUM_CORES-1:0][`XDRAM_TAG_WIDTH-1:0] per_core_dram_req_tag; - wire [`NUM_CORES-1:0] per_core_dram_req_ready; + wire [`NUM_CORES-1:0] per_core_mem_req_valid; + wire [`NUM_CORES-1:0] per_core_mem_req_rw; + wire [`NUM_CORES-1:0][`DMEM_BYTEEN_WIDTH-1:0] per_core_mem_req_byteen; + wire [`NUM_CORES-1:0][`DMEM_ADDR_WIDTH-1:0] per_core_mem_req_addr; + wire [`NUM_CORES-1:0][`DMEM_LINE_WIDTH-1:0] per_core_mem_req_data; + wire [`NUM_CORES-1:0][`XMEM_TAG_WIDTH-1:0] per_core_mem_req_tag; + wire [`NUM_CORES-1:0] per_core_mem_req_ready; - wire [`NUM_CORES-1:0] per_core_dram_rsp_valid; - wire [`NUM_CORES-1:0][`DDRAM_LINE_WIDTH-1:0] per_core_dram_rsp_data; - wire [`NUM_CORES-1:0][`XDRAM_TAG_WIDTH-1:0] per_core_dram_rsp_tag; - wire [`NUM_CORES-1:0] per_core_dram_rsp_ready; + wire [`NUM_CORES-1:0] per_core_mem_rsp_valid; + wire [`NUM_CORES-1:0][`DMEM_LINE_WIDTH-1:0] per_core_mem_rsp_data; + wire [`NUM_CORES-1:0][`XMEM_TAG_WIDTH-1:0] per_core_mem_rsp_tag; + wire [`NUM_CORES-1:0] per_core_mem_rsp_ready; - wire [`NUM_CORES-1:0] per_core_csr_req_valid; - wire [`NUM_CORES-1:0][11:0] per_core_csr_req_addr; - wire [`NUM_CORES-1:0] per_core_csr_req_rw; - wire [`NUM_CORES-1:0][31:0] per_core_csr_req_data; - wire [`NUM_CORES-1:0] per_core_csr_req_ready; + wire [`NUM_CORES-1:0] per_core_csr_req_valid; + wire [`NUM_CORES-1:0][11:0] per_core_csr_req_addr; + wire [`NUM_CORES-1:0] per_core_csr_req_rw; + wire [`NUM_CORES-1:0][31:0] per_core_csr_req_data; + wire [`NUM_CORES-1:0] per_core_csr_req_ready; - wire [`NUM_CORES-1:0] per_core_csr_rsp_valid; - wire [`NUM_CORES-1:0][31:0] per_core_csr_rsp_data; - wire [`NUM_CORES-1:0] per_core_csr_rsp_ready; + wire [`NUM_CORES-1:0] per_core_csr_rsp_valid; + wire [`NUM_CORES-1:0][31:0] per_core_csr_rsp_data; + wire [`NUM_CORES-1:0] per_core_csr_rsp_ready; - wire [`NUM_CORES-1:0] per_core_busy; - wire [`NUM_CORES-1:0] per_core_ebreak; + wire [`NUM_CORES-1:0] per_core_busy; + wire [`NUM_CORES-1:0] per_core_ebreak; for (genvar i = 0; i < `NUM_CORES; i++) begin @@ -87,18 +87,18 @@ module VX_cluster #( .clk (clk), .reset (core_reset), - .dram_req_valid (per_core_dram_req_valid[i]), - .dram_req_rw (per_core_dram_req_rw [i]), - .dram_req_byteen(per_core_dram_req_byteen[i]), - .dram_req_addr (per_core_dram_req_addr [i]), - .dram_req_data (per_core_dram_req_data [i]), - .dram_req_tag (per_core_dram_req_tag [i]), - .dram_req_ready (per_core_dram_req_ready[i]), + .mem_req_valid (per_core_mem_req_valid[i]), + .mem_req_rw (per_core_mem_req_rw [i]), + .mem_req_byteen (per_core_mem_req_byteen[i]), + .mem_req_addr (per_core_mem_req_addr [i]), + .mem_req_data (per_core_mem_req_data [i]), + .mem_req_tag (per_core_mem_req_tag [i]), + .mem_req_ready (per_core_mem_req_ready[i]), - .dram_rsp_valid (per_core_dram_rsp_valid[i]), - .dram_rsp_data (per_core_dram_rsp_data [i]), - .dram_rsp_tag (per_core_dram_rsp_tag [i]), - .dram_rsp_ready (per_core_dram_rsp_ready[i]), + .mem_rsp_valid (per_core_mem_rsp_valid[i]), + .mem_rsp_data (per_core_mem_rsp_data [i]), + .mem_rsp_tag (per_core_mem_rsp_tag [i]), + .mem_rsp_ready (per_core_mem_rsp_ready[i]), .csr_req_valid (per_core_csr_req_valid [i]), .csr_req_rw (per_core_csr_req_rw [i]), @@ -169,12 +169,12 @@ module VX_cluster #( .NUM_REQS (`NUM_CORES), .CREQ_SIZE (`L2CREQ_SIZE), .MSHR_SIZE (`L2MSHR_SIZE), - .DRSQ_SIZE (`L2DRSQ_SIZE), - .DREQ_SIZE (`L2DREQ_SIZE), + .MRSQ_SIZE (`L2MRSQ_SIZE), + .MREQ_SIZE (`L2MREQ_SIZE), .WRITE_ENABLE (1), - .CORE_TAG_WIDTH (`XDRAM_TAG_WIDTH), + .CORE_TAG_WIDTH (`XMEM_TAG_WIDTH), .CORE_TAG_ID_BITS (0), - .DRAM_TAG_WIDTH (`L2DRAM_TAG_WIDTH) + .MEM_TAG_WIDTH (`L2MEM_TAG_WIDTH) ) l2cache ( `SCOPE_BIND_VX_cluster_l2cache @@ -188,78 +188,78 @@ module VX_cluster #( `endif // Core request - .core_req_valid (per_core_dram_req_valid), - .core_req_rw (per_core_dram_req_rw), - .core_req_byteen (per_core_dram_req_byteen), - .core_req_addr (per_core_dram_req_addr), - .core_req_data (per_core_dram_req_data), - .core_req_tag (per_core_dram_req_tag), - .core_req_ready (per_core_dram_req_ready), + .core_req_valid (per_core_mem_req_valid), + .core_req_rw (per_core_mem_req_rw), + .core_req_byteen (per_core_mem_req_byteen), + .core_req_addr (per_core_mem_req_addr), + .core_req_data (per_core_mem_req_data), + .core_req_tag (per_core_mem_req_tag), + .core_req_ready (per_core_mem_req_ready), // Core response - .core_rsp_valid (per_core_dram_rsp_valid), - .core_rsp_data (per_core_dram_rsp_data), - .core_rsp_tag (per_core_dram_rsp_tag), - .core_rsp_ready (per_core_dram_rsp_ready), + .core_rsp_valid (per_core_mem_rsp_valid), + .core_rsp_data (per_core_mem_rsp_data), + .core_rsp_tag (per_core_mem_rsp_tag), + .core_rsp_ready (per_core_mem_rsp_ready), - // DRAM request - .dram_req_valid (dram_req_valid), - .dram_req_rw (dram_req_rw), - .dram_req_byteen (dram_req_byteen), - .dram_req_addr (dram_req_addr), - .dram_req_data (dram_req_data), - .dram_req_tag (dram_req_tag), - .dram_req_ready (dram_req_ready), + // Memory request + .mem_req_valid (mem_req_valid), + .mem_req_rw (mem_req_rw), + .mem_req_byteen (mem_req_byteen), + .mem_req_addr (mem_req_addr), + .mem_req_data (mem_req_data), + .mem_req_tag (mem_req_tag), + .mem_req_ready (mem_req_ready), - // DRAM response - .dram_rsp_valid (dram_rsp_valid), - .dram_rsp_tag (dram_rsp_tag), - .dram_rsp_data (dram_rsp_data), - .dram_rsp_ready (dram_rsp_ready) + // Memory response + .mem_rsp_valid (mem_rsp_valid), + .mem_rsp_tag (mem_rsp_tag), + .mem_rsp_data (mem_rsp_data), + .mem_rsp_ready (mem_rsp_ready) ); end else begin VX_mem_arb #( - .NUM_REQS (`NUM_CORES), - .DATA_WIDTH (`L2DRAM_LINE_WIDTH), - .TAG_IN_WIDTH (`XDRAM_TAG_WIDTH), - .TAG_OUT_WIDTH (`L2DRAM_TAG_WIDTH), - .BUFFERED_REQ (1), - .BUFFERED_RSP (1) - ) dram_arb ( + .NUM_REQS (`NUM_CORES), + .DATA_WIDTH (`L2MEM_LINE_WIDTH), + .TAG_IN_WIDTH (`XMEM_TAG_WIDTH), + .TAG_OUT_WIDTH (`L2MEM_TAG_WIDTH), + .BUFFERED_REQ (1), + .BUFFERED_RSP (1) + ) mem_arb ( .clk (clk), .reset (reset), // Core request - .req_valid_in (per_core_dram_req_valid), - .req_rw_in (per_core_dram_req_rw), - .req_byteen_in (per_core_dram_req_byteen), - .req_addr_in (per_core_dram_req_addr), - .req_data_in (per_core_dram_req_data), - .req_tag_in (per_core_dram_req_tag), - .req_ready_in (per_core_dram_req_ready), + .req_valid_in (per_core_mem_req_valid), + .req_rw_in (per_core_mem_req_rw), + .req_byteen_in (per_core_mem_req_byteen), + .req_addr_in (per_core_mem_req_addr), + .req_data_in (per_core_mem_req_data), + .req_tag_in (per_core_mem_req_tag), + .req_ready_in (per_core_mem_req_ready), - // DRAM request - .req_valid_out (dram_req_valid), - .req_rw_out (dram_req_rw), - .req_byteen_out (dram_req_byteen), - .req_addr_out (dram_req_addr), - .req_data_out (dram_req_data), - .req_tag_out (dram_req_tag), - .req_ready_out (dram_req_ready), + // Memory request + .req_valid_out (mem_req_valid), + .req_rw_out (mem_req_rw), + .req_byteen_out (mem_req_byteen), + .req_addr_out (mem_req_addr), + .req_data_out (mem_req_data), + .req_tag_out (mem_req_tag), + .req_ready_out (mem_req_ready), // Core response - .rsp_valid_out (per_core_dram_rsp_valid), - .rsp_data_out (per_core_dram_rsp_data), - .rsp_tag_out (per_core_dram_rsp_tag), - .rsp_ready_out (per_core_dram_rsp_ready), + .rsp_valid_out (per_core_mem_rsp_valid), + .rsp_data_out (per_core_mem_rsp_data), + .rsp_tag_out (per_core_mem_rsp_tag), + .rsp_ready_out (per_core_mem_rsp_ready), - // DRAM response - .rsp_valid_in (dram_rsp_valid), - .rsp_tag_in (dram_rsp_tag), - .rsp_data_in (dram_rsp_data), - .rsp_ready_in (dram_rsp_ready) + // Memory response + .rsp_valid_in (mem_rsp_valid), + .rsp_tag_in (mem_rsp_tag), + .rsp_data_in (mem_rsp_data), + .rsp_ready_in (mem_rsp_ready) ); end diff --git a/hw/rtl/VX_config.vh b/hw/rtl/VX_config.vh index 40c33428..2b2727fc 100644 --- a/hw/rtl/VX_config.vh +++ b/hw/rtl/VX_config.vh @@ -207,14 +207,14 @@ `define CSR_MPM_SMEM_BANK_ST 12'hB18 // bank conflicts stalls `define CSR_MPM_SMEM_BANK_ST_H 12'hB98 // PERF: memory -`define CSR_MPM_DRAM_READS 12'hB19 // dram reads -`define CSR_MPM_DRAM_READS_H 12'hB99 -`define CSR_MPM_DRAM_WRITES 12'hB1A // dram writes -`define CSR_MPM_DRAM_WRITES_H 12'hB9A -`define CSR_MPM_DRAM_ST 12'hB1B // dram request stalls -`define CSR_MPM_DRAM_ST_H 12'hB9B -`define CSR_MPM_DRAM_LAT 12'hB1C // dram latency (total) -`define CSR_MPM_DRAM_LAT_H 12'hB9C +`define CSR_MPM_MEM_READS 12'hB19 // memory reads +`define CSR_MPM_MEM_READS_H 12'hB99 +`define CSR_MPM_MEM_WRITES 12'hB1A // memory writes +`define CSR_MPM_MEM_WRITES_H 12'hB9A +`define CSR_MPM_MEM_ST 12'hB1B // memory request stalls +`define CSR_MPM_MEM_ST_H 12'hB9B +`define CSR_MPM_MEM_LAT 12'hB1C // memory latency (total) +`define CSR_MPM_MEM_LAT_H 12'hB9C // Machine Information Registers `define CSR_MVENDORID 12'hF11 @@ -264,14 +264,14 @@ `define IMSHR_SIZE `NUM_WARPS `endif -// DRAM Request Queue Size -`ifndef IDREQ_SIZE -`define IDREQ_SIZE 4 +// Memory Request Queue Size +`ifndef IMREQ_SIZE +`define IMREQ_SIZE 4 `endif -// DRAM Response Queue Size -`ifndef IDRSQ_SIZE -`define IDRSQ_SIZE 4 +// Memory Response Queue Size +`ifndef IMRSQ_SIZE +`define IMRSQ_SIZE 4 `endif // Dcache Configurable Knobs ////////////////////////////////////////////////// @@ -301,14 +301,14 @@ `define DMSHR_SIZE `LSUQ_SIZE `endif -// DRAM Request Queue Size -`ifndef DDREQ_SIZE -`define DDREQ_SIZE 4 +// Memory Request Queue Size +`ifndef DMREQ_SIZE +`define DMREQ_SIZE 4 `endif -// DRAM Response Queue Size -`ifndef DDRSQ_SIZE -`define DDRSQ_SIZE `MAX(4, (`DNUM_BANKS * 2)) +// Memory Response Queue Size +`ifndef DMRSQ_SIZE +`define DMRSQ_SIZE `MAX(4, (`DNUM_BANKS * 2)) `endif // SM Configurable Knobs ////////////////////////////////////////////////////// @@ -355,14 +355,14 @@ `define L2MSHR_SIZE 16 `endif -// DRAM Request Queue Size -`ifndef L2DREQ_SIZE -`define L2DREQ_SIZE 4 +// L2 Request Queue Size +`ifndef L2MREQ_SIZE +`define L2MREQ_SIZE 4 `endif -// DRAM Response Queue Size -`ifndef L2DRSQ_SIZE -`define L2DRSQ_SIZE `MAX(4, (`L2NUM_BANKS * 2)) +// L2 Response Queue Size +`ifndef L2MRSQ_SIZE +`define L2MRSQ_SIZE `MAX(4, (`L2NUM_BANKS * 2)) `endif // L3cache Configurable Knobs ///////////////////////////////////////////////// @@ -387,14 +387,14 @@ `define L3MSHR_SIZE 16 `endif -// DRAM Request Queue Size -`ifndef L3DREQ_SIZE -`define L3DREQ_SIZE 4 +// L3 Request Queue Size +`ifndef L3MREQ_SIZE +`define L3MREQ_SIZE 4 `endif -// DRAM Response Queue Size -`ifndef L3DRSQ_SIZE -`define L3DRSQ_SIZE `MAX(4, (`L3NUM_BANKS * 2)) +// L3 Response Queue Size +`ifndef L3MRSQ_SIZE +`define L3MRSQ_SIZE `MAX(4, (`L3NUM_BANKS * 2)) `endif `endif diff --git a/hw/rtl/VX_core.v b/hw/rtl/VX_core.v index b34b6788..3a13ac66 100644 --- a/hw/rtl/VX_core.v +++ b/hw/rtl/VX_core.v @@ -9,20 +9,20 @@ module VX_core #( input wire clk, input wire reset, - // DRAM request - output wire dram_req_valid, - output wire dram_req_rw, - output wire [`DDRAM_BYTEEN_WIDTH-1:0] dram_req_byteen, - output wire [`DDRAM_ADDR_WIDTH-1:0] dram_req_addr, - output wire [`DDRAM_LINE_WIDTH-1:0] dram_req_data, - output wire [`XDRAM_TAG_WIDTH-1:0] dram_req_tag, - input wire dram_req_ready, + // Memory request + output wire mem_req_valid, + output wire mem_req_rw, + output wire [`DMEM_BYTEEN_WIDTH-1:0] mem_req_byteen, + output wire [`DMEM_ADDR_WIDTH-1:0] mem_req_addr, + output wire [`DMEM_LINE_WIDTH-1:0] mem_req_data, + output wire [`XMEM_TAG_WIDTH-1:0] mem_req_tag, + input wire mem_req_ready, - // DRAM reponse - input wire dram_rsp_valid, - input wire [`DDRAM_LINE_WIDTH-1:0] dram_rsp_data, - input wire [`XDRAM_TAG_WIDTH-1:0] dram_rsp_tag, - output wire dram_rsp_ready, + // Memory reponse + input wire mem_rsp_valid, + input wire [`DMEM_LINE_WIDTH-1:0] mem_rsp_data, + input wire [`XMEM_TAG_WIDTH-1:0] mem_rsp_tag, + output wire mem_rsp_ready, // CSR request input wire csr_req_valid, @@ -44,29 +44,29 @@ module VX_core #( VX_perf_memsys_if perf_memsys_if(); `endif - VX_cache_dram_req_if #( - .DRAM_LINE_WIDTH(`DDRAM_LINE_WIDTH), - .DRAM_ADDR_WIDTH(`DDRAM_ADDR_WIDTH), - .DRAM_TAG_WIDTH(`XDRAM_TAG_WIDTH) - ) dram_req_if(); + VX_cache_mem_req_if #( + .MEM_LINE_WIDTH(`DMEM_LINE_WIDTH), + .MEM_ADDR_WIDTH(`DMEM_ADDR_WIDTH), + .MEM_TAG_WIDTH(`XMEM_TAG_WIDTH) + ) mem_req_if(); - VX_cache_dram_rsp_if #( - .DRAM_LINE_WIDTH(`DDRAM_LINE_WIDTH), - .DRAM_TAG_WIDTH(`XDRAM_TAG_WIDTH) - ) dram_rsp_if(); + VX_cache_mem_rsp_if #( + .MEM_LINE_WIDTH(`DMEM_LINE_WIDTH), + .MEM_TAG_WIDTH(`XMEM_TAG_WIDTH) + ) mem_rsp_if(); - assign dram_req_valid = dram_req_if.valid; - assign dram_req_rw = dram_req_if.rw; - assign dram_req_byteen= dram_req_if.byteen; - assign dram_req_addr = dram_req_if.addr; - assign dram_req_data = dram_req_if.data; - assign dram_req_tag = dram_req_if.tag; - assign dram_req_if.ready = dram_req_ready; + assign mem_req_valid = mem_req_if.valid; + assign mem_req_rw = mem_req_if.rw; + assign mem_req_byteen= mem_req_if.byteen; + assign mem_req_addr = mem_req_if.addr; + assign mem_req_data = mem_req_if.data; + assign mem_req_tag = mem_req_if.tag; + assign mem_req_if.ready = mem_req_ready; - assign dram_rsp_if.valid = dram_rsp_valid; - assign dram_rsp_if.data = dram_rsp_data; - assign dram_rsp_if.tag = dram_rsp_tag; - assign dram_rsp_ready = dram_rsp_if.ready; + assign mem_rsp_if.valid = mem_rsp_valid; + assign mem_rsp_if.data = mem_rsp_data; + assign mem_rsp_if.tag = mem_rsp_tag; + assign mem_rsp_ready = mem_rsp_if.ready; //-- @@ -168,9 +168,9 @@ module VX_core #( .icache_core_req_if (icache_core_req_if), .icache_core_rsp_if (icache_core_rsp_if), - // DRAM - .dram_req_if (dram_req_if), - .dram_rsp_if (dram_rsp_if) + // Memory + .mem_req_if (mem_req_if), + .mem_rsp_if (mem_rsp_if) ); endmodule diff --git a/hw/rtl/VX_csr_data.v b/hw/rtl/VX_csr_data.v index 502f124f..0bd5a5fc 100644 --- a/hw/rtl/VX_csr_data.v +++ b/hw/rtl/VX_csr_data.v @@ -160,15 +160,15 @@ module VX_csr_data #( `CSR_MPM_SMEM_WRITES_H : read_data_r = 32'(perf_memsys_if.smem_writes[`PERF_CTR_BITS-1:32]); `CSR_MPM_SMEM_BANK_ST : read_data_r = perf_memsys_if.smem_bank_stalls[31:0]; `CSR_MPM_SMEM_BANK_ST_H : read_data_r = 32'(perf_memsys_if.smem_bank_stalls[`PERF_CTR_BITS-1:32]); - // PERF: DRAM - `CSR_MPM_DRAM_READS : read_data_r = perf_memsys_if.dram_reads[31:0]; - `CSR_MPM_DRAM_READS_H : read_data_r = 32'(perf_memsys_if.dram_reads[`PERF_CTR_BITS-1:32]); - `CSR_MPM_DRAM_WRITES : read_data_r = perf_memsys_if.dram_writes[31:0]; - `CSR_MPM_DRAM_WRITES_H : read_data_r = 32'(perf_memsys_if.dram_writes[`PERF_CTR_BITS-1:32]); - `CSR_MPM_DRAM_ST : read_data_r = perf_memsys_if.dram_stalls[31:0]; - `CSR_MPM_DRAM_ST_H : read_data_r = 32'(perf_memsys_if.dram_stalls[`PERF_CTR_BITS-1:32]); - `CSR_MPM_DRAM_LAT : read_data_r = perf_memsys_if.dram_latency[31:0]; - `CSR_MPM_DRAM_LAT_H : read_data_r = 32'(perf_memsys_if.dram_latency[`PERF_CTR_BITS-1:32]); + // PERF: MEM + `CSR_MPM_MEM_READS : read_data_r = perf_memsys_if.mem_reads[31:0]; + `CSR_MPM_MEM_READS_H : read_data_r = 32'(perf_memsys_if.mem_reads[`PERF_CTR_BITS-1:32]); + `CSR_MPM_MEM_WRITES : read_data_r = perf_memsys_if.mem_writes[31:0]; + `CSR_MPM_MEM_WRITES_H : read_data_r = 32'(perf_memsys_if.mem_writes[`PERF_CTR_BITS-1:32]); + `CSR_MPM_MEM_ST : read_data_r = perf_memsys_if.mem_stalls[31:0]; + `CSR_MPM_MEM_ST_H : read_data_r = 32'(perf_memsys_if.mem_stalls[`PERF_CTR_BITS-1:32]); + `CSR_MPM_MEM_LAT : read_data_r = perf_memsys_if.mem_latency[31:0]; + `CSR_MPM_MEM_LAT_H : read_data_r = 32'(perf_memsys_if.mem_latency[`PERF_CTR_BITS-1:32]); `endif `CSR_SATP : read_data_r = 32'(csr_satp); diff --git a/hw/rtl/VX_define.vh b/hw/rtl/VX_define.vh index 46d6666c..79de9b8f 100644 --- a/hw/rtl/VX_define.vh +++ b/hw/rtl/VX_define.vh @@ -263,11 +263,11 @@ // Core request tag bits `define ICORE_TAG_WIDTH (`DBG_CACHE_REQ_MDATAW + `ICORE_TAG_ID_BITS) -// DRAM request data bits -`define IDRAM_LINE_WIDTH (`ICACHE_LINE_SIZE * 8) +// Memory request data bits +`define IMEM_LINE_WIDTH (`ICACHE_LINE_SIZE * 8) -// DRAM byte enable bits -`define IDRAM_BYTEEN_WIDTH `ICACHE_LINE_SIZE +// Memory byte enable bits +`define IMEM_BYTEEN_WIDTH `ICACHE_LINE_SIZE ////////////////////////// Dcache Configurable Knobs ////////////////////////// @@ -275,7 +275,7 @@ `define DCACHE_ID (32'(`L3_ENABLE) + 32'(`L2_ENABLE) * `NUM_CLUSTERS + CORE_ID * 3 + 1) // Block size in bytes -`define DCACHE_LINE_SIZE (`L2_ENABLE ? `L1_BLOCK_SIZE : `GLOBAL_BLOCK_SIZE) +`define DCACHE_LINE_SIZE (`L2_ENABLE ? `L1_BLOCK_SIZE : `GLOBAL_BLOCK_SIZE) // Word size in bytes `define DWORD_SIZE 4 @@ -286,17 +286,17 @@ // Core request tag bits `define DCORE_TAG_WIDTH (`DBG_CACHE_REQ_MDATAW + `DCORE_TAG_ID_BITS) -// DRAM request data bits -`define DDRAM_LINE_WIDTH (`DCACHE_LINE_SIZE * 8) +// Memory request data bits +`define DMEM_LINE_WIDTH (`DCACHE_LINE_SIZE * 8) -// DRAM request address bits -`define DDRAM_ADDR_WIDTH (32 - `CLOG2(`DCACHE_LINE_SIZE)) +// Memory request address bits +`define DMEM_ADDR_WIDTH (32 - `CLOG2(`DCACHE_LINE_SIZE)) -// DRAM byte enable bits -`define DDRAM_BYTEEN_WIDTH `DCACHE_LINE_SIZE +// Memory byte enable bits +`define DMEM_BYTEEN_WIDTH `DCACHE_LINE_SIZE -// DRAM request tag bits -`define DDRAM_TAG_WIDTH `DDRAM_ADDR_WIDTH +// Memory request tag bits +`define DMEM_TAG_WIDTH `DMEM_ADDR_WIDTH // Core request size `define DNUM_REQUESTS `NUM_THREADS @@ -332,17 +332,17 @@ // Core request tag bits `define L2CORE_TAG_WIDTH (`DCORE_TAG_WIDTH + `CLOG2(`NUM_CORES)) -// DRAM request data bits -`define L2DRAM_LINE_WIDTH (`L2CACHE_LINE_SIZE * 8) +// Memory request data bits +`define L2MEM_LINE_WIDTH (`L2CACHE_LINE_SIZE * 8) -// DRAM request address bits -`define L2DRAM_ADDR_WIDTH (32 - `CLOG2(`L2CACHE_LINE_SIZE)) +// Memory request address bits +`define L2MEM_ADDR_WIDTH (32 - `CLOG2(`L2CACHE_LINE_SIZE)) -// DRAM byte enable bits -`define L2DRAM_BYTEEN_WIDTH `L2CACHE_LINE_SIZE +// Memory byte enable bits +`define L2MEM_BYTEEN_WIDTH `L2CACHE_LINE_SIZE -// DRAM request tag bits -`define L2DRAM_TAG_WIDTH (`L2_ENABLE ? `L2DRAM_ADDR_WIDTH : (`XDRAM_TAG_WIDTH+`CLOG2(`NUM_CORES))) +// Memory request tag bits +`define L2MEM_TAG_WIDTH (`L2_ENABLE ? `L2MEM_ADDR_WIDTH : (`XMEM_TAG_WIDTH+`CLOG2(`NUM_CORES))) ////////////////////////// L3cache Configurable Knobs ///////////////////////// @@ -358,30 +358,30 @@ // Core request tag bits `define L3CORE_TAG_WIDTH (`L2CORE_TAG_WIDTH + `CLOG2(`NUM_CLUSTERS)) -// DRAM request data bits -`define L3DRAM_LINE_WIDTH (`L3CACHE_LINE_SIZE * 8) +// Memory request data bits +`define L3MEM_LINE_WIDTH (`L3CACHE_LINE_SIZE * 8) -// DRAM request address bits -`define L3DRAM_ADDR_WIDTH (32 - `CLOG2(`L3CACHE_LINE_SIZE)) +// Memory request address bits +`define L3MEM_ADDR_WIDTH (32 - `CLOG2(`L3CACHE_LINE_SIZE)) -// DRAM byte enable bits -`define L3DRAM_BYTEEN_WIDTH `L3CACHE_LINE_SIZE +// Memory byte enable bits +`define L3MEM_BYTEEN_WIDTH `L3CACHE_LINE_SIZE -// DRAM request tag bits -`define L3DRAM_TAG_WIDTH (`L3_ENABLE ? `L3DRAM_ADDR_WIDTH : (`L2DRAM_TAG_WIDTH+`CLOG2(`NUM_CLUSTERS))) +// Memory request tag bits +`define L3MEM_TAG_WIDTH (`L3_ENABLE ? `L3MEM_ADDR_WIDTH : (`L2MEM_TAG_WIDTH+`CLOG2(`NUM_CLUSTERS))) /////////////////////////////////////////////////////////////////////////////// -`define VX_DRAM_BYTEEN_WIDTH `L3DRAM_BYTEEN_WIDTH -`define VX_DRAM_ADDR_WIDTH `L3DRAM_ADDR_WIDTH -`define VX_DRAM_LINE_WIDTH `L3DRAM_LINE_WIDTH -`define VX_DRAM_TAG_WIDTH `L3DRAM_TAG_WIDTH +`define VX_MEM_BYTEEN_WIDTH `L3MEM_BYTEEN_WIDTH +`define VX_MEM_ADDR_WIDTH `L3MEM_ADDR_WIDTH +`define VX_MEM_LINE_WIDTH `L3MEM_LINE_WIDTH +`define VX_MEM_TAG_WIDTH `L3MEM_TAG_WIDTH `define VX_CORE_TAG_WIDTH `L3CORE_TAG_WIDTH `define VX_CSR_ID_WIDTH `LOG2UP(`NUM_CLUSTERS * `NUM_CORES) `define TO_FULL_ADDR(x) {x, (32-$bits(x))'(0)} -`define XDRAM_TAG_WIDTH (`DDRAM_TAG_WIDTH+`CLOG2(2)) +`define XMEM_TAG_WIDTH (`DMEM_TAG_WIDTH+`CLOG2(2)) `include "VX_types.vh" diff --git a/hw/rtl/VX_mem_unit.v b/hw/rtl/VX_mem_unit.v index d3d89a62..6b09af6d 100644 --- a/hw/rtl/VX_mem_unit.v +++ b/hw/rtl/VX_mem_unit.v @@ -20,25 +20,25 @@ module VX_mem_unit # ( VX_icache_core_req_if icache_core_req_if, VX_icache_core_rsp_if icache_core_rsp_if, - // DRAM - VX_cache_dram_req_if dram_req_if, - VX_cache_dram_rsp_if dram_rsp_if + // Memory + VX_cache_mem_req_if mem_req_if, + VX_cache_mem_rsp_if mem_rsp_if ); `ifdef PERF_ENABLE VX_perf_cache_if perf_icache_if(), perf_dcache_if(), perf_smem_if(); `endif - VX_cache_dram_req_if #( - .DRAM_LINE_WIDTH (`DDRAM_LINE_WIDTH), - .DRAM_ADDR_WIDTH (`DDRAM_ADDR_WIDTH), - .DRAM_TAG_WIDTH (`DDRAM_TAG_WIDTH) - ) dcache_dram_req_if(), icache_dram_req_if(); + VX_cache_mem_req_if #( + .MEM_LINE_WIDTH (`DMEM_LINE_WIDTH), + .MEM_ADDR_WIDTH (`DMEM_ADDR_WIDTH), + .MEM_TAG_WIDTH (`DMEM_TAG_WIDTH) + ) dcache_mem_req_if(), icache_mem_req_if(); - VX_cache_dram_rsp_if #( - .DRAM_LINE_WIDTH (`DDRAM_LINE_WIDTH), - .DRAM_TAG_WIDTH (`DDRAM_TAG_WIDTH) - ) dcache_dram_rsp_if(), icache_dram_rsp_if(); + VX_cache_mem_rsp_if #( + .MEM_LINE_WIDTH (`DMEM_LINE_WIDTH), + .MEM_TAG_WIDTH (`DMEM_TAG_WIDTH) + ) dcache_mem_rsp_if(), icache_mem_rsp_if(); VX_dcache_core_req_if #( .NUM_REQS (`DNUM_REQUESTS), @@ -96,13 +96,13 @@ module VX_mem_unit # ( .NUM_REQS (1), .CREQ_SIZE (`ICREQ_SIZE), .MSHR_SIZE (`IMSHR_SIZE), - .DRSQ_SIZE (`IDRSQ_SIZE), - .DREQ_SIZE (`IDREQ_SIZE), + .MRSQ_SIZE (`IMRSQ_SIZE), + .MREQ_SIZE (`IMREQ_SIZE), .WRITE_ENABLE (0), .CORE_TAG_WIDTH (`ICORE_TAG_WIDTH), .CORE_TAG_ID_BITS (`ICORE_TAG_ID_BITS), - .DRAM_TAG_WIDTH (`DDRAM_TAG_WIDTH), - .IN_ORDER_DRAM (!(`L2_ENABLE || `L3_ENABLE)) + .MEM_TAG_WIDTH (`DMEM_TAG_WIDTH), + .IN_ORDER_MEM (!(`L2_ENABLE || `L3_ENABLE)) ) icache ( `SCOPE_BIND_VX_mem_unit_icache @@ -130,20 +130,20 @@ module VX_mem_unit # ( .perf_cache_if (perf_icache_if), `endif - // DRAM Req - .dram_req_valid (icache_dram_req_if.valid), - .dram_req_rw (icache_dram_req_if.rw), - .dram_req_byteen (icache_dram_req_if.byteen), - .dram_req_addr (icache_dram_req_if.addr), - .dram_req_data (icache_dram_req_if.data), - .dram_req_tag (icache_dram_req_if.tag), - .dram_req_ready (icache_dram_req_if.ready), + // Memory Request + .mem_req_valid (icache_mem_req_if.valid), + .mem_req_rw (icache_mem_req_if.rw), + .mem_req_byteen (icache_mem_req_if.byteen), + .mem_req_addr (icache_mem_req_if.addr), + .mem_req_data (icache_mem_req_if.data), + .mem_req_tag (icache_mem_req_if.tag), + .mem_req_ready (icache_mem_req_if.ready), - // DRAM response - .dram_rsp_valid (icache_dram_rsp_if.valid), - .dram_rsp_data (icache_dram_rsp_if.data), - .dram_rsp_tag (icache_dram_rsp_if.tag), - .dram_rsp_ready (icache_dram_rsp_if.ready) + // Memory response + .mem_rsp_valid (icache_mem_rsp_if.valid), + .mem_rsp_data (icache_mem_rsp_if.data), + .mem_rsp_tag (icache_mem_rsp_if.tag), + .mem_rsp_ready (icache_mem_rsp_if.ready) ); VX_cache #( @@ -156,13 +156,13 @@ module VX_mem_unit # ( .NUM_REQS (`DNUM_REQUESTS), .CREQ_SIZE (`DCREQ_SIZE), .MSHR_SIZE (`DMSHR_SIZE), - .DRSQ_SIZE (`DDRSQ_SIZE), - .DREQ_SIZE (`DDREQ_SIZE), + .MRSQ_SIZE (`DMRSQ_SIZE), + .MREQ_SIZE (`DMREQ_SIZE), .WRITE_ENABLE (1), .CORE_TAG_WIDTH (`DCORE_TAG_WIDTH), .CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS), - .DRAM_TAG_WIDTH (`DDRAM_TAG_WIDTH), - .IN_ORDER_DRAM (!(`L2_ENABLE || `L3_ENABLE)) + .MEM_TAG_WIDTH (`DMEM_TAG_WIDTH), + .IN_ORDER_MEM (!(`L2_ENABLE || `L3_ENABLE)) ) dcache ( `SCOPE_BIND_VX_mem_unit_dcache @@ -190,20 +190,20 @@ module VX_mem_unit # ( .perf_cache_if (perf_dcache_if), `endif - // DRAM request - .dram_req_valid (dcache_dram_req_if.valid), - .dram_req_rw (dcache_dram_req_if.rw), - .dram_req_byteen (dcache_dram_req_if.byteen), - .dram_req_addr (dcache_dram_req_if.addr), - .dram_req_data (dcache_dram_req_if.data), - .dram_req_tag (dcache_dram_req_if.tag), - .dram_req_ready (dcache_dram_req_if.ready), + // Memory request + .mem_req_valid (dcache_mem_req_if.valid), + .mem_req_rw (dcache_mem_req_if.rw), + .mem_req_byteen (dcache_mem_req_if.byteen), + .mem_req_addr (dcache_mem_req_if.addr), + .mem_req_data (dcache_mem_req_if.data), + .mem_req_tag (dcache_mem_req_if.tag), + .mem_req_ready (dcache_mem_req_if.ready), - // DRAM response - .dram_rsp_valid (dcache_dram_rsp_if.valid), - .dram_rsp_data (dcache_dram_rsp_if.data), - .dram_rsp_tag (dcache_dram_rsp_if.tag), - .dram_rsp_ready (dcache_dram_rsp_if.ready) + // Memory response + .mem_rsp_valid (dcache_mem_rsp_if.valid), + .mem_rsp_data (dcache_mem_rsp_if.data), + .mem_rsp_tag (dcache_mem_rsp_if.tag), + .mem_rsp_ready (dcache_mem_rsp_if.ready) ); if (`SM_ENABLE) begin @@ -254,45 +254,45 @@ module VX_mem_unit # ( VX_mem_arb #( .NUM_REQS (2), - .DATA_WIDTH (`DDRAM_LINE_WIDTH), - .ADDR_WIDTH (`DDRAM_ADDR_WIDTH), - .TAG_IN_WIDTH (`DDRAM_TAG_WIDTH), - .TAG_OUT_WIDTH (`XDRAM_TAG_WIDTH), + .DATA_WIDTH (`DMEM_LINE_WIDTH), + .ADDR_WIDTH (`DMEM_ADDR_WIDTH), + .TAG_IN_WIDTH (`DMEM_TAG_WIDTH), + .TAG_OUT_WIDTH (`XMEM_TAG_WIDTH), .BUFFERED_REQ (1), .BUFFERED_RSP (0) - ) dram_arb ( + ) mem_arb ( .clk (clk), .reset (reset), // Source request - .req_valid_in ({dcache_dram_req_if.valid, icache_dram_req_if.valid}), - .req_rw_in ({dcache_dram_req_if.rw, icache_dram_req_if.rw}), - .req_byteen_in ({dcache_dram_req_if.byteen, icache_dram_req_if.byteen}), - .req_addr_in ({dcache_dram_req_if.addr, icache_dram_req_if.addr}), - .req_data_in ({dcache_dram_req_if.data, icache_dram_req_if.data}), - .req_tag_in ({dcache_dram_req_if.tag, icache_dram_req_if.tag}), - .req_ready_in ({dcache_dram_req_if.ready, icache_dram_req_if.ready}), + .req_valid_in ({dcache_mem_req_if.valid, icache_mem_req_if.valid}), + .req_rw_in ({dcache_mem_req_if.rw, icache_mem_req_if.rw}), + .req_byteen_in ({dcache_mem_req_if.byteen, icache_mem_req_if.byteen}), + .req_addr_in ({dcache_mem_req_if.addr, icache_mem_req_if.addr}), + .req_data_in ({dcache_mem_req_if.data, icache_mem_req_if.data}), + .req_tag_in ({dcache_mem_req_if.tag, icache_mem_req_if.tag}), + .req_ready_in ({dcache_mem_req_if.ready, icache_mem_req_if.ready}), - // DRAM request - .req_valid_out (dram_req_if.valid), - .req_rw_out (dram_req_if.rw), - .req_byteen_out (dram_req_if.byteen), - .req_addr_out (dram_req_if.addr), - .req_data_out (dram_req_if.data), - .req_tag_out (dram_req_if.tag), - .req_ready_out (dram_req_if.ready), + // Memory request + .req_valid_out (mem_req_if.valid), + .req_rw_out (mem_req_if.rw), + .req_byteen_out (mem_req_if.byteen), + .req_addr_out (mem_req_if.addr), + .req_data_out (mem_req_if.data), + .req_tag_out (mem_req_if.tag), + .req_ready_out (mem_req_if.ready), // Source response - .rsp_valid_out ({dcache_dram_rsp_if.valid, icache_dram_rsp_if.valid}), - .rsp_data_out ({dcache_dram_rsp_if.data, icache_dram_rsp_if.data}), - .rsp_tag_out ({dcache_dram_rsp_if.tag, icache_dram_rsp_if.tag}), - .rsp_ready_out ({dcache_dram_rsp_if.ready, icache_dram_rsp_if.ready}), + .rsp_valid_out ({dcache_mem_rsp_if.valid, icache_mem_rsp_if.valid}), + .rsp_data_out ({dcache_mem_rsp_if.data, icache_mem_rsp_if.data}), + .rsp_tag_out ({dcache_mem_rsp_if.tag, icache_mem_rsp_if.tag}), + .rsp_ready_out ({dcache_mem_rsp_if.ready, icache_mem_rsp_if.ready}), - // DRAM response - .rsp_valid_in (dram_rsp_if.valid), - .rsp_tag_in (dram_rsp_if.tag), - .rsp_data_in (dram_rsp_if.data), - .rsp_ready_in (dram_rsp_if.ready) + // Memory response + .rsp_valid_in (mem_rsp_if.valid), + .rsp_tag_in (mem_rsp_if.tag), + .rsp_data_in (mem_rsp_if.data), + .rsp_ready_in (mem_rsp_if.ready) ); `ifdef PERF_ENABLE @@ -321,47 +321,47 @@ end else begin assign perf_memsys_if.smem_bank_stalls = 0; end - reg [`PERF_CTR_BITS-1:0] perf_dram_lat_per_cycle; + reg [`PERF_CTR_BITS-1:0] perf_mem_lat_per_cycle; always @(posedge clk) begin if (reset) begin - perf_dram_lat_per_cycle <= 0; + perf_mem_lat_per_cycle <= 0; end else begin - perf_dram_lat_per_cycle <= perf_dram_lat_per_cycle + - `PERF_CTR_BITS'($signed(2'((dram_req_if.valid && !dram_req_if.rw && dram_req_if.ready) && !(dram_rsp_if.valid && dram_rsp_if.ready)) - - 2'((dram_rsp_if.valid && dram_rsp_if.ready) && !(dram_req_if.valid && !dram_req_if.rw && dram_req_if.ready)))); + perf_mem_lat_per_cycle <= perf_mem_lat_per_cycle + + `PERF_CTR_BITS'($signed(2'((mem_req_if.valid && !mem_req_if.rw && mem_req_if.ready) && !(mem_rsp_if.valid && mem_rsp_if.ready)) - + 2'((mem_rsp_if.valid && mem_rsp_if.ready) && !(mem_req_if.valid && !mem_req_if.rw && mem_req_if.ready)))); end end - reg [`PERF_CTR_BITS-1:0] perf_dram_reads; - reg [`PERF_CTR_BITS-1:0] perf_dram_writes; - reg [`PERF_CTR_BITS-1:0] perf_dram_lat; - reg [`PERF_CTR_BITS-1:0] perf_dram_stalls; + reg [`PERF_CTR_BITS-1:0] perf_mem_reads; + reg [`PERF_CTR_BITS-1:0] perf_mem_writes; + reg [`PERF_CTR_BITS-1:0] perf_mem_lat; + reg [`PERF_CTR_BITS-1:0] perf_mem_stalls; always @(posedge clk) begin if (reset) begin - perf_dram_reads <= 0; - perf_dram_writes <= 0; - perf_dram_lat <= 0; - perf_dram_stalls <= 0; + perf_mem_reads <= 0; + perf_mem_writes <= 0; + perf_mem_lat <= 0; + perf_mem_stalls <= 0; end else begin - if (dram_req_if.valid && dram_req_if.ready && !dram_req_if.rw) begin - perf_dram_reads <= perf_dram_reads + `PERF_CTR_BITS'd1; + if (mem_req_if.valid && mem_req_if.ready && !mem_req_if.rw) begin + perf_mem_reads <= perf_mem_reads + `PERF_CTR_BITS'd1; end - if (dram_req_if.valid && dram_req_if.ready && dram_req_if.rw) begin - perf_dram_writes <= perf_dram_writes + `PERF_CTR_BITS'd1; + if (mem_req_if.valid && mem_req_if.ready && mem_req_if.rw) begin + perf_mem_writes <= perf_mem_writes + `PERF_CTR_BITS'd1; end - if (dram_req_if.valid && !dram_req_if.ready) begin - perf_dram_stalls <= perf_dram_stalls + `PERF_CTR_BITS'd1; + if (mem_req_if.valid && !mem_req_if.ready) begin + perf_mem_stalls <= perf_mem_stalls + `PERF_CTR_BITS'd1; end - perf_dram_lat <= perf_dram_lat + perf_dram_lat_per_cycle; + perf_mem_lat <= perf_mem_lat + perf_mem_lat_per_cycle; end end - assign perf_memsys_if.dram_reads = perf_dram_reads; - assign perf_memsys_if.dram_writes = perf_dram_writes; - assign perf_memsys_if.dram_latency = perf_dram_lat; - assign perf_memsys_if.dram_stalls = perf_dram_stalls; + assign perf_memsys_if.mem_reads = perf_mem_reads; + assign perf_memsys_if.mem_writes = perf_mem_writes; + assign perf_memsys_if.mem_latency = perf_mem_lat; + assign perf_memsys_if.mem_stalls = perf_mem_stalls; `endif endmodule diff --git a/hw/rtl/Vortex.v b/hw/rtl/Vortex.v index 2f2d34e9..15a1def4 100644 --- a/hw/rtl/Vortex.v +++ b/hw/rtl/Vortex.v @@ -7,20 +7,20 @@ module Vortex ( input wire clk, input wire reset, - // DRAM request - output wire dram_req_valid, - output wire dram_req_rw, - output wire [`VX_DRAM_BYTEEN_WIDTH-1:0] dram_req_byteen, - output wire [`VX_DRAM_ADDR_WIDTH-1:0] dram_req_addr, - output wire [`VX_DRAM_LINE_WIDTH-1:0] dram_req_data, - output wire [`VX_DRAM_TAG_WIDTH-1:0] dram_req_tag, - input wire dram_req_ready, + // Memory request + output wire mem_req_valid, + output wire mem_req_rw, + output wire [`VX_MEM_BYTEEN_WIDTH-1:0] mem_req_byteen, + output wire [`VX_MEM_ADDR_WIDTH-1:0] mem_req_addr, + output wire [`VX_MEM_LINE_WIDTH-1:0] mem_req_data, + output wire [`VX_MEM_TAG_WIDTH-1:0] mem_req_tag, + input wire mem_req_ready, - // DRAM response - input wire dram_rsp_valid, - input wire [`VX_DRAM_LINE_WIDTH-1:0] dram_rsp_data, - input wire [`VX_DRAM_TAG_WIDTH-1:0] dram_rsp_tag, - output wire dram_rsp_ready, + // Memory response + input wire mem_rsp_valid, + input wire [`VX_MEM_LINE_WIDTH-1:0] mem_rsp_data, + input wire [`VX_MEM_TAG_WIDTH-1:0] mem_rsp_tag, + output wire mem_rsp_ready, // CSR Request input wire csr_req_valid, @@ -40,18 +40,18 @@ module Vortex ( output wire ebreak ); - wire [`NUM_CLUSTERS-1:0] per_cluster_dram_req_valid; - wire [`NUM_CLUSTERS-1:0] per_cluster_dram_req_rw; - wire [`NUM_CLUSTERS-1:0][`L2DRAM_BYTEEN_WIDTH-1:0] per_cluster_dram_req_byteen; - wire [`NUM_CLUSTERS-1:0][`L2DRAM_ADDR_WIDTH-1:0] per_cluster_dram_req_addr; - wire [`NUM_CLUSTERS-1:0][`L2DRAM_LINE_WIDTH-1:0] per_cluster_dram_req_data; - wire [`NUM_CLUSTERS-1:0][`L2DRAM_TAG_WIDTH-1:0] per_cluster_dram_req_tag; - wire [`NUM_CLUSTERS-1:0] per_cluster_dram_req_ready; + wire [`NUM_CLUSTERS-1:0] per_cluster_mem_req_valid; + wire [`NUM_CLUSTERS-1:0] per_cluster_mem_req_rw; + wire [`NUM_CLUSTERS-1:0][`L2MEM_BYTEEN_WIDTH-1:0] per_cluster_mem_req_byteen; + wire [`NUM_CLUSTERS-1:0][`L2MEM_ADDR_WIDTH-1:0] per_cluster_mem_req_addr; + wire [`NUM_CLUSTERS-1:0][`L2MEM_LINE_WIDTH-1:0] per_cluster_mem_req_data; + wire [`NUM_CLUSTERS-1:0][`L2MEM_TAG_WIDTH-1:0] per_cluster_mem_req_tag; + wire [`NUM_CLUSTERS-1:0] per_cluster_mem_req_ready; - wire [`NUM_CLUSTERS-1:0] per_cluster_dram_rsp_valid; - wire [`NUM_CLUSTERS-1:0][`L2DRAM_LINE_WIDTH-1:0] per_cluster_dram_rsp_data; - wire [`NUM_CLUSTERS-1:0][`L2DRAM_TAG_WIDTH-1:0] per_cluster_dram_rsp_tag; - wire [`NUM_CLUSTERS-1:0] per_cluster_dram_rsp_ready; + wire [`NUM_CLUSTERS-1:0] per_cluster_mem_rsp_valid; + wire [`NUM_CLUSTERS-1:0][`L2MEM_LINE_WIDTH-1:0] per_cluster_mem_rsp_data; + wire [`NUM_CLUSTERS-1:0][`L2MEM_TAG_WIDTH-1:0] per_cluster_mem_rsp_tag; + wire [`NUM_CLUSTERS-1:0] per_cluster_mem_rsp_ready; wire [`NUM_CLUSTERS-1:0] per_cluster_csr_req_valid; wire [`NUM_CLUSTERS-1:0][11:0] per_cluster_csr_req_addr; @@ -88,18 +88,18 @@ module Vortex ( .clk (clk), .reset (cluster_reset), - .dram_req_valid (per_cluster_dram_req_valid [i]), - .dram_req_rw (per_cluster_dram_req_rw [i]), - .dram_req_byteen(per_cluster_dram_req_byteen[i]), - .dram_req_addr (per_cluster_dram_req_addr [i]), - .dram_req_data (per_cluster_dram_req_data [i]), - .dram_req_tag (per_cluster_dram_req_tag [i]), - .dram_req_ready (per_cluster_dram_req_ready [i]), + .mem_req_valid (per_cluster_mem_req_valid [i]), + .mem_req_rw (per_cluster_mem_req_rw [i]), + .mem_req_byteen (per_cluster_mem_req_byteen[i]), + .mem_req_addr (per_cluster_mem_req_addr [i]), + .mem_req_data (per_cluster_mem_req_data [i]), + .mem_req_tag (per_cluster_mem_req_tag [i]), + .mem_req_ready (per_cluster_mem_req_ready [i]), - .dram_rsp_valid (per_cluster_dram_rsp_valid [i]), - .dram_rsp_data (per_cluster_dram_rsp_data [i]), - .dram_rsp_tag (per_cluster_dram_rsp_tag [i]), - .dram_rsp_ready (per_cluster_dram_rsp_ready [i]), + .mem_rsp_valid (per_cluster_mem_rsp_valid [i]), + .mem_rsp_data (per_cluster_mem_rsp_data [i]), + .mem_rsp_tag (per_cluster_mem_rsp_tag [i]), + .mem_rsp_ready (per_cluster_mem_rsp_ready [i]), .csr_req_valid (per_cluster_csr_req_valid [i]), .csr_req_coreid (csr_core_id), @@ -171,12 +171,12 @@ module Vortex ( .NUM_REQS (`NUM_CLUSTERS), .CREQ_SIZE (`L3CREQ_SIZE), .MSHR_SIZE (`L3MSHR_SIZE), - .DRSQ_SIZE (`L3DRSQ_SIZE), - .DREQ_SIZE (`L3DREQ_SIZE), + .MRSQ_SIZE (`L3MRSQ_SIZE), + .MREQ_SIZE (`L3MREQ_SIZE), .WRITE_ENABLE (1), - .CORE_TAG_WIDTH (`L2DRAM_TAG_WIDTH), + .CORE_TAG_WIDTH (`L2MEM_TAG_WIDTH), .CORE_TAG_ID_BITS (0), - .DRAM_TAG_WIDTH (`L3DRAM_TAG_WIDTH) + .MEM_TAG_WIDTH (`L3MEM_TAG_WIDTH) ) l3cache ( `SCOPE_BIND_Vortex_l3cache @@ -190,105 +190,105 @@ module Vortex ( `endif // Core request - .core_req_valid (per_cluster_dram_req_valid), - .core_req_rw (per_cluster_dram_req_rw), - .core_req_byteen (per_cluster_dram_req_byteen), - .core_req_addr (per_cluster_dram_req_addr), - .core_req_data (per_cluster_dram_req_data), - .core_req_tag (per_cluster_dram_req_tag), - .core_req_ready (per_cluster_dram_req_ready), + .core_req_valid (per_cluster_mem_req_valid), + .core_req_rw (per_cluster_mem_req_rw), + .core_req_byteen (per_cluster_mem_req_byteen), + .core_req_addr (per_cluster_mem_req_addr), + .core_req_data (per_cluster_mem_req_data), + .core_req_tag (per_cluster_mem_req_tag), + .core_req_ready (per_cluster_mem_req_ready), // Core response - .core_rsp_valid (per_cluster_dram_rsp_valid), - .core_rsp_data (per_cluster_dram_rsp_data), - .core_rsp_tag (per_cluster_dram_rsp_tag), - .core_rsp_ready (per_cluster_dram_rsp_ready), + .core_rsp_valid (per_cluster_mem_rsp_valid), + .core_rsp_data (per_cluster_mem_rsp_data), + .core_rsp_tag (per_cluster_mem_rsp_tag), + .core_rsp_ready (per_cluster_mem_rsp_ready), - // DRAM request - .dram_req_valid (dram_req_valid), - .dram_req_rw (dram_req_rw), - .dram_req_byteen (dram_req_byteen), - .dram_req_addr (dram_req_addr), - .dram_req_data (dram_req_data), - .dram_req_tag (dram_req_tag), - .dram_req_ready (dram_req_ready), + // Memory request + .mem_req_valid (mem_req_valid), + .mem_req_rw (mem_req_rw), + .mem_req_byteen (mem_req_byteen), + .mem_req_addr (mem_req_addr), + .mem_req_data (mem_req_data), + .mem_req_tag (mem_req_tag), + .mem_req_ready (mem_req_ready), - // DRAM response - .dram_rsp_valid (dram_rsp_valid), - .dram_rsp_data (dram_rsp_data), - .dram_rsp_tag (dram_rsp_tag), - .dram_rsp_ready (dram_rsp_ready) + // Memory response + .mem_rsp_valid (mem_rsp_valid), + .mem_rsp_data (mem_rsp_data), + .mem_rsp_tag (mem_rsp_tag), + .mem_rsp_ready (mem_rsp_ready) ); end else begin VX_mem_arb #( - .NUM_REQS (`NUM_CLUSTERS), - .DATA_WIDTH (`L3DRAM_LINE_WIDTH), - .TAG_IN_WIDTH (`L2DRAM_TAG_WIDTH), - .TAG_OUT_WIDTH (`L3DRAM_TAG_WIDTH), - .BUFFERED_REQ (1), - .BUFFERED_RSP (1) - ) dram_arb ( + .NUM_REQS (`NUM_CLUSTERS), + .DATA_WIDTH (`L3MEM_LINE_WIDTH), + .TAG_IN_WIDTH (`L2MEM_TAG_WIDTH), + .TAG_OUT_WIDTH (`L3MEM_TAG_WIDTH), + .BUFFERED_REQ (1), + .BUFFERED_RSP (1) + ) mem_arb ( .clk (clk), .reset (reset), // Core request - .req_valid_in (per_cluster_dram_req_valid), - .req_rw_in (per_cluster_dram_req_rw), - .req_byteen_in (per_cluster_dram_req_byteen), - .req_addr_in (per_cluster_dram_req_addr), - .req_data_in (per_cluster_dram_req_data), - .req_tag_in (per_cluster_dram_req_tag), - .req_ready_in (per_cluster_dram_req_ready), + .req_valid_in (per_cluster_mem_req_valid), + .req_rw_in (per_cluster_mem_req_rw), + .req_byteen_in (per_cluster_mem_req_byteen), + .req_addr_in (per_cluster_mem_req_addr), + .req_data_in (per_cluster_mem_req_data), + .req_tag_in (per_cluster_mem_req_tag), + .req_ready_in (per_cluster_mem_req_ready), - // DRAM request - .req_valid_out (dram_req_valid), - .req_rw_out (dram_req_rw), - .req_byteen_out (dram_req_byteen), - .req_addr_out (dram_req_addr), - .req_data_out (dram_req_data), - .req_tag_out (dram_req_tag), - .req_ready_out (dram_req_ready), + // Memory request + .req_valid_out (mem_req_valid), + .req_rw_out (mem_req_rw), + .req_byteen_out (mem_req_byteen), + .req_addr_out (mem_req_addr), + .req_data_out (mem_req_data), + .req_tag_out (mem_req_tag), + .req_ready_out (mem_req_ready), // Core response - .rsp_valid_out (per_cluster_dram_rsp_valid), - .rsp_data_out (per_cluster_dram_rsp_data), - .rsp_tag_out (per_cluster_dram_rsp_tag), - .rsp_ready_out (per_cluster_dram_rsp_ready), + .rsp_valid_out (per_cluster_mem_rsp_valid), + .rsp_data_out (per_cluster_mem_rsp_data), + .rsp_tag_out (per_cluster_mem_rsp_tag), + .rsp_ready_out (per_cluster_mem_rsp_ready), - // DRAM response - .rsp_valid_in (dram_rsp_valid), - .rsp_tag_in (dram_rsp_tag), - .rsp_data_in (dram_rsp_data), - .rsp_ready_in (dram_rsp_ready) + // Memory response + .rsp_valid_in (mem_rsp_valid), + .rsp_tag_in (mem_rsp_tag), + .rsp_data_in (mem_rsp_data), + .rsp_ready_in (mem_rsp_ready) ); end `SCOPE_ASSIGN (reset, reset); - `SCOPE_ASSIGN (dram_req_fire, dram_req_valid && dram_req_ready); - `SCOPE_ASSIGN (dram_req_addr, `TO_FULL_ADDR(dram_req_addr)); - `SCOPE_ASSIGN (dram_req_rw, dram_req_rw); - `SCOPE_ASSIGN (dram_req_byteen, dram_req_byteen); - `SCOPE_ASSIGN (dram_req_data, dram_req_data); - `SCOPE_ASSIGN (dram_req_tag, dram_req_tag); - `SCOPE_ASSIGN (dram_rsp_fire, dram_rsp_valid && dram_rsp_ready); - `SCOPE_ASSIGN (dram_rsp_data, dram_rsp_data); - `SCOPE_ASSIGN (dram_rsp_tag, dram_rsp_tag); + `SCOPE_ASSIGN (mem_req_fire, mem_req_valid && mem_req_ready); + `SCOPE_ASSIGN (mem_req_addr, `TO_FULL_ADDR(mem_req_addr)); + `SCOPE_ASSIGN (mem_req_rw, mem_req_rw); + `SCOPE_ASSIGN (mem_req_byteen, mem_req_byteen); + `SCOPE_ASSIGN (mem_req_data, mem_req_data); + `SCOPE_ASSIGN (mem_req_tag, mem_req_tag); + `SCOPE_ASSIGN (mem_rsp_fire, mem_rsp_valid && mem_rsp_ready); + `SCOPE_ASSIGN (mem_rsp_data, mem_rsp_data); + `SCOPE_ASSIGN (mem_rsp_tag, mem_rsp_tag); `SCOPE_ASSIGN (busy, busy); -`ifdef DBG_PRINT_DRAM +`ifdef DBG_PRINT_MEM always @(posedge clk) begin - if (dram_req_valid && dram_req_ready) begin - if (dram_req_rw) - $display("%t: DRAM Wr Req: addr=%0h, tag=%0h, byteen=%0h data=%0h", $time, `TO_FULL_ADDR(dram_req_addr), dram_req_tag, dram_req_byteen, dram_req_data); + if (mem_req_valid && mem_req_ready) begin + if (mem_req_rw) + $display("%t: MEM Wr Req: addr=%0h, tag=%0h, byteen=%0h data=%0h", $time, `TO_FULL_ADDR(mem_req_addr), mem_req_tag, mem_req_byteen, mem_req_data); else - $display("%t: DRAM Rd Req: addr=%0h, tag=%0h, byteen=%0h", $time, `TO_FULL_ADDR(dram_req_addr), dram_req_tag, dram_req_byteen); + $display("%t: MEM Rd Req: addr=%0h, tag=%0h, byteen=%0h", $time, `TO_FULL_ADDR(mem_req_addr), mem_req_tag, mem_req_byteen); end - if (dram_rsp_valid && dram_rsp_ready) begin - $display("%t: DRAM Rsp: tag=%0h, data=%0h", $time, dram_rsp_tag, dram_rsp_data); + if (mem_rsp_valid && mem_rsp_ready) begin + $display("%t: MEM Rsp: tag=%0h, data=%0h", $time, mem_rsp_tag, mem_rsp_data); end end `endif diff --git a/hw/rtl/afu/VX_avs_wrapper.v b/hw/rtl/afu/VX_avs_wrapper.v index 36f0a986..361bd2fa 100644 --- a/hw/rtl/afu/VX_avs_wrapper.v +++ b/hw/rtl/afu/VX_avs_wrapper.v @@ -15,20 +15,20 @@ module VX_avs_wrapper #( input wire clk, input wire reset, - // DRAM request - input wire dram_req_valid, - input wire dram_req_rw, - input wire [AVS_BYTEENW-1:0] dram_req_byteen, - input wire [AVS_ADDRW-1:0] dram_req_addr, - input wire [AVS_DATAW-1:0] dram_req_data, - input wire [REQ_TAGW-1:0] dram_req_tag, - output wire dram_req_ready, + // Memory request + input wire mem_req_valid, + input wire mem_req_rw, + input wire [AVS_BYTEENW-1:0] mem_req_byteen, + input wire [AVS_ADDRW-1:0] mem_req_addr, + input wire [AVS_DATAW-1:0] mem_req_data, + input wire [REQ_TAGW-1:0] mem_req_tag, + output wire mem_req_ready, - // DRAM response - output wire dram_rsp_valid, - output wire [AVS_DATAW-1:0] dram_rsp_data, - output wire [REQ_TAGW-1:0] dram_rsp_tag, - input wire dram_rsp_ready, + // Memory response + output wire mem_rsp_valid, + output wire [AVS_DATAW-1:0] mem_rsp_data, + output wire [REQ_TAGW-1:0] mem_rsp_tag, + input wire mem_rsp_ready, // AVS bus output wire [AVS_DATAW-1:0] avs_writedata, @@ -45,8 +45,8 @@ module VX_avs_wrapper #( reg [AVS_BANKS_BITS-1:0] avs_bankselect_r; reg [AVS_BURSTW-1:0] avs_burstcount_r; - wire avs_reqq_push = dram_req_valid && dram_req_ready && !dram_req_rw; - wire avs_reqq_pop = dram_rsp_valid && dram_rsp_ready; + wire avs_reqq_push = mem_req_valid && mem_req_ready && !mem_req_rw; + wire avs_reqq_pop = mem_rsp_valid && mem_rsp_ready; wire avs_rspq_push = avs_readdatavalid; wire avs_rspq_pop = avs_reqq_pop; @@ -80,8 +80,8 @@ module VX_avs_wrapper #( .reset (reset), .push (avs_reqq_push), .pop (avs_reqq_pop), - .data_in (dram_req_tag), - .data_out (dram_rsp_tag), + .data_in (mem_req_tag), + .data_out (mem_rsp_tag), `UNUSED_PIN (empty), `UNUSED_PIN (full), `UNUSED_PIN (alm_empty), @@ -98,7 +98,7 @@ module VX_avs_wrapper #( .push (avs_rspq_push), .pop (avs_rspq_pop), .data_in (avs_readdata), - .data_out (dram_rsp_data), + .data_out (mem_rsp_data), .empty (avs_rspq_empty), `UNUSED_PIN (full), `UNUSED_PIN (alm_empty), @@ -106,28 +106,28 @@ module VX_avs_wrapper #( `UNUSED_PIN (size) ); - assign avs_read = dram_req_valid && !dram_req_rw && !rsp_queue_going_full; - assign avs_write = dram_req_valid && dram_req_rw && !rsp_queue_going_full; - assign avs_address = dram_req_addr; - assign avs_byteenable = dram_req_byteen; - assign avs_writedata = dram_req_data; + assign avs_read = mem_req_valid && !mem_req_rw && !rsp_queue_going_full; + assign avs_write = mem_req_valid && mem_req_rw && !rsp_queue_going_full; + assign avs_address = mem_req_addr; + assign avs_byteenable = mem_req_byteen; + assign avs_writedata = mem_req_data; assign avs_burstcount = avs_burstcount_r; assign avs_bankselect = avs_bankselect_r; - assign dram_req_ready = !avs_waitrequest && !rsp_queue_going_full; + assign mem_req_ready = !avs_waitrequest && !rsp_queue_going_full; - assign dram_rsp_valid = !avs_rspq_empty; + assign mem_rsp_valid = !avs_rspq_empty; `ifdef DBG_PRINT_AVS always @(posedge clk) begin - if (dram_req_valid && dram_req_ready) begin - if (dram_req_rw) - $display("%t: AVS Wr Req: addr=%0h, byteen=%0h, tag=%0h, data=%0h", $time, `TO_FULL_ADDR(dram_req_addr), dram_req_byteen, dram_req_tag, dram_req_data); + if (mem_req_valid && mem_req_ready) begin + if (mem_req_rw) + $display("%t: AVS Wr Req: addr=%0h, byteen=%0h, tag=%0h, data=%0h", $time, `TO_FULL_ADDR(mem_req_addr), mem_req_byteen, mem_req_tag, mem_req_data); else - $display("%t: AVS Rd Req: addr=%0h, byteen=%0h, tag=%0h, pending=%0d", $time, `TO_FULL_ADDR(dram_req_addr), dram_req_byteen, dram_req_tag, rsp_queue_size); + $display("%t: AVS Rd Req: addr=%0h, byteen=%0h, tag=%0h, pending=%0d", $time, `TO_FULL_ADDR(mem_req_addr), mem_req_byteen, mem_req_tag, rsp_queue_size); end - if (dram_rsp_valid && dram_rsp_ready) begin - $display("%t: AVS Rd Rsp: tag=%0h, data=%0h, pending=%0d", $time, dram_rsp_tag, dram_rsp_data, rsp_queue_size); + if (mem_rsp_valid && mem_rsp_ready) begin + $display("%t: AVS Rd Rsp: tag=%0h, data=%0h, pending=%0d", $time, mem_rsp_tag, mem_rsp_data, rsp_queue_size); end end `endif diff --git a/hw/rtl/afu/VX_cci_to_mem.v b/hw/rtl/afu/VX_cci_to_mem.v index 71eb19a7..fe003b47 100644 --- a/hw/rtl/afu/VX_cci_to_mem.v +++ b/hw/rtl/afu/VX_cci_to_mem.v @@ -11,30 +11,30 @@ module VX_cci_to_mem #( input wire clk, input wire reset, - input wire dram_req_valid_in, - input wire [CCI_ADDRW-1:0] dram_req_addr_in, - input wire dram_req_rw_in, - input wire [CCI_DATAW-1:0] dram_req_data_in, - input wire [TAG_WIDTH-1:0] dram_req_tag_in, - output wire dram_req_ready_in, + input wire mem_req_valid_in, + input wire [CCI_ADDRW-1:0] mem_req_addr_in, + input wire mem_req_rw_in, + input wire [CCI_DATAW-1:0] mem_req_data_in, + input wire [TAG_WIDTH-1:0] mem_req_tag_in, + output wire mem_req_ready_in, - output wire dram_req_valid_out, - output wire [AVS_ADDRW-1:0] dram_req_addr_out, - output wire dram_req_rw_out, - output wire [AVS_BYTEENW-1:0] dram_req_byteen_out, - output wire [AVS_DATAW-1:0] dram_req_data_out, - output wire [TAG_WIDTH-1:0] dram_req_tag_out, - input wire dram_req_ready_out, + output wire mem_req_valid_out, + output wire [AVS_ADDRW-1:0] mem_req_addr_out, + output wire mem_req_rw_out, + output wire [AVS_BYTEENW-1:0] mem_req_byteen_out, + output wire [AVS_DATAW-1:0] mem_req_data_out, + output wire [TAG_WIDTH-1:0] mem_req_tag_out, + input wire mem_req_ready_out, - input wire dram_rsp_valid_in, - input wire [AVS_DATAW-1:0] dram_rsp_data_in, - input wire [TAG_WIDTH-1:0] dram_rsp_tag_in, - output wire dram_rsp_ready_in, + input wire mem_rsp_valid_in, + input wire [AVS_DATAW-1:0] mem_rsp_data_in, + input wire [TAG_WIDTH-1:0] mem_rsp_tag_in, + output wire mem_rsp_ready_in, - output wire dram_rsp_valid_out, - output wire [CCI_DATAW-1:0] dram_rsp_data_out, - output wire [TAG_WIDTH-1:0] dram_rsp_tag_out, - input wire dram_rsp_ready_out + output wire mem_rsp_valid_out, + output wire [CCI_DATAW-1:0] mem_rsp_data_out, + output wire [TAG_WIDTH-1:0] mem_rsp_tag_out, + input wire mem_rsp_ready_out ); localparam N = AVS_ADDRW - CCI_ADDRW; @@ -44,35 +44,35 @@ module VX_cci_to_mem #( `UNUSED_VAR (clk) `UNUSED_VAR (reset) - assign dram_req_valid_out = dram_req_valid_in; - assign dram_req_addr_out = dram_req_addr_in; - assign dram_req_rw_out = dram_req_rw_in; - assign dram_req_byteen_out = {AVS_BYTEENW{1'b1}}; - assign dram_req_data_out = dram_req_data_in; - assign dram_req_tag_out = dram_req_tag_in; - assign dram_req_ready_in = dram_req_ready_out; + assign mem_req_valid_out = mem_req_valid_in; + assign mem_req_addr_out = mem_req_addr_in; + assign mem_req_rw_out = mem_req_rw_in; + assign mem_req_byteen_out = {AVS_BYTEENW{1'b1}}; + assign mem_req_data_out = mem_req_data_in; + assign mem_req_tag_out = mem_req_tag_in; + assign mem_req_ready_in = mem_req_ready_out; - assign dram_rsp_valid_out = dram_rsp_valid_in; - assign dram_rsp_data_out = dram_rsp_data_in; - assign dram_rsp_tag_out = dram_rsp_tag_in; - assign dram_rsp_ready_in = dram_rsp_ready_out; + assign mem_rsp_valid_out = mem_rsp_valid_in; + assign mem_rsp_data_out = mem_rsp_data_in; + assign mem_rsp_tag_out = mem_rsp_tag_in; + assign mem_rsp_ready_in = mem_rsp_ready_out; end else begin reg [N-1:0] req_ctr, rsp_ctr; - wire [(2**N)-1:0][AVS_DATAW-1:0] dram_req_data_w_in; + wire [(2**N)-1:0][AVS_DATAW-1:0] mem_req_data_w_in; - reg [(2**N)-1:0][AVS_DATAW-1:0] dram_rsp_data_r_out, dram_rsp_data_n_out; + reg [(2**N)-1:0][AVS_DATAW-1:0] mem_rsp_data_r_out, mem_rsp_data_n_out; - wire dram_req_fire_out = dram_req_valid_out && dram_req_ready_out; - wire dram_rsp_fire_in = dram_rsp_valid_in && dram_rsp_ready_in; + wire mem_req_fire_out = mem_req_valid_out && mem_req_ready_out; + wire mem_rsp_fire_in = mem_rsp_valid_in && mem_rsp_ready_in; - assign dram_req_data_w_in = dram_req_data_in; + assign mem_req_data_w_in = mem_req_data_in; always @(*) begin - dram_rsp_data_n_out = dram_rsp_data_r_out; - dram_rsp_data_n_out[rsp_ctr] = dram_rsp_data_in; + mem_rsp_data_n_out = mem_rsp_data_r_out; + mem_rsp_data_n_out[rsp_ctr] = mem_rsp_data_in; end always @(posedge clk) begin @@ -80,28 +80,28 @@ module VX_cci_to_mem #( req_ctr <= 0; rsp_ctr <= 0; end else begin - if (dram_req_fire_out) begin + if (mem_req_fire_out) begin req_ctr <= req_ctr + 1; end - if (dram_rsp_fire_in) begin + if (mem_rsp_fire_in) begin rsp_ctr <= rsp_ctr + 1; - dram_rsp_data_r_out <= dram_rsp_data_n_out; + mem_rsp_data_r_out <= mem_rsp_data_n_out; end end end - assign dram_req_valid_out = dram_req_valid_in; - assign dram_req_addr_out = {dram_req_addr_in, req_ctr}; - assign dram_req_rw_out = dram_req_rw_in; - assign dram_req_byteen_out = {AVS_BYTEENW{1'b1}}; - assign dram_req_data_out = dram_req_data_w_in[req_ctr]; - assign dram_req_tag_out = dram_req_tag_in; - assign dram_req_ready_in = dram_req_ready_out && (req_ctr == (2**N-1)); + assign mem_req_valid_out = mem_req_valid_in; + assign mem_req_addr_out = {mem_req_addr_in, req_ctr}; + assign mem_req_rw_out = mem_req_rw_in; + assign mem_req_byteen_out = {AVS_BYTEENW{1'b1}}; + assign mem_req_data_out = mem_req_data_w_in[req_ctr]; + assign mem_req_tag_out = mem_req_tag_in; + assign mem_req_ready_in = mem_req_ready_out && (req_ctr == (2**N-1)); - assign dram_rsp_valid_out = dram_rsp_valid_in && (rsp_ctr == (2**N-1)); - assign dram_rsp_data_out = dram_rsp_data_n_out; - assign dram_rsp_tag_out = dram_rsp_tag_in; - assign dram_rsp_ready_in = dram_rsp_ready_out; + assign mem_rsp_valid_out = mem_rsp_valid_in && (rsp_ctr == (2**N-1)); + assign mem_rsp_data_out = mem_rsp_data_n_out; + assign mem_rsp_tag_out = mem_rsp_tag_in; + assign mem_rsp_ready_in = mem_rsp_ready_out; end endmodule \ No newline at end of file diff --git a/hw/rtl/afu/vortex_afu.sv b/hw/rtl/afu/vortex_afu.sv index 0f99530b..61c4cc8d 100644 --- a/hw/rtl/afu/vortex_afu.sv +++ b/hw/rtl/afu/vortex_afu.sv @@ -40,19 +40,19 @@ module vortex_afu #( localparam RESET_DELAY = 3; -localparam DRAM_LINE_WIDTH = $bits(t_local_mem_data); -localparam DRAM_ADDR_WIDTH = $bits(t_local_mem_addr); -localparam DRAM_BURST_CTRW = $bits(t_local_mem_burst_cnt); -localparam DRAM_LINE_LW = $clog2(DRAM_LINE_WIDTH); +localparam MEM_LINE_WIDTH = $bits(t_local_mem_data); +localparam MEM_ADDR_WIDTH = $bits(t_local_mem_addr); +localparam MEM_BURST_CTRW = $bits(t_local_mem_burst_cnt); +localparam MEM_LINE_LW = $clog2(MEM_LINE_WIDTH); localparam CCI_LINE_WIDTH = $bits(t_ccip_clData); localparam CCI_ADDR_WIDTH = 32 - $clog2(CCI_LINE_WIDTH / 8); -localparam VX_DRAM_LINE_LW = $clog2(`VX_DRAM_LINE_WIDTH); -localparam VX_DRAM_LINE_IDX = (DRAM_LINE_LW - VX_DRAM_LINE_LW); +localparam VX_MEM_LINE_LW = $clog2(`VX_MEM_LINE_WIDTH); +localparam VX_MEM_LINE_IDX = (MEM_LINE_LW - VX_MEM_LINE_LW); localparam AVS_RD_QUEUE_SIZE = 16; -localparam AVS_REQ_TAGW = `VX_DRAM_TAG_WIDTH + VX_DRAM_LINE_IDX; +localparam AVS_REQ_TAGW = `VX_MEM_TAG_WIDTH + VX_MEM_LINE_IDX; localparam CCI_RD_WINDOW_SIZE = 8; localparam CCI_RD_QUEUE_SIZE = 2 * CCI_RD_WINDOW_SIZE; @@ -104,18 +104,18 @@ reg [STATE_WIDTH-1:0] state; // Vortex ports /////////////////////////////////////////////////////////////// -wire vx_dram_req_valid; -wire vx_dram_req_rw; -wire [`VX_DRAM_BYTEEN_WIDTH-1:0] vx_dram_req_byteen; -wire [`VX_DRAM_ADDR_WIDTH-1:0] vx_dram_req_addr; -wire [`VX_DRAM_LINE_WIDTH-1:0] vx_dram_req_data; -wire [`VX_DRAM_TAG_WIDTH-1:0] vx_dram_req_tag; -wire vx_dram_req_ready; +wire vx_mem_req_valid; +wire vx_mem_req_rw; +wire [`VX_MEM_BYTEEN_WIDTH-1:0] vx_mem_req_byteen; +wire [`VX_MEM_ADDR_WIDTH-1:0] vx_mem_req_addr; +wire [`VX_MEM_LINE_WIDTH-1:0] vx_mem_req_data; +wire [`VX_MEM_TAG_WIDTH-1:0] vx_mem_req_tag; +wire vx_mem_req_ready; -wire vx_dram_rsp_valid; -wire [`VX_DRAM_LINE_WIDTH-1:0] vx_dram_rsp_data; -wire [`VX_DRAM_TAG_WIDTH-1:0] vx_dram_rsp_tag; -wire vx_dram_rsp_ready; +wire vx_mem_rsp_valid; +wire [`VX_MEM_LINE_WIDTH-1:0] vx_mem_rsp_data; +wire [`VX_MEM_TAG_WIDTH-1:0] vx_mem_rsp_tag; +wire vx_mem_rsp_ready; wire vx_csr_io_req_valid; wire [`VX_CSR_ID_WIDTH-1:0] vx_csr_io_req_coreid; @@ -131,7 +131,7 @@ wire vx_csr_io_rsp_ready; wire vx_busy; reg vx_reset; -reg vx_dram_en; +reg vx_mem_en; // CMD variables ////////////////////////////////////////////////////////////// @@ -343,7 +343,7 @@ always @(posedge clk) begin if (reset) begin state <= STATE_IDLE; vx_reset <= 0; - vx_dram_en <= 0; + vx_mem_en <= 0; end else begin case (state) STATE_IDLE: begin @@ -407,14 +407,14 @@ always @(posedge clk) begin // vortex reset cycles if (vx_reset_ctr == $bits(vx_reset_ctr)'(RESET_DELAY)) begin vx_reset <= 0; - vx_dram_en <= 1; + vx_mem_en <= 1; state <= STATE_RUN; end end STATE_RUN: begin if (cmd_run_done) begin - vx_dram_en <= 0; + vx_mem_en <= 0; state <= STATE_IDLE; `ifdef DBG_PRINT_OPAE $display("%t: STATE IDLE", $time); @@ -450,164 +450,164 @@ end // AVS Controller ///////////////////////////////////////////////////////////// -wire dram_req_valid; -wire dram_req_rw; -t_local_mem_byte_mask dram_req_byteen; -t_local_mem_addr dram_req_addr; -t_local_mem_data dram_req_data; -wire [AVS_REQ_TAGW:0] dram_req_tag; -wire dram_req_ready; +wire mem_req_valid; +wire mem_req_rw; +t_local_mem_byte_mask mem_req_byteen; +t_local_mem_addr mem_req_addr; +t_local_mem_data mem_req_data; +wire [AVS_REQ_TAGW:0] mem_req_tag; +wire mem_req_ready; -wire dram_rsp_valid; -t_local_mem_data dram_rsp_data; -wire [AVS_REQ_TAGW:0] dram_rsp_tag; -wire dram_rsp_ready; +wire mem_rsp_valid; +t_local_mem_data mem_rsp_data; +wire [AVS_REQ_TAGW:0] mem_rsp_tag; +wire mem_rsp_ready; -wire cci_dram_req_tmp_valid; -wire cci_dram_req_tmp_rw; -t_local_mem_byte_mask cci_dram_req_tmp_byteen; -t_local_mem_addr cci_dram_req_tmp_addr; -t_local_mem_data cci_dram_req_tmp_data; -wire [AVS_REQ_TAGW-1:0] cci_dram_req_tmp_tag; -wire cci_dram_req_tmp_ready; +wire cci_mem_req_tmp_valid; +wire cci_mem_req_tmp_rw; +t_local_mem_byte_mask cci_mem_req_tmp_byteen; +t_local_mem_addr cci_mem_req_tmp_addr; +t_local_mem_data cci_mem_req_tmp_data; +wire [AVS_REQ_TAGW-1:0] cci_mem_req_tmp_tag; +wire cci_mem_req_tmp_ready; -wire cci_dram_rsp_tmp_valid; -t_local_mem_data cci_dram_rsp_tmp_data; -wire [AVS_REQ_TAGW-1:0] cci_dram_rsp_tmp_tag; -wire cci_dram_rsp_tmp_ready; +wire cci_mem_rsp_tmp_valid; +t_local_mem_data cci_mem_rsp_tmp_data; +wire [AVS_REQ_TAGW-1:0] cci_mem_rsp_tmp_tag; +wire cci_mem_rsp_tmp_ready; -wire vx_dram_req_valid_qual; -t_local_mem_addr vx_dram_req_addr_qual; -t_local_mem_byte_mask vx_dram_req_byteen_qual; -t_local_mem_data vx_dram_req_data_qual; -wire [AVS_REQ_TAGW-1:0] vx_dram_req_tag_qual; +wire vx_mem_req_valid_qual; +t_local_mem_addr vx_mem_req_addr_qual; +t_local_mem_byte_mask vx_mem_req_byteen_qual; +t_local_mem_data vx_mem_req_data_qual; +wire [AVS_REQ_TAGW-1:0] vx_mem_req_tag_qual; -wire [(1 << VX_DRAM_LINE_IDX)-1:0][`VX_DRAM_LINE_WIDTH-1:0] vx_dram_rsp_data_unqual; -wire [AVS_REQ_TAGW-1:0] vx_dram_rsp_tag_unqual; +wire [(1 << VX_MEM_LINE_IDX)-1:0][`VX_MEM_LINE_WIDTH-1:0] vx_mem_rsp_data_unqual; +wire [AVS_REQ_TAGW-1:0] vx_mem_rsp_tag_unqual; -wire cci_dram_rd_req_valid; -wire cci_dram_wr_req_valid; -wire [CCI_ADDR_WIDTH-1:0] cci_dram_rd_req_addr; -wire [CCI_ADDR_WIDTH-1:0] cci_dram_wr_req_addr; +wire cci_mem_rd_req_valid; +wire cci_mem_wr_req_valid; +wire [CCI_ADDR_WIDTH-1:0] cci_mem_rd_req_addr; +wire [CCI_ADDR_WIDTH-1:0] cci_mem_wr_req_addr; wire [CCI_RD_RQ_DATAW-1:0] cci_rdq_dout; -wire cci_dram_req_ready; +wire cci_mem_req_ready; -wire cci_dram_rsp_valid; -wire [CCI_LINE_WIDTH-1:0] cci_dram_rsp_data; -wire [AVS_REQ_TAGW-1:0] cci_dram_rsp_tag; -wire cci_dram_rsp_ready; +wire cci_mem_rsp_valid; +wire [CCI_LINE_WIDTH-1:0] cci_mem_rsp_data; +wire [AVS_REQ_TAGW-1:0] cci_mem_rsp_tag; +wire cci_mem_rsp_ready; //-- VX_cci_to_mem #( .CCI_DATAW (CCI_LINE_WIDTH), .CCI_ADDRW (CCI_ADDR_WIDTH), - .AVS_DATAW (DRAM_LINE_WIDTH), - .AVS_ADDRW (DRAM_ADDR_WIDTH), + .AVS_DATAW (MEM_LINE_WIDTH), + .AVS_ADDRW (MEM_ADDR_WIDTH), .TAG_WIDTH (AVS_REQ_TAGW) ) cci_to_mem( .clk (clk), .reset (reset), - .dram_req_valid_in ((CMD_MEM_WRITE == state) ? cci_dram_wr_req_valid : cci_dram_rd_req_valid), - .dram_req_addr_in ((CMD_MEM_WRITE == state) ? cci_dram_wr_req_addr : cci_dram_rd_req_addr), - .dram_req_rw_in ((CMD_MEM_WRITE == state)), - .dram_req_data_in (cci_rdq_dout[CCI_RD_RQ_DATAW-1:CCI_RD_RQ_TAGW]), - .dram_req_tag_in (AVS_REQ_TAGW'(0)), - .dram_req_ready_in (cci_dram_req_ready), + .mem_req_valid_in ((CMD_MEM_WRITE == state) ? cci_mem_wr_req_valid : cci_mem_rd_req_valid), + .mem_req_addr_in ((CMD_MEM_WRITE == state) ? cci_mem_wr_req_addr : cci_mem_rd_req_addr), + .mem_req_rw_in ((CMD_MEM_WRITE == state)), + .mem_req_data_in (cci_rdq_dout[CCI_RD_RQ_DATAW-1:CCI_RD_RQ_TAGW]), + .mem_req_tag_in (AVS_REQ_TAGW'(0)), + .mem_req_ready_in (cci_mem_req_ready), - .dram_req_valid_out (cci_dram_req_tmp_valid), - .dram_req_addr_out (cci_dram_req_tmp_addr), - .dram_req_rw_out (cci_dram_req_tmp_rw), - .dram_req_byteen_out(cci_dram_req_tmp_byteen), - .dram_req_data_out (cci_dram_req_tmp_data), - .dram_req_tag_out (cci_dram_req_tmp_tag), - .dram_req_ready_out (cci_dram_req_tmp_ready), + .mem_req_valid_out (cci_mem_req_tmp_valid), + .mem_req_addr_out (cci_mem_req_tmp_addr), + .mem_req_rw_out (cci_mem_req_tmp_rw), + .mem_req_byteen_out(cci_mem_req_tmp_byteen), + .mem_req_data_out (cci_mem_req_tmp_data), + .mem_req_tag_out (cci_mem_req_tmp_tag), + .mem_req_ready_out (cci_mem_req_tmp_ready), - .dram_rsp_valid_in (cci_dram_rsp_tmp_valid), - .dram_rsp_data_in (cci_dram_rsp_tmp_data), - .dram_rsp_tag_in (cci_dram_rsp_tmp_tag), - .dram_rsp_ready_in (cci_dram_rsp_tmp_ready), + .mem_rsp_valid_in (cci_mem_rsp_tmp_valid), + .mem_rsp_data_in (cci_mem_rsp_tmp_data), + .mem_rsp_tag_in (cci_mem_rsp_tmp_tag), + .mem_rsp_ready_in (cci_mem_rsp_tmp_ready), - .dram_rsp_valid_out (cci_dram_rsp_valid), - .dram_rsp_data_out (cci_dram_rsp_data), - .dram_rsp_tag_out (cci_dram_rsp_tag), - .dram_rsp_ready_out (cci_dram_rsp_ready) + .mem_rsp_valid_out (cci_mem_rsp_valid), + .mem_rsp_data_out (cci_mem_rsp_data), + .mem_rsp_tag_out (cci_mem_rsp_tag), + .mem_rsp_ready_out (cci_mem_rsp_ready) ); -`UNUSED_VAR (cci_dram_rsp_tag) +`UNUSED_VAR (cci_mem_rsp_tag) //-- -assign vx_dram_req_valid_qual = vx_dram_req_valid && vx_dram_en; +assign vx_mem_req_valid_qual = vx_mem_req_valid && vx_mem_en; -assign vx_dram_req_addr_qual = vx_dram_req_addr[`VX_DRAM_ADDR_WIDTH-1:`VX_DRAM_ADDR_WIDTH-DRAM_ADDR_WIDTH]; +assign vx_mem_req_addr_qual = vx_mem_req_addr[`VX_MEM_ADDR_WIDTH-1:`VX_MEM_ADDR_WIDTH-MEM_ADDR_WIDTH]; -if (`VX_DRAM_LINE_WIDTH != DRAM_LINE_WIDTH) begin - wire [VX_DRAM_LINE_IDX-1:0] vx_dram_req_idx = vx_dram_req_addr[VX_DRAM_LINE_IDX-1:0]; - wire [VX_DRAM_LINE_IDX-1:0] vx_dram_rsp_idx = vx_dram_rsp_tag_unqual[VX_DRAM_LINE_IDX-1:0]; - assign vx_dram_req_byteen_qual = 64'(vx_dram_req_byteen) << (6'(vx_dram_req_addr[VX_DRAM_LINE_IDX-1:0]) << (VX_DRAM_LINE_LW-3)); - assign vx_dram_req_data_qual = DRAM_LINE_WIDTH'(vx_dram_req_data) << ((DRAM_LINE_LW'(vx_dram_req_idx)) << VX_DRAM_LINE_LW); - assign vx_dram_req_tag_qual = {vx_dram_req_tag, vx_dram_req_idx}; - assign vx_dram_rsp_data = vx_dram_rsp_data_unqual[vx_dram_rsp_idx]; +if (`VX_MEM_LINE_WIDTH != MEM_LINE_WIDTH) begin + wire [VX_MEM_LINE_IDX-1:0] vx_mem_req_idx = vx_mem_req_addr[VX_MEM_LINE_IDX-1:0]; + wire [VX_MEM_LINE_IDX-1:0] vx_mem_rsp_idx = vx_mem_rsp_tag_unqual[VX_MEM_LINE_IDX-1:0]; + assign vx_mem_req_byteen_qual = 64'(vx_mem_req_byteen) << (6'(vx_mem_req_addr[VX_MEM_LINE_IDX-1:0]) << (VX_MEM_LINE_LW-3)); + assign vx_mem_req_data_qual = MEM_LINE_WIDTH'(vx_mem_req_data) << ((MEM_LINE_LW'(vx_mem_req_idx)) << VX_MEM_LINE_LW); + assign vx_mem_req_tag_qual = {vx_mem_req_tag, vx_mem_req_idx}; + assign vx_mem_rsp_data = vx_mem_rsp_data_unqual[vx_mem_rsp_idx]; end else begin - assign vx_dram_req_byteen_qual = vx_dram_req_byteen; - assign vx_dram_req_tag_qual = vx_dram_req_tag; - assign vx_dram_req_data_qual = vx_dram_req_data; - assign vx_dram_rsp_data = vx_dram_rsp_data_unqual; + assign vx_mem_req_byteen_qual = vx_mem_req_byteen; + assign vx_mem_req_tag_qual = vx_mem_req_tag; + assign vx_mem_req_data_qual = vx_mem_req_data; + assign vx_mem_rsp_data = vx_mem_rsp_data_unqual; end -assign vx_dram_rsp_tag = vx_dram_rsp_tag_unqual[`VX_DRAM_TAG_WIDTH+VX_DRAM_LINE_IDX-1:VX_DRAM_LINE_IDX]; +assign vx_mem_rsp_tag = vx_mem_rsp_tag_unqual[`VX_MEM_TAG_WIDTH+VX_MEM_LINE_IDX-1:VX_MEM_LINE_IDX]; //-- VX_mem_arb #( .NUM_REQS (2), - .DATA_WIDTH (DRAM_LINE_WIDTH), - .ADDR_WIDTH (DRAM_ADDR_WIDTH), + .DATA_WIDTH (MEM_LINE_WIDTH), + .ADDR_WIDTH (MEM_ADDR_WIDTH), .TAG_IN_WIDTH (AVS_REQ_TAGW), .TAG_OUT_WIDTH (AVS_REQ_TAGW+1) -) dram_arb ( +) mem_arb ( .clk (clk), .reset (reset), // Source request - .req_valid_in ({cci_dram_req_tmp_valid, vx_dram_req_valid_qual}), - .req_rw_in ({cci_dram_req_tmp_rw, vx_dram_req_rw}), - .req_byteen_in ({cci_dram_req_tmp_byteen, vx_dram_req_byteen_qual}), - .req_addr_in ({cci_dram_req_tmp_addr, vx_dram_req_addr_qual}), - .req_data_in ({cci_dram_req_tmp_data, vx_dram_req_data_qual}), - .req_tag_in ({cci_dram_req_tmp_tag, vx_dram_req_tag_qual}), - .req_ready_in ({cci_dram_req_tmp_ready, vx_dram_req_ready}), + .req_valid_in ({cci_mem_req_tmp_valid, vx_mem_req_valid_qual}), + .req_rw_in ({cci_mem_req_tmp_rw, vx_mem_req_rw}), + .req_byteen_in ({cci_mem_req_tmp_byteen, vx_mem_req_byteen_qual}), + .req_addr_in ({cci_mem_req_tmp_addr, vx_mem_req_addr_qual}), + .req_data_in ({cci_mem_req_tmp_data, vx_mem_req_data_qual}), + .req_tag_in ({cci_mem_req_tmp_tag, vx_mem_req_tag_qual}), + .req_ready_in ({cci_mem_req_tmp_ready, vx_mem_req_ready}), - // DRAM request - .req_valid_out (dram_req_valid), - .req_rw_out (dram_req_rw), - .req_byteen_out (dram_req_byteen), - .req_addr_out (dram_req_addr), - .req_data_out (dram_req_data), - .req_tag_out (dram_req_tag), - .req_ready_out (dram_req_ready), + // Memory request + .req_valid_out (mem_req_valid), + .req_rw_out (mem_req_rw), + .req_byteen_out (mem_req_byteen), + .req_addr_out (mem_req_addr), + .req_data_out (mem_req_data), + .req_tag_out (mem_req_tag), + .req_ready_out (mem_req_ready), // Source response - .rsp_valid_out ({cci_dram_rsp_tmp_valid, vx_dram_rsp_valid}), - .rsp_data_out ({cci_dram_rsp_tmp_data, vx_dram_rsp_data_unqual}), - .rsp_tag_out ({cci_dram_rsp_tmp_tag, vx_dram_rsp_tag_unqual}), - .rsp_ready_out ({cci_dram_rsp_tmp_ready, vx_dram_rsp_ready}), + .rsp_valid_out ({cci_mem_rsp_tmp_valid, vx_mem_rsp_valid}), + .rsp_data_out ({cci_mem_rsp_tmp_data, vx_mem_rsp_data_unqual}), + .rsp_tag_out ({cci_mem_rsp_tmp_tag, vx_mem_rsp_tag_unqual}), + .rsp_ready_out ({cci_mem_rsp_tmp_ready, vx_mem_rsp_ready}), - // DRAM response - .rsp_valid_in (dram_rsp_valid), - .rsp_tag_in (dram_rsp_tag), - .rsp_data_in (dram_rsp_data), - .rsp_ready_in (dram_rsp_ready) + // Memory response + .rsp_valid_in (mem_rsp_valid), + .rsp_tag_in (mem_rsp_tag), + .rsp_data_in (mem_rsp_data), + .rsp_ready_in (mem_rsp_ready) ); //-- VX_avs_wrapper #( - .AVS_DATAW (DRAM_LINE_WIDTH), - .AVS_ADDRW (DRAM_ADDR_WIDTH), - .AVS_BURSTW (DRAM_BURST_CTRW), + .AVS_DATAW (MEM_LINE_WIDTH), + .AVS_ADDRW (MEM_ADDR_WIDTH), + .AVS_BURSTW (MEM_BURST_CTRW), .AVS_BANKS (NUM_LOCAL_MEM_BANKS), .REQ_TAGW (AVS_REQ_TAGW+1), .RD_QUEUE_SIZE (AVS_RD_QUEUE_SIZE) @@ -615,20 +615,20 @@ VX_avs_wrapper #( .clk (clk), .reset (reset), - // DRAM request - .dram_req_valid (dram_req_valid), - .dram_req_rw (dram_req_rw), - .dram_req_byteen (dram_req_byteen), - .dram_req_addr (dram_req_addr), - .dram_req_data (dram_req_data), - .dram_req_tag (dram_req_tag), - .dram_req_ready (dram_req_ready), + // Memory request + .mem_req_valid (mem_req_valid), + .mem_req_rw (mem_req_rw), + .mem_req_byteen (mem_req_byteen), + .mem_req_addr (mem_req_addr), + .mem_req_data (mem_req_data), + .mem_req_tag (mem_req_tag), + .mem_req_ready (mem_req_ready), - // DRAM response - .dram_rsp_valid (dram_rsp_valid), - .dram_rsp_data (dram_rsp_data), - .dram_rsp_tag (dram_rsp_tag), - .dram_rsp_ready (dram_rsp_ready), + // Memory response + .mem_rsp_valid (mem_rsp_valid), + .mem_rsp_data (mem_rsp_data), + .mem_rsp_tag (mem_rsp_tag), + .mem_rsp_ready (mem_rsp_ready), // AVS bus .avs_writedata (avs_writedata), @@ -645,10 +645,10 @@ VX_avs_wrapper #( // CCI-P Read Request /////////////////////////////////////////////////////////// -reg [CCI_ADDR_WIDTH-1:0] cci_dram_wr_req_ctr; +reg [CCI_ADDR_WIDTH-1:0] cci_mem_wr_req_ctr; reg [CCI_ADDR_WIDTH-1:0] cci_rd_req_ctr; wire [CCI_ADDR_WIDTH-1:0] cci_rd_req_ctr_next; -reg [CCI_ADDR_WIDTH-1:0] cci_dram_wr_req_addr_unqual; +reg [CCI_ADDR_WIDTH-1:0] cci_mem_wr_req_addr_unqual; wire [CCI_RD_RQ_TAGW-1:0] cci_rd_req_tag, cci_rd_rsp_tag; reg [CCI_RD_RQ_TAGW-1:0] cci_rd_rsp_ctr; t_ccip_clAddr cci_rd_req_addr; @@ -665,7 +665,7 @@ always @(*) begin af2cp_sTxPort.c0.hdr.mdata = t_ccip_mdata'(cci_rd_req_tag); end -wire cci_dram_wr_req_fire = cci_dram_wr_req_valid && cci_dram_req_ready; +wire cci_mem_wr_req_fire = cci_mem_wr_req_valid && cci_mem_req_ready; wire cci_rd_req_fire = af2cp_sTxPort.c0.valid; @@ -678,7 +678,7 @@ assign cci_rd_rsp_tag = CCI_RD_RQ_TAGW'(cp2af_sRxPort.c0.hdr.mdata); assign cci_rd_req_ctr_next = cci_rd_req_ctr + CCI_ADDR_WIDTH'(cci_rd_req_fire ? 1 : 0); -assign cci_rdq_pop = cci_dram_wr_req_fire; +assign cci_rdq_pop = cci_mem_wr_req_fire; assign cci_rdq_push = cci_rd_rsp_fire; assign cci_rdq_din = {cp2af_sRxPort.c0.data, cci_rd_rsp_tag}; @@ -697,13 +697,13 @@ VX_pending_size #( ); `UNUSED_VAR (cci_pending_reads) -assign cci_dram_wr_req_valid = !cci_rdq_empty; +assign cci_mem_wr_req_valid = !cci_rdq_empty; -assign cci_dram_wr_req_addr = cci_dram_wr_req_addr_unqual + (CCI_ADDR_WIDTH'(CCI_RD_RQ_TAGW'(cci_rdq_dout))); +assign cci_mem_wr_req_addr = cci_mem_wr_req_addr_unqual + (CCI_ADDR_WIDTH'(CCI_RD_RQ_TAGW'(cci_rdq_dout))); assign af2cp_sTxPort.c0.valid = cci_rd_req_enable && !(cci_rd_req_wait || cci_pending_reads_full); -assign cmd_write_done = (cci_dram_wr_req_ctr == cmd_data_size); +assign cmd_write_done = (cci_mem_wr_req_ctr == cmd_data_size); // Send read requests to CCI always @(posedge clk) begin @@ -713,19 +713,19 @@ always @(posedge clk) begin cci_rd_rsp_ctr <= 0; cci_rd_req_enable <= 0; cci_rd_req_wait <= 0; - cci_dram_wr_req_ctr <= 0; - cci_dram_wr_req_addr_unqual <= 0; + cci_mem_wr_req_ctr <= 0; + cci_mem_wr_req_addr_unqual <= 0; end else begin if ((STATE_IDLE == state) && (CMD_MEM_WRITE == cmd_type)) begin - cci_rd_req_addr <= cmd_io_addr; - cci_rd_req_ctr <= 0; - cci_rd_rsp_ctr <= 0; - cci_rd_req_enable <= (cmd_data_size != 0); - cci_rd_req_wait <= 0; - cci_dram_wr_req_ctr <= 0; - cci_dram_wr_req_addr_unqual <= cmd_mem_addr; + cci_rd_req_addr <= cmd_io_addr; + cci_rd_req_ctr <= 0; + cci_rd_rsp_ctr <= 0; + cci_rd_req_enable <= (cmd_data_size != 0); + cci_rd_req_wait <= 0; + cci_mem_wr_req_ctr <= 0; + cci_mem_wr_req_addr_unqual <= cmd_mem_addr; end cci_rd_req_enable <= (STATE_WRITE == state) @@ -759,9 +759,9 @@ always @(posedge clk) begin `endif end*/ - if (cci_dram_wr_req_fire) begin - cci_dram_wr_req_addr_unqual <= cci_dram_wr_req_addr_unqual + ((CCI_RD_RQ_TAGW'(cci_dram_wr_req_ctr) == CCI_RD_RQ_TAGW'(CCI_RD_WINDOW_SIZE-1)) ? CCI_ADDR_WIDTH'(CCI_RD_WINDOW_SIZE) : CCI_ADDR_WIDTH'(0)); - cci_dram_wr_req_ctr <= cci_dram_wr_req_ctr + CCI_ADDR_WIDTH'(1); + if (cci_mem_wr_req_fire) begin + cci_mem_wr_req_addr_unqual <= cci_mem_wr_req_addr_unqual + ((CCI_RD_RQ_TAGW'(cci_mem_wr_req_ctr) == CCI_RD_RQ_TAGW'(CCI_RD_WINDOW_SIZE-1)) ? CCI_ADDR_WIDTH'(CCI_RD_WINDOW_SIZE) : CCI_ADDR_WIDTH'(0)); + cci_mem_wr_req_ctr <= cci_mem_wr_req_ctr + CCI_ADDR_WIDTH'(1); end end end @@ -805,22 +805,22 @@ VX_fifo_queue #( // CCI-P Write Request ////////////////////////////////////////////////////////// -reg [CCI_ADDR_WIDTH-1:0] cci_dram_rd_req_ctr; +reg [CCI_ADDR_WIDTH-1:0] cci_mem_rd_req_ctr; reg [CCI_ADDR_WIDTH-1:0] cci_wr_req_ctr; -reg [CCI_ADDR_WIDTH-1:0] cci_dram_rd_req_addr_r; +reg [CCI_ADDR_WIDTH-1:0] cci_mem_rd_req_addr_r; t_ccip_clAddr cci_wr_req_addr; always @(*) begin af2cp_sTxPort.c1.hdr = t_ccip_c1_ReqMemHdr'(0); af2cp_sTxPort.c1.hdr.address = cci_wr_req_addr; af2cp_sTxPort.c1.hdr.sop = 1; // single line write mode - af2cp_sTxPort.c1.data = t_ccip_clData'(cci_dram_rsp_data); + af2cp_sTxPort.c1.data = t_ccip_clData'(cci_mem_rsp_data); end -wire cci_dram_rd_req_fire = cci_dram_rd_req_valid && cci_dram_req_ready; -wire cci_dram_rd_rsp_fire = cci_dram_rsp_valid && cci_dram_rsp_ready; +wire cci_mem_rd_req_fire = cci_mem_rd_req_valid && cci_mem_req_ready; +wire cci_mem_rd_rsp_fire = cci_mem_rsp_valid && cci_mem_rsp_ready; -wire cci_wr_req_fire = cci_dram_rd_rsp_fire; +wire cci_wr_req_fire = cci_mem_rd_rsp_fire; wire cci_wr_rsp_fire = (STATE_READ == state) && cp2af_sRxPort.c1.rspValid @@ -842,11 +842,11 @@ VX_pending_size #( ); `UNUSED_VAR (cci_pending_writes) -assign cci_dram_rd_req_valid = (cci_dram_rd_req_ctr != 0); -assign cci_dram_rd_req_addr = cci_dram_rd_req_addr_r; +assign cci_mem_rd_req_valid = (cci_mem_rd_req_ctr != 0); +assign cci_mem_rd_req_addr = cci_mem_rd_req_addr_r; -assign af2cp_sTxPort.c1.valid = cci_dram_rd_rsp_fire; -assign cci_dram_rsp_ready = !cp2af_sRxPort.c1TxAlmFull && !cci_pending_writes_full; +assign af2cp_sTxPort.c1.valid = cci_mem_rd_rsp_fire; +assign cci_mem_rsp_ready = !cp2af_sRxPort.c1TxAlmFull && !cci_pending_writes_full; assign cmd_read_done = (0 == cci_wr_req_ctr) && cci_pending_writes_empty; @@ -854,18 +854,18 @@ assign cmd_read_done = (0 == cci_wr_req_ctr) && cci_pending_writes_empty; always @(posedge clk) begin if (reset) begin - cci_wr_req_addr <= 0; - cci_wr_req_ctr <= 0; - cci_dram_rd_req_ctr <= 0; - cci_dram_rd_req_addr_r <= 0; + cci_wr_req_addr <= 0; + cci_wr_req_ctr <= 0; + cci_mem_rd_req_ctr <= 0; + cci_mem_rd_req_addr_r <= 0; end else begin if ((STATE_IDLE == state) && (CMD_MEM_READ == cmd_type)) begin - cci_wr_req_addr <= cmd_io_addr; - cci_wr_req_ctr <= cmd_data_size; - cci_dram_rd_req_ctr <= cmd_data_size; - cci_dram_rd_req_addr_r <= cmd_mem_addr; + cci_wr_req_addr <= cmd_io_addr; + cci_wr_req_ctr <= cmd_data_size; + cci_mem_rd_req_ctr <= cmd_data_size; + cci_mem_rd_req_addr_r <= cmd_mem_addr; end if (cci_wr_req_fire) begin @@ -883,9 +883,9 @@ begin end `endif*/ - if (cci_dram_rd_req_fire) begin - cci_dram_rd_req_addr_r <= cci_dram_rd_req_addr_r + CCI_ADDR_WIDTH'(1); - cci_dram_rd_req_ctr <= cci_dram_rd_req_ctr - CCI_ADDR_WIDTH'(1); + if (cci_mem_rd_req_fire) begin + cci_mem_rd_req_addr_r <= cci_mem_rd_req_addr_r + CCI_ADDR_WIDTH'(1); + cci_mem_rd_req_ctr <= cci_mem_rd_req_ctr - CCI_ADDR_WIDTH'(1); end end end @@ -934,20 +934,20 @@ Vortex #() vortex ( .clk (clk), .reset (reset | vx_reset), - // DRAM request - .dram_req_valid (vx_dram_req_valid), - .dram_req_rw (vx_dram_req_rw), - .dram_req_byteen(vx_dram_req_byteen), - .dram_req_addr (vx_dram_req_addr), - .dram_req_data (vx_dram_req_data), - .dram_req_tag (vx_dram_req_tag), - .dram_req_ready (vx_dram_req_ready), + // Memory request + .mem_req_valid (vx_mem_req_valid), + .mem_req_rw (vx_mem_req_rw), + .mem_req_byteen (vx_mem_req_byteen), + .mem_req_addr (vx_mem_req_addr), + .mem_req_data (vx_mem_req_data), + .mem_req_tag (vx_mem_req_tag), + .mem_req_ready (vx_mem_req_ready), - // DRAM response - .dram_rsp_valid (vx_dram_rsp_valid), - .dram_rsp_data (vx_dram_rsp_data), - .dram_rsp_tag (vx_dram_rsp_tag), - .dram_rsp_ready (vx_dram_rsp_ready), + // Memory response + .mem_rsp_valid (vx_mem_rsp_valid), + .mem_rsp_data (vx_mem_rsp_data), + .mem_rsp_tag (vx_mem_rsp_tag), + .mem_rsp_ready (vx_mem_rsp_ready), // CSR Request .csr_req_valid (vx_csr_io_req_valid), @@ -996,8 +996,8 @@ Vortex #() vortex ( `SCOPE_ASSIGN (avs_burstcount, avs_burstcount); `SCOPE_ASSIGN (avs_readdatavalid, avs_readdatavalid); `SCOPE_ASSIGN (mem_bank_select, mem_bank_select); -`SCOPE_ASSIGN (cci_dram_rd_req_ctr, cci_dram_rd_req_ctr); -`SCOPE_ASSIGN (cci_dram_wr_req_ctr, cci_dram_wr_req_ctr); +`SCOPE_ASSIGN (cci_mem_rd_req_ctr, cci_mem_rd_req_ctr); +`SCOPE_ASSIGN (cci_mem_wr_req_ctr, cci_mem_wr_req_ctr); `SCOPE_ASSIGN (cci_rd_req_ctr, cci_rd_req_ctr); `SCOPE_ASSIGN (cci_rd_rsp_ctr, cci_rd_rsp_ctr); `SCOPE_ASSIGN (cci_wr_req_ctr, cci_wr_req_ctr); @@ -1008,11 +1008,11 @@ Vortex #() vortex ( `SCOPE_ASSIGN (cci_pending_reads_full, cci_pending_reads_full); `SCOPE_ASSIGN (cci_pending_writes_empty, cci_pending_writes_empty); `SCOPE_ASSIGN (cci_pending_writes_full, cci_pending_writes_full); -`SCOPE_ASSIGN (afu_dram_req_fire, (dram_req_valid && dram_req_ready)); -`SCOPE_ASSIGN (afu_dram_req_addr, dram_req_addr); -`SCOPE_ASSIGN (afu_dram_req_tag, dram_req_tag); -`SCOPE_ASSIGN (afu_dram_rsp_fire, (dram_rsp_valid && dram_rsp_ready)); -`SCOPE_ASSIGN (afu_dram_rsp_tag, dram_rsp_tag); +`SCOPE_ASSIGN (afu_mem_req_fire, (mem_req_valid && mem_req_ready)); +`SCOPE_ASSIGN (afu_mem_req_addr, mem_req_addr); +`SCOPE_ASSIGN (afu_mem_req_tag, mem_req_tag); +`SCOPE_ASSIGN (afu_mem_rsp_fire, (mem_rsp_valid && mem_rsp_ready)); +`SCOPE_ASSIGN (afu_mem_rsp_tag, mem_rsp_tag); wire scope_changed = `SCOPE_TRIGGER; diff --git a/hw/rtl/cache/VX_bank.v b/hw/rtl/cache/VX_bank.v index 81df57ad..34c6308c 100644 --- a/hw/rtl/cache/VX_bank.v +++ b/hw/rtl/cache/VX_bank.v @@ -22,8 +22,8 @@ module VX_bank #( parameter CREQ_SIZE = 1, // Miss Reserv Queue Knob parameter MSHR_SIZE = 1, - // DRAM Request Queue Size - parameter DREQ_SIZE = 1, + // Memory Request Queue Size + parameter MREQ_SIZE = 1, // Enable cache writeable parameter WRITE_ENABLE = 1, @@ -38,7 +38,7 @@ module VX_bank #( parameter BANK_ADDR_OFFSET = 0, // in-order DRAN - parameter IN_ORDER_DRAM = 0 + parameter IN_ORDER_MEM = 0 ) ( `SCOPE_IO_VX_bank @@ -71,19 +71,19 @@ module VX_bank #( output wire [CORE_TAG_WIDTH-1:0] core_rsp_tag, input wire core_rsp_ready, - // DRAM request - output wire dram_req_valid, - output wire dram_req_rw, - output wire [CACHE_LINE_SIZE-1:0] dram_req_byteen, - output wire [`LINE_ADDR_WIDTH-1:0] dram_req_addr, - output wire [`CACHE_LINE_WIDTH-1:0] dram_req_data, - input wire dram_req_ready, + // Memory request + output wire mem_req_valid, + output wire mem_req_rw, + output wire [CACHE_LINE_SIZE-1:0] mem_req_byteen, + output wire [`LINE_ADDR_WIDTH-1:0] mem_req_addr, + output wire [`CACHE_LINE_WIDTH-1:0] mem_req_data, + input wire mem_req_ready, - // DRAM response - input wire dram_rsp_valid, - input wire [`LINE_ADDR_WIDTH-1:0] dram_rsp_addr, - input wire [`CACHE_LINE_WIDTH-1:0] dram_rsp_data, - output wire dram_rsp_ready, + // Memory response + input wire mem_rsp_valid, + input wire [`LINE_ADDR_WIDTH-1:0] mem_rsp_addr, + input wire [`CACHE_LINE_WIDTH-1:0] mem_rsp_data, + output wire mem_rsp_ready, // flush input wire flush_enable, @@ -167,8 +167,8 @@ module VX_bank #( wire is_flush_st0; wire crsq_in_valid, crsq_in_ready, crsq_in_stall; - wire dreq_alm_full; - wire drsq_pop; + wire mreq_alm_full; + wire mrsq_pop; wire crsq_in_fire = crsq_in_valid && crsq_in_ready; @@ -186,24 +186,24 @@ module VX_bank #( // determine which queue to pop next in priority order wire mshr_pop_unqual = mshr_valid - && !dreq_alm_full; // ensure DRAM request queue not full (deadlock prevention) - wire drsq_pop_unqual = !mshr_pop_unqual && dram_rsp_valid; - wire creq_pop_unqual = !mshr_pop_unqual && !drsq_pop_unqual && !creq_empty && !flush_enable; + && !mreq_alm_full; // ensure memory request queue not full (deadlock prevention) + wire mrsq_pop_unqual = !mshr_pop_unqual && mem_rsp_valid; + wire creq_pop_unqual = !mshr_pop_unqual && !mrsq_pop_unqual && !creq_empty && !flush_enable; wire is_miss_st1 = valid_st1 && (miss_st1 || force_miss_st1); assign mshr_pop = mshr_pop_unqual - && !(!IN_ORDER_DRAM && is_miss_st1 && is_mshr_st1) // do not schedule another mshr request if the previous one missed + && !(!IN_ORDER_MEM && is_miss_st1 && is_mshr_st1) // do not schedule another mshr request if the previous one missed && !crsq_in_stall; // ensure core response ready - assign drsq_pop = drsq_pop_unqual + assign mrsq_pop = mrsq_pop_unqual && !crsq_in_stall; // ensure core response ready assign creq_pop = creq_pop_unqual - && !dreq_alm_full // ensure dram request ready + && !mreq_alm_full // ensure memory request ready && !mshr_alm_full // ensure mshr enqueue ready && !crsq_in_stall; // ensure core response ready - assign dram_rsp_ready = drsq_pop; + assign mem_rsp_ready = mrsq_pop; // we have a miss in mshr or entering it for the current address wire mshr_pending_sel = mshr_pending @@ -238,12 +238,12 @@ module VX_bank #( assign creq_line_data = creq_data; end - wire [`LINE_ADDR_WIDTH-1:0] dram_rsp_addr_qual; - if (IN_ORDER_DRAM) begin - `UNUSED_VAR (dram_rsp_addr) - assign dram_rsp_addr_qual = mshr_addr; + wire [`LINE_ADDR_WIDTH-1:0] mem_rsp_addr_qual; + if (IN_ORDER_MEM) begin + `UNUSED_VAR (mem_rsp_addr) + assign mem_rsp_addr_qual = mshr_addr; end else begin - assign dram_rsp_addr_qual = dram_rsp_addr; + assign mem_rsp_addr_qual = mem_rsp_addr; end VX_pipe_register #( @@ -254,13 +254,13 @@ module VX_bank #( .reset (reset), .enable (!crsq_in_stall), .data_in ({ - flush_enable || mshr_pop || drsq_pop || creq_pop, + flush_enable || mshr_pop || mrsq_pop || creq_pop, flush_enable, mshr_pop_unqual, - drsq_pop_unqual || flush_enable, + mrsq_pop_unqual || flush_enable, mshr_pop_unqual ? 1'b0 : creq_rw, - mshr_pop_unqual ? mshr_addr : (dram_rsp_valid ? dram_rsp_addr_qual : (flush_enable ? `LINE_ADDR_WIDTH'(flush_addr) : creq_addr)), - dram_rsp_valid ? dram_rsp_data : creq_line_data, + mshr_pop_unqual ? mshr_addr : (mem_rsp_valid ? mem_rsp_addr_qual : (flush_enable ? `LINE_ADDR_WIDTH'(flush_addr) : creq_addr)), + mem_rsp_valid ? mem_rsp_data : creq_line_data, mshr_pop_unqual ? mshr_wsel : creq_wsel, mshr_pop_unqual ? mshr_byteen : creq_byteen, mshr_pop_unqual ? mshr_tid : creq_tid, @@ -307,7 +307,7 @@ module VX_bank #( ); // redundant fills - wire is_redundant_fill_st0 = !IN_ORDER_DRAM && is_fill_st0 && tag_match_st0; + wire is_redundant_fill_st0 = !IN_ORDER_MEM && is_fill_st0 && tag_match_st0; // we had a miss with prior request for the current address assign prev_miss_dep_st0 = is_miss_st1 && (addr_st0 == addr_st1); @@ -322,9 +322,9 @@ module VX_bank #( assign writeen_unqual_st0 = (WRITE_ENABLE && !is_fill_st0 && tag_match_st0 && mem_rw_st0) || (is_fill_st0 && !is_redundant_fill_st0); - assign incoming_fill_st0 = dram_rsp_valid && (addr_st0 == dram_rsp_addr_qual); + assign incoming_fill_st0 = mem_rsp_valid && (addr_st0 == mem_rsp_addr_qual); - assign fill_req_unqual_st0 = !mem_rw_st0 && (!force_miss_st0 || (!IN_ORDER_DRAM && is_mshr_st0 && !prev_miss_dep_st0)); + assign fill_req_unqual_st0 = !mem_rw_st0 && (!force_miss_st0 || (!IN_ORDER_MEM && is_mshr_st0 && !prev_miss_dep_st0)); VX_pipe_register #( .DATAW (1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `CACHE_LINE_WIDTH + (`UP(`WORD_SELECT_BITS) + WORD_SIZE + `REQS_BITS + 1) * NUM_PORTS + CORE_TAG_WIDTH), @@ -351,12 +351,12 @@ module VX_bank #( wire mshr_push_st1 = !is_fill_st1 && !mem_rw_st1 && (miss_st1 || force_miss_st1); - wire incoming_fill_qual_st1 = (dram_rsp_valid && (addr_st1 == dram_rsp_addr_qual)) + wire incoming_fill_qual_st1 = (mem_rsp_valid && (addr_st1 == mem_rsp_addr_qual)) || incoming_fill_st1; wire do_writeback_st1 = !is_fill_st1 && mem_rw_st1; - wire dreq_push_st1 = (miss_st1 && fill_req_unqual_st1 && !incoming_fill_qual_st1) + wire mreq_push_st1 = (miss_st1 && fill_req_unqual_st1 && !incoming_fill_qual_st1) || do_writeback_st1; wire [`WORDS_PER_LINE-1:0][WORD_SIZE-1:0] line_byteen_st1; @@ -408,15 +408,15 @@ module VX_bank #( assign mshr_push = valid_st1 && mshr_push_st1; wire mshr_dequeue = valid_st1 && is_mshr_st1 && !mshr_push_st1 && crsq_in_ready; - wire mshr_restore = !IN_ORDER_DRAM && is_mshr_st1; - `RUNTIME_ASSERT(!IN_ORDER_DRAM || !(mshr_push && mshr_restore), ("Oops!")) + wire mshr_restore = !IN_ORDER_MEM && is_mshr_st1; + `RUNTIME_ASSERT(!IN_ORDER_MEM || !(mshr_push && mshr_restore), ("Oops!")) // push a missed request as 'ready' if it was a forced miss that actually had a hit // or the fill request for this block is comming wire mshr_init_ready_state = !miss_st1 || incoming_fill_qual_st1; - // use dram rsp or core req address to lookup the mshr - wire [`LINE_ADDR_WIDTH-1:0] lookup_addr = dram_rsp_valid ? dram_rsp_addr_qual : creq_addr; + // use memory rsp or core req address to lookup the mshr + wire [`LINE_ADDR_WIDTH-1:0] lookup_addr = mem_rsp_valid ? mem_rsp_addr_qual : creq_addr; VX_miss_resrv #( .BANK_ID (BANK_ID), @@ -450,7 +450,7 @@ module VX_bank #( `UNUSED_PIN (enqueue_full), // lookup - .lookup_ready (drsq_pop), + .lookup_ready (mrsq_pop), .lookup_addr (lookup_addr), .lookup_match (mshr_pending), @@ -500,41 +500,41 @@ module VX_bank #( .ready_out (core_rsp_ready) ); - // Enqueue DRAM request + // Enqueue memory request - wire [CACHE_LINE_SIZE-1:0] dreq_byteen; - wire [`LINE_ADDR_WIDTH-1:0] dreq_addr; - wire [`CACHE_LINE_WIDTH-1:0] dreq_data; - wire dreq_push, dreq_pop, dreq_empty, dreq_rw; + wire [CACHE_LINE_SIZE-1:0] mreq_byteen; + wire [`LINE_ADDR_WIDTH-1:0] mreq_addr; + wire [`CACHE_LINE_WIDTH-1:0] mreq_data; + wire mreq_push, mreq_pop, mreq_empty, mreq_rw; - assign dreq_push = valid_st1 && dreq_push_st1; + assign mreq_push = valid_st1 && mreq_push_st1; - assign dreq_pop = dram_req_valid && dram_req_ready; + assign mreq_pop = mem_req_valid && mem_req_ready; - assign dreq_rw = WRITE_ENABLE && do_writeback_st1; - assign dreq_byteen = dreq_rw ? line_byteen_st1 : {CACHE_LINE_SIZE{1'b1}}; - assign dreq_addr = addr_st1; - assign dreq_data = wdata_st1; + assign mreq_rw = WRITE_ENABLE && do_writeback_st1; + assign mreq_byteen = mreq_rw ? line_byteen_st1 : {CACHE_LINE_SIZE{1'b1}}; + assign mreq_addr = addr_st1; + assign mreq_data = wdata_st1; VX_fifo_queue #( .DATAW (1 + CACHE_LINE_SIZE + `LINE_ADDR_WIDTH + `CACHE_LINE_WIDTH), - .SIZE (DREQ_SIZE), - .ALM_FULL (DREQ_SIZE-2) - ) dram_req_queue ( + .SIZE (MREQ_SIZE), + .ALM_FULL (MREQ_SIZE-2) + ) mem_req_queue ( .clk (clk), .reset (reset), - .push (dreq_push), - .pop (dreq_pop), - .data_in ({dreq_rw, dreq_byteen, dreq_addr, dreq_data}), - .data_out ({dram_req_rw, dram_req_byteen, dram_req_addr, dram_req_data}), - .empty (dreq_empty), - .alm_full (dreq_alm_full), + .push (mreq_push), + .pop (mreq_pop), + .data_in ({mreq_rw, mreq_byteen, mreq_addr, mreq_data}), + .data_out ({mem_req_rw, mem_req_byteen, mem_req_addr, mem_req_data}), + .empty (mreq_empty), + .alm_full (mreq_alm_full), `UNUSED_PIN (full), `UNUSED_PIN (alm_empty), `UNUSED_PIN (size) ); - assign dram_req_valid = !dreq_empty; + assign mem_req_valid = !mreq_empty; `SCOPE_ASSIGN (valid_st0, valid_st0); `SCOPE_ASSIGN (valid_st1, valid_st1); @@ -544,7 +544,7 @@ module VX_bank #( `SCOPE_ASSIGN (force_miss_st0, force_miss_st0); `SCOPE_ASSIGN (mshr_push, mshr_push); `SCOPE_ASSIGN (crsq_in_stall, crsq_in_stall); - `SCOPE_ASSIGN (dreq_alm_full, dreq_alm_full); + `SCOPE_ASSIGN (mreq_alm_full, mreq_alm_full); `SCOPE_ASSIGN (mshr_alm_full, mshr_alm_full); `SCOPE_ASSIGN (addr_st0, `LINE_TO_BYTE_ADDR(addr_st0, BANK_ID)); `SCOPE_ASSIGN (addr_st1, `LINE_TO_BYTE_ADDR(addr_st1, BANK_ID)); @@ -552,7 +552,7 @@ module VX_bank #( `ifdef PERF_ENABLE assign perf_read_misses = valid_st1 && !is_fill_st1 && !is_mshr_st1 && miss_st1 && !mem_rw_st1; assign perf_write_misses = valid_st1 && !is_fill_st1 && !is_mshr_st1 && miss_st1 && mem_rw_st1; - assign perf_pipe_stalls = crsq_in_stall || dreq_alm_full || mshr_alm_full; + assign perf_pipe_stalls = crsq_in_stall || mreq_alm_full || mshr_alm_full; assign perf_mshr_stalls = mshr_alm_full; `endif @@ -565,14 +565,14 @@ module VX_bank #( $display("%t: *** cache%0d:%0d miss with incoming fill - addr=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st1, BANK_ID)); assert(!is_mshr_st1); end - if (crsq_in_stall || dreq_alm_full || mshr_alm_full) begin - $display("%t: cache%0d:%0d pipeline-stall: cwbq=%b, dwbq=%b, mshr=%b", $time, CACHE_ID, BANK_ID, crsq_in_stall, dreq_alm_full, mshr_alm_full); + if (crsq_in_stall || mreq_alm_full || mshr_alm_full) begin + $display("%t: cache%0d:%0d pipeline-stall: cwbq=%b, dwbq=%b, mshr=%b", $time, CACHE_ID, BANK_ID, crsq_in_stall, mreq_alm_full, mshr_alm_full); end if (flush_enable) begin $display("%t: cache%0d:%0d flush: addr=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(flush_addr, BANK_ID)); end - if (drsq_pop) begin - $display("%t: cache%0d:%0d fill-rsp: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_rsp_addr_qual, BANK_ID), dram_rsp_data); + if (mrsq_pop) begin + $display("%t: cache%0d:%0d fill-rsp: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(mem_rsp_addr_qual, BANK_ID), mem_rsp_data); end if (mshr_pop) begin $display("%t: cache%0d:%0d mshr-rd-req: addr=%0h, tag=%0h, pmask=%0b, tid=%0d, byteen=%b, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(mshr_addr, BANK_ID), mshr_tag, mshr_pmask, mshr_tid, mshr_byteen, debug_wid_sel, debug_pc_sel); @@ -586,11 +586,11 @@ module VX_bank #( if (crsq_in_fire) begin $display("%t: cache%0d:%0d core-rsp: addr=%0h, tag=%0h, pmask=%0b, tid=%0d, data=%0h, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st1, BANK_ID), crsq_tag, crsq_pmask, crsq_tid, crsq_data, debug_wid_st1, debug_pc_st1); end - if (dreq_push) begin + if (mreq_push) begin if (do_writeback_st1) - $display("%t: cache%0d:%0d writeback: addr=%0h, data=%0h, byteen=%b, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dreq_addr, BANK_ID), dreq_data, dreq_byteen, debug_wid_st1, debug_pc_st1); + $display("%t: cache%0d:%0d writeback: addr=%0h, data=%0h, byteen=%b, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(mreq_addr, BANK_ID), mreq_data, mreq_byteen, debug_wid_st1, debug_pc_st1); else - $display("%t: cache%0d:%0d fill-req: addr=%0h, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dreq_addr, BANK_ID), debug_wid_st1, debug_pc_st1); + $display("%t: cache%0d:%0d fill-req: addr=%0h, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(mreq_addr, BANK_ID), debug_wid_st1, debug_pc_st1); end end `endif diff --git a/hw/rtl/cache/VX_cache.v b/hw/rtl/cache/VX_cache.v index 1487477f..20bbc0ab 100644 --- a/hw/rtl/cache/VX_cache.v +++ b/hw/rtl/cache/VX_cache.v @@ -21,10 +21,10 @@ module VX_cache #( parameter CREQ_SIZE = 4, // Miss Reserv Queue Knob parameter MSHR_SIZE = 8, - // DRAM Response Queue Size - parameter DRSQ_SIZE = 4, - // DRAM Request Queue Size - parameter DREQ_SIZE = 4, + // Memory Response Queue Size + parameter MRSQ_SIZE = 4, + // Memory Request Queue Size + parameter MREQ_SIZE = 4, // Enable cache writeable parameter WRITE_ENABLE = 1, @@ -35,14 +35,14 @@ module VX_cache #( // size of tag id in core request tag parameter CORE_TAG_ID_BITS = CORE_TAG_WIDTH, - // dram request tag size - parameter DRAM_TAG_WIDTH = (32 - $clog2(CACHE_LINE_SIZE)), + // Memory request tag size + parameter MEM_TAG_WIDTH = (32 - $clog2(CACHE_LINE_SIZE)), // bank offset from beginning of index range parameter BANK_ADDR_OFFSET = 0, // in-order DRAN - parameter IN_ORDER_DRAM = 0 + parameter IN_ORDER_MEM = 0 ) ( `SCOPE_IO_VX_cache @@ -64,20 +64,20 @@ module VX_cache #( output wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag, input wire [`CORE_REQ_TAG_COUNT-1:0] core_rsp_ready, - // DRAM request - output wire dram_req_valid, - output wire dram_req_rw, - output wire [CACHE_LINE_SIZE-1:0] dram_req_byteen, - output wire [`DRAM_ADDR_WIDTH-1:0] dram_req_addr, - output wire [`CACHE_LINE_WIDTH-1:0] dram_req_data, - output wire [DRAM_TAG_WIDTH-1:0] dram_req_tag, - input wire dram_req_ready, + // Memory request + output wire mem_req_valid, + output wire mem_req_rw, + output wire [CACHE_LINE_SIZE-1:0] mem_req_byteen, + output wire [`MEM_ADDR_WIDTH-1:0] mem_req_addr, + output wire [`CACHE_LINE_WIDTH-1:0] mem_req_data, + output wire [MEM_TAG_WIDTH-1:0] mem_req_tag, + input wire mem_req_ready, - // DRAM response - input wire dram_rsp_valid, - input wire [`CACHE_LINE_WIDTH-1:0] dram_rsp_data, - input wire [DRAM_TAG_WIDTH-1:0] dram_rsp_tag, - output wire dram_rsp_ready, + // Memory response + input wire mem_rsp_valid, + input wire [`CACHE_LINE_WIDTH-1:0] mem_rsp_data, + input wire [MEM_TAG_WIDTH-1:0] mem_rsp_tag, + output wire mem_rsp_ready, // PERF `ifdef PERF_ENABLE @@ -107,17 +107,17 @@ module VX_cache #( wire [NUM_BANKS-1:0][CORE_TAG_WIDTH-1:0] per_bank_core_rsp_tag; wire [NUM_BANKS-1:0] per_bank_core_rsp_ready; - wire [NUM_BANKS-1:0] per_bank_dram_req_valid; - wire [NUM_BANKS-1:0] per_bank_dram_req_rw; - wire [NUM_BANKS-1:0][CACHE_LINE_SIZE-1:0] per_bank_dram_req_byteen; - wire [NUM_BANKS-1:0][`DRAM_ADDR_WIDTH-1:0] per_bank_dram_req_addr; - wire [NUM_BANKS-1:0][`CACHE_LINE_WIDTH-1:0] per_bank_dram_req_data; - wire [NUM_BANKS-1:0] per_bank_dram_req_ready; + wire [NUM_BANKS-1:0] per_bank_mem_req_valid; + wire [NUM_BANKS-1:0] per_bank_mem_req_rw; + wire [NUM_BANKS-1:0][CACHE_LINE_SIZE-1:0] per_bank_mem_req_byteen; + wire [NUM_BANKS-1:0][`MEM_ADDR_WIDTH-1:0] per_bank_mem_req_addr; + wire [NUM_BANKS-1:0][`CACHE_LINE_WIDTH-1:0] per_bank_mem_req_data; + wire [NUM_BANKS-1:0] per_bank_mem_req_ready; - wire [NUM_BANKS-1:0] per_bank_dram_rsp_ready; + wire [NUM_BANKS-1:0] per_bank_mem_rsp_ready; - wire [`CACHE_LINE_WIDTH-1:0] dram_rsp_data_qual; - wire [DRAM_TAG_WIDTH-1:0] dram_rsp_tag_qual; + wire [`CACHE_LINE_WIDTH-1:0] mem_rsp_data_qual; + wire [MEM_TAG_WIDTH-1:0] mem_rsp_tag_qual; wire [`LINE_SELECT_BITS-1:0] flush_addr; wire flush_enable; @@ -130,35 +130,35 @@ module VX_cache #( /////////////////////////////////////////////////////////////////////////// - wire drsq_full, drsq_empty; - wire drsq_push, drsq_pop; + wire mrsq_full, mrsq_empty; + wire mrsq_push, mrsq_pop; - assign drsq_push = dram_rsp_valid && dram_rsp_ready; - assign dram_rsp_ready = !drsq_full; + assign mrsq_push = mem_rsp_valid && mem_rsp_ready; + assign mem_rsp_ready = !mrsq_full; VX_fifo_queue #( - .DATAW (DRAM_TAG_WIDTH + `CACHE_LINE_WIDTH), - .SIZE (DRSQ_SIZE), + .DATAW (MEM_TAG_WIDTH + `CACHE_LINE_WIDTH), + .SIZE (MRSQ_SIZE), .BUFFERED (1) - ) dram_rsp_queue ( + ) mem_rsp_queue ( .clk (clk), .reset (reset), - .push (drsq_push), - .pop (drsq_pop), - .data_in ({dram_rsp_tag, dram_rsp_data}), - .data_out ({dram_rsp_tag_qual, dram_rsp_data_qual}), - .empty (drsq_empty), - .full (drsq_full), + .push (mrsq_push), + .pop (mrsq_pop), + .data_in ({mem_rsp_tag, mem_rsp_data}), + .data_out ({mem_rsp_tag_qual, mem_rsp_data_qual}), + .empty (mrsq_empty), + .full (mrsq_full), `UNUSED_PIN (alm_full), `UNUSED_PIN (alm_empty), `UNUSED_PIN (size) ); if (NUM_BANKS == 1) begin - `UNUSED_VAR (dram_rsp_tag_qual) - assign drsq_pop = !drsq_empty && per_bank_dram_rsp_ready; + `UNUSED_VAR (mem_rsp_tag_qual) + assign mrsq_pop = !mrsq_empty && per_bank_mem_rsp_ready; end else begin - assign drsq_pop = !drsq_empty && per_bank_dram_rsp_ready[`DRAM_ADDR_BANK(dram_rsp_tag_qual)]; + assign mrsq_pop = !mrsq_empty && per_bank_mem_rsp_ready[`MEM_ADDR_BANK(mem_rsp_tag_qual)]; end /////////////////////////////////////////////////////////////////////////// @@ -229,17 +229,17 @@ module VX_cache #( wire [CORE_TAG_WIDTH-1:0] curr_bank_core_rsp_tag; wire curr_bank_core_rsp_ready; - wire curr_bank_dram_req_valid; - wire curr_bank_dram_req_rw; - wire [CACHE_LINE_SIZE-1:0] curr_bank_dram_req_byteen; - wire [`LINE_ADDR_WIDTH-1:0] curr_bank_dram_req_addr; - wire[`CACHE_LINE_WIDTH-1:0] curr_bank_dram_req_data; - wire curr_bank_dram_req_ready; + wire curr_bank_mem_req_valid; + wire curr_bank_mem_req_rw; + wire [CACHE_LINE_SIZE-1:0] curr_bank_mem_req_byteen; + wire [`LINE_ADDR_WIDTH-1:0] curr_bank_mem_req_addr; + wire[`CACHE_LINE_WIDTH-1:0] curr_bank_mem_req_data; + wire curr_bank_mem_req_ready; - wire curr_bank_dram_rsp_valid; - wire [`LINE_ADDR_WIDTH-1:0] curr_bank_dram_rsp_addr; - wire [`CACHE_LINE_WIDTH-1:0] curr_bank_dram_rsp_data; - wire curr_bank_dram_rsp_ready; + wire curr_bank_mem_rsp_valid; + wire [`LINE_ADDR_WIDTH-1:0] curr_bank_mem_rsp_addr; + wire [`CACHE_LINE_WIDTH-1:0] curr_bank_mem_rsp_data; + wire curr_bank_mem_rsp_ready; // Core Req assign curr_bank_core_req_valid = per_bank_core_req_valid[i]; @@ -260,28 +260,28 @@ module VX_cache #( assign per_bank_core_rsp_tag [i] = curr_bank_core_rsp_tag; assign per_bank_core_rsp_data [i] = curr_bank_core_rsp_data; - // DRAM request - assign per_bank_dram_req_valid[i] = curr_bank_dram_req_valid; - assign per_bank_dram_req_rw[i] = curr_bank_dram_req_rw; - assign per_bank_dram_req_byteen[i] = curr_bank_dram_req_byteen; + // Memory request + assign per_bank_mem_req_valid[i] = curr_bank_mem_req_valid; + assign per_bank_mem_req_rw[i] = curr_bank_mem_req_rw; + assign per_bank_mem_req_byteen[i] = curr_bank_mem_req_byteen; if (NUM_BANKS == 1) begin - assign per_bank_dram_req_addr[i] = curr_bank_dram_req_addr; + assign per_bank_mem_req_addr[i] = curr_bank_mem_req_addr; end else begin - assign per_bank_dram_req_addr[i] = `LINE_TO_DRAM_ADDR(curr_bank_dram_req_addr, i); + assign per_bank_mem_req_addr[i] = `LINE_TO_MEM_ADDR(curr_bank_mem_req_addr, i); end - assign per_bank_dram_req_data[i] = curr_bank_dram_req_data; - assign curr_bank_dram_req_ready = per_bank_dram_req_ready[i]; + assign per_bank_mem_req_data[i] = curr_bank_mem_req_data; + assign curr_bank_mem_req_ready = per_bank_mem_req_ready[i]; - // DRAM response + // Memory response if (NUM_BANKS == 1) begin - assign curr_bank_dram_rsp_valid = !drsq_empty; - assign curr_bank_dram_rsp_addr = dram_rsp_tag_qual; + assign curr_bank_mem_rsp_valid = !mrsq_empty; + assign curr_bank_mem_rsp_addr = mem_rsp_tag_qual; end else begin - assign curr_bank_dram_rsp_valid = !drsq_empty && (`DRAM_ADDR_BANK(dram_rsp_tag_qual) == i); - assign curr_bank_dram_rsp_addr = `DRAM_TO_LINE_ADDR(dram_rsp_tag_qual); + assign curr_bank_mem_rsp_valid = !mrsq_empty && (`MEM_ADDR_BANK(mem_rsp_tag_qual) == i); + assign curr_bank_mem_rsp_addr = `MEM_TO_LINE_ADDR(mem_rsp_tag_qual); end - assign curr_bank_dram_rsp_data = dram_rsp_data_qual; - assign per_bank_dram_rsp_ready[i] = curr_bank_dram_rsp_ready; + assign curr_bank_mem_rsp_data = mem_rsp_data_qual; + assign per_bank_mem_rsp_ready[i] = curr_bank_mem_rsp_ready; VX_bank #( .BANK_ID (i), @@ -294,12 +294,12 @@ module VX_cache #( .NUM_REQS (NUM_REQS), .CREQ_SIZE (CREQ_SIZE), .MSHR_SIZE (MSHR_SIZE), - .DREQ_SIZE (DREQ_SIZE), + .MREQ_SIZE (MREQ_SIZE), .WRITE_ENABLE (WRITE_ENABLE), .CORE_TAG_WIDTH (CORE_TAG_WIDTH), .CORE_TAG_ID_BITS (CORE_TAG_ID_BITS), .BANK_ADDR_OFFSET (BANK_ADDR_OFFSET), - .IN_ORDER_DRAM (IN_ORDER_DRAM) + .IN_ORDER_MEM (IN_ORDER_MEM) ) bank ( `SCOPE_BIND_VX_cache_bank(i) @@ -332,19 +332,19 @@ module VX_cache #( .core_rsp_tag (curr_bank_core_rsp_tag), .core_rsp_ready (curr_bank_core_rsp_ready), - // DRAM request - .dram_req_valid (curr_bank_dram_req_valid), - .dram_req_rw (curr_bank_dram_req_rw), - .dram_req_byteen (curr_bank_dram_req_byteen), - .dram_req_addr (curr_bank_dram_req_addr), - .dram_req_data (curr_bank_dram_req_data), - .dram_req_ready (curr_bank_dram_req_ready), + // Memory request + .mem_req_valid (curr_bank_mem_req_valid), + .mem_req_rw (curr_bank_mem_req_rw), + .mem_req_byteen (curr_bank_mem_req_byteen), + .mem_req_addr (curr_bank_mem_req_addr), + .mem_req_data (curr_bank_mem_req_data), + .mem_req_ready (curr_bank_mem_req_ready), - // DRAM response - .dram_rsp_valid (curr_bank_dram_rsp_valid), - .dram_rsp_addr (curr_bank_dram_rsp_addr), - .dram_rsp_data (curr_bank_dram_rsp_data), - .dram_rsp_ready (curr_bank_dram_rsp_ready), + // Memory response + .mem_rsp_valid (curr_bank_mem_rsp_valid), + .mem_rsp_addr (curr_bank_mem_rsp_addr), + .mem_rsp_data (curr_bank_mem_rsp_data), + .mem_rsp_ready (curr_bank_mem_rsp_ready), // flush .flush_enable (flush_enable), @@ -375,27 +375,27 @@ module VX_cache #( .core_rsp_ready (core_rsp_ready) ); - wire [NUM_BANKS-1:0][(`DRAM_ADDR_WIDTH + 1 + CACHE_LINE_SIZE + `CACHE_LINE_WIDTH)-1:0] data_in; + wire [NUM_BANKS-1:0][(`MEM_ADDR_WIDTH + 1 + CACHE_LINE_SIZE + `CACHE_LINE_WIDTH)-1:0] data_in; for (genvar i = 0; i < NUM_BANKS; i++) begin - assign data_in[i] = {per_bank_dram_req_addr[i], per_bank_dram_req_rw[i], per_bank_dram_req_byteen[i], per_bank_dram_req_data[i]}; + assign data_in[i] = {per_bank_mem_req_addr[i], per_bank_mem_req_rw[i], per_bank_mem_req_byteen[i], per_bank_mem_req_data[i]}; end VX_stream_arbiter #( .NUM_REQS (NUM_BANKS), - .DATAW (`DRAM_ADDR_WIDTH + 1 + CACHE_LINE_SIZE + `CACHE_LINE_WIDTH), + .DATAW (`MEM_ADDR_WIDTH + 1 + CACHE_LINE_SIZE + `CACHE_LINE_WIDTH), .BUFFERED (1) - ) dram_req_arb ( + ) mem_req_arb ( .clk (clk), .reset (reset), - .valid_in (per_bank_dram_req_valid), + .valid_in (per_bank_mem_req_valid), .data_in (data_in), - .ready_in (per_bank_dram_req_ready), - .valid_out (dram_req_valid), - .data_out ({dram_req_addr, dram_req_rw, dram_req_byteen, dram_req_data}), - .ready_out (dram_req_ready) + .ready_in (per_bank_mem_req_ready), + .valid_out (mem_req_valid), + .data_out ({mem_req_addr, mem_req_rw, mem_req_byteen, mem_req_data}), + .ready_out (mem_req_ready) ); - assign dram_req_tag = dram_req_addr; + assign mem_req_tag = mem_req_addr; `ifdef PERF_ENABLE // per cycle: core_reads, core_writes diff --git a/hw/rtl/cache/VX_cache_config.vh b/hw/rtl/cache/VX_cache_config.vh index bfe8b96c..4b896521 100644 --- a/hw/rtl/cache/VX_cache_config.vh +++ b/hw/rtl/cache/VX_cache_config.vh @@ -21,8 +21,8 @@ `define WORDS_PER_LINE (CACHE_LINE_SIZE / WORD_SIZE) `define WORD_ADDR_WIDTH (32-`CLOG2(WORD_SIZE)) -`define DRAM_ADDR_WIDTH (32-`CLOG2(CACHE_LINE_SIZE)) -`define LINE_ADDR_WIDTH (`DRAM_ADDR_WIDTH-`BANK_SELECT_BITS) +`define MEM_ADDR_WIDTH (32-`CLOG2(CACHE_LINE_SIZE)) +`define LINE_ADDR_WIDTH (`MEM_ADDR_WIDTH-`BANK_SELECT_BITS) // Word select `define WORD_SELECT_BITS `CLOG2(`WORDS_PER_LINE) @@ -57,11 +57,11 @@ `define BANK_READY_COUNT ((SHARED_BANK_READY != 0) ? 1 : NUM_BANKS) -`define DRAM_ADDR_BANK(x) x[`BANK_SELECT_BITS+BANK_ADDR_OFFSET-1 : BANK_ADDR_OFFSET] +`define MEM_ADDR_BANK(x) x[`BANK_SELECT_BITS+BANK_ADDR_OFFSET-1 : BANK_ADDR_OFFSET] -`define DRAM_TO_LINE_ADDR(x) x[`DRAM_ADDR_WIDTH-1 : `BANK_SELECT_BITS] +`define MEM_TO_LINE_ADDR(x) x[`MEM_ADDR_WIDTH-1 : `BANK_SELECT_BITS] -`define LINE_TO_DRAM_ADDR(x, i) {x, `BANK_SELECT_BITS'(i)} +`define LINE_TO_MEM_ADDR(x, i) {x, `BANK_SELECT_BITS'(i)} `define LINE_TO_BYTE_ADDR(x, i) {x, (32-$bits(x))'(i << (32-$bits(x)-`BANK_SELECT_BITS))} diff --git a/hw/rtl/interfaces/VX_cache_dram_req_if.v b/hw/rtl/interfaces/VX_cache_dram_req_if.v deleted file mode 100644 index 5591bf9f..00000000 --- a/hw/rtl/interfaces/VX_cache_dram_req_if.v +++ /dev/null @@ -1,22 +0,0 @@ -`ifndef VX_CACHE_DRAM_REQ_IF -`define VX_CACHE_DRAM_REQ_IF - -`include "../cache/VX_cache_config.vh" - -interface VX_cache_dram_req_if #( - parameter DRAM_LINE_WIDTH = 1, - parameter DRAM_ADDR_WIDTH = 1, - parameter DRAM_TAG_WIDTH = 1 -) (); - - wire valid; - wire rw; - wire [(DRAM_LINE_WIDTH/8)-1:0] byteen; - wire [DRAM_ADDR_WIDTH-1:0] addr; - wire [DRAM_LINE_WIDTH-1:0] data; - wire [DRAM_TAG_WIDTH-1:0] tag; - wire ready; - -endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_cache_dram_rsp_if.v b/hw/rtl/interfaces/VX_cache_dram_rsp_if.v deleted file mode 100644 index 2a3d15e0..00000000 --- a/hw/rtl/interfaces/VX_cache_dram_rsp_if.v +++ /dev/null @@ -1,18 +0,0 @@ -`ifndef VX_CACHE_DRAM_RSP_IF -`define VX_CACHE_DRAM_RSP_IF - -`include "../cache/VX_cache_config.vh" - -interface VX_cache_dram_rsp_if #( - parameter DRAM_LINE_WIDTH = 1, - parameter DRAM_TAG_WIDTH = 1 -) (); - - wire valid; - wire [DRAM_LINE_WIDTH-1:0] data; - wire [DRAM_TAG_WIDTH-1:0] tag; - wire ready; - -endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_cache_mem_req_if.v b/hw/rtl/interfaces/VX_cache_mem_req_if.v new file mode 100644 index 00000000..b761b61f --- /dev/null +++ b/hw/rtl/interfaces/VX_cache_mem_req_if.v @@ -0,0 +1,23 @@ +`ifndef VX_CACHE_MEM_REQ_IF +`define VX_CACHE_MEM_REQ_IF + +`include "../cache/VX_cache_config.vh" + +interface VX_cache_mem_req_if #( + parameter MEM_LINE_WIDTH = 1, + parameter MEM_ADDR_WIDTH = 1, + parameter MEM_TAG_WIDTH = 1, + parameter MEM_LINE_SIZE = MEM_LINE_WIDTH / 8 +) (); + + wire valid; + wire rw; + wire [MEM_LINE_SIZE-1:0] byteen; + wire [MEM_ADDR_WIDTH-1:0] addr; + wire [MEM_LINE_WIDTH-1:0] data; + wire [MEM_TAG_WIDTH-1:0] tag; + wire ready; + +endinterface + +`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_cache_mem_rsp_if.v b/hw/rtl/interfaces/VX_cache_mem_rsp_if.v new file mode 100644 index 00000000..eb4abf26 --- /dev/null +++ b/hw/rtl/interfaces/VX_cache_mem_rsp_if.v @@ -0,0 +1,18 @@ +`ifndef VX_CACHE_MEM_RSP_IF +`define VX_CACHE_MEM_RSP_IF + +`include "../cache/VX_cache_config.vh" + +interface VX_cache_mem_rsp_if #( + parameter MEM_LINE_WIDTH = 1, + parameter MEM_TAG_WIDTH = 1 +) (); + + wire valid; + wire [MEM_LINE_WIDTH-1:0] data; + wire [MEM_TAG_WIDTH-1:0] tag; + wire ready; + +endinterface + +`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_perf_memsys_if.v b/hw/rtl/interfaces/VX_perf_memsys_if.v index 21484151..a2ef4835 100644 --- a/hw/rtl/interfaces/VX_perf_memsys_if.v +++ b/hw/rtl/interfaces/VX_perf_memsys_if.v @@ -23,10 +23,10 @@ interface VX_perf_memsys_if (); wire [`PERF_CTR_BITS-1:0] smem_writes; wire [`PERF_CTR_BITS-1:0] smem_bank_stalls; - wire [`PERF_CTR_BITS-1:0] dram_reads; - wire [`PERF_CTR_BITS-1:0] dram_writes; - wire [`PERF_CTR_BITS-1:0] dram_stalls; - wire [`PERF_CTR_BITS-1:0] dram_latency; + wire [`PERF_CTR_BITS-1:0] mem_reads; + wire [`PERF_CTR_BITS-1:0] mem_writes; + wire [`PERF_CTR_BITS-1:0] mem_stalls; + wire [`PERF_CTR_BITS-1:0] mem_latency; endinterface diff --git a/hw/scripts/scope.json b/hw/scripts/scope.json index d4d8033f..6290a622 100644 --- a/hw/scripts/scope.json +++ b/hw/scripts/scope.json @@ -98,8 +98,8 @@ "avs_burstcount":4, "avs_readdatavalid":1, "mem_bank_select":1, - "cci_dram_rd_req_ctr":26, - "cci_dram_wr_req_ctr":26, + "cci_mem_rd_req_ctr":26, + "cci_mem_wr_req_ctr":26, "cci_rd_req_ctr":26, "cci_rd_rsp_ctr":3, "cci_wr_req_ctr":26, @@ -110,23 +110,23 @@ "!cci_pending_reads_full":1, "!cci_pending_writes_empty":1, "!cci_pending_writes_full": 1, - "?afu_dram_req_fire": 1, - "afu_dram_req_addr": 26, - "afu_dram_req_tag": 28, - "?afu_dram_rsp_fire": 1, - "afu_dram_rsp_tag": 28 + "?afu_mem_req_fire": 1, + "afu_mem_req_addr": 26, + "afu_mem_req_tag": 28, + "?afu_mem_rsp_fire": 1, + "afu_mem_rsp_tag": 28 }, "afu/vortex": { "!reset": 1, - "?dram_req_fire": 1, - "dram_req_addr": 32, - "dram_req_rw": 1, - "dram_req_byteen":"`VX_DRAM_BYTEEN_WIDTH", - "dram_req_data":"`VX_DRAM_LINE_WIDTH", - "dram_req_tag":"`VX_DRAM_TAG_WIDTH", - "?dram_rsp_fire": 1, - "dram_rsp_data":"`VX_DRAM_LINE_WIDTH", - "dram_rsp_tag":"`VX_DRAM_TAG_WIDTH", + "?mem_req_fire": 1, + "mem_req_addr": 32, + "mem_req_rw": 1, + "mem_req_byteen":"`VX_MEM_BYTEEN_WIDTH", + "mem_req_data":"`VX_MEM_LINE_WIDTH", + "mem_req_tag":"`VX_MEM_TAG_WIDTH", + "?mem_rsp_fire": 1, + "mem_rsp_data":"`VX_MEM_LINE_WIDTH", + "mem_rsp_tag":"`VX_MEM_TAG_WIDTH", "busy": 1 }, "afu/vortex/cluster/core/pipeline/fetch/icache_stage": { @@ -213,7 +213,7 @@ "force_miss_st0": 1, "mshr_push": 1, "?crsq_in_stall": 1, - "?dreq_alm_full": 1, + "?mreq_alm_full": 1, "?mshr_alm_full": 1 } } diff --git a/hw/simulate/Makefile b/hw/simulate/Makefile index 7b1d9b9c..dbbae208 100644 --- a/hw/simulate/Makefile +++ b/hw/simulate/Makefile @@ -13,7 +13,7 @@ DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_BANK DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_MSHR DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_TAG DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_DATA -DBG_PRINT_FLAGS += -DDBG_PRINT_DRAM +DBG_PRINT_FLAGS += -DDBG_PRINT_MEM DBG_PRINT_FLAGS += -DDBG_PRINT_OPAE DBG_PRINT_FLAGS += -DDBG_PRINT_AVS DBG_PRINT_FLAGS += -DDBG_PRINT_SCOPE diff --git a/hw/simulate/simulator.cpp b/hw/simulate/simulator.cpp index 2a4d8a1a..e19aaacd 100644 --- a/hw/simulate/simulator.cpp +++ b/hw/simulate/simulator.cpp @@ -5,10 +5,10 @@ #define RESET_DELAY 4 -#define ENABLE_DRAM_STALLS -#define DRAM_LATENCY 24 -#define DRAM_RQ_SIZE 16 -#define DRAM_STALLS_MODULO 16 +#define ENABLE_MEM_STALLS +#define MEM_LATENCY 24 +#define MEM_RQ_SIZE 16 +#define MEM_STALLS_MODULO 16 #define VL_WDATA_GETW(lwp, i, n, w) \ VL_SEL_IWII(0, n * w, 0, 0, lwp, i * w, w) @@ -56,19 +56,19 @@ Simulator::~Simulator() { void Simulator::attach_ram(RAM* ram) { ram_ = ram; - dram_rsp_vec_.clear(); + mem_rsp_vec_.clear(); } void Simulator::reset() { print_bufs_.clear(); - dram_rsp_vec_.clear(); + mem_rsp_vec_.clear(); - dram_rsp_active_ = false; + mem_rsp_active_ = false; csr_req_active_ = false; csr_rsp_value_ = nullptr; - vortex_->dram_rsp_valid = 0; - vortex_->dram_req_ready = 0; + vortex_->mem_rsp_valid = 0; + vortex_->mem_req_ready = 0; //vortex_->io_req_ready = 0; //vortex_->io_rsp_valid = 0; vortex_->csr_req_valid = 0; @@ -94,13 +94,13 @@ void Simulator::step() { vortex_->clk = 0; this->eval(); - dram_rsp_ready_ = vortex_->dram_rsp_ready; + mem_rsp_ready_ = vortex_->mem_rsp_ready; csr_req_ready_ = vortex_->csr_req_ready; vortex_->clk = 1; this->eval(); - this->eval_dram_bus(); + this->eval_mem_bus(); this->eval_io_bus(); this->eval_csr_bus(); @@ -117,83 +117,83 @@ void Simulator::eval() { ++timestamp; } -void Simulator::eval_dram_bus() { +void Simulator::eval_mem_bus() { if (ram_ == nullptr) { - vortex_->dram_req_ready = 0; + vortex_->mem_req_ready = 0; return; } - // update DRAM responses schedule - for (auto& rsp : dram_rsp_vec_) { + // update memory responses schedule + for (auto& rsp : mem_rsp_vec_) { if (rsp.cycles_left > 0) rsp.cycles_left -= 1; } - // schedule DRAM responses in FIFO order - std::list::iterator dram_rsp_it(dram_rsp_vec_.end()); - if (!dram_rsp_vec_.empty() - && (0 == dram_rsp_vec_.begin()->cycles_left)) { - dram_rsp_it = dram_rsp_vec_.begin(); + // schedule memory responses in FIFO order + std::list::iterator mem_rsp_it(mem_rsp_vec_.end()); + if (!mem_rsp_vec_.empty() + && (0 == mem_rsp_vec_.begin()->cycles_left)) { + mem_rsp_it = mem_rsp_vec_.begin(); } - // send DRAM response - if (dram_rsp_active_ - && vortex_->dram_rsp_valid && dram_rsp_ready_) { - dram_rsp_active_ = false; + // send memory response + if (mem_rsp_active_ + && vortex_->mem_rsp_valid && mem_rsp_ready_) { + mem_rsp_active_ = false; } - if (!dram_rsp_active_) { - if (dram_rsp_it != dram_rsp_vec_.end()) { - vortex_->dram_rsp_valid = 1; - memcpy((uint8_t*)vortex_->dram_rsp_data, dram_rsp_it->block.data(), GLOBAL_BLOCK_SIZE); - vortex_->dram_rsp_tag = dram_rsp_it->tag; - dram_rsp_vec_.erase(dram_rsp_it); - dram_rsp_active_ = true; + if (!mem_rsp_active_) { + if (mem_rsp_it != mem_rsp_vec_.end()) { + vortex_->mem_rsp_valid = 1; + memcpy((uint8_t*)vortex_->mem_rsp_data, mem_rsp_it->block.data(), GLOBAL_BLOCK_SIZE); + vortex_->mem_rsp_tag = mem_rsp_it->tag; + mem_rsp_vec_.erase(mem_rsp_it); + mem_rsp_active_ = true; } else { - vortex_->dram_rsp_valid = 0; + vortex_->mem_rsp_valid = 0; } } - // handle DRAM stalls - bool dram_stalled = false; -#ifdef ENABLE_DRAM_STALLS - if (0 == ((timestamp/2) % DRAM_STALLS_MODULO)) { - dram_stalled = true; + // handle memory stalls + bool mem_stalled = false; +#ifdef ENABLE_MEM_STALLS + if (0 == ((timestamp/2) % MEM_STALLS_MODULO)) { + mem_stalled = true; } else - if (dram_rsp_vec_.size() >= DRAM_RQ_SIZE) { - dram_stalled = true; + if (mem_rsp_vec_.size() >= MEM_RQ_SIZE) { + mem_stalled = true; } #endif - // process DRAM requests - if (!dram_stalled) { - if (vortex_->dram_req_valid) { - if (vortex_->dram_req_rw) { - uint64_t byteen = vortex_->dram_req_byteen; - unsigned base_addr = (vortex_->dram_req_addr * GLOBAL_BLOCK_SIZE); - uint8_t* data = (uint8_t*)(vortex_->dram_req_data); + // process memory requests + if (!mem_stalled) { + if (vortex_->mem_req_valid) { + if (vortex_->mem_req_rw) { + uint64_t byteen = vortex_->mem_req_byteen; + unsigned base_addr = (vortex_->mem_req_addr * GLOBAL_BLOCK_SIZE); + uint8_t* data = (uint8_t*)(vortex_->mem_req_data); for (int i = 0; i < GLOBAL_BLOCK_SIZE; i++) { if ((byteen >> i) & 0x1) { (*ram_)[base_addr + i] = data[i]; } } } else { - dram_req_t dram_req; - dram_req.tag = vortex_->dram_req_tag; - dram_req.addr = vortex_->dram_req_addr; - ram_->read(vortex_->dram_req_addr * GLOBAL_BLOCK_SIZE, GLOBAL_BLOCK_SIZE, dram_req.block.data()); - dram_req.cycles_left = DRAM_LATENCY; - for (auto& rsp : dram_rsp_vec_) { - if (dram_req.addr == rsp.addr) { - dram_req.cycles_left = rsp.cycles_left; + mem_req_t mem_req; + mem_req.tag = vortex_->mem_req_tag; + mem_req.addr = vortex_->mem_req_addr; + ram_->read(vortex_->mem_req_addr * GLOBAL_BLOCK_SIZE, GLOBAL_BLOCK_SIZE, mem_req.block.data()); + mem_req.cycles_left = MEM_LATENCY; + for (auto& rsp : mem_rsp_vec_) { + if (mem_req.addr == rsp.addr) { + mem_req.cycles_left = rsp.cycles_left; break; } } - dram_rsp_vec_.emplace_back(dram_req); + mem_rsp_vec_.emplace_back(mem_req); } } } - vortex_->dram_req_ready = !dram_stalled; + vortex_->mem_req_ready = !mem_stalled; } void Simulator::eval_io_bus() { diff --git a/hw/simulate/simulator.h b/hw/simulate/simulator.h index 626474bd..f800e643 100644 --- a/hw/simulate/simulator.h +++ b/hw/simulate/simulator.h @@ -51,20 +51,20 @@ private: std::array block; uint32_t addr; uint32_t tag; - } dram_req_t; + } mem_req_t; std::unordered_map print_bufs_; void eval(); - void eval_dram_bus(); + void eval_mem_bus(); void eval_io_bus(); void eval_csr_bus(); - std::list dram_rsp_vec_; - bool dram_rsp_active_; + std::list mem_rsp_vec_; + bool mem_rsp_active_; - bool dram_rsp_ready_; + bool mem_rsp_ready_; bool csr_req_ready_; bool csr_req_active_; uint32_t* csr_rsp_value_; diff --git a/hw/modelsim/Makefile b/hw/syn/modelsim/Makefile similarity index 100% rename from hw/modelsim/Makefile rename to hw/syn/modelsim/Makefile diff --git a/hw/modelsim/cshrc.modelsim b/hw/syn/modelsim/cshrc.modelsim similarity index 100% rename from hw/modelsim/cshrc.modelsim rename to hw/syn/modelsim/cshrc.modelsim diff --git a/hw/modelsim/vortex_dpi.cpp b/hw/syn/modelsim/vortex_dpi.cpp similarity index 100% rename from hw/modelsim/vortex_dpi.cpp rename to hw/syn/modelsim/vortex_dpi.cpp diff --git a/hw/modelsim/vortex_dpi.h b/hw/syn/modelsim/vortex_dpi.h similarity index 100% rename from hw/modelsim/vortex_dpi.h rename to hw/syn/modelsim/vortex_dpi.h diff --git a/hw/modelsim/vortex_tb.v b/hw/syn/modelsim/vortex_tb.v similarity index 100% rename from hw/modelsim/vortex_tb.v rename to hw/syn/modelsim/vortex_tb.v diff --git a/hw/syn/opae/README b/hw/syn/opae/README index 03233d0b..35a2a9a6 100644 --- a/hw/syn/opae/README +++ b/hw/syn/opae/README @@ -63,6 +63,7 @@ qsub-sim make ase # tests +./run_ase.sh build_ase_1c ../../../driver/tests/basic/basic -n128 -t0 ./run_ase.sh build_ase_1c ../../../driver/tests/basic/basic -n16 ./run_ase.sh build_ase_1c ../../../driver/tests/demo/demo -n16 ./run_ase.sh build_ase_1c ../../../driver/tests/dogfood/dogfood -n16 @@ -78,17 +79,15 @@ run -all tar -zcvf output_files_1c.tar.gz `find ./build_fpga_1c -type f \( -iname \*.rpt -o -iname \*.txt -o -iname \*summary -o -iname \*.log \)` # compress VCD trace -tar -zcvf vortex.vcd.tar.gz ./build_ase_1c/work/vortex.vcd +tar -zcvf trace.vcd.tar.gz ./build_ase_1c/work/trace.vcd tar -zcvf trace.vcd.tar.gz obj_dir/trace.vcd tar -zcvf trace.fst.tar.gz trace.fst run.log tar -zcvf run.log.tar.gz run.log -tar -cvjf vortex.vcd.tar.bz2 build_ase_1c/work/vortex.vcd -tar -zcvf vortex.vcd.tar.gz build_ase_1c/work/vortex.vcd -tar -zcvf run.log.tar.gz build_ase_1c/work/run.log tar -zcvf vx_scope.vcd.tar.gz vx_scope.vcd tar -cvjf vx_scope.vcd.tar.bz2 vx_scope.vcd tar -cvjf trace.fst.tar.bz2 trace.fst run.log tar -cvjf trace.vcd.tar.bz2 trace.vcd run.log +tar -cvjf trace.vcd.tar.bz2 build_ase_1c/work/run.log build_ase_1c/work/trace.vcd # decompress VCD trace tar -zxvf vortex.vcd.tar.gz diff --git a/hw/unit_tests/cache/Makefile b/hw/unit_tests/cache/Makefile index bf22bcbc..b6552316 100644 --- a/hw/unit_tests/cache/Makefile +++ b/hw/unit_tests/cache/Makefile @@ -10,7 +10,7 @@ DBG_PRINT_FLAGS = -DDBG_PRINT_CORE_ICACHE \ -DDBG_PRINT_CACHE_MSHR \ -DDBG_PRINT_CACHE_TAG \ -DDBG_PRINT_CACHE_DATA \ - -DDBG_PRINT_DRAM \ + -DDBG_PRINT_MEM \ -DDBG_PRINT_OPAE \ -DDBG_PRINT_AVS diff --git a/hw/unit_tests/cache/cachesim.cpp b/hw/unit_tests/cache/cachesim.cpp index 93bef54b..528a5dfe 100644 --- a/hw/unit_tests/cache/cachesim.cpp +++ b/hw/unit_tests/cache/cachesim.cpp @@ -18,7 +18,7 @@ CacheSim::CacheSim() { ram_ = nullptr; cache_ = new VVX_cache(); - dram_rsp_active_ = false; + mem_rsp_active_ = false; snp_req_active_ = false; //#ifdef VCD_OUTPUT @@ -39,7 +39,7 @@ CacheSim::~CacheSim() { void CacheSim::attach_ram(RAM* ram) { ram_ = ram; - dram_rsp_vec_.clear(); + mem_rsp_vec_.clear(); } void CacheSim::reset() { @@ -52,7 +52,7 @@ void CacheSim::reset() { cache_->reset = 0; this->step(); - dram_rsp_vec_.clear(); + mem_rsp_vec_.clear(); //clear req and rsp vecs } @@ -66,10 +66,10 @@ void CacheSim::step() { cache_->clk = 1; this->eval(); - //handle core and dram reqs and rsps + //handle core and memory reqs and rsps this->eval_reqs(); this->eval_rsps(); - this->eval_dram_bus(); + this->eval_mem_bus(); timestamp++; } @@ -104,7 +104,7 @@ void CacheSim::run(){ } stalls--; if (stalls == 20){ - //stall_dram(); + //stall_mem(); //send_snoop_req(); stalls--; } @@ -168,8 +168,8 @@ void CacheSim::eval_rsps(){ } } -void CacheSim::stall_dram(){ - cache_->dram_req_ready = 0; +void CacheSim::stall_mem(){ + cache_->mem_req_ready = 0; } void CacheSim::send_snoop_req(){ @@ -179,81 +179,81 @@ void CacheSim::send_snoop_req(){ cache_->snp_req_tag = 0xff; } -void CacheSim::eval_dram_bus() { +void CacheSim::eval_mem_bus() { if (ram_ == nullptr) { - cache_->dram_req_ready = 0; + cache_->mem_req_ready = 0; return; } - // schedule DRAM responses + // schedule memory responses int dequeue_index = -1; - for (int i = 0; i < dram_rsp_vec_.size(); i++) { - if (dram_rsp_vec_[i].cycles_left > 0) { - dram_rsp_vec_[i].cycles_left -= 1; + for (int i = 0; i < mem_rsp_vec_.size(); i++) { + if (mem_rsp_vec_[i].cycles_left > 0) { + mem_rsp_vec_[i].cycles_left -= 1; } if ((dequeue_index == -1) - && (dram_rsp_vec_[i].cycles_left == 0)) { + && (mem_rsp_vec_[i].cycles_left == 0)) { dequeue_index = i; } } - // send DRAM response - if (dram_rsp_active_ - && cache_->dram_rsp_valid - && cache_->dram_rsp_ready) { - dram_rsp_active_ = false; + // send memory response + if (mem_rsp_active_ + && cache_->mem_rsp_valid + && cache_->mem_rsp_ready) { + mem_rsp_active_ = false; } - if (!dram_rsp_active_) { + if (!mem_rsp_active_) { if (dequeue_index != -1) { //time to respond to the request - cache_->dram_rsp_valid = 1; + cache_->mem_rsp_valid = 1; //copy data from the rsp queue to the cache module - memcpy((uint8_t*)cache_->dram_rsp_data, dram_rsp_vec_[dequeue_index].data, GLOBAL_BLOCK_SIZE); + memcpy((uint8_t*)cache_->mem_rsp_data, mem_rsp_vec_[dequeue_index].data, GLOBAL_BLOCK_SIZE); - cache_->dram_rsp_tag = dram_rsp_vec_[dequeue_index].tag; - free(dram_rsp_vec_[dequeue_index].data); //take data out of the queue - dram_rsp_vec_.erase(dram_rsp_vec_.begin() + dequeue_index); - dram_rsp_active_ = true; + cache_->mem_rsp_tag = mem_rsp_vec_[dequeue_index].tag; + free(mem_rsp_vec_[dequeue_index].data); //take data out of the queue + mem_rsp_vec_.erase(mem_rsp_vec_.begin() + dequeue_index); + mem_rsp_active_ = true; } else { - cache_->dram_rsp_valid = 0; + cache_->mem_rsp_valid = 0; } } - // handle DRAM stalls - bool dram_stalled = false; -#ifdef ENABLE_DRAM_STALLS - if (0 == ((timestamp/2) % DRAM_STALLS_MODULO)) { - dram_stalled = true; + // handle memory stalls + bool mem_stalled = false; +#ifdef ENABLE_MEM_STALLS + if (0 == ((timestamp/2) % MEM_STALLS_MODULO)) { + mem_stalled = true; } else - if (dram_rsp_vec_.size() >= DRAM_RQ_SIZE) { - dram_stalled = true; + if (mem_rsp_vec_.size() >= MEM_RQ_SIZE) { + mem_stalled = true; } #endif - // process DRAM requests - if (!dram_stalled) { - if (cache_->dram_req_valid) { - if (cache_->dram_req_rw) { //write = 1 - uint64_t byteen = cache_->dram_req_byteen; - unsigned base_addr = (cache_->dram_req_addr * GLOBAL_BLOCK_SIZE); - uint8_t* data = (uint8_t*)(cache_->dram_req_data); + // process memory requests + if (!mem_stalled) { + if (cache_->mem_req_valid) { + if (cache_->mem_req_rw) { //write = 1 + uint64_t byteen = cache_->mem_req_byteen; + unsigned base_addr = (cache_->mem_req_addr * GLOBAL_BLOCK_SIZE); + uint8_t* data = (uint8_t*)(cache_->mem_req_data); for (int i = 0; i < GLOBAL_BLOCK_SIZE; i++) { if ((byteen >> i) & 0x1) { (*ram_)[base_addr + i] = data[i]; } } } else { - dram_req_t dram_req; - dram_req.cycles_left = DRAM_LATENCY; - dram_req.data = (uint8_t*)malloc(GLOBAL_BLOCK_SIZE); - dram_req.tag = cache_->dram_req_tag; - ram_->read(cache_->dram_req_addr * GLOBAL_BLOCK_SIZE, GLOBAL_BLOCK_SIZE, dram_req.data); - dram_rsp_vec_.push_back(dram_req); + mem_req_t mem_req; + mem_req.cycles_left = MEM_LATENCY; + mem_req.data = (uint8_t*)malloc(GLOBAL_BLOCK_SIZE); + mem_req.tag = cache_->mem_req_tag; + ram_->read(cache_->mem_req_addr * GLOBAL_BLOCK_SIZE, GLOBAL_BLOCK_SIZE, mem_req.data); + mem_rsp_vec_.push_back(mem_req); } } } - cache_->dram_req_ready = ~dram_stalled; + cache_->mem_req_ready = ~mem_stalled; } bool CacheSim::assert_equal(unsigned int* data, unsigned int tag){ @@ -302,19 +302,19 @@ void CacheSim::get_core_rsp(){ std::cout << std::hex << "core_rsp_tag: " << cache_->core_rsp_tag << std::endl; } -void CacheSim::get_dram_req(){ - std::cout << std::hex << "dram_req_valid: " << cache_->dram_req_valid << std::endl; - std::cout << std::hex << "dram_req_rw: " << cache_->dram_req_rw << std::endl; - std::cout << std::hex << "dram_req_byteen: " << cache_->dram_req_byteen << std::endl; - std::cout << std::hex << "dram_req_addr: " << cache_->dram_req_addr << std::endl; - std::cout << std::hex << "dram_req_data: " << cache_->dram_req_data << std::endl; - std::cout << std::hex << "dram_req_tag: " << cache_->dram_req_tag << std::endl; +void CacheSim::get_mem_req(){ + std::cout << std::hex << "mem_req_valid: " << cache_->mem_req_valid << std::endl; + std::cout << std::hex << "mem_req_rw: " << cache_->mem_req_rw << std::endl; + std::cout << std::hex << "mem_req_byteen: " << cache_->mem_req_byteen << std::endl; + std::cout << std::hex << "mem_req_addr: " << cache_->mem_req_addr << std::endl; + std::cout << std::hex << "mem_req_data: " << cache_->mem_req_data << std::endl; + std::cout << std::hex << "mem_req_tag: " << cache_->mem_req_tag << std::endl; } -void CacheSim::get_dram_rsp(){ - std::cout << std::hex << "dram_rsp_valid: " << cache_->dram_rsp_valid << std::endl; - std::cout << std::hex << "dram_rsp_data: " << cache_->dram_rsp_data << std::endl; - std::cout << std::hex << "dram_rsp_tag: " << cache_->dram_rsp_tag << std::endl; - std::cout << std::hex << "dram_rsp_ready: " << cache_->dram_rsp_ready << std::endl; +void CacheSim::get_mem_rsp(){ + std::cout << std::hex << "mem_rsp_valid: " << cache_->mem_rsp_valid << std::endl; + std::cout << std::hex << "mem_rsp_data: " << cache_->mem_rsp_data << std::endl; + std::cout << std::hex << "mem_rsp_tag: " << cache_->mem_rsp_tag << std::endl; + std::cout << std::hex << "mem_rsp_ready: " << cache_->mem_rsp_ready << std::endl; } diff --git a/hw/unit_tests/cache/cachesim.h b/hw/unit_tests/cache/cachesim.h index e6324bf6..2a4be624 100644 --- a/hw/unit_tests/cache/cachesim.h +++ b/hw/unit_tests/cache/cachesim.h @@ -14,17 +14,17 @@ #include #include -#define ENABLE_DRAM_STALLS -#define DRAM_LATENCY 100 -#define DRAM_RQ_SIZE 16 -#define DRAM_STALLS_MODULO 16 +#define ENABLE_MEM_STALLS +#define MEM_LATENCY 100 +#define MEM_RQ_SIZE 16 +#define MEM_STALLS_MODULO 16 #define GLOBAL_BLOCK_SIZE 16 typedef struct { int cycles_left; uint8_t *data; unsigned tag; -} dram_req_t; +} mem_req_t; typedef struct { char valid; @@ -52,7 +52,7 @@ public: //req/rsp void send_req(core_req_t *req); void clear_req(); - void stall_dram(); + void stall_mem(); void send_snoop_req(); void send_snp_fwd_in(); @@ -60,12 +60,12 @@ public: bool assert_equal(unsigned int* data, unsigned int tag); //debug funcs - void get_dram_req(); + void get_mem_req(); void get_core_req(unsigned int (&rsp)[4]); void get_core_rsp(); bool get_core_req_ready(); bool get_core_rsp_ready(); - void get_dram_rsp(); + void get_mem_rsp(); void display_miss(); private: @@ -73,12 +73,12 @@ private: void eval(); void eval_reqs(); void eval_rsps(); - void eval_dram_bus(); + void eval_mem_bus(); std::queue core_req_vec_; - std::vector dram_rsp_vec_; + std::vector mem_rsp_vec_; std::map core_rsp_vec_; - int dram_rsp_active_; + int mem_rsp_active_; uint32_t snp_req_active_; uint32_t snp_req_size_; diff --git a/hw/unit_tests/cache/testbench.cpp b/hw/unit_tests/cache/testbench.cpp index c668f26a..4a38bb7c 100644 --- a/hw/unit_tests/cache/testbench.cpp +++ b/hw/unit_tests/cache/testbench.cpp @@ -175,7 +175,7 @@ int FLUSH(CacheSim *sim){ int BACK_PRESSURE(CacheSim *sim){ - //happens whenever the core is stalled or DRAM is stalled + //happens whenever the core is stalled or memory is stalled unsigned int addr[4] = {0x12222222, 0xabbbbbbb, 0xcddddddd, 0xe4444444}; unsigned int data[4] = {0xffffffff, 0x11111111, 0x22222222, 0x33333333}; unsigned int rsp[4] = {0,0,0,0};