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code refactoring: DRAM => MEM renaming

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This commit is contained in:
Blaise Tine
2021-04-26 00:58:48 -07:00
parent d808aa2735
commit 8410c49f53
38 changed files with 1161 additions and 1161 deletions
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146
hw/rtl/cache/VX_bank.v vendored
View File

@@ -22,8 +22,8 @@ module VX_bank #(
parameter CREQ_SIZE = 1,
// Miss Reserv Queue Knob
parameter MSHR_SIZE = 1,
// DRAM Request Queue Size
parameter DREQ_SIZE = 1,
// Memory Request Queue Size
parameter MREQ_SIZE = 1,
// Enable cache writeable
parameter WRITE_ENABLE = 1,
@@ -38,7 +38,7 @@ module VX_bank #(
parameter BANK_ADDR_OFFSET = 0,
// in-order DRAN
parameter IN_ORDER_DRAM = 0
parameter IN_ORDER_MEM = 0
) (
`SCOPE_IO_VX_bank
@@ -71,19 +71,19 @@ module VX_bank #(
output wire [CORE_TAG_WIDTH-1:0] core_rsp_tag,
input wire core_rsp_ready,
// DRAM request
output wire dram_req_valid,
output wire dram_req_rw,
output wire [CACHE_LINE_SIZE-1:0] dram_req_byteen,
output wire [`LINE_ADDR_WIDTH-1:0] dram_req_addr,
output wire [`CACHE_LINE_WIDTH-1:0] dram_req_data,
input wire dram_req_ready,
// Memory request
output wire mem_req_valid,
output wire mem_req_rw,
output wire [CACHE_LINE_SIZE-1:0] mem_req_byteen,
output wire [`LINE_ADDR_WIDTH-1:0] mem_req_addr,
output wire [`CACHE_LINE_WIDTH-1:0] mem_req_data,
input wire mem_req_ready,
// DRAM response
input wire dram_rsp_valid,
input wire [`LINE_ADDR_WIDTH-1:0] dram_rsp_addr,
input wire [`CACHE_LINE_WIDTH-1:0] dram_rsp_data,
output wire dram_rsp_ready,
// Memory response
input wire mem_rsp_valid,
input wire [`LINE_ADDR_WIDTH-1:0] mem_rsp_addr,
input wire [`CACHE_LINE_WIDTH-1:0] mem_rsp_data,
output wire mem_rsp_ready,
// flush
input wire flush_enable,
@@ -167,8 +167,8 @@ module VX_bank #(
wire is_flush_st0;
wire crsq_in_valid, crsq_in_ready, crsq_in_stall;
wire dreq_alm_full;
wire drsq_pop;
wire mreq_alm_full;
wire mrsq_pop;
wire crsq_in_fire = crsq_in_valid && crsq_in_ready;
@@ -186,24 +186,24 @@ module VX_bank #(
// determine which queue to pop next in priority order
wire mshr_pop_unqual = mshr_valid
&& !dreq_alm_full; // ensure DRAM request queue not full (deadlock prevention)
wire drsq_pop_unqual = !mshr_pop_unqual && dram_rsp_valid;
wire creq_pop_unqual = !mshr_pop_unqual && !drsq_pop_unqual && !creq_empty && !flush_enable;
&& !mreq_alm_full; // ensure memory request queue not full (deadlock prevention)
wire mrsq_pop_unqual = !mshr_pop_unqual && mem_rsp_valid;
wire creq_pop_unqual = !mshr_pop_unqual && !mrsq_pop_unqual && !creq_empty && !flush_enable;
wire is_miss_st1 = valid_st1 && (miss_st1 || force_miss_st1);
assign mshr_pop = mshr_pop_unqual
&& !(!IN_ORDER_DRAM && is_miss_st1 && is_mshr_st1) // do not schedule another mshr request if the previous one missed
&& !(!IN_ORDER_MEM && is_miss_st1 && is_mshr_st1) // do not schedule another mshr request if the previous one missed
&& !crsq_in_stall; // ensure core response ready
assign drsq_pop = drsq_pop_unqual
assign mrsq_pop = mrsq_pop_unqual
&& !crsq_in_stall; // ensure core response ready
assign creq_pop = creq_pop_unqual
&& !dreq_alm_full // ensure dram request ready
&& !mreq_alm_full // ensure memory request ready
&& !mshr_alm_full // ensure mshr enqueue ready
&& !crsq_in_stall; // ensure core response ready
assign dram_rsp_ready = drsq_pop;
assign mem_rsp_ready = mrsq_pop;
// we have a miss in mshr or entering it for the current address
wire mshr_pending_sel = mshr_pending
@@ -238,12 +238,12 @@ module VX_bank #(
assign creq_line_data = creq_data;
end
wire [`LINE_ADDR_WIDTH-1:0] dram_rsp_addr_qual;
if (IN_ORDER_DRAM) begin
`UNUSED_VAR (dram_rsp_addr)
assign dram_rsp_addr_qual = mshr_addr;
wire [`LINE_ADDR_WIDTH-1:0] mem_rsp_addr_qual;
if (IN_ORDER_MEM) begin
`UNUSED_VAR (mem_rsp_addr)
assign mem_rsp_addr_qual = mshr_addr;
end else begin
assign dram_rsp_addr_qual = dram_rsp_addr;
assign mem_rsp_addr_qual = mem_rsp_addr;
end
VX_pipe_register #(
@@ -254,13 +254,13 @@ module VX_bank #(
.reset (reset),
.enable (!crsq_in_stall),
.data_in ({
flush_enable || mshr_pop || drsq_pop || creq_pop,
flush_enable || mshr_pop || mrsq_pop || creq_pop,
flush_enable,
mshr_pop_unqual,
drsq_pop_unqual || flush_enable,
mrsq_pop_unqual || flush_enable,
mshr_pop_unqual ? 1'b0 : creq_rw,
mshr_pop_unqual ? mshr_addr : (dram_rsp_valid ? dram_rsp_addr_qual : (flush_enable ? `LINE_ADDR_WIDTH'(flush_addr) : creq_addr)),
dram_rsp_valid ? dram_rsp_data : creq_line_data,
mshr_pop_unqual ? mshr_addr : (mem_rsp_valid ? mem_rsp_addr_qual : (flush_enable ? `LINE_ADDR_WIDTH'(flush_addr) : creq_addr)),
mem_rsp_valid ? mem_rsp_data : creq_line_data,
mshr_pop_unqual ? mshr_wsel : creq_wsel,
mshr_pop_unqual ? mshr_byteen : creq_byteen,
mshr_pop_unqual ? mshr_tid : creq_tid,
@@ -307,7 +307,7 @@ module VX_bank #(
);
// redundant fills
wire is_redundant_fill_st0 = !IN_ORDER_DRAM && is_fill_st0 && tag_match_st0;
wire is_redundant_fill_st0 = !IN_ORDER_MEM && is_fill_st0 && tag_match_st0;
// we had a miss with prior request for the current address
assign prev_miss_dep_st0 = is_miss_st1 && (addr_st0 == addr_st1);
@@ -322,9 +322,9 @@ module VX_bank #(
assign writeen_unqual_st0 = (WRITE_ENABLE && !is_fill_st0 && tag_match_st0 && mem_rw_st0)
|| (is_fill_st0 && !is_redundant_fill_st0);
assign incoming_fill_st0 = dram_rsp_valid && (addr_st0 == dram_rsp_addr_qual);
assign incoming_fill_st0 = mem_rsp_valid && (addr_st0 == mem_rsp_addr_qual);
assign fill_req_unqual_st0 = !mem_rw_st0 && (!force_miss_st0 || (!IN_ORDER_DRAM && is_mshr_st0 && !prev_miss_dep_st0));
assign fill_req_unqual_st0 = !mem_rw_st0 && (!force_miss_st0 || (!IN_ORDER_MEM && is_mshr_st0 && !prev_miss_dep_st0));
VX_pipe_register #(
.DATAW (1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `CACHE_LINE_WIDTH + (`UP(`WORD_SELECT_BITS) + WORD_SIZE + `REQS_BITS + 1) * NUM_PORTS + CORE_TAG_WIDTH),
@@ -351,12 +351,12 @@ module VX_bank #(
wire mshr_push_st1 = !is_fill_st1 && !mem_rw_st1 && (miss_st1 || force_miss_st1);
wire incoming_fill_qual_st1 = (dram_rsp_valid && (addr_st1 == dram_rsp_addr_qual))
wire incoming_fill_qual_st1 = (mem_rsp_valid && (addr_st1 == mem_rsp_addr_qual))
|| incoming_fill_st1;
wire do_writeback_st1 = !is_fill_st1 && mem_rw_st1;
wire dreq_push_st1 = (miss_st1 && fill_req_unqual_st1 && !incoming_fill_qual_st1)
wire mreq_push_st1 = (miss_st1 && fill_req_unqual_st1 && !incoming_fill_qual_st1)
|| do_writeback_st1;
wire [`WORDS_PER_LINE-1:0][WORD_SIZE-1:0] line_byteen_st1;
@@ -408,15 +408,15 @@ module VX_bank #(
assign mshr_push = valid_st1 && mshr_push_st1;
wire mshr_dequeue = valid_st1 && is_mshr_st1 && !mshr_push_st1 && crsq_in_ready;
wire mshr_restore = !IN_ORDER_DRAM && is_mshr_st1;
`RUNTIME_ASSERT(!IN_ORDER_DRAM || !(mshr_push && mshr_restore), ("Oops!"))
wire mshr_restore = !IN_ORDER_MEM && is_mshr_st1;
`RUNTIME_ASSERT(!IN_ORDER_MEM || !(mshr_push && mshr_restore), ("Oops!"))
// push a missed request as 'ready' if it was a forced miss that actually had a hit
// or the fill request for this block is comming
wire mshr_init_ready_state = !miss_st1 || incoming_fill_qual_st1;
// use dram rsp or core req address to lookup the mshr
wire [`LINE_ADDR_WIDTH-1:0] lookup_addr = dram_rsp_valid ? dram_rsp_addr_qual : creq_addr;
// use memory rsp or core req address to lookup the mshr
wire [`LINE_ADDR_WIDTH-1:0] lookup_addr = mem_rsp_valid ? mem_rsp_addr_qual : creq_addr;
VX_miss_resrv #(
.BANK_ID (BANK_ID),
@@ -450,7 +450,7 @@ module VX_bank #(
`UNUSED_PIN (enqueue_full),
// lookup
.lookup_ready (drsq_pop),
.lookup_ready (mrsq_pop),
.lookup_addr (lookup_addr),
.lookup_match (mshr_pending),
@@ -500,41 +500,41 @@ module VX_bank #(
.ready_out (core_rsp_ready)
);
// Enqueue DRAM request
// Enqueue memory request
wire [CACHE_LINE_SIZE-1:0] dreq_byteen;
wire [`LINE_ADDR_WIDTH-1:0] dreq_addr;
wire [`CACHE_LINE_WIDTH-1:0] dreq_data;
wire dreq_push, dreq_pop, dreq_empty, dreq_rw;
wire [CACHE_LINE_SIZE-1:0] mreq_byteen;
wire [`LINE_ADDR_WIDTH-1:0] mreq_addr;
wire [`CACHE_LINE_WIDTH-1:0] mreq_data;
wire mreq_push, mreq_pop, mreq_empty, mreq_rw;
assign dreq_push = valid_st1 && dreq_push_st1;
assign mreq_push = valid_st1 && mreq_push_st1;
assign dreq_pop = dram_req_valid && dram_req_ready;
assign mreq_pop = mem_req_valid && mem_req_ready;
assign dreq_rw = WRITE_ENABLE && do_writeback_st1;
assign dreq_byteen = dreq_rw ? line_byteen_st1 : {CACHE_LINE_SIZE{1'b1}};
assign dreq_addr = addr_st1;
assign dreq_data = wdata_st1;
assign mreq_rw = WRITE_ENABLE && do_writeback_st1;
assign mreq_byteen = mreq_rw ? line_byteen_st1 : {CACHE_LINE_SIZE{1'b1}};
assign mreq_addr = addr_st1;
assign mreq_data = wdata_st1;
VX_fifo_queue #(
.DATAW (1 + CACHE_LINE_SIZE + `LINE_ADDR_WIDTH + `CACHE_LINE_WIDTH),
.SIZE (DREQ_SIZE),
.ALM_FULL (DREQ_SIZE-2)
) dram_req_queue (
.SIZE (MREQ_SIZE),
.ALM_FULL (MREQ_SIZE-2)
) mem_req_queue (
.clk (clk),
.reset (reset),
.push (dreq_push),
.pop (dreq_pop),
.data_in ({dreq_rw, dreq_byteen, dreq_addr, dreq_data}),
.data_out ({dram_req_rw, dram_req_byteen, dram_req_addr, dram_req_data}),
.empty (dreq_empty),
.alm_full (dreq_alm_full),
.push (mreq_push),
.pop (mreq_pop),
.data_in ({mreq_rw, mreq_byteen, mreq_addr, mreq_data}),
.data_out ({mem_req_rw, mem_req_byteen, mem_req_addr, mem_req_data}),
.empty (mreq_empty),
.alm_full (mreq_alm_full),
`UNUSED_PIN (full),
`UNUSED_PIN (alm_empty),
`UNUSED_PIN (size)
);
assign dram_req_valid = !dreq_empty;
assign mem_req_valid = !mreq_empty;
`SCOPE_ASSIGN (valid_st0, valid_st0);
`SCOPE_ASSIGN (valid_st1, valid_st1);
@@ -544,7 +544,7 @@ module VX_bank #(
`SCOPE_ASSIGN (force_miss_st0, force_miss_st0);
`SCOPE_ASSIGN (mshr_push, mshr_push);
`SCOPE_ASSIGN (crsq_in_stall, crsq_in_stall);
`SCOPE_ASSIGN (dreq_alm_full, dreq_alm_full);
`SCOPE_ASSIGN (mreq_alm_full, mreq_alm_full);
`SCOPE_ASSIGN (mshr_alm_full, mshr_alm_full);
`SCOPE_ASSIGN (addr_st0, `LINE_TO_BYTE_ADDR(addr_st0, BANK_ID));
`SCOPE_ASSIGN (addr_st1, `LINE_TO_BYTE_ADDR(addr_st1, BANK_ID));
@@ -552,7 +552,7 @@ module VX_bank #(
`ifdef PERF_ENABLE
assign perf_read_misses = valid_st1 && !is_fill_st1 && !is_mshr_st1 && miss_st1 && !mem_rw_st1;
assign perf_write_misses = valid_st1 && !is_fill_st1 && !is_mshr_st1 && miss_st1 && mem_rw_st1;
assign perf_pipe_stalls = crsq_in_stall || dreq_alm_full || mshr_alm_full;
assign perf_pipe_stalls = crsq_in_stall || mreq_alm_full || mshr_alm_full;
assign perf_mshr_stalls = mshr_alm_full;
`endif
@@ -565,14 +565,14 @@ module VX_bank #(
$display("%t: *** cache%0d:%0d miss with incoming fill - addr=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st1, BANK_ID));
assert(!is_mshr_st1);
end
if (crsq_in_stall || dreq_alm_full || mshr_alm_full) begin
$display("%t: cache%0d:%0d pipeline-stall: cwbq=%b, dwbq=%b, mshr=%b", $time, CACHE_ID, BANK_ID, crsq_in_stall, dreq_alm_full, mshr_alm_full);
if (crsq_in_stall || mreq_alm_full || mshr_alm_full) begin
$display("%t: cache%0d:%0d pipeline-stall: cwbq=%b, dwbq=%b, mshr=%b", $time, CACHE_ID, BANK_ID, crsq_in_stall, mreq_alm_full, mshr_alm_full);
end
if (flush_enable) begin
$display("%t: cache%0d:%0d flush: addr=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(flush_addr, BANK_ID));
end
if (drsq_pop) begin
$display("%t: cache%0d:%0d fill-rsp: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_rsp_addr_qual, BANK_ID), dram_rsp_data);
if (mrsq_pop) begin
$display("%t: cache%0d:%0d fill-rsp: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(mem_rsp_addr_qual, BANK_ID), mem_rsp_data);
end
if (mshr_pop) begin
$display("%t: cache%0d:%0d mshr-rd-req: addr=%0h, tag=%0h, pmask=%0b, tid=%0d, byteen=%b, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(mshr_addr, BANK_ID), mshr_tag, mshr_pmask, mshr_tid, mshr_byteen, debug_wid_sel, debug_pc_sel);
@@ -586,11 +586,11 @@ module VX_bank #(
if (crsq_in_fire) begin
$display("%t: cache%0d:%0d core-rsp: addr=%0h, tag=%0h, pmask=%0b, tid=%0d, data=%0h, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st1, BANK_ID), crsq_tag, crsq_pmask, crsq_tid, crsq_data, debug_wid_st1, debug_pc_st1);
end
if (dreq_push) begin
if (mreq_push) begin
if (do_writeback_st1)
$display("%t: cache%0d:%0d writeback: addr=%0h, data=%0h, byteen=%b, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dreq_addr, BANK_ID), dreq_data, dreq_byteen, debug_wid_st1, debug_pc_st1);
$display("%t: cache%0d:%0d writeback: addr=%0h, data=%0h, byteen=%b, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(mreq_addr, BANK_ID), mreq_data, mreq_byteen, debug_wid_st1, debug_pc_st1);
else
$display("%t: cache%0d:%0d fill-req: addr=%0h, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dreq_addr, BANK_ID), debug_wid_st1, debug_pc_st1);
$display("%t: cache%0d:%0d fill-req: addr=%0h, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(mreq_addr, BANK_ID), debug_wid_st1, debug_pc_st1);
end
end
`endif

188
hw/rtl/cache/VX_cache.v vendored
View File

@@ -21,10 +21,10 @@ module VX_cache #(
parameter CREQ_SIZE = 4,
// Miss Reserv Queue Knob
parameter MSHR_SIZE = 8,
// DRAM Response Queue Size
parameter DRSQ_SIZE = 4,
// DRAM Request Queue Size
parameter DREQ_SIZE = 4,
// Memory Response Queue Size
parameter MRSQ_SIZE = 4,
// Memory Request Queue Size
parameter MREQ_SIZE = 4,
// Enable cache writeable
parameter WRITE_ENABLE = 1,
@@ -35,14 +35,14 @@ module VX_cache #(
// size of tag id in core request tag
parameter CORE_TAG_ID_BITS = CORE_TAG_WIDTH,
// dram request tag size
parameter DRAM_TAG_WIDTH = (32 - $clog2(CACHE_LINE_SIZE)),
// Memory request tag size
parameter MEM_TAG_WIDTH = (32 - $clog2(CACHE_LINE_SIZE)),
// bank offset from beginning of index range
parameter BANK_ADDR_OFFSET = 0,
// in-order DRAN
parameter IN_ORDER_DRAM = 0
parameter IN_ORDER_MEM = 0
) (
`SCOPE_IO_VX_cache
@@ -64,20 +64,20 @@ module VX_cache #(
output wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag,
input wire [`CORE_REQ_TAG_COUNT-1:0] core_rsp_ready,
// DRAM request
output wire dram_req_valid,
output wire dram_req_rw,
output wire [CACHE_LINE_SIZE-1:0] dram_req_byteen,
output wire [`DRAM_ADDR_WIDTH-1:0] dram_req_addr,
output wire [`CACHE_LINE_WIDTH-1:0] dram_req_data,
output wire [DRAM_TAG_WIDTH-1:0] dram_req_tag,
input wire dram_req_ready,
// Memory request
output wire mem_req_valid,
output wire mem_req_rw,
output wire [CACHE_LINE_SIZE-1:0] mem_req_byteen,
output wire [`MEM_ADDR_WIDTH-1:0] mem_req_addr,
output wire [`CACHE_LINE_WIDTH-1:0] mem_req_data,
output wire [MEM_TAG_WIDTH-1:0] mem_req_tag,
input wire mem_req_ready,
// DRAM response
input wire dram_rsp_valid,
input wire [`CACHE_LINE_WIDTH-1:0] dram_rsp_data,
input wire [DRAM_TAG_WIDTH-1:0] dram_rsp_tag,
output wire dram_rsp_ready,
// Memory response
input wire mem_rsp_valid,
input wire [`CACHE_LINE_WIDTH-1:0] mem_rsp_data,
input wire [MEM_TAG_WIDTH-1:0] mem_rsp_tag,
output wire mem_rsp_ready,
// PERF
`ifdef PERF_ENABLE
@@ -107,17 +107,17 @@ module VX_cache #(
wire [NUM_BANKS-1:0][CORE_TAG_WIDTH-1:0] per_bank_core_rsp_tag;
wire [NUM_BANKS-1:0] per_bank_core_rsp_ready;
wire [NUM_BANKS-1:0] per_bank_dram_req_valid;
wire [NUM_BANKS-1:0] per_bank_dram_req_rw;
wire [NUM_BANKS-1:0][CACHE_LINE_SIZE-1:0] per_bank_dram_req_byteen;
wire [NUM_BANKS-1:0][`DRAM_ADDR_WIDTH-1:0] per_bank_dram_req_addr;
wire [NUM_BANKS-1:0][`CACHE_LINE_WIDTH-1:0] per_bank_dram_req_data;
wire [NUM_BANKS-1:0] per_bank_dram_req_ready;
wire [NUM_BANKS-1:0] per_bank_mem_req_valid;
wire [NUM_BANKS-1:0] per_bank_mem_req_rw;
wire [NUM_BANKS-1:0][CACHE_LINE_SIZE-1:0] per_bank_mem_req_byteen;
wire [NUM_BANKS-1:0][`MEM_ADDR_WIDTH-1:0] per_bank_mem_req_addr;
wire [NUM_BANKS-1:0][`CACHE_LINE_WIDTH-1:0] per_bank_mem_req_data;
wire [NUM_BANKS-1:0] per_bank_mem_req_ready;
wire [NUM_BANKS-1:0] per_bank_dram_rsp_ready;
wire [NUM_BANKS-1:0] per_bank_mem_rsp_ready;
wire [`CACHE_LINE_WIDTH-1:0] dram_rsp_data_qual;
wire [DRAM_TAG_WIDTH-1:0] dram_rsp_tag_qual;
wire [`CACHE_LINE_WIDTH-1:0] mem_rsp_data_qual;
wire [MEM_TAG_WIDTH-1:0] mem_rsp_tag_qual;
wire [`LINE_SELECT_BITS-1:0] flush_addr;
wire flush_enable;
@@ -130,35 +130,35 @@ module VX_cache #(
///////////////////////////////////////////////////////////////////////////
wire drsq_full, drsq_empty;
wire drsq_push, drsq_pop;
wire mrsq_full, mrsq_empty;
wire mrsq_push, mrsq_pop;
assign drsq_push = dram_rsp_valid && dram_rsp_ready;
assign dram_rsp_ready = !drsq_full;
assign mrsq_push = mem_rsp_valid && mem_rsp_ready;
assign mem_rsp_ready = !mrsq_full;
VX_fifo_queue #(
.DATAW (DRAM_TAG_WIDTH + `CACHE_LINE_WIDTH),
.SIZE (DRSQ_SIZE),
.DATAW (MEM_TAG_WIDTH + `CACHE_LINE_WIDTH),
.SIZE (MRSQ_SIZE),
.BUFFERED (1)
) dram_rsp_queue (
) mem_rsp_queue (
.clk (clk),
.reset (reset),
.push (drsq_push),
.pop (drsq_pop),
.data_in ({dram_rsp_tag, dram_rsp_data}),
.data_out ({dram_rsp_tag_qual, dram_rsp_data_qual}),
.empty (drsq_empty),
.full (drsq_full),
.push (mrsq_push),
.pop (mrsq_pop),
.data_in ({mem_rsp_tag, mem_rsp_data}),
.data_out ({mem_rsp_tag_qual, mem_rsp_data_qual}),
.empty (mrsq_empty),
.full (mrsq_full),
`UNUSED_PIN (alm_full),
`UNUSED_PIN (alm_empty),
`UNUSED_PIN (size)
);
if (NUM_BANKS == 1) begin
`UNUSED_VAR (dram_rsp_tag_qual)
assign drsq_pop = !drsq_empty && per_bank_dram_rsp_ready;
`UNUSED_VAR (mem_rsp_tag_qual)
assign mrsq_pop = !mrsq_empty && per_bank_mem_rsp_ready;
end else begin
assign drsq_pop = !drsq_empty && per_bank_dram_rsp_ready[`DRAM_ADDR_BANK(dram_rsp_tag_qual)];
assign mrsq_pop = !mrsq_empty && per_bank_mem_rsp_ready[`MEM_ADDR_BANK(mem_rsp_tag_qual)];
end
///////////////////////////////////////////////////////////////////////////
@@ -229,17 +229,17 @@ module VX_cache #(
wire [CORE_TAG_WIDTH-1:0] curr_bank_core_rsp_tag;
wire curr_bank_core_rsp_ready;
wire curr_bank_dram_req_valid;
wire curr_bank_dram_req_rw;
wire [CACHE_LINE_SIZE-1:0] curr_bank_dram_req_byteen;
wire [`LINE_ADDR_WIDTH-1:0] curr_bank_dram_req_addr;
wire[`CACHE_LINE_WIDTH-1:0] curr_bank_dram_req_data;
wire curr_bank_dram_req_ready;
wire curr_bank_mem_req_valid;
wire curr_bank_mem_req_rw;
wire [CACHE_LINE_SIZE-1:0] curr_bank_mem_req_byteen;
wire [`LINE_ADDR_WIDTH-1:0] curr_bank_mem_req_addr;
wire[`CACHE_LINE_WIDTH-1:0] curr_bank_mem_req_data;
wire curr_bank_mem_req_ready;
wire curr_bank_dram_rsp_valid;
wire [`LINE_ADDR_WIDTH-1:0] curr_bank_dram_rsp_addr;
wire [`CACHE_LINE_WIDTH-1:0] curr_bank_dram_rsp_data;
wire curr_bank_dram_rsp_ready;
wire curr_bank_mem_rsp_valid;
wire [`LINE_ADDR_WIDTH-1:0] curr_bank_mem_rsp_addr;
wire [`CACHE_LINE_WIDTH-1:0] curr_bank_mem_rsp_data;
wire curr_bank_mem_rsp_ready;
// Core Req
assign curr_bank_core_req_valid = per_bank_core_req_valid[i];
@@ -260,28 +260,28 @@ module VX_cache #(
assign per_bank_core_rsp_tag [i] = curr_bank_core_rsp_tag;
assign per_bank_core_rsp_data [i] = curr_bank_core_rsp_data;
// DRAM request
assign per_bank_dram_req_valid[i] = curr_bank_dram_req_valid;
assign per_bank_dram_req_rw[i] = curr_bank_dram_req_rw;
assign per_bank_dram_req_byteen[i] = curr_bank_dram_req_byteen;
// Memory request
assign per_bank_mem_req_valid[i] = curr_bank_mem_req_valid;
assign per_bank_mem_req_rw[i] = curr_bank_mem_req_rw;
assign per_bank_mem_req_byteen[i] = curr_bank_mem_req_byteen;
if (NUM_BANKS == 1) begin
assign per_bank_dram_req_addr[i] = curr_bank_dram_req_addr;
assign per_bank_mem_req_addr[i] = curr_bank_mem_req_addr;
end else begin
assign per_bank_dram_req_addr[i] = `LINE_TO_DRAM_ADDR(curr_bank_dram_req_addr, i);
assign per_bank_mem_req_addr[i] = `LINE_TO_MEM_ADDR(curr_bank_mem_req_addr, i);
end
assign per_bank_dram_req_data[i] = curr_bank_dram_req_data;
assign curr_bank_dram_req_ready = per_bank_dram_req_ready[i];
assign per_bank_mem_req_data[i] = curr_bank_mem_req_data;
assign curr_bank_mem_req_ready = per_bank_mem_req_ready[i];
// DRAM response
// Memory response
if (NUM_BANKS == 1) begin
assign curr_bank_dram_rsp_valid = !drsq_empty;
assign curr_bank_dram_rsp_addr = dram_rsp_tag_qual;
assign curr_bank_mem_rsp_valid = !mrsq_empty;
assign curr_bank_mem_rsp_addr = mem_rsp_tag_qual;
end else begin
assign curr_bank_dram_rsp_valid = !drsq_empty && (`DRAM_ADDR_BANK(dram_rsp_tag_qual) == i);
assign curr_bank_dram_rsp_addr = `DRAM_TO_LINE_ADDR(dram_rsp_tag_qual);
assign curr_bank_mem_rsp_valid = !mrsq_empty && (`MEM_ADDR_BANK(mem_rsp_tag_qual) == i);
assign curr_bank_mem_rsp_addr = `MEM_TO_LINE_ADDR(mem_rsp_tag_qual);
end
assign curr_bank_dram_rsp_data = dram_rsp_data_qual;
assign per_bank_dram_rsp_ready[i] = curr_bank_dram_rsp_ready;
assign curr_bank_mem_rsp_data = mem_rsp_data_qual;
assign per_bank_mem_rsp_ready[i] = curr_bank_mem_rsp_ready;
VX_bank #(
.BANK_ID (i),
@@ -294,12 +294,12 @@ module VX_cache #(
.NUM_REQS (NUM_REQS),
.CREQ_SIZE (CREQ_SIZE),
.MSHR_SIZE (MSHR_SIZE),
.DREQ_SIZE (DREQ_SIZE),
.MREQ_SIZE (MREQ_SIZE),
.WRITE_ENABLE (WRITE_ENABLE),
.CORE_TAG_WIDTH (CORE_TAG_WIDTH),
.CORE_TAG_ID_BITS (CORE_TAG_ID_BITS),
.BANK_ADDR_OFFSET (BANK_ADDR_OFFSET),
.IN_ORDER_DRAM (IN_ORDER_DRAM)
.IN_ORDER_MEM (IN_ORDER_MEM)
) bank (
`SCOPE_BIND_VX_cache_bank(i)
@@ -332,19 +332,19 @@ module VX_cache #(
.core_rsp_tag (curr_bank_core_rsp_tag),
.core_rsp_ready (curr_bank_core_rsp_ready),
// DRAM request
.dram_req_valid (curr_bank_dram_req_valid),
.dram_req_rw (curr_bank_dram_req_rw),
.dram_req_byteen (curr_bank_dram_req_byteen),
.dram_req_addr (curr_bank_dram_req_addr),
.dram_req_data (curr_bank_dram_req_data),
.dram_req_ready (curr_bank_dram_req_ready),
// Memory request
.mem_req_valid (curr_bank_mem_req_valid),
.mem_req_rw (curr_bank_mem_req_rw),
.mem_req_byteen (curr_bank_mem_req_byteen),
.mem_req_addr (curr_bank_mem_req_addr),
.mem_req_data (curr_bank_mem_req_data),
.mem_req_ready (curr_bank_mem_req_ready),
// DRAM response
.dram_rsp_valid (curr_bank_dram_rsp_valid),
.dram_rsp_addr (curr_bank_dram_rsp_addr),
.dram_rsp_data (curr_bank_dram_rsp_data),
.dram_rsp_ready (curr_bank_dram_rsp_ready),
// Memory response
.mem_rsp_valid (curr_bank_mem_rsp_valid),
.mem_rsp_addr (curr_bank_mem_rsp_addr),
.mem_rsp_data (curr_bank_mem_rsp_data),
.mem_rsp_ready (curr_bank_mem_rsp_ready),
// flush
.flush_enable (flush_enable),
@@ -375,27 +375,27 @@ module VX_cache #(
.core_rsp_ready (core_rsp_ready)
);
wire [NUM_BANKS-1:0][(`DRAM_ADDR_WIDTH + 1 + CACHE_LINE_SIZE + `CACHE_LINE_WIDTH)-1:0] data_in;
wire [NUM_BANKS-1:0][(`MEM_ADDR_WIDTH + 1 + CACHE_LINE_SIZE + `CACHE_LINE_WIDTH)-1:0] data_in;
for (genvar i = 0; i < NUM_BANKS; i++) begin
assign data_in[i] = {per_bank_dram_req_addr[i], per_bank_dram_req_rw[i], per_bank_dram_req_byteen[i], per_bank_dram_req_data[i]};
assign data_in[i] = {per_bank_mem_req_addr[i], per_bank_mem_req_rw[i], per_bank_mem_req_byteen[i], per_bank_mem_req_data[i]};
end
VX_stream_arbiter #(
.NUM_REQS (NUM_BANKS),
.DATAW (`DRAM_ADDR_WIDTH + 1 + CACHE_LINE_SIZE + `CACHE_LINE_WIDTH),
.DATAW (`MEM_ADDR_WIDTH + 1 + CACHE_LINE_SIZE + `CACHE_LINE_WIDTH),
.BUFFERED (1)
) dram_req_arb (
) mem_req_arb (
.clk (clk),
.reset (reset),
.valid_in (per_bank_dram_req_valid),
.valid_in (per_bank_mem_req_valid),
.data_in (data_in),
.ready_in (per_bank_dram_req_ready),
.valid_out (dram_req_valid),
.data_out ({dram_req_addr, dram_req_rw, dram_req_byteen, dram_req_data}),
.ready_out (dram_req_ready)
.ready_in (per_bank_mem_req_ready),
.valid_out (mem_req_valid),
.data_out ({mem_req_addr, mem_req_rw, mem_req_byteen, mem_req_data}),
.ready_out (mem_req_ready)
);
assign dram_req_tag = dram_req_addr;
assign mem_req_tag = mem_req_addr;
`ifdef PERF_ENABLE
// per cycle: core_reads, core_writes

10
hw/rtl/cache/VX_cache_config.vh vendored
View File

@@ -21,8 +21,8 @@
`define WORDS_PER_LINE (CACHE_LINE_SIZE / WORD_SIZE)
`define WORD_ADDR_WIDTH (32-`CLOG2(WORD_SIZE))
`define DRAM_ADDR_WIDTH (32-`CLOG2(CACHE_LINE_SIZE))
`define LINE_ADDR_WIDTH (`DRAM_ADDR_WIDTH-`BANK_SELECT_BITS)
`define MEM_ADDR_WIDTH (32-`CLOG2(CACHE_LINE_SIZE))
`define LINE_ADDR_WIDTH (`MEM_ADDR_WIDTH-`BANK_SELECT_BITS)
// Word select
`define WORD_SELECT_BITS `CLOG2(`WORDS_PER_LINE)
@@ -57,11 +57,11 @@
`define BANK_READY_COUNT ((SHARED_BANK_READY != 0) ? 1 : NUM_BANKS)
`define DRAM_ADDR_BANK(x) x[`BANK_SELECT_BITS+BANK_ADDR_OFFSET-1 : BANK_ADDR_OFFSET]
`define MEM_ADDR_BANK(x) x[`BANK_SELECT_BITS+BANK_ADDR_OFFSET-1 : BANK_ADDR_OFFSET]
`define DRAM_TO_LINE_ADDR(x) x[`DRAM_ADDR_WIDTH-1 : `BANK_SELECT_BITS]
`define MEM_TO_LINE_ADDR(x) x[`MEM_ADDR_WIDTH-1 : `BANK_SELECT_BITS]
`define LINE_TO_DRAM_ADDR(x, i) {x, `BANK_SELECT_BITS'(i)}
`define LINE_TO_MEM_ADDR(x, i) {x, `BANK_SELECT_BITS'(i)}
`define LINE_TO_BYTE_ADDR(x, i) {x, (32-$bits(x))'(i << (32-$bits(x)-`BANK_SELECT_BITS))}