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code refactoring: DRAM => MEM renaming

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This commit is contained in:
Blaise Tine
2021-04-26 00:58:48 -07:00
parent d808aa2735
commit 8410c49f53
38 changed files with 1161 additions and 1161 deletions
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106
hw/rtl/afu/VX_cci_to_mem.v
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@@ -11,30 +11,30 @@ module VX_cci_to_mem #(
input wire clk,
input wire reset,
input wire dram_req_valid_in,
input wire [CCI_ADDRW-1:0] dram_req_addr_in,
input wire dram_req_rw_in,
input wire [CCI_DATAW-1:0] dram_req_data_in,
input wire [TAG_WIDTH-1:0] dram_req_tag_in,
output wire dram_req_ready_in,
input wire mem_req_valid_in,
input wire [CCI_ADDRW-1:0] mem_req_addr_in,
input wire mem_req_rw_in,
input wire [CCI_DATAW-1:0] mem_req_data_in,
input wire [TAG_WIDTH-1:0] mem_req_tag_in,
output wire mem_req_ready_in,
output wire dram_req_valid_out,
output wire [AVS_ADDRW-1:0] dram_req_addr_out,
output wire dram_req_rw_out,
output wire [AVS_BYTEENW-1:0] dram_req_byteen_out,
output wire [AVS_DATAW-1:0] dram_req_data_out,
output wire [TAG_WIDTH-1:0] dram_req_tag_out,
input wire dram_req_ready_out,
output wire mem_req_valid_out,
output wire [AVS_ADDRW-1:0] mem_req_addr_out,
output wire mem_req_rw_out,
output wire [AVS_BYTEENW-1:0] mem_req_byteen_out,
output wire [AVS_DATAW-1:0] mem_req_data_out,
output wire [TAG_WIDTH-1:0] mem_req_tag_out,
input wire mem_req_ready_out,
input wire dram_rsp_valid_in,
input wire [AVS_DATAW-1:0] dram_rsp_data_in,
input wire [TAG_WIDTH-1:0] dram_rsp_tag_in,
output wire dram_rsp_ready_in,
input wire mem_rsp_valid_in,
input wire [AVS_DATAW-1:0] mem_rsp_data_in,
input wire [TAG_WIDTH-1:0] mem_rsp_tag_in,
output wire mem_rsp_ready_in,
output wire dram_rsp_valid_out,
output wire [CCI_DATAW-1:0] dram_rsp_data_out,
output wire [TAG_WIDTH-1:0] dram_rsp_tag_out,
input wire dram_rsp_ready_out
output wire mem_rsp_valid_out,
output wire [CCI_DATAW-1:0] mem_rsp_data_out,
output wire [TAG_WIDTH-1:0] mem_rsp_tag_out,
input wire mem_rsp_ready_out
);
localparam N = AVS_ADDRW - CCI_ADDRW;
@@ -44,35 +44,35 @@ module VX_cci_to_mem #(
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
assign dram_req_valid_out = dram_req_valid_in;
assign dram_req_addr_out = dram_req_addr_in;
assign dram_req_rw_out = dram_req_rw_in;
assign dram_req_byteen_out = {AVS_BYTEENW{1'b1}};
assign dram_req_data_out = dram_req_data_in;
assign dram_req_tag_out = dram_req_tag_in;
assign dram_req_ready_in = dram_req_ready_out;
assign mem_req_valid_out = mem_req_valid_in;
assign mem_req_addr_out = mem_req_addr_in;
assign mem_req_rw_out = mem_req_rw_in;
assign mem_req_byteen_out = {AVS_BYTEENW{1'b1}};
assign mem_req_data_out = mem_req_data_in;
assign mem_req_tag_out = mem_req_tag_in;
assign mem_req_ready_in = mem_req_ready_out;
assign dram_rsp_valid_out = dram_rsp_valid_in;
assign dram_rsp_data_out = dram_rsp_data_in;
assign dram_rsp_tag_out = dram_rsp_tag_in;
assign dram_rsp_ready_in = dram_rsp_ready_out;
assign mem_rsp_valid_out = mem_rsp_valid_in;
assign mem_rsp_data_out = mem_rsp_data_in;
assign mem_rsp_tag_out = mem_rsp_tag_in;
assign mem_rsp_ready_in = mem_rsp_ready_out;
end else begin
reg [N-1:0] req_ctr, rsp_ctr;
wire [(2**N)-1:0][AVS_DATAW-1:0] dram_req_data_w_in;
wire [(2**N)-1:0][AVS_DATAW-1:0] mem_req_data_w_in;
reg [(2**N)-1:0][AVS_DATAW-1:0] dram_rsp_data_r_out, dram_rsp_data_n_out;
reg [(2**N)-1:0][AVS_DATAW-1:0] mem_rsp_data_r_out, mem_rsp_data_n_out;
wire dram_req_fire_out = dram_req_valid_out && dram_req_ready_out;
wire dram_rsp_fire_in = dram_rsp_valid_in && dram_rsp_ready_in;
wire mem_req_fire_out = mem_req_valid_out && mem_req_ready_out;
wire mem_rsp_fire_in = mem_rsp_valid_in && mem_rsp_ready_in;
assign dram_req_data_w_in = dram_req_data_in;
assign mem_req_data_w_in = mem_req_data_in;
always @(*) begin
dram_rsp_data_n_out = dram_rsp_data_r_out;
dram_rsp_data_n_out[rsp_ctr] = dram_rsp_data_in;
mem_rsp_data_n_out = mem_rsp_data_r_out;
mem_rsp_data_n_out[rsp_ctr] = mem_rsp_data_in;
end
always @(posedge clk) begin
@@ -80,28 +80,28 @@ module VX_cci_to_mem #(
req_ctr <= 0;
rsp_ctr <= 0;
end else begin
if (dram_req_fire_out) begin
if (mem_req_fire_out) begin
req_ctr <= req_ctr + 1;
end
if (dram_rsp_fire_in) begin
if (mem_rsp_fire_in) begin
rsp_ctr <= rsp_ctr + 1;
dram_rsp_data_r_out <= dram_rsp_data_n_out;
mem_rsp_data_r_out <= mem_rsp_data_n_out;
end
end
end
assign dram_req_valid_out = dram_req_valid_in;
assign dram_req_addr_out = {dram_req_addr_in, req_ctr};
assign dram_req_rw_out = dram_req_rw_in;
assign dram_req_byteen_out = {AVS_BYTEENW{1'b1}};
assign dram_req_data_out = dram_req_data_w_in[req_ctr];
assign dram_req_tag_out = dram_req_tag_in;
assign dram_req_ready_in = dram_req_ready_out && (req_ctr == (2**N-1));
assign mem_req_valid_out = mem_req_valid_in;
assign mem_req_addr_out = {mem_req_addr_in, req_ctr};
assign mem_req_rw_out = mem_req_rw_in;
assign mem_req_byteen_out = {AVS_BYTEENW{1'b1}};
assign mem_req_data_out = mem_req_data_w_in[req_ctr];
assign mem_req_tag_out = mem_req_tag_in;
assign mem_req_ready_in = mem_req_ready_out && (req_ctr == (2**N-1));
assign dram_rsp_valid_out = dram_rsp_valid_in && (rsp_ctr == (2**N-1));
assign dram_rsp_data_out = dram_rsp_data_n_out;
assign dram_rsp_tag_out = dram_rsp_tag_in;
assign dram_rsp_ready_in = dram_rsp_ready_out;
assign mem_rsp_valid_out = mem_rsp_valid_in && (rsp_ctr == (2**N-1));
assign mem_rsp_data_out = mem_rsp_data_n_out;
assign mem_rsp_tag_out = mem_rsp_tag_in;
assign mem_rsp_ready_in = mem_rsp_ready_out;
end
endmodule