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code refactoring: DRAM => MEM renaming

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This commit is contained in:
Blaise Tine
2021-04-26 00:58:48 -07:00
parent d808aa2735
commit 8410c49f53
38 changed files with 1161 additions and 1161 deletions
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96
driver/opae/vlsim/opae_sim.cpp
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@@ -10,10 +10,10 @@
#define RESET_DELAY 4
#define ENABLE_DRAM_STALLS
#define DRAM_LATENCY 24
#define DRAM_RQ_SIZE 16
#define DRAM_STALLS_MODULO 16
#define ENABLE_MEM_STALLS
#define MEM_LATENCY 24
#define MEM_RQ_SIZE 16
#define MEM_STALLS_MODULO 16
uint64_t timestamp = 0;
@@ -138,7 +138,7 @@ void opae_sim::flush() {
void opae_sim::reset() {
host_buffers_.clear();
dram_reads_.clear();
mem_reads_.clear();
cci_reads_.clear();
cci_writes_.clear();
vortex_afu_->vcp2af_sRxPort_c0_rspValid = 0;
@@ -268,87 +268,87 @@ void opae_sim::sTxPort_bus() {
}
void opae_sim::avs_bus() {
// update DRAM responses schedule
for (auto& rsp : dram_reads_) {
// update memory responses schedule
for (auto& rsp : mem_reads_) {
if (rsp.cycles_left > 0)
rsp.cycles_left -= 1;
}
// schedule DRAM responses in FIFO order
std::list<dram_rd_req_t>::iterator dram_rd_it(dram_reads_.end());
if (!dram_reads_.empty()
&& (0 == dram_reads_.begin()->cycles_left)) {
dram_rd_it = dram_reads_.begin();
// schedule memory responses in FIFO order
std::list<mem_rd_req_t>::iterator mem_rd_it(mem_reads_.end());
if (!mem_reads_.empty()
&& (0 == mem_reads_.begin()->cycles_left)) {
mem_rd_it = mem_reads_.begin();
}
// send DRAM response
// send memory response
vortex_afu_->avs_readdatavalid = 0;
if (dram_rd_it != dram_reads_.end()) {
if (mem_rd_it != mem_reads_.end()) {
vortex_afu_->avs_readdatavalid = 1;
memcpy(vortex_afu_->avs_readdata, dram_rd_it->data.data(), DRAM_BLOCK_SIZE);
uint32_t addr = dram_rd_it->addr;
dram_reads_.erase(dram_rd_it);
/*printf("%0ld: [sim] DRAM Rd Rsp: addr=%x, pending={", timestamp, addr * DRAM_BLOCK_SIZE);
for (auto& req : dram_reads_) {
memcpy(vortex_afu_->avs_readdata, mem_rd_it->data.data(), MEM_BLOCK_SIZE);
uint32_t addr = mem_rd_it->addr;
mem_reads_.erase(mem_rd_it);
/*printf("%0ld: [sim] MEM Rd Rsp: addr=%x, pending={", timestamp, addr * MEM_BLOCK_SIZE);
for (auto& req : mem_reads_) {
if (req.cycles_left != 0)
printf(" !%0x", req.addr * DRAM_BLOCK_SIZE);
printf(" !%0x", req.addr * MEM_BLOCK_SIZE);
else
printf(" %0x", req.addr * DRAM_BLOCK_SIZE);
printf(" %0x", req.addr * MEM_BLOCK_SIZE);
}
printf("}\n");*/
}
// handle DRAM stalls
bool dram_stalled = false;
#ifdef ENABLE_DRAM_STALLS
if (0 == ((timestamp/2) % DRAM_STALLS_MODULO)) {
dram_stalled = true;
// handle memory stalls
bool mem_stalled = false;
#ifdef ENABLE_MEM_STALLS
if (0 == ((timestamp/2) % MEM_STALLS_MODULO)) {
mem_stalled = true;
} else
if (dram_reads_.size() >= DRAM_RQ_SIZE) {
dram_stalled = true;
if (mem_reads_.size() >= MEM_RQ_SIZE) {
mem_stalled = true;
}
#endif
// process DRAM requests
if (!dram_stalled) {
// process memory requests
if (!mem_stalled) {
assert(!vortex_afu_->avs_read || !vortex_afu_->avs_write);
if (vortex_afu_->avs_write) {
uint64_t byteen = vortex_afu_->avs_byteenable;
unsigned base_addr = vortex_afu_->avs_address * DRAM_BLOCK_SIZE;
unsigned base_addr = vortex_afu_->avs_address * MEM_BLOCK_SIZE;
uint8_t* data = (uint8_t*)(vortex_afu_->avs_writedata);
for (int i = 0; i < DRAM_BLOCK_SIZE; i++) {
for (int i = 0; i < MEM_BLOCK_SIZE; i++) {
if ((byteen >> i) & 0x1) {
ram_[base_addr + i] = data[i];
}
}
/*printf("%0ld: [sim] DRAM Wr Req: addr=%x, data=", timestamp, base_addr);
for (int i = 0; i < DRAM_BLOCK_SIZE; i++) {
printf("%0x", data[(DRAM_BLOCK_SIZE-1)-i]);
/*printf("%0ld: [sim] MEM Wr Req: addr=%x, data=", timestamp, base_addr);
for (int i = 0; i < MEM_BLOCK_SIZE; i++) {
printf("%0x", data[(MEM_BLOCK_SIZE-1)-i]);
}
printf("\n");*/
}
if (vortex_afu_->avs_read) {
dram_rd_req_t dram_req;
dram_req.addr = vortex_afu_->avs_address;
ram_.read(vortex_afu_->avs_address * DRAM_BLOCK_SIZE, DRAM_BLOCK_SIZE, dram_req.data.data());
dram_req.cycles_left = DRAM_LATENCY;
for (auto& rsp : dram_reads_) {
if (dram_req.addr == rsp.addr) {
dram_req.cycles_left = rsp.cycles_left;
mem_rd_req_t mem_req;
mem_req.addr = vortex_afu_->avs_address;
ram_.read(vortex_afu_->avs_address * MEM_BLOCK_SIZE, MEM_BLOCK_SIZE, mem_req.data.data());
mem_req.cycles_left = MEM_LATENCY;
for (auto& rsp : mem_reads_) {
if (mem_req.addr == rsp.addr) {
mem_req.cycles_left = rsp.cycles_left;
break;
}
}
dram_reads_.emplace_back(dram_req);
/*printf("%0ld: [sim] DRAM Rd Req: addr=%x, pending={", timestamp, dram_req.addr * DRAM_BLOCK_SIZE);
for (auto& req : dram_reads_) {
mem_reads_.emplace_back(mem_req);
/*printf("%0ld: [sim] MEM Rd Req: addr=%x, pending={", timestamp, mem_req.addr * MEM_BLOCK_SIZE);
for (auto& req : mem_reads_) {
if (req.cycles_left != 0)
printf(" !%0x", req.addr * DRAM_BLOCK_SIZE);
printf(" !%0x", req.addr * MEM_BLOCK_SIZE);
else
printf(" %0x", req.addr * DRAM_BLOCK_SIZE);
printf(" %0x", req.addr * MEM_BLOCK_SIZE);
}
printf("}\n");*/
}
}
vortex_afu_->avs_waitrequest = dram_stalled;
vortex_afu_->avs_waitrequest = mem_stalled;
}