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Fixed DRAM random latency simulator

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This commit is contained in:
felsabbagh3
2020-03-31 20:33:45 -07:00
parent 1b9d9f3625
commit 7b4b44e5ab
1 changed files with 10 additions and 10 deletions
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20
rtl/simulate/simulator.cpp
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@@ -132,6 +132,16 @@ void Simulator::dbus_driver() {
} }
} }
#ifdef ENABLE_DRAM_STALLS
dram_stalled_ = false;
if (0 == (total_cycles_ % DRAM_STALLS_MODULO)) {
dram_stalled_ = true;
} else
if (dram_req_vec_.size() >= DRAM_RQ_SIZE) {
dram_stalled_ = true;
}
#endif
#ifdef USE_MULTICORE #ifdef USE_MULTICORE
if (vortex_->out_dram_req && !dram_stalled_) { if (vortex_->out_dram_req && !dram_stalled_) {
@@ -228,16 +238,6 @@ void Simulator::dbus_driver() {
#endif #endif
#ifdef ENABLE_DRAM_STALLS
dram_stalled_ = false;
if (0 == (total_cycles_ % DRAM_STALLS_MODULO)) {
dram_stalled_ = true;
} else
if (dram_req_vec_.size() >= DRAM_RQ_SIZE) {
dram_stalled_ = true;
}
#endif
#ifdef USE_MULTICORE #ifdef USE_MULTICORE
vortex_->out_dram_req_delay = dram_stalled_; vortex_->out_dram_req_delay = dram_stalled_;
#else #else